Semiconductor device and preparation method thereof, and storage system

Abstract

At least one embodiment of the invention provides a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a laminated structure, a storage column and a transistor. The laminated structure comprises first electrode layers and dielectric layers which are alternately stacked, wherein the first electrode layers extend in the direction perpendicular to the stacking direction of the laminated structure. The storage column extends in the laminated structure along the stacking direction, and comprises a second electrode layer and a storage function layer from inside to outside. The transistor is arranged on one side of the laminated structure, and a grid electrode of the transistor is connected with the second electrode layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] Taking memory as an example, in semiconductor devices, planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms or manufacturing processes. However, as the feature size of planar memory cells approaches the lower limit, planar processes and manufacturing technologies become challenging and costly.

[0003] Three-dimensional memory architecture can achieve higher storage density. However, as the number of stacked layers in semiconductor devices increases significantly, such as from 32 layers to 64 layers, then to 96 layers or even 128 layers, its reliability and read performance will decrease.

[0004] Therefore, how to improve the reliability and reading performance of semiconductor devices while improving the storage density of semiconductor devices is a problem that needs to be solved urgently. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and a storage system that can at least partially solve the above-mentioned problems or other problems existing in the related art.

[0006] On the one hand, the present application provides a semiconductor device, which includes: a stacked structure, including a first electrode layer and a dielectric layer alternately stacked, wherein the first electrode layer extends in a direction perpendicular to the stacking direction; a storage column, which extends in the stacked structure along the stacking direction and includes a second electrode layer and a storage function layer from the inside to the outside; and a transistor, which is arranged on one side of the stacked structure, wherein the gate of the transistor is connected to the second electrode layer.

[0007] In one embodiment of the present application, the transistor further comprises a source, a channel and a drain arranged in a plane perpendicular to the stacking direction, wherein the channel is located between the source and the drain.

[0008] In one embodiment of the present application, in a plane perpendicular to the stacking direction, the source, the channel and the drain are arranged around the gate to form a closed ring structure, wherein a gate dielectric layer is arranged between the gate and the ring structure.

[0009] In one embodiment of the present application, the semiconductor device further includes: a source contact structure connected to the source, and a drain contact structure connected to the drain, wherein, in a plane perpendicular to the stacking direction, the source contact structure and the drain contact structure are respectively located on opposite sides of the transistor.

[0010] In one embodiment of the present application, the semiconductor material layer included in the source contact structure and the source contain the same type of doping elements, wherein the doping concentration of the doping element of the source contact structure is greater than the doping concentration of the doping element of the source; and / or the semiconductor material layer included in the drain contact structure and the drain contain the same type of doping elements, wherein the doping concentration of the doping element of the drain contact structure is greater than the doping concentration of the doping element of the drain.

[0011] In one embodiment of the present application, the semiconductor device further includes: a source line connecting a plurality of the source contact structures, and a bit line connecting a plurality of the drain contact structures, wherein, in a plane perpendicular to the stacking direction, a projection of the source line intersects with a projection of the bit line.

[0012] In one embodiment of the present application, in a plane perpendicular to the stacking direction, the bit line extends along a first direction; and the source contact structure and the drain contact structure are respectively located on two opposite sides of the transistor in the first direction.

[0013] In one embodiment of the present application, the source line extends in a wavy shape in a direction perpendicular to the stacking direction.

[0014] In one embodiment of the present application, the stacked structure also includes a spacer layer, wherein the first electrode layer and the dielectric layer are located on a first side of the spacer layer, and the transistor is located on a second side of the spacer layer opposite to the first side; and in the stacking direction, the depth to which the gate extends into the stacked structure is less than or equal to the thickness of the spacer layer.

[0015] In one embodiment of the present application, the storage function layer includes a ferroelectric material layer.

[0016] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: alternately stacking a first electrode layer and a dielectric layer on one side of a substrate to form a stacked structure; forming a first opening extending along the stacking direction of the stacked structure, and sequentially forming an initial storage function layer and an initial second electrode layer on the inner wall and bottom surface of the first opening; removing a portion of the substrate from the other side opposite to the one side to form a second opening, wherein the second opening exposes a portion of the initial storage function layer; removing a portion of the initial storage function layer and a portion of the initial second electrode layer through the second opening to form a storage function layer and a second electrode layer; and forming a gate of a transistor connected to the second electrode layer in the second opening.

[0017] In one embodiment of the present application, the substrate includes an isolation layer and a plurality of source contact structures spaced apart in the isolation layer, and the method further includes: stopping the process of forming the first opening at the isolation layer.

[0018] In one embodiment of the present application, the method also includes forming the transistor, and the forming of the transistor includes: expanding the second opening in a direction perpendicular to the stacking direction to remove at least the portion of the isolation layer located between the second opening and the source contact structure; forming the source, channel and drain of the transistor in the expanded portion of the expanded second opening, wherein the source is connected to the source contact structure, and the channel is located between the source and the drain; forming a gate dielectric layer covering at least the source, the channel and the drain; and filling the gate in the remaining space of the expanded second opening.

[0019] In one embodiment of the present application, the source, the channel, and the drain are formed into a closed ring structure in a plane perpendicular to the stacking direction.

[0020] In one embodiment of the present application, the method also includes forming the substrate, and forming the substrate includes: arranging a plurality of source contact structures at intervals in an isolation layer; and forming a source line connecting the plurality of source contact structures, wherein the source line extends in a wavy shape in a direction perpendicular to the stacking direction.

[0021] In one embodiment of the present application, after forming the gate, the method further includes: forming a drain contact structure in the spacer layer, wherein, in a plane perpendicular to the stacking direction, the source contact structure and the drain contact structure are respectively located on opposite sides of the corresponding transistor.

[0022] In one embodiment of the present application, the method further includes: forming a bit line connecting the plurality of drain contact structures, wherein, in a plane perpendicular to the stacking direction, a projection of the source line intersects with a projection of the bit line.

[0023] In one embodiment of the present application, the stacked structure also includes a spacer layer, the first electrode layer and the dielectric layer are located above the spacer layer, and removing part of the initial storage functional layer and part of the initial second electrode layer through the second opening includes: removing the parts of the initial storage functional layer and the initial second electrode layer located in the spacer layer.

[0024] In one embodiment of the present application, the method further includes: forming the initial storage function layer using a ferroelectric material.

[0025] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: forming a transistor in a substrate; alternately stacking a first electrode layer and a dielectric layer on the substrate to form a stacked structure; and forming a first opening extending along the stacking direction of the stacked structure, and sequentially forming a storage function layer and a second electrode layer on the inner wall of the first opening, wherein the second electrode layer is connected to the gate of the transistor.

[0026] In one embodiment of the present application, the method further includes: stopping the process of forming the first opening at the gate.

[0027] In one embodiment of the present application, forming the transistor includes: in the isolation layer of the substrate, arranging a source contact structure and a drain contact structure at intervals along a direction perpendicular to the stacking direction; forming a second opening between the source contact structure and the drain contact structure that passes through the isolation layer along the stacking direction; enlarging the second opening to remove part of the isolation layer, wherein the removed part of the isolation layer is located between the second opening and the source contact structure and between the second opening and the drain contact structure; forming the source, channel and drain of the transistor in the enlarged part of the enlarged second opening, wherein the source is connected to the source contact structure, the drain is connected to the drain contact structure, and the channel is located between the source and the drain; forming a gate dielectric layer that at least covers the source, the channel and the drain; and filling the gate in the remaining space of the enlarged second opening.

[0028] In one embodiment of the present application, the source, the channel, and the drain are formed into a closed ring structure in a plane perpendicular to the stacking direction.

[0029] In one embodiment of the present application, the method further includes: forming a source line connecting the plurality of source contact structures in the substrate, wherein the source line extends in a wavy shape in a direction perpendicular to the stacking direction.

[0030] In one embodiment of the present application, the method further includes: forming a source line connecting multiple source contact structures in the substrate, and forming a bit line connecting multiple drain contact structures in the substrate, wherein in a plane perpendicular to the stacking direction, the projection of the source line intersects with the projection of the bit line.

[0031] In one embodiment of the present application, the method further includes: using ferroelectric material to form the storage function layer.

[0032] Another aspect of the present application provides a storage system, which includes the semiconductor device provided in one aspect of the present application and a controller coupled to the semiconductor device, wherein the controller is used to store data in the semiconductor device.

[0033] According to the semiconductor device, semiconductor device manufacturing method and storage system provided by at least one embodiment of the present application, non-destructive reading of the semiconductor device can be achieved by connecting the gate of the transistor to the second electrode layer of the storage column, thereby improving the reliability and reading performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0035] Figure 1 is a top perspective schematic diagram of a semiconductor device according to one embodiment of the present application;

[0036] Figure 2 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present application;

[0037] Figure 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present application;

[0038] Figure 4 is a flow chart of a method for preparing a semiconductor device according to one embodiment of the present application;

[0039] Figure 5-Figure 16 is a process schematic diagram of a method for preparing a semiconductor device according to an embodiment of the present application;

[0040] Fig.17 is a flow chart of a method for preparing a semiconductor device according to another embodiment of the present application;

[0041] Figure 18-Figure 22 is a process schematic diagram of a method for preparing a semiconductor device according to another embodiment of the present application; and

[0042] Fig.23 It is a schematic diagram of the storage system structure according to one embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first channel layer discussed in this application may also be referred to as the second channel layer, and vice versa.

[0045] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0046] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0047] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0048] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0049] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0050] Figure 1 is a schematic top perspective view of a semiconductor device 1000 according to one embodiment of the present application. Figure 2 is a schematic cross-sectional view of a semiconductor device 1000 according to an embodiment of the present application. Figure 3 is a schematic cross-sectional view of a semiconductor device 1000 according to another embodiment of the present application.

[0051] like Figures 1 to 3 As shown, the semiconductor device 1000 may include: a stacked structure 100, a storage pillar 200 and a transistor 300. The stacked structure 100 includes a first electrode layer 120 and a dielectric layer 130 alternately stacked, wherein the first electrode layer 120 extends in a direction (e.g., an x ​​direction or a y direction) perpendicular to the stacking direction (z direction) of the stacked structure 100. The storage pillar 200 extends in the stacked structure 100 along the z direction, and includes a second electrode layer 210 and a storage function layer 220 from the inside to the outside. The transistor 300 is arranged on one side of the stacked structure 100, wherein the gate 310 of the transistor 300 is connected to the second electrode layer 210. By connecting the gate of the transistor to the second electrode layer of the storage pillar, non-destructive reading of the semiconductor device 1000 can be achieved, and the reliability and reading performance of the semiconductor device 1000 can be improved.

[0052] It should be noted that Figure 1 For the convenience of observation, the source line 400 and the bit line 500 of the semiconductor device 1000 are arranged in the same figure. In fact, the source line 400 and the bit line 500 are located at different heights of the semiconductor device 1000 along the z direction. Figure 1Only the positional relationship between the source line 400 and the bit line 500, as well as the shape and extension direction of the source line 400 and the bit line 500 are shown. Figure 2 and Figure 3 The number of stacking layers in the stacked structure 100 is only illustrative, and the semiconductor device 1000 provided in the embodiment of the present application may also include other numbers of stacking layers, such as 4, 16, 32, 64, etc.

[0053] Specifically, taking ferroelectric memory as an example, ferroelectric memory uses the ferroelectric effect of the ferroelectric material layer to achieve data storage. The ferroelectric effect means that when an electric field is applied to the transistor of the ferroelectric memory, the central atoms of the ferroelectric material layer of the ferroelectric memory stop at the low energy state I position along the electric field. When the external electric field is reversed and applied to the same transistor, the central atoms will move in the crystal along the direction of the electric field and stop at another low energy state II. As a result, a large number of central atoms in the ferroelectric material layer move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarized charges under the action of the electric field. The polarized charge formed by the reversal of the ferroelectric domain under the electric field is higher, and the polarized charge formed by the non-reversal of the ferroelectric domain under the electric field is lower. This binary stable state of the ferroelectric material allows the ferroelectric material to be used as a memory.

[0054] By reading the voltage of the reference capacitor connected in series with the storage unit, it is possible to determine whether the ferroelectric domain of the ferroelectric material layer is reversed, thereby identifying the logical information in the storage unit formed by the ferroelectric material layer. However, this reading method is destructive, and the voltage reading will cause the ferroelectric domain of the ferroelectric material layer to reverse. After the reading operation, the original logical information state needs to be rewritten in the read storage unit, resulting in poor reading performance and reliability of the semiconductor device.

[0055] In the semiconductor device provided by at least one embodiment of the present application, the gate of the transistor is coupled to an electrode layer of a storage column, which can realize non-destructive reading of the semiconductor device, and thus improve the reliability and reading performance of the semiconductor device. Specifically, taking the ferroelectric memory as an example, the semiconductor device includes a transistor and a capacitor storage unit, and the gate of the transistor is connected to a plate of the capacitor storage unit, so that a voltage can be induced. The logical information state in the capacitor storage unit is different, the polarization state of the ferroelectric domain is different, and the voltage induced by the gate of the transistor is also different. In the case where a voltage difference occurs between the source and drain voltage of the transistor, whether the transistor is turned on depends on the induced voltage of the gate. For example, when the logical information state in the capacitor storage unit is a high state "1", the gate induces a positive voltage and the transistor is turned on; when the logical information state in the capacitor storage unit is a low state "0", the gate induced voltage is zero and the transistor is not turned on. By judging the on state of the transistor, the logical information in the capacitor storage unit can be read, and the ferroelectric domain of the ferroelectric material layer will not be reversed during the reading operation, so that non-destructive reading of the capacitor storage unit can be realized.

[0056] In one embodiment of the present application, the first electrode layer 120 extends in a direction perpendicular to the z direction (e.g., the x direction or the y direction). The first electrode layer 120 may include a first conductive material layer, wherein the first conductive material may include but is not limited to single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium, etc. Exemplarily, the first electrode layer 120 may include a polycrystalline silicon layer.

[0057] In addition, the dielectric layer 130 extends in a direction perpendicular to the z direction (e.g., the x direction or the y direction). The dielectric layer 130 may include an insulating material layer, wherein the insulating material may include but is not limited to silicon oxide, silicon nitride, or silicon oxynitride, etc. Exemplarily, the dielectric layer 130 may include a silicon oxide layer.

[0058] In addition, the semiconductor device 1000 may further include a substrate (not shown) supporting the stacked structure 100. The substrate may include a semiconductor material layer, wherein the semiconductor material may include but is not limited to a single semiconductor material (e.g., silicon, germanium), a III-V compound semiconductor material, a II-VI compound semiconductor material, an organic semiconductor material, or other semiconductor materials known in the art. Exemplarily, the substrate may be a silicon substrate.

[0059] In one embodiment of the application, the storage pillar 200 extends in the stacked structure 100 along the z direction and includes a second electrode layer 210 and a storage function layer 220 from the inside to the outside. As an option, the storage function layer 220 extends in the stacked structure 100 along the z direction and includes: a ferroelectric material layer or an antiferroelectric material layer, etc. For example, hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si a (HfO2)b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b ) or zirconium oxide (ZrO), etc., where a and b are positive numbers.

[0060] In addition, the second electrode layer 210 extends in the stacked structure 100 along the z direction and may include: a second conductive material layer 210-1 and an electrode bonding layer 210-2, wherein the electrode bonding layer 210-2 is located between the second conductive material layer 210-1 and the storage function layer 220. By forming the electrode bonding layer 210-2 between the energy storage function layer 220 and the second conductive material layer 210-1, the adhesion between the energy storage function layer 220 and the second electrode layer 210 can be increased, which is conducive to reducing the probability of the second electrode layer 210 falling off.

[0061] Optionally, the constituent material of the second conductive material layer 210-1 may include, but is not limited to, single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium, etc. Exemplarily, the second conductive material layer 210-1 may be a tungsten layer. Optionally, the constituent material of the electrode bonding layer 210-2 may include, but is not limited to, metal nitrides, such as tungsten nitride, titanium nitride or tantalum nitride, etc. Exemplarily, the electrode bonding layer 210-2 may be a titanium nitride layer.

[0062] In one embodiment of the application, the transistor 300 is disposed on one side of the stacked structure 100, wherein the gate 310 of the transistor 300 is connected to the second electrode layer 210. Optionally, the gate 310 may include a gate conductive material layer 310-1, wherein the constituent material of the gate conductive layer 310-1 may include but is not limited to single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, etc. Exemplarily, the gate conductive material layer 310-1 may be a polycrystalline silicon layer.

[0063] In addition, the gate 310 may further include a gate adhesion layer 310-2. The constituent material of the gate adhesion layer 310-2 may include but is not limited to metal nitrides, such as tungsten nitride, titanium nitride or tantalum nitride, etc. Exemplarily, the gate adhesion layer 310-2 may be a titanium nitride layer.

[0064] In addition, the transistor 300 further includes a source 320, a channel 340 and a drain 330 arranged in a plane (xy) perpendicular to the z direction, wherein the channel 340 is located between the source 320 and the drain 330. The source 320 and the drain 330 of the transistor 300 are located in the same plane, which can make the structure layout of the transistor 300 compact and improve the unit storage density of the semiconductor device 1000.

[0065] Optionally, the constituent materials of the source 320 , the channel 340 and the drain 330 may include but are not limited to semiconductor materials, such as single crystal silicon, polycrystalline silicon, amorphous silicon, doped single crystal silicon, doped polycrystalline silicon or doped amorphous silicon.

[0066] In addition, in the xy plane, the source 320, the channel 340 and the drain 330 can be arranged around the gate 310 to form a closed ring structure. For example, the transistor 300 can be a vertical ring channel device structure (CAA, Channel-All-Around). By forming the source 320, the channel 340 and the drain 330 of the transistor 300 into a closed ring structure, the distance between the source 320 and the drain 330 can be shortened, and the structural layout of the transistor 300 can be made more compact, effectively reducing the device area, and further improving the unit storage density of the semiconductor device 1000.

[0067] In addition, the transistor 300 further includes a gate dielectric layer 350 located between the gate 310 and the ring structure. Optionally, the gate dielectric layer 350 may include an insulating material layer, wherein the insulating material includes but is not limited to silicon oxide, silicon nitride or silicon oxynitride.

[0068] In one embodiment of the application, the semiconductor device 1000 further includes a source contact structure 410 connected to the source 320, and a drain contact structure 510 connected to the drain 330, wherein in the xy plane, the source contact structure 410 and the drain contact structure 510 are respectively located on opposite sides of the transistor 300. By arranging the source contact structure 410 and the drain contact structure 510 in the same plane, the structural layout of the semiconductor device can be made more compact, thereby improving the unit storage density of the semiconductor device.

[0069] For example, in the xy plane, the bit line 500 of the semiconductor device 1000 extends along the x direction. Optionally, the source contact structure 410 and the drain contact structure 510 may be respectively located on opposite sides of the transistor 300 in the x direction, so as to facilitate the connection between the drain contact structure 510 and the bit line 500, shorten the length of the connection line, reduce the device area, and further improve the unit storage density of the semiconductor device 1000.

[0070] The constituent materials of the source contact structure 410 and the drain contact structure 510 may include, but are not limited to, semiconductor materials, such as single crystal silicon, polycrystalline silicon, amorphous silicon, doped single crystal silicon, doped polycrystalline silicon, or doped amorphous silicon.

[0071] As an option, both the source contact structure 410 and the source 320 include a doped semiconductor material layer. The semiconductor material layer included in the source contact structure 410 and the source 320 may contain the same type of doping elements, and the doping concentration of the doping element of the source contact structure 410 is greater than the doping concentration of the doping element of the source 320.

[0072] The channel of a semiconductor device is a key passage for carrier migration. The source 320 includes an undoped semiconductor material layer or a relatively low-concentration doped semiconductor material layer, which can form a larger doping concentration difference of the conductive doping element between the source contact structure 410 and the source 320, thereby facilitating the carriers mainly composed of conductive doping elements to flow toward the source 320, and then flow into the channel 340 of the transistor 300, thereby improving the current conduction capability of the channel 340.

[0073] Specifically, the doping element may include two types (understandable conductivity type), the first type may be P-type, and the second type may be N-type. As an option, the semiconductor material layer included in the source contact structure 410 and the semiconductor material layer included in the source 320 may be doped with any suitable, for example, N-type dopant (e.g., phosphorus (P), arsenic (Ar) or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. As another option, the semiconductor material layer included in the source contact structure 410 and the semiconductor material layer included in the source 320 may be doped with any suitable, for example, P-type dopant (e.g., boron (B), gallium (Ga) or indium (In)) to absorb free electrons and increase the conductivity of the intrinsic semiconductor.

[0074] In addition, as another option, the drain contact structure 510 and the drain 330 both include a doped semiconductor material layer. The semiconductor material layer included in the drain contact structure 510 and the drain 330 contain the same type of doping elements, and the doping concentration of the doping element of the drain contact structure 510 is greater than the doping concentration of the doping element of the drain 330.

[0075] Similarly, the drain 330 includes an undoped semiconductor material layer or a relatively low-concentration doped semiconductor material layer, which can form a larger doping concentration difference of the conductive doping element between the drain contact structure 510 and the drain 330, thereby facilitating the flow of carriers mainly composed of conductive doping elements toward the drain 330, and then flow into the channel 340 of the transistor 300, thereby improving the current conduction capability of the channel 340.

[0076] Specifically, the doping element may include two types (understandable conductivity type), the first type may be P-type, and the second type may be N-type. As an option, the semiconductor material layer included in the drain contact structure 510 and the semiconductor material layer included in the drain 330 may be doped with any suitable, for example, N-type dopant (for example, phosphorus (P), arsenic (Ar) or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. As another option, the semiconductor material layer included in the drain contact structure 510 and the semiconductor material layer included in the drain 330 may be doped with any suitable, for example, P-type dopant (for example, boron (B), gallium (Ga) or indium (In)) to absorb free electrons and increase the conductivity of the intrinsic semiconductor.

[0077] In addition, if Figure 1 As shown, in one embodiment of the present application, the semiconductor device 1000 further includes: a source line 400 and a bit line 500, wherein the source line 400 connects a plurality of source contact structures 410, and the bit line 500 connects a plurality of drain contact structures 510. Optionally, in the xy plane, the projection of the source line 400 intersects with the projection of the bit line 500. For example, in the xy plane, the projection of the source line 400 is perpendicular to the projection of the bit line 500.

[0078] In addition, in one embodiment of the present application, in the xy plane, the source line 400 may extend in a wavy line. For example, the source line 400 extends in a wavy line along the y direction in the xy plane. Setting the shape of the source line 400 to be wavy can make the layout of the transistor 300 more compact and increase the storage density of the semiconductor device 1000. In addition, in the process of preparing the conductor device 1000, the groove accommodating the source line 400 is in the form of a wavy line, so that the tensile stress on the groove can actually act on multiple waves and can be decomposed at the waves, so that the force in the normal direction of each face element divided by the side of the groove becomes smaller, thereby reducing the risk of cracking of the groove and improving the stability and conductivity of the semiconductor device 1000.

[0079] refer to Figure 2 and Figure 3 In one embodiment of the present application, the stacked structure 100 further includes a spacer layer 110. The spacer layer 110 includes a first side and a second side opposite to each other along the z direction, and has a predetermined thickness in the z direction. The spacer layer 110 may include an insulating material layer, wherein the insulating material may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride. Exemplarily, the spacer layer 110 may include a silicon oxide layer. Optionally, the spacer layer 110 may be made of the same material as the dielectric layer 130.

[0080] The first electrode layer 120 and the dielectric layer 130 are located on a first side of the spacer layer 110, and the transistor 300 is located on a second side of the spacer layer 110. Optionally, in the z direction, the gate 310 of the transistor 300 extends into the stacked structure 100 to a depth that is less than or equal to the thickness of the spacer layer 110. Since the spacer layer 110 includes an insulating material layer, the gate 310 of the transistor 300 extends into the spacer layer 110, which can reduce the risk of the gate 310 contacting the first electrode layer 120 during the preparation of the semiconductor device 1000, and is conducive to reducing the occurrence of leakage of the semiconductor device 1000.

[0081] Therefore, according to the semiconductor device provided by at least one embodiment of the present application, by connecting the gate of the transistor to the second electrode layer of the storage column, non-destructive reading of the semiconductor device can be achieved, thereby improving the reliability and reading performance of the semiconductor device.

[0082] Figure 4 FIG. 2 is a flow chart of a method 2000 for manufacturing a semiconductor device according to an embodiment of the present application. Figure 4 As shown, the present application provides a method 2000 for preparing a semiconductor device, comprising:

[0083] S11, alternately stacking first electrode layers and dielectric layers on one side of the substrate to form a stacked structure.

[0084] S12, forming a first opening extending along the stacking direction of the stacked structure, and sequentially forming an initial storage function layer and an initial second electrode layer on the inner wall and bottom surface of the first opening.

[0085] S13, removing a portion of the substrate from the other side opposite to the one side to form a second opening, wherein the second opening exposes a portion of the initial storage function layer.

[0086] S14, removing a portion of the initial storage function layer and a portion of the initial second electrode layer through the second opening to form a storage function layer and a second electrode layer.

[0087] S15, forming a gate of a transistor connected to the second electrode layer in the second opening.

[0088] The following will be combined Figures 4 to 16 The specific process of each step of the above-mentioned preparation method 2000 is described in detail.

[0089] Step S11

[0090] Figure 5 It is a cross-sectional schematic diagram of a structure formed after an initial storage function layer 220 ′ and an initial second electrode layer 210 ′ are formed according to a preparation method in one embodiment of the present application and flipped 180°. Figure 6It is a schematic top view of a structure formed after forming an initial storage function layer 220 ′ and an initial second electrode layer 210 ′ according to a preparation method in one embodiment of the present application.

[0091] like Figures 4 to 6 As shown, step S11 alternately stacks first electrode layers and dielectric layers on one side of the substrate to form a stacked structure, which may for example include: preparing a substrate (not shown); alternately stacking first electrode layers 120 and dielectric layers 130 along the z direction on the first side of the substrate to form a stacked structure 100.

[0092] Specifically, in some embodiments, as an example, the substrate may be selected according to actual requirements of the device, and the substrate may be a composite structure, for example, including an isolation layer 11. The substrate has a first side and a second side opposite to each other in the z direction.

[0093] Materials for preparing the substrate may include silicon (Si), germanium (Ge), silicon germanium (SiGe), SOI (Silicon-on-Insulator) or GOI (Germanium-on-Insulator), etc. In other embodiments, the substrate may also include other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc. In addition, the substrate may also be a composite structure, such as a silicon stack or a germanium silicon stack.

[0094] In addition, in the semiconductor device manufacturing method 2000 provided in the present application, the substrate can be completely removed in subsequent steps, so a common substrate structure can generally be used without making other structures therein, which not only saves costs but also reduces process difficulty.

[0095] refer to Figure 5 to Figure 6 In one embodiment of the present application, the substrate may include an isolation layer 11 , a plurality of source contact structures 410 spaced apart in the isolation layer 11 , and a source line 400 connecting the plurality of source contact structures 400 .

[0096] For example, forming the substrate may include: arranging a plurality of source contact structures 410 in the isolation layer 11 at intervals; and forming a source line 400 connecting the plurality of source contact structures 410 , wherein the source line 400 extends in a wavy shape in a direction perpendicular to the z direction (eg, the y direction).

[0097] Specifically, the isolation layer 11 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present application. Optionally, the isolation layer 11 may include but is not limited to an insulating dielectric material layer such as a silicon nitride layer.

[0098] After the isolation layer 11 is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to form a groove (not shown) penetrating the isolation layer 11; and a source contact structure 400 is formed in the groove by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0099] In addition, the groove may extend in a wavy line in the xy plane, so that the source contact structure 400 formed in the groove extends in a wavy line. The groove accommodating the source line 400 is in a wavy line shape, so that the tensile stress on the groove can actually act on multiple waves and can be decomposed at the waves, so that the force in the normal direction of each face element divided by the side of the groove becomes smaller, thereby reducing the risk of groove cracking and improving the stability and conductivity of the semiconductor device finally formed.

[0100] The material for preparing the source line 400 may include a conductive material, such as a metal material, wherein the metal material may be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) and other conductive materials, and the present application does not limit this.

[0101] After forming the substrate, the stacked structure 100 may be formed on the substrate by one or more thin film deposition processes, wherein the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present application. Optionally, the stacked structure 100 further includes a spacer layer 110, which is located on the spacer layer 110 and alternately stacks the first electrode layer 120 and the dielectric layer 130.

[0102] Specifically, a spacer layer 110 may be formed above the isolation layer 11, and a first electrode layer 120 and a dielectric layer 130 may be alternately stacked above the spacer layer 110. The spacer layer 110 extends in a direction perpendicular to the z direction (e.g., the x direction or the y direction). The material for preparing the spacer layer 110 may include an insulating material, wherein the insulating material may include but is not limited to silicon oxide, silicon nitride, or silicon oxynitride. Exemplarily, the spacer layer 110 may include a silicon oxide layer.

[0103] The first electrode layer 120 extends in a direction perpendicular to the z direction (e.g., the x direction or the y direction). The material for preparing the first electrode layer 120 may include a first conductive material, wherein the first conductive material may include but is not limited to single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium, etc. Exemplarily, the first electrode layer 120 may include a polycrystalline silicon layer.

[0104] In addition, the dielectric layer 130 extends in a direction perpendicular to the z direction (e.g., the x direction or the y direction). The material for preparing the dielectric layer 130 may include an insulating material, wherein the insulating material may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride, etc. Exemplarily, the dielectric layer 130 may include a silicon oxide layer.

[0105] Optionally, in order to save costs and simplify the manufacturing process, the spacer layer 110 and the dielectric layer 130 may be formed using the same material and manufacturing process.

[0106] Step S12

[0107] Reference again Figures 4 to 6 Step S12 forms a first opening extending along the stacking direction of the stacked structure, and sequentially forms an initial storage function layer and an initial second electrode layer on the inner wall and bottom surface of the first opening, which may, for example, include: forming a first opening (not shown) extending along the z direction; and sequentially forming an initial storage function layer 220' and an initial second electrode layer 210' on the inner wall and bottom surface of the first opening.

[0108] Specifically, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, to form a first opening extending along the z direction.

[0109] Optionally, the process of forming the first opening stops at the isolation layer 11. By setting the isolation layer 11 as a stop layer, the etching of the first opening can be stopped at the isolation layer 11 during the process of forming the first opening through the etching process, thereby reducing the probability of over-etching of the first opening and reducing the occurrence of the first opening penetrating into the substrate. On the one hand, the morphology of the first opening is improved, for example, multiple first openings have the same extension length in the z direction; on the other hand, the leakage problem of the semiconductor device formed subsequently due to the electrode layer penetrating into the substrate can be reduced. Both aspects contribute to improving the electrical performance of the semiconductor device finally formed.

[0110] After the first opening is formed, an initial storage function layer 220 ′ and an initial second electrode layer 210 ′ may be sequentially formed on the inner wall and bottom surface of the first opening by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0111] Optionally, the material forming the initial storage function layer 220' includes a ferroelectric material or an antiferroelectric material. For example, hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si a (HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b ) or zirconium oxide (ZrO), etc., where a and b are positive numbers.

[0112] Optionally, the initial second electrode layer 210' includes an initial second conductive material layer 210'-1 and an initial electrode bonding layer 210'-2, wherein the initial electrode bonding layer 210'-2 is located between the initial second conductive material layer 210'-1 and the initial storage functional layer 220'. By forming the initial electrode bonding layer 210'-2 between the initial energy storage functional layer 220' and the initial second conductive material layer 210'-1, the adhesion between the subsequently formed energy storage functional layer and the second electrode layer can be increased, which is conducive to reducing the probability of the second electrode layer falling off.

[0113] Optionally, the material forming the initial second conductive material layer 210'-1 may include, but is not limited to, single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium, etc. Exemplarily, the initial second conductive material layer 210'-1 may be a tungsten layer. Optionally, the material forming the initial electrode bonding layer 210'-2 may include, but is not limited to, metal nitrides, such as tungsten nitride, titanium nitride or tantalum nitride, etc. Exemplarily, the initial electrode bonding layer 210'-2 may be a titanium nitride layer.

[0114] Step S13

[0115] Figure 7 It is a schematic cross-sectional view of a structure formed after forming the second opening 12 according to a preparation method in one embodiment of the present application. Figure 8 It is a schematic top view of a structure formed after forming the second opening 12 according to a preparation method in one embodiment of the present application.

[0116] like Figures 5 to 8 As shown, step S13 removes a portion of the substrate from the other side opposite to the one side to form a second opening, wherein the second opening exposes a portion of the initial storage functional layer and may, for example, include: being formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove a portion of the substrate from the other side to form a second opening 12, wherein the second opening 12 exposes a portion of the initial storage functional layer 220'.

[0117] In other words, the substrate includes one side and another side opposite to each other along the z direction, wherein the stacked structure 100 is formed on one side of the substrate, and a second opening 12 extending along the z direction is formed on the other side of the substrate. Optionally, the second opening 12 extends along the z direction to the bottom of the initial storage function layer 220', thereby exposing the bottom of the initial storage function layer 220'.

[0118] Fig. 9 It is a schematic cross-sectional view of a structure formed after forming a channel 340 of a transistor according to a preparation method in one embodiment of the present application. Fig.10 It is a schematic top view of a structure formed after forming a channel 340 of a transistor according to a preparation method in one embodiment of the present application.

[0119] Optionally, in one embodiment of the present application, the method 2000 for manufacturing a semiconductor device may further include forming a transistor. Therefore, this step may further include forming a source 320, a channel 340 and a drain 330 of the transistor.

[0120] Specifically, refer to Figures 7 to 10 , the second opening 12 can be enlarged in a direction perpendicular to the z direction to remove at least the portion of the isolation layer 11 between the second opening and the source contact structure 410; in the enlarged portion 12'-1 of the enlarged second opening 12', a source 320, a channel 340 and a drain 330 are formed, wherein the source 320 is connected to the source contact structure 410, and the channel 340 is located between the source 320 and the drain 330.

[0121] Optionally, by a thin film deposition process such as CVD, PVD, ALD or any combination thereof, the source 320, the channel 340 and the drain 330 may be formed in the enlarged portion 12'-1 of the enlarged second opening 12', and the materials may include but are not limited to semiconductor materials, such as single crystal silicon, polycrystalline silicon, amorphous silicon, doped single crystal silicon, doped polycrystalline silicon or doped amorphous silicon.

[0122] Optionally, the enlarged portion 12'-1 is annular in the xy plane. Therefore, as an option, the source 320, the channel 340 and the drain 330 are formed into a closed annular structure in the xy plane. By forming the source 320, the channel 340 and the drain 330 of the transistor into a closed annular structure, the distance between the source 320 and the drain 330 can be shortened, and the structural layout of the transistor can be made more compact, effectively reducing the device area, and further improving the unit storage density of the semiconductor device finally formed.

[0123] Step S14

[0124] Fig.11 It is a schematic cross-sectional view of a structure formed after forming a gate dielectric layer 350 according to a preparation method in one embodiment of the present application. Fig.12 It is a schematic top view of a structure formed after forming a gate dielectric layer 350 according to a preparation method in one embodiment of the present application.

[0125] like Figures 7 to 12 As shown, step S14 removes part of the initial storage function layer and part of the initial second electrode layer through the second opening to form a storage function layer and a second electrode layer, which may, for example, include: forming by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove part of the initial storage function layer 220' and part of the initial second electrode layer 210' to form a storage function layer 220 and a second electrode layer 210.

[0126] Optionally, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to sequentially remove the bottom of the initial storage functional layer 220' and a portion of the side wall connected to the bottom, the bottom of the initial electrode bonding layer 210'-2 and a portion of the side wall connected to the bottom, and a portion of the side wall connected to the bottom of the initial second conductive material layer 210'-1.

[0127] In one embodiment of the present application, removing part of the initial storage function layer 220' and part of the initial second electrode layer 210' through the second opening 12 may include: removing the part of the initial storage function layer 220' and the initial second electrode layer 210' located in the spacer layer 110. Since the spacer layer 110 includes an insulating material layer, the gate of the transistor connected to the second electrode layer 210 formed subsequently may extend into the spacer layer 110. Therefore, in the process of preparing the semiconductor device 1000, the risk of the gate 310 formed subsequently contacting the first electrode layer can be reduced, which is conducive to reducing the occurrence of leakage in the finally formed semiconductor device.

[0128] Step S15

[0129] Fig.13 It is a schematic cross-sectional view of a structure formed after forming a gate 310 according to a preparation method in one embodiment of the present application. Fig.14 It is a schematic top view of a structure formed after forming a gate 310 according to a preparation method in one embodiment of the present application.

[0130] like Figures 9 to 14 As shown, step S15 of forming a gate of a transistor connected to the second electrode layer in the second opening may, for example, include: forming a gate 310 of a transistor connected to the second electrode layer 210 in the second opening 12 by one or more thin film deposition processes, wherein the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present application.

[0131] like Figure 11 to Figure 12 As shown, after forming the storage function layer 220 and the second electrode layer 210, a gate dielectric layer 350 may be formed on the sidewall of the second opening 12 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The material forming the gate dielectric layer 350 may include an insulating material, wherein the insulating material includes but is not limited to silicon oxide, silicon nitride or silicon oxynitride.

[0132] Combination Figures 9 to 14 After forming the gate dielectric layer 350 , a gate 310 may be formed in the remaining space of the second opening 12 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0133] In one embodiment of the application, the gate 310 of the transistor is connected to the second electrode layer 210. Optionally, the gate 310 may include a gate conductive material layer 310-1, wherein the material forming the gate conductive layer 310-1 may include but is not limited to single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, etc. Exemplarily, the gate conductive material layer 310-1 may be a polycrystalline silicon layer. In addition, the gate 310 may also include a gate adhesion layer 310-2. The material forming the gate adhesion layer 310-2 may include but is not limited to metal nitrides, such as tungsten nitride, titanium nitride or tantalum nitride. Exemplarily, the gate adhesion layer 310-2 may be a titanium nitride layer.

[0134] After forming the gate 310, the transistor 300 connected to the second electrode layer 210 is formed. By connecting the gate of the transistor to the second electrode layer of the storage pillar, non-destructive reading of the final semiconductor device can be achieved, thereby improving the reliability and reading performance of the final semiconductor device.

[0135] Fig.15 It is a schematic cross-sectional view of a structure formed after forming a drain contact structure 510 according to a preparation method in one embodiment of the present application. Fig.16 It is a schematic top view of a structure formed after forming a drain contact structure 510 according to a preparation method in one embodiment of the present application.

[0136] like Figures 13 to 16 As shown, in one embodiment of the application, the method 2000 for preparing a semiconductor device further includes: after forming the gate 310, forming a drain contact structure 510 in the spacer layer 110, wherein in the xy plane, the source contact structure 410 and the drain contact structure 510 are respectively located on opposite sides of the corresponding transistor 300. By arranging the source contact structure 410 and the drain contact structure 510 in the same plane, the structural layout of the semiconductor device can be made more compact, and the unit storage density of the semiconductor device can be improved.

[0137] A drain contact structure 510 may be formed in the spacer layer 110 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof, wherein the drain contact structure 510 contacts the drain 330 of the transistor 300. The material forming the drain contact structure 510 may include, but is not limited to, semiconductor materials such as single crystal silicon, polycrystalline silicon, amorphous silicon, doped single crystal silicon, doped polycrystalline silicon or doped amorphous silicon.

[0138] In addition, the same type of doping elements can also be used to dope the drain 330 and the drain contact structure 510. Specifically, doping can be performed using, for example, an ion implantation process or a laser annealing process, and a drain 330 and a drain contact structure 510 containing doping elements of a single conductivity type are formed by introducing an appropriate amount of dopant (impurity source). The doping elements may include two types (understandable conductivity types), the first type may be P-type, and the second type may be N-type. As an option, N-type dopants (e.g., phosphorus (P), arsenic (Ar) or antimony (Sb)) are used to contribute free electrons and increase the conductivity of the intrinsic semiconductor. As another option, P-type dopants (e.g., boron (B), gallium (Ga) or indium (In)) are used to absorb free electrons and increase the conductivity of the intrinsic semiconductor.

[0139] Optionally, the drain contact structure 510 and the drain 330 both include a doped semiconductor material layer, wherein the semiconductor material layer included in the drain contact structure 510 and the drain 330 include the same type of doping elements, and the doping concentration of the doping element of the drain contact structure 510 is greater than the doping concentration of the doping element of the drain 330 .

[0140] Similarly, the drain 330 includes an undoped semiconductor material layer or a relatively low-concentration doped semiconductor material layer, which can form a larger doping concentration difference of the conductive doping element between the drain contact structure 510 and the drain 330, thereby facilitating the flow of carriers mainly composed of conductive doping elements toward the drain 330, and then flow into the channel 340 of the transistor 300, thereby improving the current conduction capability of the channel 340.

[0141] Alternatively, any suitable doping process, such as a chemical vapor doping process, may be used to form the drain contact structure 510 or the drain 330 during the process of forming the drain contact structure 510 or the drain 330. Chemical vapor doping refers to the process of doping impurity elements into the thin film through the gas phase during the CVD thin film deposition process. In other words, when the CVD process is used, a drain contact structure 510 or the drain 330 containing a doping element of a single conductivity type may be formed by introducing an appropriate amount of dopant (impurity source).

[0142] In addition, reference Figure 1 to Figure 2 , Figure 15 to Figure 16 In one embodiment of the present application, the method 2000 for preparing a semiconductor device further includes: forming a bit line 500 connecting a plurality of drain contact structures 510, wherein in the xy plane, the projection of the source line 400 intersects with the projection of the bit line 500. For example, in the xy plane, the projection of the source line 400 is perpendicular to the projection of the bit line 500. The projection of the source line 400 intersects with the projection of the bit line 500 in the xy plane, which can make the structural layout of the finally formed semiconductor device more compact and improve the unit storage density of the semiconductor device.

[0143] Fig.17 FIG. 3 is a flow chart of a method 3000 for manufacturing a semiconductor device according to another embodiment of the present application. Fig.17 As shown, the present application provides a method 3000 for preparing a semiconductor device, comprising:

[0144] S21, forming a transistor in the substrate.

[0145] S22, alternately stacking first electrode layers and dielectric layers on the substrate to form a stacked structure.

[0146] S23, forming a first opening extending along the stacking direction of the stacked structure, and sequentially forming a storage function layer and a second electrode layer on the inner wall of the first opening, wherein the second electrode layer is connected to the gate of the transistor.

[0147] Since the contents involved in the manufacturing method described in the semiconductor device manufacturing method 2000 above are completely or partially applicable to the semiconductor device manufacturing method described here, the contents related or similar thereto are not repeated. However, those skilled in the art can understand that the semiconductor device 1000 (such as the semiconductor device 1000) can be formed according to the semiconductor device manufacturing method 2000. Figure 1 to Figure 2 ), the semiconductor device 1000 (as shown) can also be formed according to the method 3000 for preparing the semiconductor device Figure 1 , Figure 3 Based on this, the methods 2000 and 3000 for preparing the semiconductor device have the same beneficial effects as the semiconductor device 1000, which will not be described in detail herein.

[0148] The following will be combined Figures 17 to 22 The specific process of each step of the above-mentioned preparation method 3000 is described in detail.

[0149] Step S21

[0150] Fig.18 It is a schematic cross-sectional view of a structure formed after a substrate 600 is formed according to a preparation method in one embodiment of the present application. Fig.19 It is a schematic cross-sectional view of a structure formed after forming the first opening 13 according to a preparation method in one embodiment of the present application. Fig. 20 It is a cross-sectional schematic diagram of a structure formed after forming a source electrode 320 and a drain electrode 330 according to a preparation method in one embodiment of the present application. Fig.21 It is a schematic cross-sectional view of a structure formed after forming a gate dielectric layer 350 according to a preparation method in one embodiment of the present application. Fig. 22 It is a schematic cross-sectional view of a structure formed after forming a gate 310 according to a preparation method in one embodiment of the present application.

[0151] like Figures 17 to 22 As shown, step S21 of forming a transistor in a substrate may, for example, include: forming a substrate 600 , wherein the substrate 600 includes an isolation layer 11 ; and forming a transistor 300 in the isolation layer 11 .

[0152] Specifically, in one embodiment of the present application, the method 3000 for preparing a semiconductor device further includes: forming a source line 400 (see FIG. 4 ) connecting a plurality of source contact structures 410 in the substrate 600. Figure 1 and Figure 3 ), wherein the source line extends in a wavy shape in a direction 400 perpendicular to the z direction.

[0153] In addition, in one embodiment of the present application, the method 3000 for preparing a semiconductor device further includes: forming a source line 400 (see FIG. 4 ) connecting a plurality of source contact structures 410 in the substrate 600. Figure 1 and Figure 3 ), and forming a bit line 500 (see Figure 1 and Fig.18 ). Optionally, Figure 1 As shown, in the xy plane, the projection of the source line 400 intersects the projection of the bit line 500. For example, in the xy plane, the projection of the source line 400 is perpendicular to the projection of the bit line 500.

[0154] In addition, in one embodiment of the present application, forming the transistor 300 may include: in the isolation layer 11 of the substrate 600, arranging a source contact structure 410 and a drain contact structure 510 in a direction perpendicular to the z direction; forming a second opening 13 penetrating the isolation layer 11 along the z direction between the source contact structure 410 and the drain contact structure 510; expanding the second opening 13 to remove a portion of the isolation layer 11, wherein the removed portion of the isolation layer 11 is located between the second opening 13 and the source contact structure 510 and between the second opening 13 and the drain contact structure. The structure 510 is formed between the transistors, thereby forming an enlarged second opening 14; in the enlarged portion of the enlarged second opening 14, a source 320, a channel 340 and a drain 330 of the transistor are formed, wherein the source 320 is connected to the source contact structure 410, the drain 330 is connected to the drain contact structure 510, and the channel 340 is located between the source 320 and the drain 330; a gate dielectric layer 350 is formed that at least covers the source 320, the channel 340 and the drain 330; and the gate 310 is filled in the remaining space of the enlarged second opening 14.

[0155] Optionally, the source 320 , the channel 340 , and the drain 330 are formed as a closed ring structure in the xy plane.

[0156] Step S22

[0157] refer to Figure 1 , Figure 3 as well as Fig. 22 , step S22 alternately stacking first electrode layers and dielectric layers on the substrate to form a stacked structure may, for example, include: alternately stacking first electrode layers 120 and dielectric layers 130 along the z direction on the first side of the substrate through one or more thin film deposition processes to form a stacked structure 100, wherein the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present application.

[0158] Step S23

[0159] refer to Figure 1 , Figure 3 as well as Fig. 22 In step S23, a first opening extending along the stacking direction of the stacked structure is formed, and a storage function layer and a second electrode layer are sequentially formed on the inner wall of the first opening, wherein the second electrode layer is connected to the gate of the transistor, for example, including: forming a first opening (not shown) extending along the z direction; and sequentially forming a storage function layer and a second electrode layer on the inner wall of the first opening.

[0160] Specifically, in one embodiment of the present application, the first opening can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to form a first opening in the stacked structure 100, wherein the first opening extends to the gate 310. In other words, the gate 310 is a stop layer for the process of forming the first opening. By setting the gate 310 as a stop layer, the etching of the first opening can be stopped at the gate 310 during the process of forming the first opening by the etching process, thereby reducing the probability of over-etching of the first opening and reducing the occurrence of the first opening penetrating into the substrate. On the one hand, the morphology of the first opening is improved, for example, multiple first openings have the same extension length in the z direction; on the other hand, the leakage problem caused by the electrode layer penetrating into the substrate in the subsequently formed semiconductor device can be reduced. Both aspects contribute to improving the electrical performance of the finally formed semiconductor device.

[0161] After the first opening is formed, a storage function layer 220 and a second electrode layer 210 may be sequentially formed on the sidewall of the first opening by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0162] Optionally, the material forming the storage function layer 220 includes a ferroelectric material or an antiferroelectric material. For example, hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si a (HfO2)b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b ) or zirconium oxide (ZrO), etc., where a and b are positive numbers.

[0163] Fig.23 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0164] like Fig.23 As shown, at least one embodiment of the present application further provides a storage system 30000. The storage system 30000 may include a controller 32200 and at least one semiconductor device 32100. The semiconductor device 32100 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it.

[0165] Specifically, the memory system 30000 may include a controller 32200 and a memory 32300. As an alternative, the semiconductor device 32100 may be a part of the memory 32300; as another alternative, the semiconductor device 32100 may be the memory 3230.

[0166] In addition, the storage system 30000 also includes a host 31000. Information can be exchanged between the host 31000 and the controller 32200. The controller 32200 is coupled to the semiconductor device 32100 through a channel CH to control the semiconductor device 32100 to store data. The semiconductor device 32100 can receive a command CMD and an address ADDR from the controller 32200 through the channel CH and access a region selected from the memory cell array in response to the address. In other words, the semiconductor device 32100 can perform an internal operation corresponding to the command on the region selected by the address.

[0167] In some embodiments, the storage system 30000 may be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor device provided in the present application because it is provided with the semiconductor device provided in the present application, and no further description is given here.

[0168] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A semiconductor device, characterized in that: include: A laminated structure comprising first electrode layers and dielectric layers alternately stacked, wherein the first electrode layers extend in a direction perpendicular to a stacking direction; a storage column extending in the stacked structure along the stacking direction and including, from the inside to the outside, a second electrode layer and a storage function layer; and A transistor is arranged on one side of the stacked structure, wherein a gate of the transistor is connected to the second electrode layer.

2. The semiconductor device according to claim 1, wherein The transistor further comprises a source, a channel and a drain arranged in a plane perpendicular to the stacking direction, Wherein, the channel is located between the source and the drain.

3. The semiconductor device according to claim 2, wherein: In a plane perpendicular to the stacking direction, the source, the channel and the drain are arranged around the gate to form a closed ring structure. Wherein, a gate dielectric layer is arranged between the gate and the annular structure.

4. The semiconductor device according to claim 2, wherein: The semiconductor device further comprises: a source contact structure connected to the source, and a drain contact structure connected to the drain, Wherein, in a plane perpendicular to the stacking direction, the source contact structure and the drain contact structure are respectively located on two opposite sides of the transistor.

5. The semiconductor device according to claim 4, wherein: The semiconductor material layer included in the source contact structure and the source electrode contain the same type of doping elements, wherein the doping concentration of the doping element of the source contact structure is greater than the doping concentration of the doping element of the source electrode; and / or The semiconductor material layer included in the drain contact structure and the drain electrode contain the same type of doping elements, wherein the doping concentration of the doping element of the drain contact structure is greater than the doping concentration of the doping element of the drain electrode.

6. The semiconductor device according to claim 4, wherein: The semiconductor device further comprises: a source line connecting a plurality of the source contact structures, and a bit line connecting a plurality of the drain contact structures, Wherein, in a plane perpendicular to the stacking direction, the projection of the source line intersects with the projection of the bit line.

7. The semiconductor device according to claim 6, wherein: In a plane perpendicular to the stacking direction, the bit line extends along a first direction; as well as The source contact structure and the drain contact structure are respectively located on two opposite sides of the transistor in the first direction.

8. The semiconductor device according to claim 6, wherein: The source line extends in a wave shape in a direction perpendicular to the stacking direction.

9. The semiconductor device according to claim 1, wherein: The laminate structure further comprises a spacer layer, Wherein, the first electrode layer and the dielectric layer are located on a first side of the spacer layer, and the transistor is located on a second side of the spacer layer opposite to the first side; and In the stacking direction, the gate extends into the stacked structure to a depth that is less than or equal to the thickness of the spacer layer.

10. The semiconductor device according to any one of claims 1 to 8, wherein: The storage function layer includes a ferroelectric material layer.

11. A method for manufacturing a semiconductor device, characterized in that: include: Alternatingly stacking first electrode layers and dielectric layers on one side of the substrate to form a stacked structure; forming a first opening extending along the stacking direction of the stacked structure, and sequentially forming an initial storage function layer and an initial second electrode layer on the inner wall and bottom surface of the first opening; Removing a portion of the substrate from the other side opposite to the one side to form a second opening, wherein the second opening exposes a portion of the initial storage function layer; removing part of the initial storage function layer and part of the initial second electrode layer through the second opening to form a storage function layer and a second electrode layer; as well as A gate of a transistor connected to the second electrode layer is formed in the second opening.

12. The method according to claim 11, wherein: The substrate includes an isolation layer and a plurality of source contact structures spaced apart in the isolation layer, and the method further includes: The process of forming the first opening is stopped at the isolation layer.

13. The method according to claim 12, wherein: The method further includes forming the transistor, wherein forming the transistor includes: Enlarging the second opening along a direction perpendicular to the stacking direction to remove at least a portion of the isolation layer between the second opening and the source contact structure; forming a source, a channel and a drain of the transistor in an enlarged portion of the enlarged second opening, wherein the source is connected to the source contact structure, and the channel is located between the source and the drain; forming a gate dielectric layer covering at least the source, the channel and the drain; and The gate is filled in the remaining space of the enlarged second opening.

14. The method according to claim 13, wherein: The source, the channel, and the drain are formed into a closed ring structure in a plane perpendicular to the stacking direction.

15. The method according to claim 11, wherein: The method further includes forming the substrate, wherein forming the substrate includes: Disposing a plurality of source contact structures at intervals in the isolation layer; and forming a source line connecting a plurality of said source contact structures, Wherein, the source line extends in a wave shape in a direction perpendicular to the stacking direction.

16. The method according to claim 15, wherein: After forming the gate, the method further includes: forming a drain contact structure in the spacer layer, Wherein, in a plane perpendicular to the stacking direction, the source contact structure and the drain contact structure are respectively located on two opposite sides of the corresponding transistor.

17. The method according to claim 16, wherein: The method further comprises: forming a bit line connecting a plurality of the drain contact structures, Wherein, in a plane perpendicular to the stacking direction, the projection of the source line intersects with the projection of the bit line.

18. The method according to claim 11, wherein: The stacked structure further includes a spacer layer, the first electrode layer and the dielectric layer are located above the spacer layer, and removing a portion of the initial storage function layer and a portion of the initial second electrode layer through the second opening includes: The portions of the initial storage function layer and the initial second electrode layer located in the spacer layer are removed.

19. The method according to any one of claims 11 to 18, wherein: The method further comprises: The initial storage function layer is formed by using ferroelectric material.

20. A method for manufacturing a semiconductor device, characterized in that: include: forming a transistor in a substrate; Alternatingly stacking first electrode layers and dielectric layers on a substrate to form a stacked structure; as well as forming a first opening extending along the stacking direction of the stacked structure, and sequentially forming a storage function layer and a second electrode layer on the inner wall of the first opening, Wherein, the second electrode layer is connected to the gate of the transistor.

21. The method according to claim 20, wherein: The method further comprises: The process of forming the first opening is stopped at the gate.

22. The method according to claim 20, wherein: Forming the transistor includes: In the isolation layer of the substrate, a source contact structure and a drain contact structure are arranged at intervals in a direction perpendicular to the stacking direction; Between the source contact structure and the drain contact structure, a second opening is formed that penetrates the isolation layer along the stacking direction; Enlarging the second opening to remove a portion of the isolation layer, wherein the removed portion of the isolation layer is located between the second opening and the source contact structure and between the second opening and the drain contact structure; In the enlarged portion of the enlarged second opening, a source, a channel and a drain of the transistor are formed, wherein the source is connected to the source contact structure, the drain is connected to the drain contact structure, and the channel is located between the source and the drain; forming a gate dielectric layer covering at least the source, the channel and the drain; and The gate is filled in the remaining space of the enlarged second opening.

23. The method according to claim 22, wherein: The source, the channel, and the drain are formed into a closed ring structure in a plane perpendicular to the stacking direction.

24. The method according to claim 22, wherein: The method further comprises: forming a source line connecting a plurality of the source contact structures in the substrate, Wherein, the source line extends in a wave shape in a direction perpendicular to the stacking direction.

25. The method according to claim 22, wherein: The method further comprises: forming a source line connecting a plurality of the source contact structures in the substrate, forming a bit line connecting a plurality of the drain contact structures in the substrate, Wherein, in a plane perpendicular to the stacking direction, the projection of the source line intersects with the projection of the bit line.

26. The method according to any one of claims 22 to 25, wherein: The method further comprises: The storage function layer is formed by using ferroelectric material.

27. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 10; as well as The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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