Laminated hafnium-zirconium-oxygen multi-bit ferroelectric storage unit and preparation method thereof

Abstract

The invention discloses a laminated hafnium-zirconium-oxygen multi-bit ferroelectric memory cell and a preparation method thereof, and the memory cell comprises a first electrode, a second electrode, and a multi-state ferroelectric laminated layer disposed between the first electrode and the second electrode. The multi-state ferroelectric lamination layer comprises hafnium oxide layers and zirconium oxide layers which are sequentially and alternately laminated, and the multi-state ferroelectric lamination layer realizes multi-bit information storage through a multi-state polarization state. The hafnium zirconium oxide ferroelectric lamination layer (polymorphic ferroelectric lamination layer) has stable polymorphisms for storing multi-bit data, and can be quickly switched among different storage states; the electrode layer is used for providing electric field driving force and regulating stress and oxygen vacancy space distribution of the electrode-ferroelectric interface layer at the same time; and meanwhile, the stability of the polarization state and the driving electric field intensity of each bit polarization state are optimized. According to the regulation and control method, the lattice stability and the polarization stability can be optimized, and the rewriting performance and the long-term stability of the memory are improved.

Description

Technical Field

[0001] The present invention relates to the field of novel storage materials and microelectronic devices, and in particular to a stacked hafnium zirconium oxygen multi-bit ferroelectric storage unit and a preparation method thereof. Background Art

[0002] Ferroelectric random access memory (FeRAM) is a non-volatile storage material with the characteristics of high-speed read and write capabilities, low operating voltage, high integration and low power consumption. It is regarded as one of the effective solutions to replace DRAM in the future.

[0003] By using ferroelectric thin films to replace traditional DRAM dielectric materials, multiple stable states (such as "00", "01", "10", "11") can be achieved by using different polarization directions of ferroelectric materials. Increasing the number of stable storage states from two to multiple allows FeRAM to have both the fast response speed of DRAM and the high storage density of NAND. Since the ferroelectric polarization strength can change with voltage, incompletely polarized multi-state storage can be achieved using a voltage lower than the complete polarization flip.

[0004] At the same time, it needs to meet the requirements of DRAM's low-voltage reading and writing and the durability equivalent to DRAM. However, due to the defects and instability in the hafnium-based ferroelectric film, the polarization amount of the ferroelectric film with continuous polarization at a fixed voltage will decay as the number of flips increases due to the instability and randomness of the defects, making it difficult to form a high-durability multi-stable polarization.

[0005] Therefore, it is an urgent goal to introduce a method to control the phase composition (ferroelectric phase O-phase, antiferroelectric phase T-phase) of hafnium zirconium oxide thin films so that ferroelectric capacitors can form multiple steady-state polarization current peaks to achieve multi-stable storage. Summary of the invention

[0006] In view of the above defects and shortcomings of the prior art, the present invention aims to provide a novel ultra-low power consumption multi-state lossless reading ferroelectric memcapacitor and a preparation method thereof to solve the above technical problems.

[0007] To achieve the above objectives, the present invention provides a stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell, comprising:

[0008] A first electrode and a second electrode, with a multi-state ferroelectric stack disposed therebetween;

[0009] The multi-state ferroelectric stack comprises hafnium oxide layers and zirconium oxide layers which are alternately stacked in sequence, and the multi-state ferroelectric stack realizes multi-bit information storage through multi-state polarization states.

[0010] A further improvement of the present invention is that the thickness of the first electrode and the second electrode is 2-50 nm.

[0011] A further improvement of the present invention is that the material of the first electrode and the second electrode is any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, chromium, or any one of the alloys, nitride oxides, and metal oxide semiconductors of the above materials.

[0012] A further improvement of the present invention is that the thickness of the polymorphic ferroelectric stack is 1.5 to 30 nm.

[0013] A further improvement of the present invention is that in the polymorphic ferroelectric stack, the single layer thickness of the hafnium oxide layer and the zirconium oxide layer is 0.2-2 nm, and the stacking ratio of the two is 10-0.1.

[0014] A further improvement of the present invention is that an insulating insertion regulating layer is provided between the ferroelectric layer and the first electrode, or between the ferroelectric layer and the second electrode, or in the ferroelectric layer; the insulating insertion regulating layer is made of aluminum oxide or titanium oxide; and its thickness is 0.8nm to 1.2nm.

[0015] The present invention also provides a method for preparing a stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell, which is used to prepare the stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell, and comprises the following steps:

[0016] S1: growing an insulating material on the surface of the semiconductor as an insulating dielectric layer. In this step, the insulating material can be grown by sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy.

[0017] S2: preparing a first electrode on the surface of the insulating dielectric layer; in this step, a conductive medium is deposited as the first electrode by spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation.

[0018] S3: sequentially prepare the layers of the polymorphic ferroelectric stack on the surface of the first electrode to form a stacked structure; in this step, the polymorphic ferroelectric stack is prepared by sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy.

[0019] S4: preparing a second electrode on the polymorphic ferroelectric stack; in this method, the conductive medium can be deposited as the second electrode by spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation.

[0020] S5: performing high temperature annealing treatment on the device, so that the material of the polymorphic ferroelectric stack undergoes a phase transformation under the combined action of the thin film stack and the electrode to form a mixed crystal of a ferroelectric phase, an antiferroelectric phase, and a non-ferroelectric phase.

[0021] A further improvement of the present invention is that in step S5, the temperature of the high temperature annealing treatment is 350-650°C.

[0022] The combined effects of stacking ratio, electrode stress, and high-temperature phase regulation can adjust the stability of polymorphism and the memory write voltage point to meet the needs of the driving circuit; the method has more uniform spatial position of phase mixing and less defect aggregation, thereby effectively reducing the operating voltage and improving the durability of the memory.

[0023] The advantages of the present invention are as follows:

[0024] (1) Hafnium zirconium oxygen ferroelectric stack (polymorphic ferroelectric stack) has a stable polymorphism for storing multi-bit data and can quickly switch between different storage states; the electrode layer is used to provide an electric field driving force and simultaneously regulate the stress and the oxygen vacancy spatial distribution of the electrode-ferroelectric interface layer; and optimize the stability of the polarization state and the driving electric field strength of each bit polarization state. This regulation method can optimize the lattice stability and polarization stability, and improve the rewrite performance and long-term stability of the memory. In addition, the distribution and concentration of the elements can be controlled by doping elements and the joint action of the electrodes to adjust the material phase composition and the distribution of oxygen vacancies in the ferroelectric layer;

[0025] (2) Data durability can reach 1E11, which is close to the durability index of current DRAM.

[0026] (3) Clear multi-bit polymorphic storage can be achieved.

[0027] (4) It is fully compatible with the current CMOS process and does not require the introduction of additional doping elements and process equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic structural diagram of a ferroelectric storage capacitor provided in an embodiment of the present application;

[0029] Figure 2 It is a schematic diagram of the current continuous polarization multi-state problem;

[0030] Figure 3 A schematic structural diagram of a device structure provided in an embodiment of the present application;

[0031] Figure 4 Schematic polarization current and polarization state of the device provided in the embodiment of the present application;

[0032] Figure 5 The schematic principle of the device provided in the embodiment of the present application;

[0033] Figure 6 The following are illustrative results of the device provided in the embodiments of the present application.

[0034] Wherein, the accompanying drawings are marked as follows:

[0035] 1-first electrode, 2-second electrode, 3-multi-state ferroelectric stack; 31-hafnium oxide layer, 32-zirconium oxide layer. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0037] While some exemplary embodiments of the present invention have been described for the purpose of illustration, it should be understood that the present invention may be implemented in other ways not specifically shown in the drawings.

[0038] like Figure 1 As shown, the device structure of the stacked hafnium zirconium oxygen multi-bit ferroelectric memory unit provided in this embodiment includes: a sandwich structure formed by a first electrode 1, a second electrode 2, and a polymorphic ferroelectric stack 3. The above-mentioned sandwich structure can be a metal electrode-ferroelectric film-metal electrode (MFM) structure but is not limited thereto. In some embodiments, the electrode 1 and the electrode 2 can also be made of materials other than metals, such as metal oxide semiconductors. In this embodiment, the material of the two electrodes is not limited.

[0039] In the present application, the polymorphic ferroelectric stack 3 includes alternately stacked hafnium oxide layers 31 and zirconium oxide layers 32. The ferroelectric material of the polymorphic ferroelectric stack is a stack of hafnium oxide (HfO2) and zirconium oxide (ZrO2), thereby ensuring the compatibility of the ferroelectric device with the CMOS process and the scalability of the size.

[0040] Since polymorphic storage plays a positive role in reducing memory power consumption and improving integration, the remnant polarization (Pr) of most hafnium oxide-based ferroelectric materials increases linearly with the increase of the electric field when the applied electric field is greater than the coercive field (reference Figure 2-01), this phenomenon can be polarized in multiple states. However, due to the bottom electrode and post-annealing treatment, the metal electrode takes away the oxygen of the ferroelectric film (oxygen scavenging), thus generating a certain number of oxygen vacancies at the metal-ferroelectric layer interface, causing a built-in electric field, which initially pins part of the ferroelectric dipole (ferroelectric dipole), and even causes the opposite polarization direction. Due to the instability of oxygen vacancy pinning and the characteristics of oxygen vacancies being easy to move under electric fields, and oxygen vacancies also play a role in stabilizing the ferroelectric phase. When oxygen vacancies begin to diffuse and transfer to the ferroelectric film bulk phase, they can transform part of the non-ferroelectric phase (M-phase) into the ferroelectric phase (O-phase), further increasing Pr (reference Figure 2 -02). As the electric field continues to circulate, oxygen continues to be lost in the ferroelectric film, the electrode interface is continuously oxidized, more defects and oxygen vacancies begin to form, and the interface begins to divide the applied electric field, causing the electric field on the ferroelectric layer to decrease. At the same time, the charges and vacancies captured by the defects also begin to pin some ferroelectric dipoles to prevent them from flipping, causing Pr to decrease. This is "fatigue" (reference Figure 2 -02). Therefore, using linear incomplete polarization to perform polymorphic storage will cause polymorphic logic ambiguity during the cycle due to the above reasons (refer to Figure 2 -02).

[0041] The ferroelectric device provided in the embodiment of the present application changes the solid solution structure of most of the hafnium-based ferroelectrics in the ferroelectric layer 3, and utilizes the stacked layers of hafnium oxide and zirconium oxide (refer to Figure 3 ) This is due to the local regulation of the zirconium component in the stacking space. After annealing, the structure can generate the above-mentioned O-phase and antiferroelectric phase T-phase in the ferroelectric layer 3. The O-phase and antiferroelectric phase T-phase coexist in the ferroelectric layer 3 (refer to Figure 4 ).

[0042] The O / T-phase uniform hybrid structure is conducive to the synergistic effect of the internal electric field and the polarization dipole, and multiple stable Pr states appear with different external strong electric field strengths. Figure 3 As shown, when the FE (ferroelectric phase) polarization reaches the strongest (storage state 1), the AFE (antiferroelectric) that originally could not maintain the polarization state when the power is off can also maintain the polarization state, so that the polarization intensity reaches the maximum. Similarly, when the O-phase polarization weakens, the polarization of the AFE part also weakens accordingly, forming a relatively weak storage state 2. When driven by electric fields with different polarization directions, this configuration can form two other storage states 3 and 4 with opposite polarization directions to storage states 1 and 2.

[0043] Different from the current mainstream O-phase dominated iron electrode memory, this configuration will have multiple stable polarization current peaks during the polarization reversal process (reference Figure 4 -01), corresponding to this, Pr (reference Figure 4 -02) is the maximum in storage states 1 and 4, corresponding to the sum of polarizations 1, 2 or 3, 4, respectively, while storage states 3 and 4 are incomplete polarization states. Since each polarization state needs to be driven at a voltage with a relatively large interval, the storage state caused by each ferroelectric polarization is logically more stable than the linear polarization device, which is conducive to maintaining a stable polarization window during the long-term flipping process.

[0044] In this embodiment, the stable multi-bit state is to use the O-phase in the stack to first generate a first polarization current peak (semi-polarization state) with a relatively small polarization voltage. When the electric field continues to increase and reaches the polarization condition of the T-phase in the stack, another polarization current peak will appear. At this time, the state of the ferroelectric layer 3 can be regarded as a full polarization state. The semi-polarization state and the full polarization state in both positive and negative directions are placed in the memory to generate four stable dual-bit states.

[0045] It should be noted that the difference between the two polarization electric field magnitudes is caused by the polarization electric field strength required by the O / T-phase itself. Therefore, the O / T-phase mixed ferroelectric layer 3 will naturally split into two polarization states in different electric field phases.

[0046] It is understood by those skilled in the art that the polarization state of the antiferroelectric layer cannot be maintained when the electric field is removed. Therefore, a pure antiferroelectric layer is not used for nonvolatile storage. Figure 5 As shown in the present configuration, when full polarization is completed, semi-polarization in the O-phase will generate charge pinning in the electrode. Even after the external electric field is removed, part of the polarization electric field generated by the O-phase polarization can still be maintained in the capacitor. When the electric field of the O-phase is greater than the depolarization field of the T-phase, the polarization charge in the fully polarized state can still be maintained when the electric field is 0, thereby realizing two storage states in the positive and negative directions.

[0047] In some embodiments, an insulating insertion regulating layer is provided between the ferroelectric layer and the first electrode, or between the ferroelectric layer and the second electrode, or in the ferroelectric layer; the insulating insertion regulating layer is made of aluminum oxide or titanium oxide; and its thickness is 0.8nm to 1.2nm. The insulating insertion regulating layer can improve leakage, enhance device reliability, and reduce device power consumption; it has important value for industrial applications.

[0048] In some embodiments, a doped layer is inserted into the polymorphic ferroelectric stack; in the process of preparing the stacked polymorphic ferroelectric stack, the doped material is prepared as a separate layer in the polymorphic ferroelectric stack, and in the high-temperature annealing stage, the doped material diffuses into other layers of the polymorphic ferroelectric stack to form a solid solution. The distribution and concentration of the doped elements are controlled by the combined action of the electrodes to adjust the distribution of the material phase composition and the oxygen vacancies in the ferroelectric layer. By changing the concentration and spatial position of the doping elements, the phase composition and stability can be regulated, thereby meeting the device parameter adjustment requirements in practical applications. Optional doping elements include: Group II elements calcium (Ca), strontium (Sr) or barium (Ba); or Group III elements scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga) and indium (In); or doping lanthanide elements lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu).

[0049] On the other hand, electrode stress also plays a great role in the proportion and durability of the phase components. The stacking ratio, thickness and sequence of the ferroelectric layer 3 in the arrangement will be adjusted accordingly according to the electrode.

[0050] It should be noted that this setting has more outstanding advantages than other methods of regulating O / T phase composition, such as being fully compatible with current CMOS processes and not requiring the introduction of additional doping elements and process equipment.

[0051] On the other hand, this configuration can be thinned to 5nm and still maintain higher Pr and lower operating voltage, which can achieve the characteristics of high integration and low power consumption.

[0052] On the other hand, Figure 6 As shown, the durability of the device in this embodiment can reach 1E11, which is close to the durability index of current DRAM.

[0053] On the other hand, the device uniformity of this configuration can meet the requirements of the array.

[0054] In a specific embodiment:

[0055] like Figure 3 As shown, this embodiment provides a stacked hafnium zirconium oxygen multi-bit ferroelectric memory unit, which includes: a first electrode 1, a second electrode 2, and a polymorphic ferroelectric stack 3 is arranged between the two. The polymorphic ferroelectric stack 3 includes hafnium oxide layers 31 and zirconium oxide layers 32 alternately stacked in sequence. The polymorphic ferroelectric stack realizes multi-bit information storage through multi-state polarization states. The material of the first electrode is copper, and the thickness is 10nm; the material of the second electrode is copper, and the thickness of the second electrode is 10nm. The thickness of the hafnium oxide layer 31 and the zirconium oxide layer 32 are both 1nm.

[0056] The method for preparing the device comprises the following steps:

[0057] S1: growing insulating material as an insulating dielectric layer on the surface of the semiconductor by chemical vapor deposition;

[0058] S2: preparing a first electrode on the surface of the insulating dielectric layer by magnetron sputtering;

[0059] S3: sequentially preparing layers of the polymorphic ferroelectric stack by chemical vapor deposition on the surface of the first electrode to form a stacked structure;

[0060] S4: preparing a second electrode on the multi-state ferroelectric stack by magnetron sputtering;

[0061] S5: Perform high temperature annealing on the device, so that the material of the polymorphic ferroelectric stack undergoes phase transformation to form a mixed crystal of ferroelectric phase, antiferroelectric phase and non-ferroelectric phase under the joint action of the thin film stack and the electrode. In step S5, the temperature of the high temperature annealing is 350-650°C.

[0062] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell, characterized in that include: A first electrode and a second electrode, with a multi-state ferroelectric stack disposed therebetween; The multi-state ferroelectric stack comprises hafnium oxide layers and zirconium oxide layers which are alternately stacked in sequence, and the multi-state ferroelectric stack realizes multi-bit information storage through multi-state polarization states.

2. The stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell according to claim 1, characterized in that: The thickness of the first electrode and the second electrode is 2-50 nm.

3. The stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell according to claim 1, characterized in that: The material of the first electrode and the second electrode is any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, and chromium, or any one of alloys, nitride oxides, and metal oxide semiconductors of the above materials.

4. The stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell according to claim 1, characterized in that: The thickness of the multi-state ferroelectric stack is 1.5-30 nm.

5. The stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell according to claim 1, characterized in that: In the polymorphic ferroelectric stack, the single layer thickness of the hafnium oxide layer and the zirconium oxide layer is 0.2-2 nm, and the stacking ratio of the two is 10-0.

1.

6. The stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell according to claim 1, characterized in that: An insulating insertion regulating layer is arranged between the ferroelectric layer and the first electrode, or between the ferroelectric layer and the second electrode, or in the ferroelectric layer; the insulating insertion regulating layer is made of aluminum oxide or titanium oxide; and its thickness is 0.8nm to 1.2nm.

7. A method for preparing a stacked hafnium zirconium oxide multi-bit ferroelectric memory cell, used for preparing the stacked hafnium zirconium oxide multi-bit ferroelectric memory cell according to any one of claims 1 to 6, characterized in that The following steps are involved: S1: growing insulating material on the surface of the semiconductor as an insulating dielectric layer; S2: preparing a first electrode on the surface of the insulating dielectric layer; S3: sequentially preparing layers of a multi-state ferroelectric stack on the surface of the first electrode to form a stacked structure; S4: preparing a second electrode on the multi-state ferroelectric stack; S5: performing high temperature annealing treatment on the device, so that the material of the polymorphic ferroelectric stack undergoes a phase transformation under the combined action of the thin film stack and the electrode to form a mixed crystal of a ferroelectric phase, an antiferroelectric phase, and a non-ferroelectric phase.

8. The method for preparing a stacked hafnium zirconium oxygen multi-bit ferroelectric memory cell according to claim 7, characterized in that: In step S5, the temperature of the high temperature annealing treatment is 350-650°C.

Images