A method for manufacturing a silicon carbide trench gate MOSFET power device

Abstract

The application discloses a preparation method of a silicon carbide trench gate MOSFET power device and belongs to the technical field of semiconductor devices, and comprises the following steps: one, forming an N-Drift region and an N-CSL layer on an N-type substrate; two, arranging a P+ transition region and a P+ source contact region on the N-CSL layer; three, sequentially forming a P-well region and an N+ active region on the N-CSL layer; four, etching a gate trench; five, depositing a field oxide layer; six, etching the field oxide layer to reserve only the field oxide layer outside the P+ transition region; seven, depositing polysilicon; eight, etching the polysilicon to reserve only the polysilicon in the gate trench, directly above the P+ source contact region and directly above the P+ transition region; nine, arranging a source through hole and a source contact; eleven, arranging a gate through hole and a gate contact; twelve, arranging a source electrode, a gate electrode and a drain electrode. The method solves the technical problems of high manufacturing difficulty, high cost and high specific on-resistance in the prior art.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and particularly relates to a preparation method of a silicon carbide trench gate MOSFET power device. BACKGROUND

[0002] Semiconductor power devices are the core elements for completing efficient conversion, control and regulation of electric energy. In recent years, silicon carbide power devices can effectively meet the requirements of high efficiency, miniaturization and light weight of electronic power systems due to their excellent high-voltage resistance, high-temperature resistance and low loss, and have obvious advantages in the fields of new energy vehicles, photovoltaic power generation, rail transit and smart grid. Therefore, the research and application of power devices based on silicon carbide materials have become one of the frontiers and hotspots of semiconductor power device research.

[0003] At present, silicon carbide metal oxide semiconductor field effect transistors are mainly divided into planar gate structures and trench gate structures, and the trench gate metal oxide semiconductor field effect transistor is further divided into single-trench structures and double-trench structures. The silicon carbide power device with a planar gate structure is limited in practical application due to its low channel carrier mobility and large device cell size, which leads to excessive on-resistance. The silicon carbide power device with a trench gate structure becomes a mainstream direction of current silicon carbide power device research because it adopts a vertical gate structure, reduces the cell size area and increases the channel carrier mobility.

[0004] For the above-mentioned trench gate type silicon carbide power device, the patent document with the publication number CN118538763A discloses a trench gate silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method thereof, which comprises:

[0005] The P+ substrate is provided with an N+ buffer layer on the front surface thereof; the N+ buffer layer is provided with an N- drift region on the front surface thereof; an N-type CSL layer is formed on the upper surface of the N- drift region; the N-type CSL layer is provided with a P-base region on the upper surface thereof; the P-base region is provided with a P-channel region at the central position thereof; the upper surfaces of the P-base region and the P-channel region are provided with an N+ emitter region; the N+ emitter region and the P-base region are provided with a P+ contact region at the edge position thereof; the N+ emitter region is provided with a deep trench at the central position thereof; the deep trench is provided with a P+ shielding region at the bottom thereof; and the deep trench above the P+ shielding region is provided with a polysilicon gate.

[0006] Although this method can prepare a device that meets high-voltage resistance and high-gate oxide reliability, the technology still has the following technical problems:

[0007] 1. Because the distance between the bottom of the gate trench and the P-base region is very close, a JFET effect will occur between the two P regions during conduction, narrowing the conductive channel, resulting in a decrease in the on-current, thereby increasing the on-resistance and affecting the device's specific on-resistance.

[0008] 2. When preparing devices, this technology requires extremely high precision in etching the gate polysilicon in order to ensure isolation between the gate and the source, and to ensure that the source contact covers the top of the N+ without excessively increasing the width of the device. This is because if the left and right errors of the etching are large, not only will the source contact area above the N+ be insufficient, making the device unable to conduct, but it will also cause the gate and source to be connected, resulting in device failure.

[0009] 3. This technology uses a double trench and deep trench structure, which increases the difficulty of trench etching and the process cost.

[0010] Therefore, it is necessary to provide a new preparation method to solve the above technical problems. Summary of the Invention

[0011] The purpose of the present invention is to overcome the above-mentioned problems existing in the prior art and provide a method for preparing a silicon carbide trench gate MOSFET power device. The method solves the technical problems existing in the prior art, such as the difficulty of the manufacturing process, the high production cost, and the high specific on-resistance of the prepared device.

[0012] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0013] A method for preparing a silicon carbide trench gate MOSFET power device comprises the following steps:

[0014] Step 1: forming a doped N-Drift region and an N-CSL layer in sequence on a heavily doped N-type substrate;

[0015] Step 2: Setting a P+ transition region around the N-CSL layer, and evenly setting multiple P+ source contact regions on the N-CSL layer. The multiple P+ source contact regions divide the N-CSL layer into multiple blocks, and the multiple P+ source contact regions and the multiple N-CSL layers are alternately set in the P+ transition region;

[0016] Step 3: Use ion implantation to sequentially form the P-well region and N+ active region directly above each N-CSL layer, followed by annealing at high temperature to activate the impurities;

[0017] Step 4: Etching from the middle of each N+ active region downward to the upper part of the N-CSL layer to form a gate trench;

[0018] Step five: Field oxide layer is deposited by chemical vapor deposition method to cover P+ transition zone and the area within P+ transition zone;

[0019] Step six: Field oxide layer within P+ transition zone and the area within P+ transition zone is removed by photoetching, only field oxide layer outside P+ transition zone is reserved, then gate oxide layer is grown in the position where field oxide layer is removed;

[0020] Step seven: Polysilicon is deposited to cover field oxide layer and gate oxide layer;

[0021] Step eight: Excess polysilicon is removed by photoetching, only polysilicon within gate trench, directly above P+ source contact area and directly above P+ transition zone is reserved;

[0022] Step nine: ILD isolation layer is deposited by chemical vapor deposition method to cover polysilicon and the area between polysilicon;

[0023] Step ten: Gap is etched on ILD isolation layer above each P+ source contact area by dry photoetching, ILD isolation layer and polysilicon under the gap are removed by wet etching method to form source via, then Ni alloy is deposited in source via to form source contact;

[0024] Step eleven: Mask layer is deposited on ILD isolation layer, ILD isolation layer above field oxide layer is etched by photoetching to form gate via, then Ti alloy is deposited in gate via to form gate contact;

[0025] Step twelve: Metal layer is deposited to cover source contact and gate contact, glue is coated on metal layer, source electrode and gate electrode are formed by photoetching, finally metal is deposited under N-type substrate to form drain electrode, and the preparation is completed.

[0026] In step one, N-Drift zone on N-type substrate is formed by epitaxy process, N-CSL layer can be formed by epitaxy process or doped by high-energy ion implantation, and the doping concentration of N-type substrate is 10 19 ~ 10 20 cm -3 order of magnitude, the doping concentration of N-Drift zone is 10 14 ~ 10 16 cm -3 order of magnitude, and the doping concentration of N-CSL layer is 10 15 ~ 10 17 cm -3 order of magnitude.

[0027] In step two, the P+ transition region and the P+ source contact region are formed by first digging a groove on the N-CSL layer and then using high-energy injection, the P+ transition region is enclosed around the N-CSL layer in a head-to-tail manner, the width of the P+ transition region is 40-200 μm, and the width of the P+ source contact region is 0.3-1.2 μm; the depth of the P+ source contact region and the P+ transition region is 2.0-2.5 μm.

[0028] In step three, the doping concentration of the P-well region is 10 16 ~ 10 17 cm -3 order of magnitude, and the doping concentration of the N+ active region is 10 18 ~ 10 20 cm -3 order of magnitude.

[0029] In step four, after etching to obtain the gate trench, the gate trench is sequentially subjected to trench surface roughness treatment and trench corner treatment, and sacrificial oxidation treatment.

[0030] In step four, the width of the gate trench is 0.5-1.5 μm, and the depth is 0.9-1.5 μm.

[0031] In step five, the thickness of the field oxide layer above the P+ transition region is 1-2 μm.

[0032] In step six, the inner side of the P+ transition region refers to the side of the upper surface of the P+ transition region close to the N-CSL layer, and the outer side of the P+ transition region refers to the side of the upper surface of the P+ transition region away from the N-CSL layer, and the area of the inner side is smaller than that of the outer side.

[0033] In step eight, the polysilicon in the gate trench and the polysilicon directly above the P+ source contact region are both located below the gate oxide layer directly above the N+ active region.

[0034] In step ten, the two sides of the source via respectively extend to the adjacent two N-CSL layers, and the two sides of the source contact also respectively cover the adjacent two N-CSL layers.

[0035] The advantages of the present application are as follows:

[0036] 1. The present application adopts specific steps and has the following advantages, specifically,

[0037] The advantage of step one is that the heavily doped N-type substrate has the effect of reducing resistance when forming an ohmic contact on the back of the device; the N-Drift region has the effect of bearing higher forward voltage; and the N-CSL layer has the effects of increasing channel carrier mobility, reducing leakage current, and reducing specific on-resistance.

[0038] The step two has the advantages that: the P+ transition zone is arranged around the N-CSL layer, which is beneficial to reduce the electric field concentration at the edge of the chip, and the electric field peak is introduced from the surface into the body, thereby improving the breakdown voltage of the device; in addition, a plurality of P+ source contact zones are uniformly arranged on the N-CSL layer, and the N-CSL layer is divided into a plurality of blocks by the plurality of P+ source contact zones, and the plurality of P+ source contact zones and the plurality of N-CSL layers are alternately arranged in the P+ transition zone, which is beneficial to reduce the device area and improve the chip area utilization.

[0039] The step three has the advantages that: the lightly doped P-well zone is beneficial to form a conductive channel, and the heavily doped N+ active zone is beneficial to access the source electrode.

[0040] The step four has the advantages that: compared with the planar MOS, the trench type gate changes the conductive channel from horizontal to vertical, thereby improving the mobility of the carrier and reducing the size of the device cell.

[0041] The step five has the advantages that: the chemical vapor deposition method has the advantages of low deposition temperature (<500 DEG C) and fast deposition speed.

[0042] The step six has the advantages that: the grown gate oxide layer has excellent step coverage, high purity and uniformity.

[0043] The steps seven and eight have the advantages that: the effective isolation between the gate and the source is beneficial to be ensured.

[0044] The steps nine and ten have the advantages that: the deposition of the ILD isolation layer is beneficial to isolate the gate and the source, the dry etching of the gap and the wet etching of the residual polysilicon can ensure that the polysilicon can be completely removed.

[0045] The steps eleven and twelve have the advantages that: the gate via hole is beneficial to be formed, the deposited metal layer is vertically connected to the source contact and the gate contact respectively, even if there is an error in the horizontal direction during the etching of the polysilicon, the phenomenon that the device cannot be turned on will not occur, and the width of the device is reduced, and the specific on-resistance is reduced.

[0046] In summary, the specific process is adopted in the application, and when the device is prepared, only the shallow gate trench and the source shallow trench are needed to complete the preparation of the device, so that the manufacturing process is simplified, the production cost is reduced, the specific on-resistance of the device is reduced, and the effect is better.

[0047] 2, the specific doping concentration is adopted for the N-type substrate, the N-Drift region and the N-CSL layer, which has the effects of further reducing the resistance, improving the bearing of higher positive withstand voltage, reducing the leakage current and the specific on-resistance, otherwise, if the doping concentration exceeds the limited range, the corresponding performance of the device will be affected.

[0048] 3、The present application has the advantages of reducing the micro-trench effect of the trench, improving the reliability of the gate oxide and reducing the lattice damage after etching the gate trench, by sequentially performing trench surface roughness treatment and trench rounding treatment and sacrificial oxidation treatment on the gate trench.

[0049] 4、The present application defines specific widths and depths for the P+ transition region, the P+ source contact region and the gate trench, which comprehensively considers the cost and performance of the device, and can reduce the production cost of the device while ensuring the better performance of the device.

[0050] 5、The present application extends the two sides of the source via hole to the adjacent two N-CSL layers respectively, and covers the two sides of the source contact on the adjacent two N-CSL layers respectively. The advantage is that it can ensure the effective contact between the source and the N+ active region, so that the device maintains better conductivity. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 is a schematic diagram of the planar structure of step one;

[0052] Figure 2 is a schematic diagram of the planar structure of step two;

[0053] Figure 3 is a schematic diagram of the planar structure of step three;

[0054] Figure 4 is a schematic diagram of the planar structure of step four;

[0055] Figure 5 is a schematic diagram of the planar structure of step five;

[0056] Figure 6 is a schematic diagram of the planar structure of step six;

[0057] Figure 7 is a schematic diagram of the planar structure of step seven;

[0058] Figure 8 is a schematic diagram of the planar structure of step eight;

[0059] Figure 9 is a schematic diagram of the planar structure of step nine;

[0060] Figure 10 is a schematic diagram of the planar structure of step ten;

[0061] Figure 11 is a schematic diagram of the planar structure of step eleven;

[0062] Figure 12 is a schematic diagram of the planar structure of step twelve;

[0063] Figure 13 This is a simulation result diagram of the threshold voltage and specific on-resistance of the device prepared by the present invention;

[0064] Figures 14-16 The electric field simulation and data diagram of the bottom of the gate trench when a voltage of 1600V is applied to the gate of the present invention;

[0065] Figure 17 This is the injection energy diagram when the P+ transition region and P+ source contact region are directly set on the N-CSL layer without trenching;

[0066] Figure 18 This is the injection energy diagram when setting the P+ transition region and P+ source contact region by digging grooves on the N-CSL layer.

[0067] Markings in the figure are: 1-1, N-type substrate, 1-2, N-Drift region, 1-3, N-CSL layer, 1-4, P+ source contact region, 1-5, P+ transition region, 1-6, P-well region, 1-7, N+ active region, 1-8, gate trench, 1-9, field oxide layer, 1-10, gate oxide layer, 1-11, polysilicon, 1-12, ILD isolation layer, 1-13, source contact, 1-14, gate contact, 1-15, source electrode, 1-16, drain electrode, 1-17, gate electrode. DETAILED DESCRIPTION

[0068] Example 1

[0069] This embodiment provides a method for preparing a silicon carbide trench gate MOSFET power device, which includes the following steps:

[0070] Step 1: If Figure 1 As shown, a doped N-Drift region 1-2 and an N-CSL layer 1-3 are sequentially formed on the upper surface of a heavily doped N-type substrate 1-1. The N-Drift region 1-2 and the N-CSL layer 1-3 on the N-type substrate 1-1 can be doped and formed by an epitaxial process, wherein the N-CSL layer 1-3 can also be doped and formed by high-energy ion implantation, and the doping concentration of the N-CSL layer 1-3 is higher than the doping concentration of the N-Drift region 1-2.

[0071] Preferably, the doping concentration of the N-type substrate 1-1 is 10 19 cm -3 The doping concentration of N-Drift region 1-2 is 10 14 cm -3 The doping concentration of N-CSL layer 1-3 is 10 15 cm -3The specific doping concentration is adopted in the embodiment, which is beneficial to further reduce the resistance, improve the higher forward voltage withstand, reduce the leakage current and reduce the specific on-resistance.

[0072] Step two: as shown in the figure, P+ transition region 1-5 is arranged by grooving around N-CSL layer 1-3, and multiple P+ source contact regions 1-4 are uniformly arranged on N-CSL layer 1-3 by grooving, multiple P+ source contact regions 1-4 separate N-CSL layer 1-3 into multiple blocks, multiple P+ source contact regions 1-4 and multiple blocks of N-CSL layer 1-3 are alternately arranged in P+ transition region 1-5, and cell regions are formed between multiple P+ source contact regions 1-4. Figure 2

[0073] Preferably, P+ transition region 1-5 and P+ source contact region 1-4 are both formed by grooving on N-CSL layer 1-3 first and then high-energy injection, P+ transition region 1-5 encloses N-CSL layer 1-3 in a head-to-tail manner around N-CSL layer 1-3. In addition, the width of P+ transition region 1-5 is 40 μm, the width of P+ source contact region 1-4 is 0.3 μm, and the depth of P+ transition region 1-5 and P+ source contact region 1-4 is 2.0 μm. The specific parameters are adopted in the embodiment, which is beneficial to reduce the production cost of the device under the premise of ensuring the better performance of the device.

[0074] Step three: as shown in the figure, P-well region 1-6 and N+ active region 1-7 are sequentially formed above each N-CSL layer 1-3 by ion implantation, and then the impurities are activated by annealing at high temperature. Figure 3

[0075] Preferably, the doping concentration of P-well region 1-6 is 10 16 cm -3 order of magnitude, and the doping concentration of N+ active region 1-7 is 10 18 cm -3 order of magnitude. The P-well region 1-6 and N+ active region 1-7 with the specific doping concentration are adopted in the embodiment, which is beneficial to form the conductive channel and access the source electrode.

[0076] Step four: as shown in the figure, after the impurities are activated by annealing, gate trench 1-8 is etched from the middle of each N+ active region 1-7 to the upper part of N-CSL layer 1-3, and the width of gate trench 1-8 is usually 0.5 μm and the depth is 0.9 μm. Figure 4

[0077] ​​​Further, after the gate trench 1-8 is etched, the gate trench 1-8 is sequentially subjected to trench surface roughness treatment and trench rounding treatment, and sacrificial oxidation treatment, which is beneficial to reduce the micro-trench effect at the bottom of the trench, and thus can improve the gate oxide reliability and gate breakdown voltage.

[0078] Step five: as shown in FIG. 1F, a field oxide layer 1-9 is deposited by chemical vapor deposition method to cover the P+ transition region 1-5 and the region located in the P+ transition region 1-5, specifically, to completely cover the upper surface of the device after step four. After the field oxide layer 1-9 is deposited, the thickness of the field oxide layer 1-9 located above the P+ transition region 1-5 is ensured to be 1 μm. Figure 5

[0079] Step six: as shown in FIG. 1G, the field oxide layer 1-9 inside the P+ transition region 1-5 and located in the P+ transition region 1-5 is removed by photolithography and etching, only the field oxide layer 1-9 outside the P+ transition region 1-5 is reserved, and then a gate oxide layer 1-10 is grown at the position where the field oxide layer 1-9 is removed. Figure 6

[0080] Those skilled in the art can understand that the inside of the P+ transition region 1-5 refers to the side of the upper surface of the P+ transition region 1-5 close to the N-CSL layer 1-3, the outside of the P+ transition region 1-5 refers to the side of the upper surface of the P+ transition region 1-5 away from the N-CSL layer 1-3, and the area of the inside is less than the area of the outside.

[0081] Step seven: as shown in FIG. 1H, the polysilicon 1-11 is deposited to cover the field oxide layer 1-9 and the gate oxide layer 1-10, and in order to facilitate subsequent etching, the deposited polysilicon 1-11 fills the trench on the upper surface of the device after step six. Figure 7

[0082] Step eight: as shown in FIG. 1I, the excess polysilicon 1-11 is removed by photolithography and etching, only the polysilicon 1-11 in the gate trench 1-8, the upper part of the corresponding trench above the P+ source contact region 1-4, and the upper part of the corresponding trench above the P+ transition region 1-5 are reserved. Figure 8 It should be noted that when etching the excess polysilicon 1-11, the polysilicon 1-11 on the upper part of the gate trench 1-8 and the polysilicon 1-11 on the upper part of the corresponding trench above the P+ source contact region 1-4 need to be etched down by zero point several microns, so that the polysilicon 1-11 in the gate trench 1-8 and the polysilicon 1-11 above the P+ source contact region 1-4 are both located below the gate oxide layer 1-10 above the N+ active region 1-7, thereby playing a role in ensuring the effective isolation between the gate and the source.

[0083] Step nine: as shown in FIG. 1J, the gate electrode 1-12 is deposited by chemical vapor deposition method to cover the polysilicon 1-11, and the thickness of the gate electrode 1-12 is ensured to be 1 μm.

[0084] Figure 9 ​​​​As shown, the ILD isolation layer 1-12 is deposited by chemical vapor deposition method to cover the polysilicon 1-11 and the area between the polysilicon 1-11, and specifically, the ILD isolation layer 1-12 is deposited to cover the upper surface of the device after step eight.

[0085] Step ten: as shown in the figure, first, etch a gap in the ILD isolation layer 1-12 above each P+ source contact 1-4 using photolithography dry etching method, then remove the ILD isolation layer 1-12 and the polysilicon 1-11 below the gap by wet etching method to form a source via, and then deposit Ni alloy in the source via to form a source contact 1-13. Figure 10

[0086] It should be noted that the source via extends to the adjacent two N-CSL layers 1-3 on both sides, and the source contact 1-13 also covers the adjacent two N-CSL layers 1-3 on both sides, so as to ensure the effective conduction of the device by making the source contact the N+ active region 1-7 effectively.

[0087] Step eleven: as shown in the figure, deposit a mask layer on the ILD isolation layer 1-12, etch the ILD isolation layer 1-12 directly above the field oxide layer 1-9 by photolithography etching to form a gate via, and then deposit Ti alloy in the gate via to form a gate contact 1-14. Figure 11

[0088] Step twelve: as shown in the figure, deposit a metal layer to cover the source contact 1-13 and the gate contact 1-14, coat glue on the metal layer, and form mutually isolated source electrodes 1-15 and gate electrodes 1-17 by photolithography etching, the source electrodes 1-15 are vertically fixed on each source contact 1-13, and the gate electrodes 1-17 are vertically fixed on the gate contact 1-14. Finally, deposit a metal under the N-type substrate 1-1 to form a drain electrode 1-16, and the preparation is completed. Figure 12 Example 2

[0089] The embodiment provides a preparation method of a silicon carbide trench gate MOSFET power device, which comprises the following steps:

[0090] Step one: as shown in the figure, form a doped N-Drift region 1-2 and an N-CSL layer 1-3 on the upper surface of the heavily doped N-type substrate 1-1 in sequence, the N-Drift region 1-2 and the N-CSL layer 1-3 on the N-type substrate 1-1 can be formed by doping through epitaxy, the N-CSL layer 1-3 can also be formed by doping through high-energy ion implantation, and the doping concentration of the N-CSL layer 1-3 is higher than that of the N-Drift region 1-2.

[0091] Figure 1 It should be noted that the source via extends to the adjacent two N-CSL layers 1-3 on both sides, and the source contact 1-13 also covers the adjacent two N-CSL layers 1-3 on both sides, so as to ensure the effective conduction of the device by making the source contact the N+ active region 1-7 effectively.​​​

[0092] Preferably, the doping concentration of the N-type substrate 1-1 is 5×10 19 cm -3 The doping concentration of N-Drift region 1-2 is 10 15 cm -3 The doping concentration of N-CSL layer 1-3 is 10 16 cm -3 The specific doping concentration used in this embodiment is beneficial to further reduce resistance, increase forward withstand voltage, reduce leakage current and reduce specific on-resistance.

[0093] Step 2: If Figure 2 As shown, P+ transition regions 1-5 are set around the N-CSL layer 1-3 by trenching, and multiple P+ source contact regions 1-4 are evenly set on the N-CSL layer 1-3 by trenching. The multiple P+ source contact regions 1-4 separate the N-CSL layer 1-3 into multiple blocks. The multiple P+ source contact regions 1-4 and the multiple N-CSL layers 1-3 are alternately set in the P+ transition region 1-5, and the P+ source contact regions 1-4 constitute a cell region.

[0094] Preferably, both the P+ transition region 1-5 and the P+ source contact region 1-4 are formed by first trenching the N-CSL layer 1-3 and then employing high-energy implantation. The P+ transition region 1-5 surrounds the N-CSL layer 1-3 in an end-to-end fashion, enclosing the N-CSL layer 1-3. Furthermore, the width of the P+ transition region 1-5 is typically 120 μm, and the width of the P+ source contact region 1-4 is typically 0.8 μm. Both the P+ source contact region 1-4 and the P+ transition region 1-5 have a depth of 2.2 μm. This embodiment employs these specific parameters, which helps reduce device production costs while maintaining superior device performance.

[0095] Step 3: If Figure 3 As shown, P-well regions 1-6 and N+ active regions 1-7 are sequentially formed directly above each N-CSL layer 1-3 by ion implantation, and then annealing is performed at a high temperature to activate the impurities.

[0096] Preferably, the doping concentration of the P-well regions 1-6 is 5×10 16 The doping concentration of N+ active region 1-7 is 10 19 cm -3 This embodiment uses the P-well regions 1-6 and N+ active regions 1-7 with the specific doping concentration, which is conducive to forming a conductive channel and accessing the source electrode.

[0097] Step 4: If Figure 4As shown, after annealing to activate the impurities, a gate trench 1-8 is formed by etching downward from the middle of each N+ active region 1-7 to the upper portion of the N-CSL layer 1-3. The width of the gate trench 1-8 is typically 1 μm and the depth is 1.2 μm.

[0098] Furthermore, after etching to obtain the gate trench 1-8, the gate trench 1-8 is sequentially subjected to trench surface roughness treatment, trench rounding treatment, and sacrificial oxidation treatment, which is beneficial to reducing the micro-trench effect at the bottom of the trench, thereby improving gate oxide reliability and gate breakdown voltage.

[0099] Step 5: If Figure 5 As shown, a field oxide layer 1-9 is deposited by chemical vapor deposition to simultaneously cover the P+ transition region 1-5 and the area within the P+ transition region 1-5. Specifically, the field oxide layer 1-9 completely covers the top surface of the device after processing in step 4. After depositing the field oxide layer 1-9, the thickness of the field oxide layer 1-9 above the P+ transition region 1-5 is ensured to be 1.5 μm.

[0100] Step 6: If Figure 6 As shown, the field oxide layer 1-9 inside the P+ transition region 1-5 and located in the P+ transition region 1-5 is removed by photolithography and etching, leaving only the field oxide layer 1-9 outside the P+ transition region 1-5, and then the gate oxide layer 1-10 is grown corresponding to the position where the field oxide layer 1-9 is removed.

[0101] Step 7: If Figure 7 As shown, the deposited polysilicon 1-11 covers the field oxide layer 1-9 and the gate oxide layer 1-10 at the same time, and to facilitate subsequent etching, the deposited polysilicon 1-11 also fills the trench on the upper surface of the device processed in step six.

[0102] Step 8: If Figure 8 As shown, redundant polysilicon 1-11 is removed by photolithography and etching, leaving only the polysilicon 1-11 in the gate trench 1-8, the upper portion of the trench corresponding to the P+ source contact region 1-4, and the polysilicon 1-11 directly above the P+ transition region 1-5.

[0103] It should be noted that when etching the excess polysilicon 1-11, the polysilicon 1-11 on the upper part of the gate trench 1-8 and the polysilicon 1-11 on the upper part of the trench corresponding to the P+ source contact area 1-4 need to be overetched by a few tenths of a micron, so that the polysilicon 1-11 in the gate trench 1-8 and the polysilicon 1-11 directly above the P+ source contact area 1-4 are both located below the gate oxide layer 1-10 directly above the N+ active area 1-7, thereby ensuring effective isolation between the gate and the source.

[0104] Step 9: If Figure 9As shown, the ILD isolation layer 1-12 is deposited by chemical vapor deposition to cover the polysilicon 1-11 and the area between the polysilicon 1-11. Specifically, the ILD isolation layer 1-12 is deposited to cover the upper surface of the device after the processing in step eight.

[0105] Step 10: If Figure 10 As shown, a notch is first etched on the ILD isolation layer 1-12 above each P+ source contact region 1-4 using a dry photolithography method, and then the ILD isolation layer 1-12 and polysilicon 1-11 below the notch are removed using a wet etching method to form a source through hole, and then Ni alloy is deposited in the source through hole to form a source contact 1-13.

[0106] It should be noted that both sides of the source through hole extend to the two adjacent N-CSL layers 1-3, and both sides of the source contact 1-13 also cover the two adjacent N-CSL layers 1-3, so as to ensure effective conduction of the device by making the source effectively contact with the N+ active area 1-7.

[0107] Step 11: If Figure 11 As shown, a mask layer is deposited on the ILD isolation layer 1-12, and the ILD isolation layer 1-12 directly above the field oxide layer 1-9 is etched by photolithography to form a gate through hole, and then Ti alloy is deposited in the gate through hole to form a gate contact 1-14.

[0108] Step 12: Figure 12 As shown, a metal layer is deposited to cover both the source contact 1-13 and the gate contact 1-14. A paste is applied to the metal layer, and photolithography is used to form isolated source electrodes 1-15 and gate electrodes 1-17. The source electrodes 1-15 are vertically fixed to each source contact 1-13, and the gate electrodes 1-17 are vertically fixed to the gate contacts 1-14. Finally, metal is deposited beneath the N-type substrate 1-1 to form the drain electrode 1-16, completing the fabrication.

[0109] Example 3

[0110] This embodiment provides a method for preparing a silicon carbide trench gate MOSFET power device, which includes the following steps:

[0111] Step 1: If Figure 1 As shown, a doped N-Drift region 1-2 and an N-CSL layer 1-3 are sequentially formed on the upper surface of a heavily doped N-type substrate 1-1. The N-Drift region 1-2 and the N-CSL layer 1-3 on the N-type substrate 1-1 can be doped and formed by an epitaxial process, wherein the N-CSL layer 1-3 can also be doped and formed by high-energy ion implantation, and the doping concentration of the N-CSL layer 1-3 is higher than the doping concentration of the N-Drift region 1-2.

[0112] Preferably, the doping concentration of the N-type substrate 1-1 is 10 20 cm -3 The doping concentration of N-Drift region 1-2 is 10 16 cm -3 The doping concentration of N-CSL layer 1-3 is 10 17 cm -3 The specific doping concentration used in this embodiment is beneficial to further reduce resistance, increase forward withstand voltage, reduce leakage current and reduce specific on-resistance.

[0113] Step 2: If Figure 2 As shown, P+ transition regions 1-5 are set around the N-CSL layer 1-3 by trenching, and multiple P+ source contact regions 1-4 are evenly set on the N-CSL layer 1-3 by trenching. The multiple P+ source contact regions 1-4 separate the N-CSL layer 1-3 into multiple blocks. The multiple P+ source contact regions 1-4 and the multiple N-CSL layers 1-3 are alternately set in the P+ transition region 1-5, and the P+ source contact regions 1-4 constitute a cell region.

[0114] Preferably, both the P+ transition region 1-5 and the P+ source contact region 1-4 are formed by first trenching the N-CSL layer 1-3 and then employing high-energy implantation. The P+ transition region 1-5 surrounds the N-CSL layer 1-3 in an end-to-end fashion. Furthermore, the width of the P+ transition region 1-5 is typically 200 μm, and the width of the P+ source contact region 1-4 is typically 1.2 μm. Both the P+ source contact region 1-4 and the P+ transition region 1-5 have a depth of 2.5 μm. This embodiment employs these specific parameters to reduce device production costs while maintaining superior device performance.

[0115] Step 3: If Figure 3 As shown, P-well regions 1-6 and N+ active regions 1-7 are sequentially formed directly above each N-CSL layer 1-3 by ion implantation, and then annealing is performed at a high temperature to activate the impurities.

[0116] Preferably, the doping concentration of the P-well regions 1-6 is 10 17 cm -3 The doping concentration of N+ active region 1-7 is 10 20 cm -3 This embodiment uses the P-well regions 1-6 and N+ active regions 1-7 with the specific doping concentration, which is conducive to forming a conductive channel and accessing the source electrode.

[0117] Step 4: If Figure 4As shown, after annealing to activate the impurities, a gate trench 1-8 is formed by etching downward from the middle of each N+ active region 1-7 to the upper portion of the N-CSL layer 1-3. The width of the gate trench 1-8 is typically 1.5 μm and the depth is 1.5 μm.

[0118] Furthermore, after etching to obtain the gate trench 1-8, the gate trench 1-8 is sequentially subjected to trench surface roughness treatment, trench rounding treatment, and sacrificial oxidation treatment, which is beneficial to reducing the micro-trench effect at the bottom of the trench, thereby improving gate oxide reliability and gate breakdown voltage.

[0119] Step 5: If Figure 5 As shown, a field oxide layer 1-9 is deposited by chemical vapor deposition to simultaneously cover the P+ transition region 1-5 and the area within the P+ transition region 1-5. Specifically, the field oxide layer 1-9 completely covers the top surface of the device after processing in step 4. After depositing the field oxide layer 1-9, the thickness of the field oxide layer 1-9 above the P+ transition region 1-5 is ensured to be 2 μm.

[0120] Step 6: If Figure 6 As shown, the field oxide layer 1-9 inside the P+ transition region 1-5 and located in the P+ transition region 1-5 is removed by photolithography and etching, leaving only the field oxide layer 1-9 outside the P+ transition region 1-5, and then the gate oxide layer 1-10 is grown corresponding to the position where the field oxide layer 1-9 is removed.

[0121] Step 7: If Figure 7 As shown, the deposited polysilicon 1-11 covers the field oxide layer 1-9 and the gate oxide layer 1-10 at the same time, and to facilitate subsequent etching, the deposited polysilicon 1-11 also fills the trench on the upper surface of the device processed in step six.

[0122] Step 8: If Figure 8 As shown, redundant polysilicon 1-11 is removed by photolithography and etching, leaving only the polysilicon 1-11 in the gate trench 1-8, the upper portion of the trench corresponding to the P+ source contact region 1-4, and the polysilicon 1-11 directly above the P+ transition region 1-5.

[0123] It should be noted that when etching the excess polysilicon 1-11, the polysilicon 1-11 on the upper part of the gate trench 1-8 and the polysilicon 1-11 on the upper part of the trench corresponding to the P+ source contact area 1-4 need to be overetched by a few tenths of a micron, so that the polysilicon 1-11 in the gate trench 1-8 and the polysilicon 1-11 directly above the P+ source contact area 1-4 are both located below the gate oxide layer 1-10 directly above the N+ active area 1-7, thereby ensuring effective isolation between the gate and the source.

[0124] Step 9: If Figure 9As shown, the ILD isolation layer 1-12 is deposited by chemical vapor deposition to cover the polysilicon 1-11 and the area between the polysilicon 1-11. Specifically, the ILD isolation layer 1-12 is deposited to cover the upper surface of the device after the processing in step eight.

[0125] Step 10: If Figure 10 As shown, a notch is first etched on the ILD isolation layer 1-12 above each P+ source contact region 1-4 using a dry photolithography method, and then the ILD isolation layer 1-12 and polysilicon 1-11 below the notch are removed using a wet etching method to form a source through hole, and then Ni alloy is deposited in the source through hole to form a source contact 1-13.

[0126] It should be noted that both sides of the source through hole extend to the two adjacent N-CSL layers 1-3, and both sides of the source contact 1-13 also cover the two adjacent N-CSL layers 1-3, so as to ensure effective conduction of the device by making the source effectively contact with the N+ active area 1-7.

[0127] Step 11: If Figure 11 As shown, a mask layer is deposited on the ILD isolation layer 1-12, and the ILD isolation layer 1-12 directly above the field oxide layer 1-9 is etched by photolithography to form a gate through hole, and then Ti alloy is deposited in the gate through hole to form a gate contact 1-14.

[0128] Step 12: Figure 12 As shown, a metal layer is deposited to cover both the source contact 1-13 and the gate contact 1-14. A paste is applied to the metal layer, and photolithography is used to form isolated source electrodes 1-15 and gate electrodes 1-17. The source electrodes 1-15 are vertically fixed to each source contact 1-13, and the gate electrodes 1-17 are vertically fixed to the gate contacts 1-14. Finally, metal is deposited beneath the N-type substrate 1-1 to form the drain electrode 1-16, completing the fabrication.

[0129] Example 4

[0130] This embodiment conducts simulation tests on the preparation processes and the resulting devices of Examples 1-3, as follows:

[0131] 1. The applicant conducted simulation tests on the threshold voltage and specific on-resistance of the devices obtained in Examples 1-3, and the test results are as follows: Figure 13 The threshold voltage of the device in Example 1 is about 3.1V, and the specific on-resistance is about 2.5mΩ·cm 2 In Example 2, the threshold voltage of the device is about 3.0 V, and the specific on-resistance is about 2.1 mΩ·cm 2 In Example 3, the threshold voltage of the device is about 2.7 V, and the specific on-resistance is about 1.8 mΩ·cm2 From the data, it can be known that the device with lower on-resistance can be prepared by using the method.

[0132] 2, the applicant respectively on the device obtained in example 1-3, when the gate outside 1600V voltage to the gate trench bottom electric field simulation, specific simulation chart and data results as shown in Figures 14-16 , wherein, the electric field of the device in example 1 is about 3.3MV / cm, the electric field of the device in example 2 is about 3.0MV / cm, and the electric field of the device in example 2 is about 2.9MV / cm.

[0133] It should be noted that in the silicon carbide trench MOS device, there is usually a gate trench bottom gate oxide reliability problem, and through the foregoing test, it can be known that the deep P+ implantation and the rounding treatment of the gate trench can improve the gate oxide reliability, and ensure that there is lower risk of breakdown at the bottom of the gate trench under the applied 1600V gate voltage.

[0134] 3, the applicant sets P+ transition zone and P+ source contact zone, respectively, using no groove and groove method for preparation, wherein, as shown in Figure 17 , 18 , when setting P+ transition zone and P+ source contact zone, the maximum implantation energy needs to reach 2.4-2.5Mev without groove. And through the design scheme of the present application, the maximum implantation energy only needs 1.7Mev, which greatly reduces the cost and damage to the lattice.

[0135] The above is only a specific embodiment of the present application, any feature disclosed in the specification can be replaced by other equivalent or similar purpose replacement features, unless specifically described; all features disclosed, or steps in all methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A method of fabricating a silicon carbide trench-gate MOSFET power device, comprising: Comprising the following steps: Step one: Forming doped N-Drift region (1-2) and N-CSL layer (1-3) on heavily doped N-type substrate (1-1) in turn; Step two: Setting P+ transition region (1-5) around N-CSL layer (1-3), and setting multiple P+ source contact regions (1-4) on N-CSL layer (1-3) uniformly, multiple P+ source contact regions (1-4) separate N-CSL layer (1-3) into multiple blocks, and multiple P+ source contact regions (1-4) and multiple blocks of N-CSL layer (1-3) are arranged in P+ transition region (1-5) alternately; Step three: Forming P-well region (1-6) and N+ active region (1-7) on each N-CSL layer (1-3) in turn by ion implantation, and then annealing and activating impurities at high temperature; Step four: Etching from the middle of each N+ active region (1-7) to the upper part of N-CSL layer (1-3) to form gate trench (1-8); Step five: Depositing field oxide layer (1-9) by chemical vapor deposition method to cover P+ transition region (1-5) and the region in P+ transition region (1-5); Step six: Removing field oxide layer (1-9) inside P+ transition region (1-5) and in P+ transition region (1-5) by photoetching and etching, only retaining field oxide layer (1-9) outside P+ transition region (1-5), and then growing gate oxide layer (1-10) at the position where field oxide layer (1-9) is removed; Step seven: Depositing polysilicon (1-11) to cover field oxide layer (1-9) and gate oxide layer (1-10); Step eight: Removing excess polysilicon (1-11) by photoetching and etching, only retaining polysilicon (1-11) in gate trench (1-8), above P+ source contact region (1-4) and above P+ transition region (1-5); Step nine: Depositing ILD isolation layer (1-12) by chemical vapor deposition method to cover polysilicon (1-11) and the region between polysilicon (1-11); Step ten: Etching a notch on ILD isolation layer (1-12) above each P+ source contact region (1-4) by dry lithography, removing ILD isolation layer (1-12) and polysilicon (1-11) below the notch by wet etching method to form a source through hole, and then depositing Ni alloy in the source through hole to form a source contact (1-13); Step eleven: Depositing a mask layer on ILD isolation layer (1-12), etching ILD isolation layer (1-12) above field oxide layer (1-9) by photoetching and etching to form a gate through hole, and then depositing Ti alloy in the gate through hole to form a gate contact (1-14); Step twelve: Depositing a metal layer to cover source contact (1-13) and gate contact (1-14), coating glue on the metal layer, and forming mutually isolated source electrode (1-15) and gate electrode (1-17) by photoetching and etching, and finally depositing metal under N-type substrate (1-1) to form drain electrode (1-16), completing the preparation.

2. The method of claim 1, wherein the N-Drift region (1-2) on the N-type substrate (1-1) is formed by epitaxy, and the N-CSL layer (1-3) is formed by epitaxy or high-energy ion implantation, and the doping concentration of the N-type substrate (1-1) is 10 19 ~ 10 20 cm -3 order of magnitude, the doping concentration of the N-Drift region (1-2) is 10 14 ~ 10 16 cm -3 order of magnitude, and the doping concentration of the N-CSL layer (1-3) is 10 15 ~ 10 17 cm -3 order of magnitude.

3. The method of manufacturing a silicon carbide trench gate MOSFET power device of claim 1, wherein: In step two, the P+ transition region (1-5) and the P+ source contact region (1-4) are formed by high-energy implantation after trenching on the N-CSL layer (1-3), the P+ transition region (1-5) is enclosed around the N-CSL layer (1-3) in a head-to-tail manner, the width of the P+ transition region (1-5) is 40-200 μm, the width of the P+ source contact region (1-4) is 0.3-1.2 μm, and the depth of the P+ source contact region (1-4) and the P+ transition region (1-5) is 2.0-2.5 μm.

4. The method of producing a silicon carbide trench-gate MOSFET power device according to Claim 1, wherein: In step three, the P-well region (1-6) has a doping concentration of 10 16 ~ 10 17 cm -3 order of magnitude, and the N+ active region (1-7) has a doping concentration of 10 18 ~ 10 20 cm -3 order of magnitude.

5. The method of producing a silicon carbide trench-gate MOSFET power device according to any one of claims 1 to 4, characterized by: In step four, after the gate trench (1-8) is etched, the gate trench (1-8) is subjected to trench surface roughness treatment and trench corner treatment, and sacrificial oxidation treatment in sequence.

6. The method of producing a silicon carbide trench gate MOSFET power device according to claim 1, wherein: In step four, the width of the gate trench (1-8) is 0.5-1.5 μm, and the depth is 0.9-1.5 μm.

7. The method of producing a silicon carbide trench gate MOSFET power device according to claim 1, wherein: In step five, the thickness of the field oxide layer (1-9) above the P+ transition region (1-5) is 1-2 μm.

8. The method of producing a silicon carbide trench gate MOSFET power device according to claim 1, wherein: In step six, the inner side of the P+ transition region (1-5) refers to the side on the upper surface of the P+ transition region (1-5) close to the N-CSL layer (1-3), the outer side of the P+ transition region (1-5) refers to the side on the upper surface of the P+ transition region (1-5) away from the N-CSL layer (1-3), and the area of the inner side is smaller than that of the outer side.

9. The method of producing a silicon carbide trench gate MOSFET power device according to claim 1, wherein: In step eight, the polysilicon (1-11) in the gate trench (1-8) and the polysilicon (1-11) directly above the P+ source contact region (1-4) are both located below the gate oxide layer (1-10) directly above the N+ active region (1-7).

10. The method of producing a silicon carbide trench gate MOSFET power device according to claim 1, wherein: In step ten, the two sides of the source via hole extend to the adjacent two N-CSL layers (1-3) respectively, and the two sides of the source contact (1-13) also cover the adjacent two N-CSL layers (1-3) respectively.

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