Device based on active region driving force redistribution, fabrication method and layout structure

Abstract

The application discloses a device based on active region driving force redistribution, a preparation method and a layout structure, and the device structure comprises a substrate layer, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode and a gate electrode; the substrate layer, the nucleation layer, the buffer layer, the channel layer and the barrier layer are sequentially stacked from bottom to top to form an epitaxial wafer; the source electrode active region and the drain electrode active region are formed in the epitaxial wafer; the source electrode and the drain electrode are correspondingly arranged on one side of the source electrode active region and one side of the drain electrode active region; the gate electrode is arranged between the source electrode and the drain electrode; and the source electrode active region and the drain electrode active region are asymmetrically distributed on both sides of the gate electrode. According to the scheme, only the mask plate for the two-step photolithography of ohmic and active region isolation needs to be changed on the basis of the conventional device standard process, no additional process needs to be introduced, the device linearity is improved without increasing the process complexity and the preparation cost, and the compatibility between the yield, stable device performance and high linearity is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a device based on redistribution of driving force of an active region, a preparation method and a layout structure. BACKGROUND

[0002] Thanks to the material characteristics of high electron mobility, high electron saturation velocity and high breakdown field strength, a gallium nitride-based high electron mobility transistor (GaN HEMT) is compatible with the advantages of high working frequency and large output power, and its market share in the field of telecommunications infrastructure above 3GHz is leading the first generation of semiconductor devices (Si Laterally Diffused Metal Oxide Semiconductor, Si LDMOS) and the second generation of semiconductor devices (GaAs Metal-Semiconductor Field Effect Transistor, GaAs MESFET) year by year. However, compared with Si LDMOS and GaAs MESFET, the radio frequency GaN HEMT exposes more serious nonlinearity problems, which will adversely affect signal transmission quality and amplification capacity under high input power. With the continuous widening of the application frequency band and the exponential growth of data throughput, modern wireless communication technology has put forward urgent demands for high data transmission rate and high spectrum utilization efficiency, prompting the radio frequency GaN to take measures to solve its nonlinearity problems and play a more active role in the current fierce market competition environment.

[0003] At present, the solutions to the nonlinearity problem of radio frequency GaN mainly start from the aspects of circuit and device. The linearization technology at the circuit level includes power backoff, feedback, digital pre-distortion and Doherty architecture, which has been developed relatively maturely and has been widely applied. However, considering the cost, integration and design complexity problems brought by the circuit level technology, research begins to focus on more basic and device level solutions.

[0004] The nonlinear growth of the source-end series resistance (R S ) under large current (I DS ) is considered to be one of the sources of the inherent nonlinearity of GaN HEMT at the device level, and the growth trend of the source resistance is further directly related to the flatness of the transconductance (G m ) profile. Since the transconductance curve has the characteristics of intuitiveness and controllability, the device level linearity technology often takes the flat transconductance profile as the optimization direction, including epitaxial material optimization schemes represented by double heterojunction and polarization-doped channel and device structure optimization schemes represented by field plate, fin-type gate and source injection.

[0005] wherein the source implantation technology forms a heavily doped n ++ The low resistance region reduces the resistance of the source terminal series resistance relative to the drain terminal series resistance, so that the drain terminal bears more channel electric field, weakens the dependence of the source terminal series resistance on the drain current, and improves the flatness of the transconductance profile. The fin-type gate technology adopts a special photolithography and etching process to periodically block the channel below the gate in the gate width direction, forming a top gate and two sidewall gates for a total of three-dimensional control. By designing the fin width, fin height, and array ratio, the ratio relationship between the active region width corresponding to the source resistance and the active region width corresponding to the channel is adjusted, the source resistance corresponding to a single fin-type channel is reduced, the trend of the source resistance increasing with the increase of the drain current is suppressed, and the linearity of the transconductance of the device is improved. The double heterojunction structure controls the threshold voltage at which the upper and lower channels are turned on by adjusting the coupling degree between the channels. When the upper channel is turned on, the corresponding R S When the nonlinear growth trend occurs and the transconductance rolls off, the lower channel is just turned on, and the corresponding R S is small, and the transconductance is lifted. S The upper and lower channels are in parallel, the equivalent R S is reduced, and the transconductance presents a wide profile after splicing, and the linearity is improved.

[0006] However, the above device-level linearity optimization scheme still has the following disadvantages:

[0007] For the source implantation technology, on the one hand, it introduces an additional process in the device preparation process. The implantation process needs to reasonably design the mask and the implantation dose to control the area and the implantation depth of the implantation region, and the implantation process has an out-of-expansion amount, which is not conducive to the reduction of the lateral size of the device. On the other hand, although the implanted Si reduces the resistance of the source active region and reduces the voltage division, the ionized impurity scattering introduced by the doping will reduce the mobility of the channel carriers at the source, which is not conducive to the improvement of the frequency characteristics of the device.

[0008] The implementation of the fin-type gate technology needs to add one step of photolithography and etching process based on the conventional GaN HEMT preparation process. The etching damage produced by the etching process will induce interface state trap related problems, and the off-state current of the device will also be deteriorated. In addition, in order to form the sidewall gate control, the FinFET periodically blocks the channel in the gate width direction, resulting in a decrease in the on-state current of the device. The gate metal of the sidewall also introduces extra parasitic capacitance, and the improvement of the frequency characteristics of the device is limited.

[0009] For double heterojunction devices, the inherent bimodal transconductance characteristic provides a natural advantage for broadening the transconductance profile. However, coupling between transconductance peaks often requires the assistance of other techniques; otherwise, valleys that are difficult to fill will form between the two transconductance peaks, hindering the improvement of transconductance flatness. Furthermore, due to the greater distance between the lower channel and the gate, double heterojunction devices are more difficult to achieve stable gate control than conventional devices at the same gate length, easily leading to problems related to short-channel effects.

[0010] In summary, existing device-level linearization techniques often sacrifice fabrication costs and extend process cycles to improve linearity, and generally suffer from high process complexity and trade-offs between linearity and other performance indicators. Summary of the Invention

[0011] To address the aforementioned problems in the prior art, this invention provides a device, fabrication method, and layout structure based on active region driving force redistribution. The technical problem to be solved by this invention is achieved through the following technical solution:

[0012] In a first aspect, the present invention proposes a device based on an asymmetric active region, the device comprising: a substrate layer, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, and a gate electrode;

[0013] The substrate layer, nucleation layer, buffer layer, channel layer and barrier layer are stacked sequentially from bottom to top to form an epitaxial substrate;

[0014] Active and drain regions are formed in the epitaxial substrate;

[0015] The source electrode and drain electrode are respectively disposed on one side of the source active region and the other side of the drain active region; the gate electrode is disposed between the source electrode and the drain electrode;

[0016] The source and drain active regions are asymmetrically distributed on both sides of the gate electrode, forming an asymmetrical active region, thereby realizing the redistribution of the driving capability of the source and drain active regions of the device.

[0017] Secondly, this invention proposes a device layout structure based on the redistribution of active region driving force. This layout structure includes a device core region, which includes a source active region, a source electrode, a drain active region, a drain electrode, and a gate electrode. The source active region and the drain active region are asymmetrically distributed on both sides of the gate electrode. The device core region adopts the active region design scheme of the device based on the redistribution of active region driving force provided in the first aspect of this invention, and leads out metal PADs through T-type or U-type interconnection to realize probe testing.

[0018] In a third aspect, the application provides a preparation method of the device based on active region driving force redistribution, which is used for preparing the device based on active region driving force redistribution provided in the first aspect of the application, and comprises the following steps:

[0019] A nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially prepared on a substrate to form an epitaxial wafer;

[0020] A source electrode region and a drain electrode region are photoetched on the barrier layer by using a pre-prepared asymmetric ohmic mask, and the source electrode and the drain electrode are made;

[0021] Active region isolation is performed on the epitaxial wafer by using a pre-prepared asymmetric active region mask to form asymmetric source active regions and drain active regions;

[0022] A dielectric layer is formed on the source electrode, the drain electrode and the barrier layer;

[0023] A gate electrode region is photoetched and etched on the dielectric layer, and a gate electrode is made in the gate electrode region; the gate electrode is located between the source electrode and the drain electrode;

[0024] The dielectric layer above the source electrode and the drain electrode is removed, and a metal interconnection layer is made, so that the device preparation is completed.

[0025] The application has the following beneficial effects:

[0026] By designing the source active regions and the drain active regions into an asymmetric structure, the application improves the conduction capacity of the source active regions relative to the drain active regions by redistributing the driving capacity of the source active regions and the drain active regions of the device, reduces the source end voltage division, hinders the electric field of the source active regions from reaching the critical level of inducing electron speed quasi-saturation, suppresses the decrease of electron mobility and the increase of source end series resistance, improves the clock-shaped profile of transconductance, and further improves the linearity of the device. Compared with the existing device-level linearization technology, the scheme only needs to change the mask of the two-step photoetching of ohmic and active region isolation on the basis of the conventional device standard process, without introducing additional processes, and improves the device linearity without increasing the process complexity and preparation cost; and the process cycle is not prolonged compared with the current mature standard process, realizing the compatibility between the yield, stable device performance and high linearity.

[0027] The application will be further described in detail below in combination with the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a structure schematic diagram of a device based on active region driving force redistribution provided by an embodiment of the application;

[0029] Figure 2is a top view structural schematic diagram of a device based on active region driving force redistribution provided by an embodiment of the present application and a conventional device;

[0030] Figure 3 is a comparison diagram of source end series resistance change trend with drain current of a device based on active region driving force redistribution and a conventional device provided by an embodiment of the present application;

[0031] Figure 4 is a transfer characteristic curve comparison diagram of a device based on active region driving force redistribution and a conventional device provided by an embodiment of the present application;

[0032] Figure 5 is a layout structure schematic diagram of a commonly used radio frequency GaN HEMT T-type interconnection at present;

[0033] Figure 6 is a layout structure schematic diagram of a commonly used radio frequency GaN HEMT U-type interconnection at present;

[0034] Figure 7 is a first layout structure schematic diagram of a device core region in a radio frequency GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present application;

[0035] Figure 8 is a second layout structure schematic diagram of a device core region in a radio frequency GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present application;

[0036] Figure 9 is a third layout structure schematic diagram of a device core region in a radio frequency GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present application;

[0037] Figure 10 is a fourth layout structure schematic diagram of a device core region in a radio frequency GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present application;

[0038] Figure 11 is a fifth layout structure schematic diagram of a device core region in a radio frequency GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present application;

[0039] Figure 12 is a sixth layout structure schematic diagram of a device core region in a radio frequency GaN HEMT T-type and U-type interconnection structure provided by an embodiment of the present application;

[0040] Figure 13 is a flow schematic diagram of a preparation method of a device based on active region driving force redistribution provided by an embodiment of the present application;

[0041] Figure 14A preparation process flow chart of a device based on active region driving force redistribution is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the protection scope of the present application.

[0043] For GaN HEMT devices, the nonlinear increase of source series resistance (R S ) under large current (I DS ) is one of the sources of inherent nonlinearity, which makes the transconductance of the device roll off under large gate voltage, and the signal amplification ability is inhibited under high input power, resulting in additional signal distortion, which is difficult to meet the application requirements of high linearity. Since the DC transconductance of the device has the characteristics of intuitive and easy to characterize, when the trend of transconductance roll-off is alleviated by adjusting R S , it can be initially considered that the linearity of the device is improved.

[0044] Generally, the relationship between the extrinsic transconductance (G m,ext ) of the device and the source series resistance (R S ) can be represented by the following formula (1):

[0045] G m,ext =G m,int / (1+R s ·G m,int ) (1);

[0046] In the formula, G m,int is the intrinsic transconductance obtained by ignoring the series resistance.

[0047] According to formula (1), the extrinsic transconductance (G m,ext ) of the device is highly related to the source series resistance (R S ). When the linearity of the device is not optimized, the source series resistance shows a nonlinear increase trend with the increase of the drain current, which makes the transconductance show a non-ideal bell shape. Although the influence of the source series resistance during the actual device preparation process cannot be completely removed, the bell-shaped profile of the transconductance can be improved by suppressing the nonlinear increase trend of the source series resistance.

[0048] Since the resistance of the source and drain active regions is directly related to the current driving capability of the corresponding source and drain, the relative size of the source and drain active region resistance can be changed by redistributing the driving capability of the two, so as to improve the linearity of the device. According to the resistance law, when the resistivity p is constant, the resistance of the conductor is proportional to its length L and inversely proportional to the cross-sectional area S, as shown in formula (2):

[0049]

[0050] Through the above analysis, it can be seen that the conduction capability of the source and drain can be changed by adjusting the width of the source / drain active region (i.e. the cross-sectional area S of the active region resistance) or the length L of the active region (i.e. the gate-source / gate-drain spacing).

[0051] Based on this, the present application provides a device-level linearity improvement technology based on active region driving force redistribution, which redistributes the driving capability of the device source and drain active regions by designing asymmetric active regions, aiming to improve the conduction capability of the source active region relative to the drain active region, reduce the source end voltage division, suppress the electric field of the source active region to the critical level of inducing electron speed quasi-saturation, and weaken the dependence of the source end series resistance on the drain current.

[0052] Specifically, the first aspect of the present application provides a device based on active region driving force redistribution. Please refer to Figure 1 , Figure 1 is a structure diagram of a device based on active region driving force redistribution provided by an embodiment of the present application, which comprises: a substrate layer, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode S, a drain electrode G and a gate electrode D;

[0053] The substrate layer, the nucleation layer, the buffer layer, the channel layer and the barrier layer are sequentially stacked from bottom to top to form an epitaxial substrate;

[0054] The source and drain active regions are formed in the epitaxial substrate;

[0055] The source and drain electrodes are correspondingly arranged on one side of the source active region and one side of the drain active region; the gate electrode is arranged between the source and drain electrodes;

[0056] Among them, the source and drain active regions are asymmetrically distributed on both sides of the gate electrode to form asymmetric active regions, so as to realize the redistribution of the driving capability of the device source and drain active regions.

[0057] The device based on active region driving force redistribution (i.e. asymmetric active region device) provided by the embodiment is mainly exemplified by a radio frequency GaN HEMT device. As to the material of each layer structure of the device, the embodiment is designed as follows: the substrate layer material includes but is not limited to one of silicon carbide (SiC), silicon (Si), sapphire and the like; the buffer layer material includes but is not limited to one of GaN, aluminum nitride (AlN), aluminum gallium nitride (AlGaN) and the like; the channel layer material includes but is not limited to one of GaN, indium gallium nitride (InGaN), AlGaN and the like; the barrier layer material includes but is not limited to one of AlGaN, indium aluminum nitride (InAlN), AlN and the like; the source electrode and the drain electrode are a Ti, Al, Ni, Au metal stack structure from bottom to top; the gate electrode is a Ni, Au two-layer metal stack structure from bottom to top. The thickness and other size design of each layer structure can be in accordance with the existing device structure design, which is not specifically limited in the embodiment.

[0058] Further, according to the above formula (2), the asymmetric active region design of the embodiment can be realized by the following three ways:

[0059] The first way: the source active region and the drain active region form asymmetric active regions with unequal widths based on the width redistribution principle.

[0060] The second way: the source active region and the drain active region form asymmetric active regions with unequal lengths based on the length redistribution principle.

[0061] The third way: the source active region and the drain active region form asymmetric active regions with unequal lengths and widths based on the length and width redistribution principle.

[0062] Optionally, as a specific implementation form of the first way, the asymmetric design can be adopted that the source active region and the drain active region are in a trapezoidal structure, and the width of the source active region is greater than that of the drain active region.

[0063] Specifically, please refer to Figure 2 , Figure 2 is a top view structural schematic diagram of the device based on active region driving force redistribution (i.e. asymmetric active region device) and a conventional device provided by the embodiment of the application. Wherein, the left (a) figure is a top view structural schematic diagram of the device based on active region driving force redistribution (i.e. asymmetric active region device), and the right (b) figure is a top view structural schematic diagram of the conventional device. In Figure 2 , the width of the source active region is W S , the length is L GS , the width of the drain active region is W D , and the length is L GD . It can be seen that the width W SThe width W of the active region of the drain is greater than D The width W of the source active region of the conventional device on the right S Width W of the drain active region D equal.

[0064] It should be noted that mature GaN RF devices now generally adopt a design where the gate electrode is biased towards the source electrode (i.e., Figure 2 L in GD It is usually greater than L. GS This invention modifies the structure of the ohmic electrode and the active region isolation mask while retaining the gate bias source design, thereby improving the frequency characteristics of the device.

[0065] Optionally, as a second implementation of method one, both the source and drain active regions can be rectangular structures; the drain electrode is arranged in an array structure under the periodic blocking of the active region isolation mask, resulting in an asymmetric design where the width of the source active region is greater than the width of the drain active region. For this structural design, please refer to the following text and... Figure 8 For version Figure 2 To understand the introduction.

[0066] Furthermore, regarding the second method described above, as a first optional implementation, this embodiment can employ the following asymmetric active region design with unequal lengths: the source active region is a rectangular structure, and the drain active region has a bulge-like structure with concave ends and a protruding middle in the width direction. This further increases the difference between the lengths of the source and drain active regions, building upon the existing gate electrode biased towards the source electrode design. For details on this structural design, please refer to the following text and... Figure 9 For version Figure 3 To understand the introduction.

[0067] Furthermore, as a second implementation of Method Two, this embodiment can employ the following asymmetric active region design with unequal lengths: the source active region is a rectangular structure, and the drain active region has a bowl-shaped structure with protruding ends and a concave middle in the width direction. This further increases the difference between the lengths of the source and drain active regions, building upon the existing design where the gate electrode is biased towards the source electrode. For details on this structural design, please refer to the following text and... Figure 10 For version Figure 4 To understand the introduction.

[0068] Further, for the above-mentioned mode three, as a first optional implementation form, the embodiment can adopt the following asymmetric active region design with unequal length and width, that is, the source active region is in a rectangular structure, the drain active region is in a comb structure in the width direction, the drain electrode is in an array structure, and the adjacent arrays are not blocked, so as to make the width of the source active region greater than the width of the drain active region, and increase the difference between the length of the source active region and the length of the drain active region, on the basis of the existing gate electrode biasing towards the source electrode design. For this structure design, reference can also be made to the following and Figure 11 For the introduction of the above-mentioned mode three, reference can be made to the above-mentioned mode one and mode two. Figure 5 For the introduction of the above-mentioned mode three, reference can be made to the above-mentioned mode one and mode two.

[0069] In addition, as a second implementation form of mode three, the embodiment can adopt the following asymmetric active region design with unequal length and width, that is, the source active region is in a rectangular structure, the drain active region and the drain electrode are in a comb structure in the width direction, so as to make the width of the source active region greater than the width of the drain active region, and increase the difference between the length of the source active region and the length of the drain active region, on the basis of the existing gate electrode biasing towards the source electrode design. For this structure design, reference can also be made to the following and Figure 12 For the introduction of the above-mentioned mode three, reference can be made to the above-mentioned mode one and mode two. Figure 6 For the introduction of the above-mentioned mode three, reference can be made to the above-mentioned mode one and mode two.

[0070] It can be understood that, in addition to the above-mentioned asymmetric active region structure design, other forms of asymmetric design can also be adopted, for example, a layout design including but not limited to a comb structure, a bowl structure, a drum structure, etc. is adopted on one side of the source active region, the driving capability of the source active region relative to the drain active region is improved, the dependence of the source series resistance on the drain current is weakened, and the purpose of improving the linearity of the device is achieved.

[0071] In addition, the upper surface of the above-mentioned asymmetric active region device is also provided with a dielectric layer, and the dielectric layer material includes but is not limited to one of silicon nitride (SiN), silicon oxide (SiO2), aluminum oxide (Al2O3), etc. A metal interconnection layer is also provided on each electrode of the device, and the metal interconnection layer is a two-layer metal stack structure of Ti and Au from bottom to top. The thickness and size design of each layer structure can be in accordance with the existing device structure design, and the embodiment does not make specific limitations.

[0072] The performance comparison between the device based on active region driving force redistribution provided by the embodiment of the present application and the conventional device is shown in Figure 3 and Figure 4 , wherein, Figure 3 is the normalized source series resistance (R S / R S0 ) of the device based on active region driving force redistribution and the conventional device, and the change trend of the normalized source series resistance with the drain current is shown in Figure 4The transfer characteristic curve contrast chart of the device based on active region driving force redistribution and the conventional device is shown in the figure.

[0073] It can be seen that, by designing the source active region and the drain active region into an asymmetric structure, the conduction capability of the source active region relative to the drain active region is improved, the source end voltage division is reduced, the electric field applied on the source active region is hindered from reaching the critical level of inducing electron speed quasi-saturation, thereby the dependence of the source end series resistance on the drain current is weakened, the clock-shaped profile of the transconductance is improved, and the linearity of the device is improved. When the asymmetric active region scheme is implemented, only the photolithography mask used for active region isolation needs to be redesigned, and the photolithography mask of the ohmic region is correspondingly changed.

[0074] Compared with the existing device-level linearization technology, the scheme only needs to change the mask of the two-step photolithography of the ohmic and active region isolation on the basis of the conventional device standard process, without introducing additional processes, and improves the device linearity without increasing the process complexity and preparation cost; and the process cycle is not prolonged compared with the current mature standard process, and the compatibility between the yield, stable device performance and high linearity is achieved.

[0075] Based on the same inventive concept, the second aspect of the present application also provides a device layout structure based on active region driving force redistribution, the layout structure comprising a device core region, the device core region comprising a source active region, a source electrode, a drain active region, a drain electrode and a gate electrode, the source active region and the drain active region being asymmetrically distributed on both sides of the gate electrode; wherein the device core region adopts the active region design scheme of the device based on active region driving force redistribution proposed in the first aspect, and a metal PAD is led out outwardly through a T-shaped or U-shaped interconnection mode to realize probe testing.

[0076] Specifically, please refer to Figure 5 and Figure 6 , Figure 5 is a schematic diagram of the layout structure of the current commonly used RF GaN HEMT T-shaped interconnection. The gate is two fingers, one finger on the left and one finger on the right, which are connected to the gate interconnection PAD through the middle interconnection opening area. Figure 6is a commonly used RF GaN HEMT U-shaped interconnection layout structure schematic diagram. Among them, the gate is two fingers parallel from top to bottom, which is connected with the gate interconnection PAD through the left interconnection opening area. The gate index of the U-shaped interconnection structure is not limited to two fingers, and two fingers and multiples of two fingers can adopt the interconnection structure, and the source electrode and the drain electrode between the multiple fingers also need to be connected by air bridge process.

[0077] The application designs different asymmetric active region structures in the device core area of the T-shaped and U-shaped interconnection layout structure. It can be understood that the difference between the layout design of the device core area of the T-shaped and U-shaped interconnection structure is only that the interconnection forms are different, and the functions realized are the same. The different layout designs of the device core area of the T-shaped and U-shaped interconnection structure are described in detail below in combination with the implementation modes of the above three asymmetric structures.

[0078] Layout Figure 1

[0079] Please refer to Figure 7 , Figure 7 is a first layout structure schematic diagram of a device core area in a RF GaN HEMT T-shaped and U-shaped interconnection structure provided by the embodiment of the application; wherein the upper drawing is a T-shaped interconnection structure, and the lower drawing is a U-shaped interconnection structure. In Figure 7 , the shapes of the source active region and the drain active region are both trapezoidal, and the width W S of the source active region is greater than the width W D of the drain active region. Figure 1 and Figure 2 , that is, the first implementation form of the above mode one. Compared with the preparation process of a conventional GaN HEMT device, Figure 7 , the structure shown in the figure needs to replace the mask plate for two steps of photoetching of ohmic and active region isolation.

[0080] Layout Figure 2

[0081] Please refer to Figure 8 , Figure 8 is a second layout structure schematic diagram of a device core area in a RF GaN HEMT T-shaped and U-shaped interconnection structure provided by the embodiment of the application, corresponding to the second implementation form of the above mode one; wherein the upper drawing is a T-shaped interconnection structure, and the lower drawing is a U-shaped interconnection structure. In Figure 8 , the source active region and the drain active region are both rectangular, the drain active region mask plate is comb-shaped, the drain ohmic region mask plate is blocked along the gate width direction to be an array structure, so that the drain electrode is also an array structure, the array-shaped drain electrode is connected with the interconnection metal through the opening area mask plate, and the current collection is completed. The width of the drain active region corresponding to the single tooth of the drain ohmic region mask plate is Δw, and when the number of teeth is n, the total width WD =n×Δw, this design can still guarantee W S >W D Understandably, Figure 8 The structure shown requires replacing the photomasks used in the two-step lithography process for ohm and active region isolation.

[0082] version Figure 3

[0083] Please see Figure 9 , Figure 9 This is a schematic diagram of the third layout structure of the core area of ​​the device in the RF GaN HEMT T-type and U-type interconnect structure provided in the embodiments of the present invention, corresponding to the first implementation of the above-mentioned method two; wherein, the upper figure is the T-type interconnect structure and the lower figure is the U-type interconnect structure. Figure 9 In the diagram, the source active region is rectangular, while the drain active region is a bulge-like structure with concave ends and a protruding middle. Specifically, for Figure 9 The asymmetric structure shown has the lowest current resistance when the current flows out from the source, through the gate, and then through L. GDmin The distance is collected on both sides of the drain, and the way with the greatest resistance to current conduction is that it flows out from the source, through the gate, and then through L. GDmax Only at a distance of [distance] is the middle of the drain electrode collected.

[0084] version Figure 4

[0085] Please see Figure 10 , Figure 10 This is a schematic diagram of the fourth layout structure of the core area of ​​the device in the RF GaN HEMT T-type and U-type interconnect structure provided in the embodiments of the present invention, corresponding to the second implementation of the above-mentioned method two; wherein, the upper figure is the T-type interconnect structure and the lower figure is the U-type interconnect structure. Figure 10 In the diagram, the source active region is rectangular, while the drain active region is a bowl-shaped structure with protruding ends and a concave center. (Similar to...) Figure 9 The structure, Figure 10 The asymmetric structure shown has the lowest current resistance when the current flows out from the source, through the gate, and then through L. GDmin The distance is collected in the middle of the drain, and the way with the greatest resistance to current conduction is that it flows out from the source, through the gate, and then through L. GDmax Only when the distance is such that the material is collected from both sides of the drain electrode.

[0086] version Figure 5

[0087] Please see Figure 11 , Figure 11This is a schematic diagram of the fifth layout structure of the core area of ​​the device in the RF GaN HEMT T-type and U-type interconnect structure provided in the embodiments of the present invention, corresponding to the first implementation of the above-mentioned method three; wherein, the upper figure is the T-type interconnect structure and the lower figure is the U-type interconnect structure. Figure 11 In this structure, the source active region is rectangular, the drain active region has a comb-like structure in the width direction, and the drain ohmic region has an array-like structure in the width direction. Adjacent arrays are not blocked and still possess the ability to conduct current. Specifically, for Figure 11 The asymmetric structure shown has the lowest current resistance when the current flows out from the source, through the gate, and then through L. GDmin The distance is collected by the drain, and the way with the greatest resistance to current conduction is that it flows out from the source, through the gate, and then through L. GDmax The current is collected at the side of the arrayed ohmic electrodes only after reaching the other end of the drain. In contrast, the source ohmic region is continuous and complete, possessing stronger current driving capability, thus creating an asymmetry in the conduction capability between the source and drain terminals.

[0088] version Figure 6

[0089] Please see Figure 12 , Figure 12 This is a schematic diagram of the sixth layout structure of the core area of ​​the device in the RF GaN HEMT T-type and U-type interconnect structure provided in the embodiments of the present invention, corresponding to the second implementation of the above-mentioned method three; wherein, the upper figure is the T-type interconnect structure and the lower figure is the U-type interconnect structure. Figure 12 In the gate, the source active region is rectangular, and the drain active region and the drain ohmic electrode are arranged in a comb-like structure along the gate width direction. Specifically, for Figure 12 The asymmetric structure shown has three possible current conduction methods, which can be classified according to the resistance encountered during conduction from smallest to largest: First, the current flows out from the source, through the gate, and through L. GDmin The first part is collected by the drain after a distance of L, and the second part flows out from the source, through the gate, and then flows a distance of L. GDmin <L<L GDmax Then it is collected on the side of the comb-shaped ohmic electrode, and thirdly, it flows out from the source, through the gate, and through L. GDmax The current is collected by the ohmic electrode only after a distance of [distance]. In contrast, the source ohmic region has only one way of conducting current with the least resistance, and has a stronger ability to drive current, thus creating an asymmetry in the conduction capabilities of the source and drain terminals.

[0090] The above six maps can be summarized as follows: Figure 1 and 2 Both methods control the inequality of conduction capabilities between the source and drain terminals by adjusting the width of the active region, i.e., the cross-sectional area S of the resistor in formula (2); Figure 3 and4 The asymmetry of the active region is achieved by adjusting the length of the active region, i.e. the length L of the resistance in formula (2), to control the non-equivalence of the on-state capability of the source end and the drain end. Figure 5 and 6 The asymmetry of the active region is achieved by simultaneously changing the width and length of the drain active region, i.e. the cross-sectional area S and the length L of the resistance in formula (2), to control the non-equivalence of the on-state capability of the source end and the drain end.

[0091] It can be understood that the interconnection structure based on the asymmetry of the active region provided by the present application is not limited to one of the T-shaped and U-shaped structures, and can be adaptively changed according to actual conditions.

[0092] The third aspect of the present application also provides a preparation method of a device based on the redistribution of the driving force of the active region. Please refer to Figure 13 , Figure 13 is a flowchart of the preparation method of a device based on the redistribution of the driving force of the active region provided by the embodiment of the present application. The preparation method mainly includes the following steps:

[0093] Step 1, sequentially preparing a nucleation layer, a buffer layer, a channel layer and a barrier layer on a substrate to form an epitaxial wafer.

[0094] It can be understood that after obtaining the epitaxial wafer, a pattern with a certain depth and being easy to identify needs to be formed on the surface of the epitaxial wafer as an alignment mark for the subsequent steps; it can be an etching alignment mark or a metal alignment mark, etc.

[0095] Step 2, based on the alignment mark, using a pre-prepared ohmic region mask to photoetch the source electrode region and the drain electrode region on the barrier layer, and manufacturing the source electrode and the drain electrode.

[0096] The source electrode and the drain electrode are a bottom-up Ti, Al, Ni, Au metal stack structure, and an annealing process needs to be used to sink the source electrode and the drain electrode into the buffer layer and locate them at the two ends of the buffer layer, respectively.

[0097] It needs to be explained here that since the active region of the device is designed to be asymmetrical, the shape of the source electrode and the drain electrode also needs to be changed accordingly, and therefore, an ohmic region mask with a corresponding shape needs to be prepared in advance according to the actual preparation of the active region. It can be understood that after this step is completed, the width of the source active region and the current driving capability of the drain active region on both sides of the gate are not equivalent.

[0098] Step 3, using a pre-prepared asymmetrical active region mask to isolate the active region on the epitaxial wafer to form asymmetrical source active region and drain active region.

[0099] The asymmetric active region mask plate can be prepared by referring to the structure design of the second aspect of the present application or the layout design of the second aspect. Based on the prepared asymmetric active region mask plate, an etching process or an ion implantation process is used to isolate the active regions of the epitaxial wafer to prevent electrical connection between devices.

[0100] Step 4: Forming a dielectric layer on the source electrode, the drain electrode and the barrier layer.

[0101] Step 5: Photoetching and etching the gate electrode region on the dielectric layer, and manufacturing a gate electrode in the gate electrode region; the gate electrode is located between the source electrode and the drain electrode.

[0102] The gate electrode is a two-layer metal stack structure of Ni and Au from bottom to top.

[0103] Step 6: Removing the dielectric layer above the source electrode and the drain electrode, and manufacturing a metal interconnection layer, thereby completing the device preparation.

[0104] It can be seen that, in the process of preparing the device provided by the present application, only the mask plates for the two photoetching steps of ohmic and active region isolation are changed, no additional process is introduced, and the process cycle is not prolonged compared with the current mature standard process.

[0105] The preparation method provided by the present application will be described in detail below in combination with the preparation process flowchart shown in Figure 14 It should be noted that, Figure 14 the steps with "*" in the middle adopt a photoetching mask plate different from the mask plate used in the conventional device preparation process.

[0106] S1: Preparing an epitaxial wafer, as shown in (a) of FIG. 1. Figure 14

[0107] Specifically, the epitaxial wafer can be grown by a metal organic chemical vapor deposition (MOCVD) system, and triethyl gallium (TEGa) is used as a Ga source, trimethyl aluminum (TMAl) is used as an Al source, ammonia (NH3) is used as an N source, and high-purity hydrogen (H2) is used as a carrier gas. The epitaxial wafer includes, from bottom to top, a substrate layer, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

[0108] S2: Manufacturing alignment marks on the epitaxial wafer, as shown in (b) of FIG. 1. Figure 14

[0109] First, the epitaxial wafer is photoetched with an alignment mark pattern, specifically as follows:

[0110] (a) placing the sample on a hot plate at 200°C for pre-baking for 5 min;

[0111] ​​(b) coating photoresist (EPI621) on the sample, spin speed 3000 rad / min, spin time 40 sec, thickness of photoresist should be more than 800 nm, and then baking the sample on a hot plate at 90 °C for 1 min;

[0112] (c) exposing the sample with coated photoresist to light in a photoetching machine for 280 ms, and then baking the sample with exposed photoresist on a hot plate at 110 °C for 1 min;

[0113] (d) developing the sample with exposed photoresist in a developing solution (EPD1000) for 75 sec, and then rinsing the sample with ultrapure water and blowing dry with nitrogen;

[0114] (e) hard baking the sample before etching the pattern, and then baking the sample on a hot plate at 100 °C for 1 min;

[0115] Then, using an ICP etching process, the reaction gas is Cl2 and BCl3, Cl2 = 8 sccm, BCl3 = 20 sccm, pressure = 5 mT, upper electrode power = 50 W, and lower electrode power = 15 W, and the alignment mark pattern with a depth of more than 400 nm is etched on the epitaxial wafer.

[0116] Finally, the sample with etched alignment mark is cleaned to remove the residual photoresist on the surface.

[0117] S3, making ohmic contacts of source electrode and drain electrode on the epitaxial wafer, as shown in FIG. (c) of Figure 14 .

[0118] First, the source electrode area and the drain electrode area are photoetched on the barrier layer, as follows:

[0119] (a) baking the epitaxial wafer on a hot plate at 200 °C for 5 min;

[0120] (b) coating a stripping resist (PMGI SF6) on the barrier layer, spin speed 2000 rad / min, spin time 40 sec, and thickness of the stripping resist is 0.35 μm, and then baking the sample on a hot plate at 200 °C for 5 min;

[0121] (c) coating a photoresist (EPI621) on the stripping resist, spin speed 5000 rad / min, spin time 30 sec, and thickness of the photoresist is 0.77 μm, and then baking the sample on a hot plate at 90 °C for 1 min;

[0122] (d) Put the sample with finished coating and glue throwing into a photoetching machine to expose, adopt the Ohm area mask designed by the application, exposure time is 230 ms, and put the sample with finished exposure on a hot plate of 110℃ to bake for 1 min;

[0123] (e) Put into developing liquid (EPD1000) to remove photoresist and stripping glue, developing time is 45 sec, then wash with ultrapure water and dry with nitrogen, to obtain the source electrode area and drain electrode area defined by the application.

[0124] Then, evaporate the source electrode and drain electrode on the barrier layer in the source electrode and drain electrode Ohm area and the photoresist outside the source and drain Ohm area, as follows:

[0125] (a) Put the sample with active electrode and drain electrode photoetching pattern into a plasma glue removing machine to process the bottom film, power is 200 W, O2=100 sccm, processing time is 5 min;

[0126] (b) Put the sample into an electron beam evaporation table, after the reaction chamber of the electron beam evaporation table reaches a vacuum degree of 2×10 -6 Torr, evaporate metal on the barrier layer in the source electrode area and drain electrode area and the photoresist outside the source electrode area and drain electrode area to form the source electrode and drain electrode, the metal is in turn from bottom to top

[0127] (c) Strip the sample with finished metal evaporation to remove the metal, photoresist and stripping glue outside the source electrode and drain electrode, then wash the sample with ultrapure water and dry with nitrogen.

[0128] Finally, put the sample with finished metal evaporation and stripping into a rapid thermal annealing furnace for annealing treatment, so that the metal on the surface of the barrier layer in the area where the source electrode and drain electrode are located sinks to the channel layer, thereby forming good Ohm contact between the electrode and the heterojunction channel, wherein the annealing atmosphere is N2, the annealing temperature is 840℃, and the annealing time is 60 s.

[0129] S4, isolate the active area on the epitaxial substrate by etching, as shown in the (d) of FIG. Figure 14 .

[0130] First, determine the position of the active area on the barrier layer by photoetching, as follows:

[0131] (a) Put the epitaxial substrate on a hot plate of 200℃ to pre-bake for 5 min;

[0132] (b) coating photoresist (EPI621) on the surface of the epitaxial wafer, spinning speed 3000 rad / min, spinning time 30 sec, photoresist thickness greater than 800 nm, and then baking the sample on a hot plate at 90°C for 1 min;

[0133] (c) placing the sample with coated and spun photoresist into a photoetching machine for exposure, using the active region isolation mask designed in the application, exposure time 230 ms, and baking the exposed sample on a hot plate at 110°C for 1 min;

[0134] (d) removing the photoresist in a developing solution (EPD1000), developing time 75 sec, and then rinsing the sample with ultrapure water and drying it with nitrogen to obtain the active region defined in the application;

[0135] (e) hardening the film before etching, and baking the sample on a hot plate at 100°C for 1 min.

[0136] Then, using ICP technology, etching down to remove a portion of the sample surface outside the active region with a thickness of about 120 nm, ensuring that the region outside the active region on the epitaxial wafer does not have the ability to conduct current, etching reaction gas Cl2 and BCl3, Cl2 = 8 sccm, BCl3 = 20 sccm, pressure = 5 mT, upper electrode power = 50 W, lower electrode power = 15 W.

[0137] Finally, cleaning the etched sample to remove residual photoresist on the surface.

[0138] It can be understood that the active region isolation in step S4 can also be achieved by ion implantation, and the detailed implementation process can refer to the related prior art, which is not specifically introduced in this embodiment.

[0139] S5, on the surface of the epitaxial wafer on which the source electrode and the drain electrode are prepared, growing a dielectric layer using a plasma-enhanced chemical vapor deposition process, as shown in the (e) of FIG. Figure 14 .

[0140] First, surface cleaning the sample on which the source electrode and the drain electrode are prepared, as follows:

[0141] (a) placing the sample in an acetone solution for ultrasonic cleaning for 5 min;

[0142] (b) placing the sample in a stripping solution at a temperature of 60°C for water bath heating for 15 min;

[0143] (c) placing the sample in an acetone solution and an isopropyl alcohol solution for ultrasonic cleaning for 3 min, respectively;

[0144] (d) rinsing the sample with ultrapure water and drying it with nitrogen.

[0145] Then, a passivation layer with a thickness of 120 nm is grown on the source electrode, the drain electrode and the barrier layer of the active region by a PECVD process. For example, the passivation layer is SiN, and the process conditions for growing the passivation layer are as follows: SiN (2% SiH4 / N2) = 200 sccm, NH3 = 2 sccm, N2 = 0 sccm, He = 200 sccm, pressure = 600 mT, temperature = 250 °C, power = 22 W, and deposition time = 25 min.

[0146] S6. A grid slot region is photoetched on the passivation layer, and the passivation layer in the grid slot region is etched by an inductively coupled plasma (ICP) process, as shown in (f) of FIG. 4. Figure 14

[0147] First, a grid slot region is photoetched on the passivation layer, and the photoetching is performed as follows:

[0148] (a) The sample is placed on a hot plate at 200 °C for pre-baking for 5 min;

[0149] (b) Electron beam photoresist is coated and spun on the sample at a spinning speed of 3500 rad / min for 40 s to form a photoresist layer with a thickness of 450 nm, and the sample is placed on a hot plate at 150 °C for baking for 1 min;

[0150] (c) The sample is placed in an electron beam lithography machine to expose the photoresist in the grid slot region;

[0151] (d) The sample after the exposure is placed in a developing solution to remove the photoresist in the grid slot region, and the sample is blown dry with nitrogen after the development is completed;

[0152] (e) The sample is placed on a hot plate at 130 °C for baking for 1 min before the grid slot is etched.

[0153] Then, the passivation layer in the grid slot region is removed by an ICP etching process, and the etching conditions are as follows: CF4 = 60 sccm, O2 = 2 sccm, pressure = 5 mT, upper electrode power = 100 W, and lower electrode power = 25 W. The etching depth is equal to the thickness of the SiN layer.

[0154] Finally, the sample after the grid slot etching is cleaned to remove the residual photoresist on the surface.

[0155] S7. A grid electrode region is photoetched, and the grid electrode is fabricated by an electron beam evaporation process, as shown in (g) of FIG. 4. Figure 14

[0156] First, a grid electrode region is photoetched on the barrier layer, and the photoetching is performed as follows:

[0157] (a) The sample is placed on a hot plate at 200 °C for pre-baking for 5 min; ​​

[0158] (b) On the passivation layer, the stripping glue (PMGI SF6) is coated, the spinning speed is 1000 rad / min, the spinning time is 40 sec, the spinning thickness is 0.5 μm, and then the sample is baked on a hot plate at 200 °C for 5 min;

[0159] (c) On the stripping glue, the photoresist (EPI621) is coated, the spinning speed is 5000 rad / min, the spinning time is 30 sec, the spinning thickness is 0.77 μm, and then the sample is baked on a hot plate at 90 °C for 1 min;

[0160] (d) The sample with completed coating and spinning is put into a photoetching machine to expose the coated surface, the exposure time is 280 ms, and the sample with completed exposure is baked on a hot plate at 110 °C for 1 min;

[0161] (e) The photoresist and stripping glue are removed by putting into a developing solution (EPD1000) for 60 sec, and then the sample is washed with ultrapure water and dried with nitrogen.

[0162] Then, the gate electrode is evaporated on the barrier layer in the gate electrode area and the photoresist outside the gate electrode area, as follows:

[0163] (a) The sample with the gate electrode photoetching pattern is put into a plasma stripping machine for bottom film processing, the power is 200 W, O2= 100 sccm, and the processing time is 5 min;

[0164] (b) The sample is put into an electron beam evaporation table, and after the reaction chamber of the electron beam evaporation table reaches a vacuum degree of 2 x 10 - 6 Torr, the gate metal is evaporated on the barrier layer in the gate electrode area and the photoresist outside the gate electrode area, the gate metal is from bottom to top in turn

[0165] (c) The sample with completed gate metal evaporation is stripped to remove the gate metal, photoresist and stripping glue outside the gate electrode area, and then the sample is washed with ultrapure water and dried with nitrogen to form the gate electrode.

[0166] S8, the metal interconnection opening area is photoetched on the passivation layer, and the passivation layer in the metal interconnection opening area is etched by ICP process, as shown in the (h) figure in ​ .

[0167] First, the metal interconnection opening area is photoetched on the passivation layer, as follows:

[0168] (a) The sample is pre-baked on a hot plate at 200 °C for 5 min;

[0169] (b) spin-coating a photoresist (EPI621) on the sample at a spin speed of 3000 rpm for 30 seconds, and then baking the sample on a hot plate at 90 °C for 1 minute;

[0170] (c) exposing the surface of the sample on which the photoresist has been coated to light in a photoetching machine for 280 ms, and then baking the sample on a hot plate at 110 °C for 1 minute;

[0171] (d) developing the sample on which the photoresist has been exposed in a developer (EPD1000) for 75 seconds to remove the photoresist in the interconnection opening region, and then rinsing the sample with ultrapure water and drying it with nitrogen;

[0172] (e) hard-baking the sample before etching the metal interconnection opening region, and then baking the sample on a hot plate at 100 °C for 1 minute.

[0173] Then, the ICP etching process is used to remove the passivation layer in the interconnection opening region, with CF4and O2as the reaction gases, CF4= 60 sccm, O2= 2 sccm, pressure = 5 mT, upper electrode power = 100 W, and lower electrode power = 25 W.

[0174] Finally, the sample on which the interconnection opening region has been etched is cleaned to remove the photoresist remaining on the surface.

[0175] S9, photoetching the region of the metal interconnection layer on the source electrode and the drain electrode of the metal interconnection opening region and the passivation layer that has not been etched, and then using the electron beam evaporation process to form the metal interconnection layer, as shown in (i) of FIG. 1. ​

[0176] First, the region of the metal interconnection layer on the source electrode and the drain electrode of the metal interconnection opening region and the passivation layer that has not been etched is photoetched, as follows:

[0177] (a) baking the sample on which the metal interconnection opening region has been etched on a hot plate at 200 °C for 5 minutes;

[0178] (b) spin-coating a photoresist (EPI621) on the sample at a spin speed of 3000 rpm for 30 seconds, and then baking the sample on a hot plate at 90 °C for 1 minute;

[0179] (c) spin-coating a photoresist (EPI621) on the sample at a spin speed of 3000 rpm for 30 seconds, and then baking the sample on a hot plate at 90 °C for 1 minute;

[0180] ​(d) Put the sample with completed glue coating and glue throwing into a photoetching machine to expose the surface with coated glue, exposure time 270 ms, and put the sample with completed exposure into a hot plate at 110 DEG C to bake for 1 min;

[0181] (e) Put into a developing solution (EPD1000) to remove photoresist and stripping glue in the metal interconnection area, developing time 60 sec, and then rinse with ultrapure water and dry with nitrogen.

[0182] Then, evaporate the metal interconnection layer on the electrode and passivation layer in the metal interconnection area and the photoresist outside the metal interconnection area, as follows:

[0183] (a) Put the sample with metal interconnection area into a plasma glue removing machine to perform bottom film processing, power 200 W, O2=100 sccm, processing time 5 min;

[0184] (b) Put the sample into an electron beam evaporation station, and after the reaction chamber of the electron beam evaporation station reaches a vacuum degree of 2x10 - 6 Torr, evaporate the interconnection metal on the electrode and passivation layer in the metal interconnection area and the photoresist outside the metal interconnection area to form a metal interconnection layer, which is sequentially composed of a lead-out electrode,

[0185] (c) Strip the sample with completed interconnection metal evaporation to remove the metal, photoresist and stripping glue outside the metal interconnection layer, and rinse the sample with ultrapure water and dry with nitrogen.

[0186] Thus far, the preparation of the asymmetric active region device is completed.

[0187] In summary, the asymmetric active region device provided by the present application has the following beneficial effects:

[0188] Firstly, the nonlinearity of the GaN HEMT can be improved; secondly, compared with the device-level linearization technology reported in the prior art, only the photoetching mask for isolating the ohmic and active regions is changed on the basis of the conventional process, so the process complexity is low and the process period is short; finally, since only the mask in the standard process is changed, greater design margin and process window are provided for improving other performances (such as working frequency and output power) of the device.

[0189] In the description of the application, it needs to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the application.

[0190] In the present application, unless otherwise explicitly specified and limited, "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, "on", "above" and "over" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is higher in horizontal height than the second feature. "Under", "below" and "under" of the first feature to the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the first feature is lower in horizontal height than the second feature.

[0191] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present application.

[0192] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or replacements can be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A device based on active region driving force redistribution, characterized in that, The device includes: a substrate layer, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, and a gate electrode; The substrate layer, the nucleation layer, the buffer layer, the channel layer, and the barrier layer are stacked sequentially from bottom to top to form an epitaxial substrate; An active electrode active region and a drain electrode active region are formed in the epitaxial substrate; The source electrode and the drain electrode are respectively disposed on one side of the source active region and on one side of the drain active region; the gate electrode is disposed between the source electrode and the drain electrode; The source active region and the drain active region are asymmetrically distributed on both sides of the gate electrode to form an asymmetrical active region, thereby realizing the redistribution of the driving capability of the source active region and the drain active region of the device. The source active region has a rectangular structure, and the drain active region has a bulge-shaped structure with concave ends and protruding middle in the width direction, so as to increase the difference between the length of the source active region and the length of the drain active region. Alternatively, the source active region may be a rectangular structure, and the drain active region may be a bowl-shaped structure with protruding ends and a concave middle in the width direction, so as to increase the difference between the length of the source active region and the length of the drain active region. Alternatively, the source active region may be rectangular, the drain active region may be comb-shaped in the width direction, and the drain electrodes may be array-shaped with no obstruction between adjacent arrays, so that the width of the source active region is greater than the width of the drain active region, and the difference between the length of the source active region and the length of the drain active region is increased.

2. A device layout structure based on active region driving force redistribution, characterized in that, The layout structure includes a device core region, which includes a source active region, a source electrode, a drain active region, a drain electrode, and a gate electrode. The source and drain active regions are asymmetrically distributed on both sides of the gate electrode. The device core region adopts the active region design scheme of the device based on the redistribution of active region driving force as described in claim 1, and leads out metal PADs through T-shaped or U-shaped interconnection to realize probe testing.

3. A method for fabricating a device based on active region driving force redistribution, used to fabricate the device based on active region driving force redistribution as described in claim 1, characterized in that, The preparation method includes the following steps: A core layer, a buffer layer, a channel layer, and a barrier layer are sequentially fabricated on a substrate to form an epitaxial substrate; Using a pre-prepared asymmetric ohmic region mask, the source electrode region and the drain electrode region are photolithographically etched on the barrier layer, and the source electrode and the drain electrode are fabricated. Using a pre-prepared asymmetric active region mask, active regions are isolated on the epitaxial substrate to form asymmetric source and drain active regions; A dielectric layer is formed on the source electrode, the drain electrode, and the barrier layer; The gate electrode region is photolithographically etched and etched on the dielectric layer, and a gate electrode is fabricated within the gate electrode region; the gate electrode is located between the source electrode and the drain electrode. The dielectric layer above the source electrode and the drain electrode is removed, and a metal interconnect layer is fabricated to complete the device fabrication.

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