A GaN HEMT with strong non-pincer inductive switch capability under irradiation scene and a preparation method thereof

Abstract

The application provides a GaN HEMT with strong non-clamping inductive switching capability under irradiation and a preparation method thereof, and belongs to the technical field of semiconductors. The GaN HEMT comprises a substrate layer, a gallium nitride layer, a passivation layer, a channel layer, a barrier layer and an electrode structure layer. The electrode structure layer comprises a gate structure, a source structure and a drain structure arranged on both sides of the gate structure. The gate structure is in a strip shape and is arranged above the barrier layer along a first direction. The source structure and the drain structure are connected with the channel layer. A plurality of rectangular P-type gallium nitride layers arranged in groups are arranged between the gate structure and the drain structure. The plurality of rectangular P-type gallium nitride layers arranged in groups are uniformly and spacedly arranged along the first direction and are connected through metal wires. The top of the metal wires is connected with a negative potential electrode. The region between the barrier layer and the negative potential electrode is filled with a dielectric layer. The technical problem that the normal switching capability of a device and the degradation of overvoltage robustness of a traditional HEMT are affected due to the accumulation of holes after irradiation can be solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) materials possess advantages such as high breakdown voltage, high critical breakdown field strength, high saturated carrier mobility, high thermal conductivity, high power quality factor, and good radiation tolerance. In recent years, GaN power electronic devices, represented by high electron mobility transistors (HEMTs), and power systems composed of GaN, have been widely used in aerospace, nuclear detection, and special military equipment. GaN HEMTs must achieve fast switching capabilities, and fast switching in power systems can lead to the generation of instantaneous strong voltage pulses. This necessitates that power devices possess robustness under strong instantaneous overvoltage pulses.

[0003] In related technologies, unclamped inductive switch (UIS) testing can effectively simulate overvoltage conditions in actual switching scenarios and is currently a common test for the overvoltage robustness of power electronic devices. Furthermore, in extreme and special operating environments such as space stations and nuclear power plants, power electronic devices and systems are exposed to radiation induced by particles such as heavy ions, protons, neutrons, X-rays, and gamma rays. The radiation excitation inside HEMT devices easily generates a large number of excess charge carriers, which severely affects and degrades the device's normal switching capability and overvoltage robustness, even threatening the safe operation of the entire electronic system. Summary of the Invention

[0004] This invention provides a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions and its fabrication method. It solves the technical problem in existing HEMTs where hole accumulation after irradiation affects the device's normal switching capability and overvoltage robustness, leading to degradation. The technical solution is as follows:

[0005] In a first aspect, the present invention provides a GaN HEMT with strong non-clamping inductive switching ability in an irradiation scenario, including a substrate layer, a gallium nitride layer, a passivation layer, a channel layer, a barrier layer, and an electrode structure layer arranged from bottom to top. The electrode structure layer includes a gate structure, a source structure, and a drain structure arranged on both sides of the gate structure. The gate structure is strip-shaped and arranged above the barrier layer along a first direction. The source structure and the drain structure are both connected to the channel layer. A plurality of rectangular P-type gallium nitride layers arranged in groups are provided between the gate structure and the drain structure. The plurality of rectangular P-type gallium nitride layers arranged in groups are evenly spaced along the first direction and are connected at the top by a metal wire. A negative potential electrode is connected to the top of the metal wire. The region between the barrier layer and the negative potential electrode is filled with a dielectric layer.

[0006] Optionally, multiple groups of the rectangular P-type gallium nitride layers are provided between the gate structure and the drain structure. The multiple groups of rectangular P-type gallium nitride layers are evenly spaced along a second direction, and the second direction is perpendicular to the first direction.

[0007] Optionally, front metal and rear metal arranged along the second direction are respectively provided at both ends of the multiple groups of rectangular P-type gallium nitride layers in the first direction. The multiple groups of rectangular P-type gallium nitride layers are respectively connected to the front metal and the rear metal through the metal wire to form an interdigital structure. The front metal and the rear metal are connected to the negative potential electrode.

[0008] Optionally, between adjacent two groups of the rectangular P-type gallium nitride layers, the connection line between the rectangular center of any one rectangular P-type gallium nitride layer and the rectangular center of the rectangular P-type gallium nitride layer closest to it in the other group is arranged at an angle with the second direction.

[0009] Optionally, the range of the length L of the rectangular P-type gallium nitride layer in the first direction is 0 < L < 100 μm, the range of the width W of the rectangular P-type gallium nitride layer in the second direction is 1 < W < 100 μm, and the range of the spacing Lp between adjacent rectangular P-type gallium nitride layers in each group of rectangular P-type gallium nitride layers is L < Lp < 100 μm.

[0010] Optionally, the source structure includes a source ohmic metal layer, a source top metal layer, and a source arranged from bottom to top. The drain structure includes a drain ohmic metal layer, a drain top metal layer, and a drain arranged from bottom to top. The top height of the metal wire is lower than the bottom height of the drain top metal layer.

[0011] Optionally, in the first direction, the front metal and the rear metal are respectively located on both sides of the drain top metal layer.

[0012] Optionally, the width of the front metal and the rear metal in the first direction ranges from 10 to 50 μm.

[0013] Optionally, the dielectric layer is a silicon dioxide, silicon nitride, or aluminum oxide layer.

[0014] In a second aspect, embodiments of the present invention provide a preparation method for fabricating a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions as described in the first aspect, comprising:

[0015] Step 1: The epitaxial wafer is grown sequentially from bottom to top, consisting of the substrate layer, the gallium nitride layer, the passivation layer, the channel layer, the barrier layer, and the dielectric layer;

[0016] Step 2: Etch and deposit the source structure and the drain structure that are connected to the channel layer on the barrier layer;

[0017] Step 3: Etch and deposit the gate structure and the plurality of rectangular P-type gallium nitride layers located between the gate structure and the drain structure on the dielectric layer;

[0018] Step 4: Deposit Schottky metal on the plurality of rectangular P-type gallium nitride layers to obtain the metal lines;

[0019] Step 5: Continue to deposit dielectric layers on the entire device, and etch and deposit negative potential electrodes connected to the metal lines above the plurality of rectangular P-type gallium nitride layers.

[0020] The beneficial effects of the technical solution provided by this invention include at least the following:

[0021] The GaN HEMT with strong non-clamped inductive switching capability under irradiation conditions provided by this invention distributes multiple orderly arranged rectangular P-type gallium nitride layers in the region between the drain and gate structures. This allows holes generated under irradiation, especially those generated between the rectangular P-type gallium nitride layers and the drain structure, to flow through the gaps between the multiple rectangular P-type gallium nitride layers. This avoids damage to the transistor's conductive channel after adding the region of P-type gallium nitride material, ensuring good conduction characteristics of the device. At the same time, by applying a negative potential bias voltage to the negative potential electrode set above the multiple rectangular P-type gallium nitride layers, the holes can be effectively discharged through the discharge channel formed by the multiple rectangular P-type gallium nitride layers, the metal line, and the negative potential electrode. Furthermore, by additionally setting a channel layer and a passivation layer between the barrier layer and the gallium nitride layer, two-dimensional hole gas is generated at the junction of the passivation layer and the channel layer due to polarization. While applying a negative bias voltage to the upper rectangular P-type gallium nitride layer region, holes can be simultaneously conducted from below the barrier layer, helping excess induced holes collected in the two-dimensional hole gas to exit the channel, further improving the hole drainage efficiency. This avoids the increase in local electric field peaks and the generation of leakage channels caused by hole accumulation near the gate structure, effectively improving the non-clamped inductive switching capability of HEMTs under irradiation conditions. It solves the technical problem in existing HEMTs where hole accumulation after irradiation affects the normal switching capability and overvoltage robustness degradation. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a conventional GaN HEMT device structure in related technologies;

[0024] Figure 2 This is a schematic diagram of the steps for fabricating a GaN HEMT substrate layer, gallium nitride layer, passivation layer, channel layer, barrier layer, and dielectric layer under irradiation conditions, as provided in this embodiment of the invention.

[0025] Figure 3 This is a schematic diagram illustrating the steps involved in fabricating the source and drain structures of a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions, as described in this embodiment of the invention.

[0026] Figure 4 This is a schematic diagram of the steps for fabricating the gate structure and rectangular P-type gallium nitride layer of a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions in an embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of the steps for fabricating a GaN HEMT metal wire with strong non-clamping inductive switching capability under irradiation conditions in an embodiment of the present invention.

[0028] Figure 6 This is a schematic diagram illustrating the steps for further fabricating the source, drain, and gate structures of a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions, as provided in this embodiment of the invention.

[0029] Figure 7 This is a schematic diagram of the fabrication and etching of a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions, provided in an embodiment of the present invention.

[0030] Figure 8 This is a three-dimensional structural schematic diagram of a GaN HEMT with strong non-clamping inductive switching capability under irradiation scenarios provided in this embodiment of the invention.

[0031] Figure 9 This is a flowchart of the preparation method provided in the embodiments of the present invention.

[0032] In the diagram: 1-Substrate layer; 2-Gallium nitride layer; 3-Passivation layer; 4-Channel layer; 5-Barrier layer; 6-Electrode structure layer; 7-Dielectric layer; 61-Gate structure; 62-Source structure; 63-Drain structure; 64-Rectangular P-type gallium nitride layer; 65-Metal line; 66-Negative potential electrode; 71-Etched hole; 611-Gate gallium nitride layer; 612-Gate metal layer; 613-Gate; 621-Source ohmic metal layer; 622-Source top metal layer; 623-Source; 631-Drain ohmic metal layer; 632-Drain top metal layer; 633-Drain; 641-Front metal; 642-Back metal; 64a-First rectangular P-type gallium nitride layer group; 64b-Second rectangular P-type gallium nitride layer group; m-Conventional drain; n-Conventional source; o-Conventional gate. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0034] Figure 1 This is a schematic diagram of a conventional GaN HEMT device structure in related technologies. For example... Figure 1As shown, in existing GaN HEMTs, the conventional drain m is typically forward biased during operation. When excess electron-hole pairs are generated in a GaN HEMT under irradiation, electrons can be discharged from the conventional drain m under the forward bias. However, holes cannot cross the potential barrier or penetrate the dielectric layer, so they cannot be discharged and will accumulate in the region near the conventional gate o located between the conventional source n and the conventional drain m, affecting the electric field distribution in this region and potentially forming a conductive path near the conventional gate o. When the device is in a fast switching state, its overvoltage robustness will be greatly reduced, and in severe cases, it may cause the transistor to lose its switching capability or even burn out completely.

[0035] Figure 2 This is a schematic diagram of the steps for fabricating a GaN HEMT substrate layer, gallium nitride layer, passivation layer, channel layer, barrier layer, and dielectric layer under irradiation conditions, as provided in this embodiment of the invention.

[0036] Figure 3 This is a schematic diagram illustrating the steps involved in fabricating the source and drain structures of a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions, as described in this embodiment of the invention. Figure 4 This is a schematic diagram of the steps for fabricating the gate structure and rectangular P-type gallium nitride layer of a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions in an embodiment of the present invention. Figure 5 This is a schematic diagram of the steps for fabricating a GaN HEMT metal wire with strong non-clamping inductive switching capability under irradiation conditions in an embodiment of the present invention. Figure 6 This is a schematic diagram illustrating the steps for further fabricating the source, drain, and gate structures of a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions, as provided in this embodiment of the invention. Figure 7 This is a schematic diagram of the fabrication and etching of a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions, provided in an embodiment of the present invention. Figure 8 This is a three-dimensional structural diagram of a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions provided in this embodiment of the invention.

[0037] like Figures 2 to 8As shown, based on the aforementioned deficiencies, this embodiment of the invention provides a GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions, comprising a substrate layer 1, a gallium nitride layer 2, a passivation layer 3, a channel layer 4, a barrier layer 5, and an electrode structure layer 6 arranged from bottom to top. The electrode structure layer 6 includes a gate structure 61 and a source structure 62 and a drain structure 63 disposed on both sides of the gate structure 61. The gate structure 61 is strip-shaped and disposed above the barrier layer 5 along a first direction. The source structure 62 and the drain structure 63 are both connected to the channel layer 4. A plurality of rectangular P-type gallium nitride layers 64 are arranged in groups between the gate structure 61 and the drain structure 63. The plurality of rectangular P-type gallium nitride layers 64 are evenly spaced along the first direction and connected at their top by a metal line 65. A negative potential electrode 66 is connected to the top of the metal line 65. The region between the barrier layer 5 and the negative potential electrode 66 is filled with a dielectric layer 7.

[0038] In this embodiment of the invention, the GaN HEMT with strong non-clamping inductive switching capability under this irradiation scenario is fabricated as follows: Figure 2 As shown, firstly, a 0.65 mm thick substrate layer 1, a 300 μm thick gallium nitride layer 2, a 30 nm thick passivation layer 3, a 100 μm thick channel layer 4, and a 60 nm thick barrier layer 5 are sequentially grown on the epitaxial wafer from bottom to top. A 20 μm thick dielectric layer 7 is then deposited on the barrier layer 5. The passivation layer 3 and barrier layer 5 are made of AlGaN, the channel layer 4 is made of Si-doped n-type gallium nitride, and the dielectric layer 7 is made of any one or a combination of two or more of silicon dioxide, silicon nitride, or aluminum oxide, serving as the electrical isolation element for the transistor structure.

[0039] Afterwards, refer to Figure 3 The dielectric layer 7 and part of the barrier layer 5 are etched using inductively coupled plasma dry etching to create deposition regions for ohmic metal deposition. Ohmic metal is then deposited within these regions to obtain the source structure 62 and the drain structure 63. Exemplarily, in this embodiment of the invention, the source structure 62 includes a source ohmic metal layer 621, a top source metal layer 622, and a source 623 arranged from bottom to top. The drain structure 63 includes a drain ohmic metal layer 631, a top drain metal layer 632, and a drain 633 arranged from bottom to top. In this step, only the bottommost source ohmic metal layer 621 and drain ohmic metal layer 631 are deposited. Both have a length of 300 μm in the first direction and a width of 20 μm in the second direction. The source ohmic metal layer 621 and drain ohmic metal layer 631 form ohmic contacts with the gallium nitride of the channel layer 4.

[0040] Afterwards, refer to Figure 4The dielectric layer 7 is etched using inductively coupled plasma dry etching to create a deposition region for p-type gallium nitride (GaN) growth. A gate structure 61 and a plurality of neatly arranged rectangular GaN layers 64 are then deposited within this region. Exemplarily, in this embodiment of the invention, the gate structure 61 includes a gate GaN layer 611, a gate metal layer 612, and a gate 613 arranged from bottom to top. In this step diagram, only the bottom gate GaN layer 611 is deposited, formed by sequentially depositing a 10 nm layer of Schottky metal (Ni) and a 5 μm thick layer of Schottky metal (Al).

[0041] Afterwards, refer to Figure 5 Schottky metal is deposited on the deposited gate gallium nitride layer 611 to form a gate metal layer 612, thereby obtaining a complete gate structure 61. Schottky metal is deposited on a plurality of rectangular P-type gallium nitride layers 64 arranged in a group to obtain a metal line 65 connecting the plurality of rectangular P-type gallium nitride layers 64 in series.

[0042] Afterwards, refer to Figure 6 A 5μm thick dielectric layer 7, ranging from 100 to 300μm in thickness, is deposited on the entire device using plasma-enhanced chemical vapor deposition. Metal is then deposited on the source ohmic metal layer 621 and the drain ohmic metal layer 631, resulting in a 5μm thick top source metal layer 622 and a 5μm thick top drain metal layer 632 that extend towards but do not cover the gate structure 61, forming a field plate structure. The metal line 65 above the rectangular P-type gallium nitride layer 64 does not contact the bottom of the top drain metal layer 632 in the height direction, maintaining a 2μm gap.

[0043] Afterwards, refer to Figure 7 By using plasma-enhanced chemical vapor deposition, a dielectric layer 7 is deposited on the entire device. Vertical etching holes 71 are obtained by etching the dielectric layer in the areas where the source top metal layer 622, the drain top metal layer 632, the gate metal layer 612 of the gate structure 61, and the metal line 65 are located. Metal Al is deposited in these holes to form an interconnect structure. The diameter of the etching holes 71 is approximately 2 μm.

[0044] Finally, refer to Figure 8 A 10μm thick metal electrode is deposited in different regions on the top surface of the dielectric layer 7. The top metal layer 622 of the source is connected to the deposited source 623 through the interconnect metal above. The gate metal layer 612 is connected to the deposited gate 613 through the interconnect metal above. The top metal layer 632 of the drain is connected to the deposited drain 633 through the interconnect metal above. The metal line 65 is connected to the negative potential electrode 66 deposited above multiple rectangular P-type gallium nitride layers 64 through the interconnect metal, thus completing the fabrication of the device structure.

[0045] The GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions provided in this embodiment of the invention utilizes multiple orderly arranged rectangular P-type gallium nitride layers 64 distributed in the region between the drain structure 63 and the gate structure 61. This allows holes generated under irradiation, especially those generated between the rectangular P-type gallium nitride layers 64 and the drain structure 63, to flow through the gaps between the multiple rectangular P-type gallium nitride layers 64. This avoids damage to the transistor's conductive channel after the addition of the P-type gallium nitride material, ensuring good conduction characteristics of the device. At the same time, by applying a negative potential bias voltage to the negative potential electrode 66 provided above the multiple rectangular P-type gallium nitride layers 64, the holes can be effectively discharged through the discharge channel formed by the multiple rectangular P-type gallium nitride layers 64, the metal line 65, and the negative potential electrode 66. Furthermore, by additionally setting a channel layer 4 and a passivation layer 3 between the barrier layer 5 and the gallium nitride layer 2, a two-dimensional hole gas is generated at the junction of the passivation layer 3 and the channel layer 4 due to polarization. While applying a negative potential bias voltage to the region of the upper rectangular P-type gallium nitride layer 64, holes can be simultaneously conducted from below the barrier layer, helping excess induced holes collected in the two-dimensional hole gas to be discharged from the channel, further improving the hole discharge efficiency. This avoids the increase in local electric field peaks and the generation of leakage channels caused by hole accumulation near the gate structure 61, effectively improving the non-clamped inductive switching capability of HEMT under irradiation. It solves the technical problem in the prior art where hole accumulation after irradiation affects the normal switching capability and overvoltage robustness degradation of traditional HEMTs.

[0046] Preferably, multiple sets of rectangular P-type gallium nitride (GaN) layers 64 are disposed between the gate structure 61 and the drain structure 63. These multiple sets of rectangular P-type GaN layers 64 are evenly spaced along a second direction, which is perpendicular to the first direction. Exemplarily, in this embodiment of the invention, five sets of rectangular P-type GaN layers 64, arranged in columns along the first direction, are provided. The column closest to the drain structure 63 is designated as the first column, and they are sequentially arranged parallel to each other towards the gate structure 61 along the second direction. The odd-numbered columns (i.e., columns 1, 3, and 5) are designated as the first rectangular P-type GaN layer group 64a; the even-numbered columns (i.e., columns 2 and 4) are designated as the second rectangular P-type GaN layer group 64b. By providing multiple sets of rectangular P-type GaN layers 64, multiple entrances for collecting and discharging holes are formed between the gate structure 61 and the drain structure 63, improving the hole discharge efficiency. Simultaneously, it avoids excessively large unused distances between the gate structure 61 and the drain structure 63, preventing increased device area from affecting the normal performance of the transistor.

[0047] Preferably, multiple sets of rectangular P-type gallium nitride layers 64 have front metal 641 and rear metal 642 arranged along the second direction at both ends in the first direction. The multiple sets of rectangular P-type gallium nitride layers 64 are connected to the front metal 641 and rear metal 642 respectively through metal lines 65 to form an interdigitated structure. The front metal 641 and rear metal 642 are connected to the negative potential electrode 66. Exemplarily, in this embodiment of the invention, the first rectangular P-type gallium nitride layer group 64a is connected to the front metal 641 through the metal line 65 provided on the top surface, and the second rectangular P-type gallium nitride layer group 64b are all connected to the rear metal 642 on the other side in the first direction through the metal line 65 provided on the top surface, forming an interdigitated structure. The etching hole 71 structure for connecting to the upper negative potential electrode 66 can be centrally disposed on the front metal 641 and rear metal 642, avoiding the need to separately set etching holes 71 above the metal lines 65 of the multiple sets of rectangular P-type gallium nitride layers 64 to connect to the negative potential electrode 66, and reducing the manufacturing difficulty through reasonable arrangement planning.

[0048] For example, in an embodiment of the present invention, the width of the front metal 641 and the rear metal 642 in the first direction ranges from 10 to 50 μm.

[0049] Furthermore, in the first direction, the front metal 641 and the rear metal 642 are located on both sides of the top drain metal layer 632. This arrangement, without affecting device performance, connects the top negative potential electrode 66 via the front metal 641 and the rear metal 642, eliminating the need for etching holes 71 above the grouped rectangular p-type gallium nitride layers 64. This allows for a larger negative potential electrode without significantly increasing the device area. A larger negative potential electrode facilitates subsequent transistor packaging and testing. Reducing the device size further increases the layout utilization of the transistor structure pattern area, which is beneficial for improving the induced charge extraction capability of gallium nitride p-GaN enhancement transistors under irradiation conditions.

[0050] Preferably, between two adjacent groups of rectangular GaN P-type layers 64, the line connecting the center of any rectangular GaN P-type layer 64 to the nearest rectangular GaN P-type layer 64 in the other group forms an angle with the second direction. For example, in this embodiment of the invention, the angle between the line connecting the center of any rectangular GaN P-type layer 64 to the nearest rectangular GaN P-type layer 64 in the other group and the second direction is 45°. The first group of rectangular GaN P-type layers 64a consists of five rectangular GaN P-type layers 64, while the second group of rectangular GaN P-type layers 64b consists of four rectangular GaN P-type layers 64. This staggered arrangement further improves the hole ejection efficiency.

[0051] Optionally, the length L of the rectangular P-type gallium nitride layer 64 in the first direction ranges from 0 < L < 100 μm, the width W of the rectangular P-type gallium nitride layer 64 in the second direction ranges from 1 < W < 100 μm, and the spacing Lp between adjacent rectangular P-type gallium nitride layers 64 in each group of rectangular P-type gallium nitride layers 64 ranges from L < Lp < 100 μm. Exemplarily, in the embodiments of the present invention, the width of a single rectangular P-type gallium nitride layer 64 in the second direction is 20 μm, the length in the first direction is 20 μm. In the same group, the spacing between two adjacent rectangular P-type gallium nitride layers 64 in the first direction is 40 μm, the distance between the gate structure 61 and the drain structure 63 is 160 μm, and the spacing between the first rectangular P-type gallium nitride layer group 64a and the adjacent second rectangular P-type gallium nitride layer group 64b is 10 μm.

[0052] Figure 9 is a flowchart of the preparation method provided by the embodiments of the present invention. As Figure 9 shown, the embodiments of the present invention further provide a preparation method for fabricating a GaN HEMT with strong unclamped inductive switching ability under the irradiation scenario as Figures 1 to 8 shown. The method includes the following steps:

[0053] S1: An epitaxial wafer is sequentially grown with a substrate layer 1, a gallium nitride layer 2, a passivation layer 3, a channel layer 4, a barrier layer 5, and a dielectric layer 7 from bottom to top.

[0054] Specifically, first, a 0.65 mm thick substrate layer 1, a 300 μm thick gallium nitride layer 2, a 30 nm thick passivation layer 3, a 100 μm thick channel layer 4, a 60 nm thick barrier layer 5 are sequentially grown on the epitaxial wafer from bottom to top, and a 20 μm thick dielectric layer 7 is deposited as a whole layer on the barrier layer 5. Among them, the materials of the passivation layer 3 and the barrier layer 5 are AlGaN, the material of the channel layer 4 is Si-doped n-type gallium nitride, and the material of the dielectric layer 7 is any one or a combination of two or more of silicon dioxide, silicon nitride, or aluminum oxide, serving as the electrical isolation of the transistor structure.

[0055] S2: The source structure 62 and the drain structure 63 connected to the channel layer 4 are etched and deposited on the barrier layer 5.

[0056] Specifically, the dielectric layer 7 and part of the barrier layer 5 are etched using inductively coupled plasma dry etching to create deposition regions for depositing ohmic metal, and ohmic metal is deposited therein to obtain the source structure 62 and the drain structure 63. Exemplarily, in this embodiment of the invention, the source structure 62 includes a source ohmic metal layer 621, a top source metal layer 622, and a source 623 arranged from bottom to top; the drain structure 63 includes a drain ohmic metal layer 631, a top drain metal layer 632, and a drain 633 arranged from bottom to top. In this step diagram, only the bottommost source ohmic metal layer 621 and drain ohmic metal layer 631 are deposited, each with a length of 300 μm in the first direction and a width of 20 μm in the second direction. The source ohmic metal layer 621 and drain ohmic metal layer 631 form ohmic contacts with the gallium nitride of the channel layer 4.

[0057] S3: Etch and deposit a gate structure 61 and a plurality of rectangular P-type gallium nitride layers 64 between the gate structure 61 and the drain structure 63 on the dielectric layer 7.

[0058] Specifically, the dielectric layer 7 is etched using inductively coupled plasma dry etching to create a deposition region for p-type gallium nitride (GaN) growth, and a gate structure 61 and a plurality of neatly arranged rectangular GaN layers 64 are deposited therein. Exemplarily, in this embodiment of the invention, the gate structure 61 includes a gate GaN layer 611, a gate metal layer 612, and a gate 613 arranged from bottom to top. In this step diagram, only the bottom gate GaN layer 611 is formed by sequentially depositing a 10 nm layer of Schottky metal (Ni) and a 5 μm thick layer of Schottky metal (Al).

[0059] S4: Deposit Schottky metal on multiple rectangular P-type gallium nitride layers 64 to obtain metal lines 65.

[0060] Specifically, Schottky metal is deposited on the deposited gate gallium nitride layer 611 to form a gate metal layer 612, thereby obtaining a complete gate structure 61. Schottky metal is deposited on a plurality of rectangular P-type gallium nitride layers 64 arranged in a group to obtain a metal line 65 connecting the plurality of rectangular P-type gallium nitride layers 64 in series.

[0061] S5: Continue to deposit dielectric layer 7 over the entire device, and etch and deposit negative potential electrode 66 connected to metal line 65 above multiple rectangular P-type gallium nitride layers 64.

[0062] Specifically, a 5μm thick dielectric layer 7, ranging from 100 to 300μm, is deposited on the entire device using plasma-enhanced chemical vapor deposition. Metal is then deposited on the source ohmic metal layer 621 and the drain ohmic metal layer 631, resulting in a 5μm thick top metal layer 622 extending towards but not covering the gate structure 61, forming a field plate structure. The metal line 65 above the rectangular P-type gallium nitride layer 64 does not contact the bottom of the drain top metal layer 632 in the height direction, maintaining a 2μm gap.

[0063] Subsequently, a dielectric layer 7 is deposited on the entire device using plasma-enhanced chemical vapor deposition. Vertical etching holes 71 are obtained by etching the dielectric layer in the areas where the source top metal layer 622, drain top metal layer 632, gate metal layer 612 of gate structure 61, and metal line 65 are located. Metal Al is deposited in these holes to form an interconnect structure. The diameter of the etching holes 71 is approximately 2 μm.

[0064] Finally, 10μm thick metal electrodes are deposited in different regions on the top surface of the dielectric layer 7, so that the top metal layer 622 of the source is connected to the deposited source 623 through the interconnect metal above, the gate metal layer 612 is connected to the deposited gate 613 through the interconnect metal above, the top metal layer 632 of the drain is connected to the deposited drain 633 through the interconnect metal above, and the metal line 65 is connected to the negative potential electrode 66 deposited above the multiple rectangular P-type gallium nitride layers 64 through the interconnect metal, thus completing the fabrication of the device structure.

[0065] The GaN HEMT with strong non-clamping inductive switching capability under irradiation conditions, fabricated using the method provided in this embodiment of the invention, utilizes multiple orderly arranged rectangular P-type gallium nitride layers 64 distributed in the region between the drain structure 63 and the gate structure 61. This allows holes generated under irradiation, especially those generated between the rectangular P-type gallium nitride layers 64 and the drain structure 63, to flow through the gaps between the multiple rectangular P-type gallium nitride layers 64. This avoids damage to the transistor's conductive channel after the addition of the P-type gallium nitride material, ensuring good device conduction characteristics. At the same time, by applying a negative potential bias voltage to the negative potential electrode 66 positioned above the multiple rectangular P-type gallium nitride layers 64, the holes can be effectively discharged through the discharge channel formed by the multiple rectangular P-type gallium nitride layers 64, the metal line 65, and the negative potential electrode 66. Furthermore, by additionally setting a channel layer 4 and a passivation layer 3 between the barrier layer 5 and the gallium nitride layer 2, a two-dimensional hole gas is generated at the junction of the passivation layer 3 and the channel layer 4 due to polarization. While applying a negative potential bias voltage to the region of the upper rectangular P-type gallium nitride layer 64, holes can be simultaneously conducted from below the barrier layer, helping excess induced holes collected in the two-dimensional hole gas to be discharged from the channel, further improving the hole discharge efficiency. This avoids the increase in local electric field peaks and the generation of leakage channels caused by hole accumulation near the gate structure 61, effectively improving the non-clamped inductive switching capability of HEMT under irradiation. It solves the technical problem in the prior art where hole accumulation after irradiation affects the normal switching capability and overvoltage robustness degradation of traditional HEMTs.

[0066] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0067] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A GaN HEMT with strong non-pinning inductive switching capability under irradiation, characterized in that, The application relates to a gallium nitride transistor, which comprises, from bottom to top, a substrate layer (1), a gallium nitride layer (2), a passivation layer (3), a channel layer (4), a barrier layer (5) and an electrode structure layer (6), wherein the electrode structure layer (6) comprises a gate structure (61) and source and drain structures (62 and 63) arranged on both sides of the gate structure (61), the gate structure (61) is in a strip shape and arranged above the barrier layer (5) along a first direction, the source and drain structures (62 and 63) are connected with the channel layer (4), a plurality of rectangular P-type gallium nitride layers (64) arranged in groups are arranged between the gate structure (61) and the drain structure (63), the rectangular P-type gallium nitride layers (64) arranged in groups are uniformly spaced along the first direction and the top portions of the rectangular P-type gallium nitride layers (64) arranged in groups are connected by metal wires (65), the top portion of the metal wires (65) is connected with a negative potential electrode (66), and the region between the barrier layer (5) and the negative potential electrode (66) is filled with a dielectric layer (7).

2. The GaN HEMT with strong non-pinning inductive switching capability under irradiation scenario according to claim 1, characterized in that, A plurality of groups of the rectangular P-type gallium nitride layers (64) are arranged between the gate structure (61) and the drain structure (63), and the rectangular P-type gallium nitride layers (64) arranged in groups are uniformly spaced along a second direction, wherein the second direction is perpendicular to the first direction.

3. The GaN HEMT with strong non-pinning inductive switching capability under irradiation scenario according to claim 2, characterized in that, The two ends of the rectangular P-type gallium nitride layers (64) arranged in groups in the first direction are respectively provided with front and rear metals (641 and 642) arranged along the second direction, the rectangular P-type gallium nitride layers (64) arranged in groups are connected to the front and rear metals (641 and 642) through the metal wires (65) to form an interdigital structure, and the front and rear metals (641 and 642) are connected with the negative potential electrode (66).

4. The GaN HEMT with strong non-pinning inductive switching capability under irradiation scenario according to claim 2, characterized in that, Between two adjacent groups of the rectangular P-type gallium nitride layers (64), the line connecting the rectangular center of any rectangular P-type gallium nitride layer (64) and the rectangular center of the closest rectangular P-type gallium nitride layer (64) in another group is arranged at an angle with the second direction.

5. The GaN HEMT with strong non-pinning inductive switching capability under irradiation scenario according to claim 2, characterized in that, The length L of the rectangular P-type gallium nitride layer (64) in the first direction ranges from 0 to 100 mu m, the width W of the rectangular P-type gallium nitride layer (64) in the second direction ranges from 1 to 100 mu m, and the spacing Lp between adjacent rectangular P-type gallium nitride layers (64) in each group of the rectangular P-type gallium nitride layers (64) ranges from L to 100 mu m.

6. The GaN HEMT with strong non-pinning inductive switching capability under irradiation scenario according to claim 3, characterized in that, The source structure (62) comprises, from bottom to top, a source ohmic metal layer (621), a source top metal layer (622) and a source electrode (623), the drain structure (63) comprises, from bottom to top, a drain ohmic metal layer (631), a drain top metal layer (632) and a drain electrode (633), and the top portion of the metal wire (65) is lower than the bottom portion of the drain top metal layer (632).

7. The GaN HEMT with strong non-pinning inductive switching capability under irradiation according to claim 6, characterized in that, In the first direction, the front and rear metals (641 and 642) are respectively located on both sides of the drain top metal layer (632).

8. The GaN HEMT with strong non-pinning inductive switching capability under irradiation according to claim 7, characterized in that, The front metal (641) and the back metal (642) have a width ranging from 10 to 50 μm in the first direction.

9. The GaN HEMT with strong non-pinning inductive switching capability under irradiation according to any one of claims 1 to 8, characterized in that, The medium layer (7) is a silicon dioxide, silicon nitride or aluminum oxide layer.

10. A method of manufacture for making a GaN HEMT with strong non-pinning inductive switching capability under irradiation as claimed in any one of claims 1 to 8, characterized in that, Comprise: Step 1: epitaxial wafer grows the substrate layer (1), the gallium nitride layer (2), the passivation layer (3), the channel layer (4), the barrier layer (5) and the medium layer (7) from bottom to top in sequence; Step 2: etching and depositing the source structure (62) and the drain structure (63) connected with the channel layer (4) on the barrier layer (5); Step 3: etching and depositing the gate structure (61) and the plurality of rectangular P-type gallium nitride layers (64) between the gate structure (61) and the drain structure (63) on the medium layer (7); Step 4: depositing Schottky metal on the plurality of rectangular P-type gallium nitride layers (64) to obtain the metal line (65); Step 5: continuing to deposit the medium layer (7) on the whole device, etching and depositing the negative electrode (66) connected with the metal line (65) above the plurality of rectangular P-type gallium nitride layers (64).

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