Semiconductor structure, manufacturing method thereof and semiconductor device

Abstract

The invention discloses a semiconductor structure, a semiconductor device and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a substrate; the transistor structure is located on the surface of the substrate, the transistor structure comprises a channel region, a gate dielectric layer, a gate conducting layer, a source region and a drain region, the gate dielectric layer and the gate conducting layer are located over the channel region, the source region and the drain region are located on the two sides of the channel region, and the channel region is provided with a first top surface making contact with the gate dielectric layer; the source electrode region is provided with a second top surface, and the drain electrode region is provided with a third top surface; wherein the second top surface and the third top surface are both lower than the first top surface, and the semiconductor structure has high reliability and stability.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof, as well as a semiconductor device. Background Art

[0002] Image sensors are semiconductor devices that convert optical information into electrical signals. For example, image sensors can convert the variable attenuation of light waves into signals (i.e., small current bursts that convey information), and such image sensors can include charge coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. Based on the difference in light paths, CMOS image sensors can be further divided into front-illuminated (FSI) image sensors and back-illuminated (BSI) image sensors. Summary of the invention

[0003] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a transistor structure located on a surface of the substrate, the transistor structure comprising a channel region, a gate dielectric layer and a gate conductive layer located directly above the channel region, and a source region and a drain region located on both sides of the channel region, the channel region having a first top surface in contact with the gate dielectric layer, the source region having a second top surface, the drain region having a third top surface, the source region and the drain region being doped with first type ions; wherein the second top surface and the third top surface are both lower than the first top surface.

[0004] In some embodiments, the source region and / or the drain region further has a protrusion, which protrudes toward the channel region, so that the minimum distance between the source region and the drain region is the distance from the protrusion of one to the other or the protrusion of the other.

[0005] In some embodiments, the third top surface of the drain region is no higher than the second top surface of the source region.

[0006] In some embodiments, the semiconductor structure further includes: an isolation layer covering the gate conductive layer and the gate dielectric layer surface and located above the source region and the drain region, wherein a first bottom surface of the isolation layer is flush with the first top surface of the channel region.

[0007] In some embodiments, the semiconductor structure also includes: a first supplementary isolation layer, located between the isolation layer and the source region, the first supplementary isolation layer is in contact with the second top surface of the source region; a second supplementary isolation layer, located between the isolation layer and the drain region, the second supplementary isolation layer is in contact with the second top surface of the drain region; the material of the first supplementary isolation layer and the second supplementary isolation layer is an insulating dielectric material or a semiconductor dielectric material.

[0008] In some embodiments, the material of the first supplementary isolation layer and the second supplementary isolation layer is a semiconductor dielectric material, and the first supplementary isolation layer and the second supplementary isolation layer are doped with second type ions, and the second type ions are of opposite types to the first type ions, and are N-type and P-type to each other.

[0009] In some embodiments, the thickness of the first supplementary isolation layer and the second supplementary isolation layer are both in the range of 3-10 nm.

[0010] In some embodiments, the channel region is doped with third type ions, and the third type ions are of the same type as the first type ions, both of which are N-type or P-type.

[0011] In some embodiments, the channel region includes a shallow layer and a deep layer, the shallow layer is located above the deep layer and in contact with the gate dielectric layer, and the first top surface is the top surface of the shallow layer; wherein the shallow layer is doped with fourth type ions, and the deep layer is doped with fifth type ions, the fourth type ions and the fifth type ions are of opposite types, being N type and P type respectively, and the fifth type ions are of the same type as the first type ions, both being N type or P type.

[0012] In some embodiments, the semiconductor structure further includes: contacts respectively inserted into the gate conductive layer, the source region, and the drain region.

[0013] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate; forming a channel region having a first top surface and an initial source region and an initial drain region on both sides of the channel region on the surface of the substrate, the top surfaces of the initial source region and the initial drain region being coplanar with the first top surface; thinning the initial source region and the initial drain region to obtain a source region having a second top surface and a drain region having a third top surface, wherein the second top surface and the third top surface are both lower than the first top surface; forming a gate dielectric layer and a gate conductive layer in sequence directly above the channel region, the first top surface being in contact with the gate dielectric layer, and the source region, the drain region, the channel region, the gate dielectric layer and the gate conductive layer together constitute a transistor structure.

[0014] In some embodiments, a channel region having a first top surface and an initial source region and an initial drain region on both sides of the channel region are formed on the surface of the substrate, including: forming a first mask layer on the surface of the substrate; using the first mask layer as a mask, performing a first ion implantation on the substrate on both sides of the first mask layer, and performing annealing to form the initial source region and the initial drain region on the surface of the substrate on both sides of the first mask layer.

[0015] In some embodiments, after performing the first ion implantation and before performing the annealing, it also includes: reducing at least the width dimension of the first mask layer, using the reduced first mask layer as a mask, and performing a second ion implantation on the substrate on both sides of the reduced first mask layer, wherein the depth of the second ion implantation is less than the depth of the first ion implantation, and the ion doping type of the second ion implantation is the same as the ion doping type of the first ion implantation; after performing the annealing, protrusions protruding toward the channel region are formed in the initial source region and the initial drain region.

[0016] In some embodiments, the initial source region and the initial drain region are thinned, including: using the first mask layer or the reduced first mask layer as a mask, etching the initial source region and the initial drain region to remove part of the thickness, so that the remaining thickness of the initial source region serves as the source region and the remaining thickness of the initial drain region serves as the drain region; wherein the third top surface of the drain region is flush with the second top surface of the source region, or the third top surface of the drain region is lower than the second top surface of the source region.

[0017] In some embodiments, a first supplementary isolation layer is formed on the second top surface of the source region, and a second supplementary isolation layer is formed on the third top surface of the drain region, and the thickness of the first supplementary isolation layer and the second supplementary isolation layer is the same as the thickness of the portion that is etched away from the initial source region and the initial drain region.

[0018] In some embodiments, the initial source region and the initial drain region are thinned, including: using the first mask layer as a mask, performing a third ion implantation on the initial source region and the initial drain region to respectively form a first supplementary isolation layer on the surface of the initial source region and a second supplementary isolation layer on the surface of the initial drain region, the depth of the third ion implantation is less than the depth of the first ion implantation, and the ion doping type of the third ion implantation is opposite to the ion doping type of the first ion implantation; the thickness of the first supplementary isolation layer and the second supplementary isolation layer is equal to the depth of the third ion implantation, the remaining portion of the initial source region after removing the first supplementary isolation layer serves as the source region, and the remaining portion of the initial drain region after removing the second supplementary isolation layer serves as the drain region.

[0019] In some embodiments, after forming the source region and the drain region, it also includes: performing a fourth ion implantation on the channel region, the depth of the fourth ion implantation is lower than the second top surface and the third top surface, and the ion doping type of the fourth ion implantation is the same as the ion doping type of the first ion implantation; or, performing a fourth ion implantation and a fifth ion implantation on the channel region, the depth of the fourth ion implantation is lower than the second top surface and the third top surface, the depth of the fifth ion implantation is less than the depth of the fourth ion implantation, the ion doping type of the fourth ion implantation is the same as the ion doping type of the first ion implantation, and the ion doping type of the fifth ion implantation is opposite to the ion doping type of the first ion implantation.

[0020] In some embodiments, after performing the first ion implantation and before performing the annealing, it also includes: using the first mask layer as a mask, performing a sixth ion implantation on the substrate on both sides of the first mask layer, the implantation direction of the sixth ion implantation has an inclination angle toward the channel region, and the ion doping type of the sixth ion implantation is the same as the ion doping type of the first ion implantation; after performing the annealing, a protrusion protruding toward the channel region is formed in the initial source region and the initial drain region.

[0021] In some embodiments, after forming the gate dielectric layer and the gate conductive layer, it also includes: forming an isolation layer, covering the surface of the gate conductive layer and the gate dielectric layer, and being located above the source region and the drain region, wherein the first bottom surface of the isolation layer is flush with the first top surface of the channel region; forming contact pieces, wherein the contact pieces are respectively inserted into the gate conductive layer, the source region, and the drain region.

[0022] According to a third aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a source follower transistor, comprising the transistor structure in any semiconductor structure in the aforementioned embodiments; a photoelectric conversion element, used to generate charges through photoelectric conversion; a floating diffusion region, connected to the gate conductive layer of the source follower transistor, used to store the charges and generate a potential; a transfer transistor, respectively connected to the photoelectric conversion element and the floating diffusion region, used to transfer the charges from the photoelectric conversion element to the floating diffusion region; a reset transistor, connected to the floating diffusion region, used to reset the potential of the floating diffusion region; a selection transistor, connected in series with the source of the source follower transistor; wherein the source follower transistor is used to respond to changes in the potential of the floating diffusion region, amplify the changes in the potential to obtain signal changes, and output the signal changes through the selection transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of a semiconductor structure according to an exemplary related art;

[0024] Figure 2 is a schematic diagram of a semiconductor structure according to an exemplary embodiment 1;

[0025] Figure 3 is a schematic diagram of a semiconductor structure according to a second exemplary embodiment;

[0026] Figure 4 is a schematic diagram of a semiconductor structure according to a third exemplary embodiment;

[0027] Figure 5 is a schematic diagram of a semiconductor structure shown according to a fourth exemplary embodiment;

[0028] Figure 6 is a schematic diagram of a semiconductor structure shown according to a fifth exemplary embodiment;

[0029] Figure 7 is a schematic diagram of a semiconductor structure according to a sixth exemplary embodiment;

[0030] Figures 8A-8K is a schematic diagram of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0031] Figures 9A-9C is a schematic diagram of a method for manufacturing a protrusion in a semiconductor structure according to an exemplary embodiment;

[0032] Figures 10A-10B is a schematic diagram of a method for manufacturing a source region and a drain region in a semiconductor structure according to another exemplary embodiment;

[0033] Fig.11 The present invention is a schematic diagram of a method for manufacturing a first supplementary isolation layer and a second supplementary isolation layer in a semiconductor structure according to another exemplary embodiment.

[0034] Figures 12A-12B is a schematic diagram of a method for doping a channel region in a semiconductor structure according to an exemplary embodiment;

[0035] Fig.13 is a schematic diagram of a method for manufacturing a protrusion in a semiconductor structure according to another exemplary embodiment;

[0036] Fig.14 is a circuit diagram of a semiconductor device according to an exemplary embodiment;

[0037] Fig.15 is a schematic diagram of an imaging system according to an exemplary embodiment. DETAILED DESCRIPTION

[0038] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0039] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0040] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0041] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0042] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0043] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0044] In the related art, in the basic pixel unit circuit of CMOS Image Sensor (CIS), the source follower (SF) transistor is an important component, which is usually used to sense and amplify the change of photoelectric signal and output the corresponding sensing signal, such as Figure 1 The figure shows a schematic diagram of a semiconductor structure according to an exemplary related art, wherein the SF transistor includes a source 410, a drain 420, a channel 30 located between the source 410 and the drain 420, and a gate 20 and a gate dielectric layer 50, wherein the top surface S1 of the channel 30 is coplanar with the top surface S2 of the source 410 and the top surface S3 of the drain 420. However, the inventor of the present application found that during the manufacturing process of the SF transistor in the CIS, the top surface S1 of the channel 30, i.e., the contact interface between the channel 30 and the gate dielectric layer 50, is prone to introduce interface bound states / defect states (Dits) such as charge defects and dangling chemical bonds, and when the source follower transistor is in the working state, the carriers E0 in the channel 30 will continue to be bound and dissociated with the silicon / silicon dioxide interface bound states / defect states (Dits) at the interface S1, so that the output voltage of the source 410 has random transient fluctuations over time, thereby affecting the stability of the output voltage. In the related art, the bound state / defect state (Dit) at the interface S1 is difficult to remove or passivate through conventional approaches.

[0045] In view of the above technical problems, the present disclosure provides a semiconductor structure, a semiconductor device and a method for manufacturing the semiconductor structure. Figures 2 to 15 The present disclosure specifically introduces a semiconductor structure and a manufacturing method thereof, a semiconductor device and an imaging system exemplarily provided by the present disclosure. Figures 2 to 7 8 to 9 are schematic diagrams of semiconductor structures according to multiple exemplary embodiments of the present disclosure. Fig.13 is a schematic diagram of a method for manufacturing a semiconductor structure according to multiple exemplary embodiments of the present disclosure. Fig.14is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present disclosure. Fig.15 It is a schematic diagram of an imaging system according to an exemplary embodiment of the present disclosure.

[0046] In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, referring to Figure 2 As shown, the semiconductor structure includes: a substrate 1; a transistor structure, located on the surface of the substrate 1, and the transistor structure includes a channel region 3, a gate dielectric layer 5 and a gate conductive layer 2 located directly above the channel region 3, and a source region 41 and a drain region 42 located on both sides of the channel region 3. The channel region 3 has a first top surface TS1 in contact with the gate dielectric layer 5, the source region 41 has a second top surface TS2, and the drain region 42 has a third top surface TS3. The source region 41 and the drain region 42 are doped with first type ions, wherein the second top surface TS2 and the third top surface TS3 are both lower than the first top surface TS1. It should be noted that the height direction in the above is the direction in the figure that is upward away from and perpendicular to the substrate 1, and the "surface" in the above should be understood as the area near the surface, including not only part of the area above the surface, but also part of the shallow surface area below the surface.

[0047] The material of the substrate 1 may be at least one of the following materials: semiconductor materials or III-V materials such as silicon, germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI). In an exemplary embodiment of the present disclosure, the substrate 1 is a P-type silicon substrate formed by doping a single crystal silicon material with a trace amount of III-group elements, such as boron, aluminum, gallium or indium.

[0048] Continue to refer to Figure 2 As shown, the source region 41 and the drain region 42 are both located on the surface of the substrate 1, specifically, the source region 41 and the drain region 42 are both adjacent to the surface of the substrate 1 and are located in a partial shallow surface area below the surface of the substrate 1. In some embodiments, the first type of ions doped in the source region 41 and the drain region 42 are N-type, specifically, including ions of group V elements, such as ions of phosphorus, arsenic, antimony or bismuth. In an exemplary embodiment of the present disclosure, the source region 41 and the drain region 42 are both doped with arsenic ions. The channel region 3 is located on the surface of the substrate 1 between the source region 41 and the drain region 42, specifically, it is also adjacent to the surface of the substrate 1 and is located in a partial shallow surface area below the surface of the substrate 1. In an exemplary embodiment of the present disclosure, no doping is used in the channel region 3.

[0049] The gate dielectric layer 5 is located in a partial area above the surface of the substrate 1, specifically, directly above the channel region 3, and the first top surface TS1 of the channel region 3 is in direct contact with the gate dielectric layer 5. In some embodiments, the material of the gate dielectric layer 5 can be any one or more combinations of silicon oxide, hafnium oxide, zirconium oxide, and aluminum oxide. In an exemplary embodiment of the present disclosure, the material of the gate dielectric layer 5 is silicon oxide.

[0050] The gate conductive layer 2 is located directly above the gate dielectric layer 5, and the top surface of the gate dielectric layer 5 is in direct contact with the gate conductive layer 2. In some embodiments, the material of the gate conductive layer 2 can be any one or more combinations of doped polysilicon, tungsten, and titanium nitride. In an exemplary embodiment of the present disclosure, the material of the gate conductive layer 2 is doped polysilicon.

[0051] When the above-mentioned semiconductor structure is in the working state, the transistor structure is turned on, and a channel is formed in the channel region 3, so that the carriers E flow from the drain region 42 to the source region 41 through the channel. Since the second top surface TS2 of the source region 41 and the third top surface 42 of the drain region 42 are both lower than the contact interface between the channel region 3 (Si) and the gate dielectric layer 5 (SiO2) (that is, the first top surface TS1 of the channel region 3), the formed channel is at a greater distance from the first top surface TS1, thereby reducing the influence of the interface bound state / defect state (Dit) on the on-current of the transistor.

[0052] In some embodiments, the source region 41 further has a protrusion 41a and the drain region 42 further has a protrusion 42a, and both the protrusions 41a and 42a protrude toward the channel region 3, so that the minimum distance between the source region 41 and the drain region 42 is the distance from the protrusion 41a to the protrusion 42a. For details, please refer to Figure 3 , 4 , 7. In some embodiments, Figure 3 , 4 As shown, the protrusion 41a is formed at the second top surface TS2 close to the source region 41, and / or the protrusion 42a is formed at the third top surface TS3 close to the drain region 42. In other embodiments, as Figure 7As shown, the protrusion 41a is formed at the second top surface TS2 away from the source region 41, and / or the protrusion 42a is formed at the third top surface TS3 away from the drain region 42. In other embodiments, only one of the source region 41 and the drain region 42 may have the protrusion 41a (or 42a), and the minimum distance between the source region 41 and the drain region 42 is the distance from the protrusion 41a (or 42a) of one to the other. The provision of the protrusion 41a and / or 42a ensures that when the gate conductive layer 2 has a turn-on voltage, a conductive channel can still be formed in the channel region 3 at a distance from the first top surface TS1, so that the transistor structure is turned on and the state is stable.

[0053] In some embodiments, the semiconductor structure provided by the present disclosure further includes an isolation layer 6, which covers the surface of the gate conductive layer 2 and the gate dielectric layer 5, and is located above the source region 41 and the drain region 42, wherein the isolation layer 6 is flush with the first top surface TS1 of the channel region 3 at the first bottom surface BS1 located above the source region 41 or the drain region 42. In some embodiments, the material of the isolation layer 6 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride oxide. In an exemplary embodiment of the present disclosure, the material of the isolation layer 6 is silicon oxide. The isolation layer 6 is used to protect the exposed surfaces of the gate conductive layer 2, the gate dielectric layer 5, and the source region 41 and the drain region 42 to prevent damage such as oxidation or erosion by water vapor in the external environment.

[0054] In some embodiments, the semiconductor structure provided by the present disclosure further includes a first supplementary isolation layer 71 and a second supplementary isolation layer 72. The first supplementary isolation layer 71 is located between the isolation layer 6 and the source region 41, and contacts the second top surface TS2 of the source region 41; the second supplementary isolation layer 72 is located between the isolation layer 6 and the drain region 42, and contacts the third top surface TS3 of the drain region 42. The first supplementary isolation layer 71 and the second supplementary isolation layer 72, on the one hand, compensate for the downward movement of the second top surface TS2 of the source region 41 and the third top surface TS3 of the drain region 42, and on the other hand, further protect the exposed surfaces of the source region 41 and the drain region 42 to prevent damage such as oxidation or erosion by water vapor in the external environment.

[0055] In some embodiments, the material of the first supplementary isolation layer 71 and the second supplementary isolation layer 72 is an insulating dielectric material, for example, it can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0056] In other embodiments, the material of the first supplementary isolation layer 71 and the second supplementary isolation layer 72 is a semiconductor dielectric material, for example, it can be doped silicon or germanium. Specifically, the first supplementary isolation layer 71 and the second supplementary isolation layer 72 are doped with second type ions, and the second type ions are opposite to the first type ions doped in the source region 41 and the drain region 42, and are N-type and P-type to each other. In some embodiments, the first type ions are N-type and the second type ions are P-type. Specifically, the N-type ions include ions of group V elements, such as ions of phosphorus, arsenic, antimony or bismuth, and the P-type ions include ions of group III elements, such as ions of boron, aluminum, gallium or indium. In an exemplary embodiment of the present disclosure, the first supplementary isolation layer 71 and the second supplementary isolation layer 72 are doped with boron ions.

[0057] In some embodiments, the thickness of the first supplementary isolation layer 71 and the second supplementary isolation layer 72 are both in the range of 3 to 10 nm, for example, 3 nm, 3.5 nm, 4 nm, 5 nm, 6 nm, 7.5 nm, 8 nm, and 10 nm. In some embodiments, the thickness of the first supplementary isolation layer 71 is consistent with that of the second supplementary isolation layer 72, that is, the second top surface TS2 of the source region 41 in contact with the first supplementary isolation layer 71 and the third top surface TS3 of the drain region 42 in contact with the second supplementary isolation layer 72 are located on the same horizontal plane. In other embodiments, the thickness of the first supplementary isolation layer 71 and the second supplementary isolation layer 72 are different, for example, the thickness of the second supplementary isolation layer 72 is greater than the thickness of the first supplementary isolation layer 71, that is, the horizontal plane where the third top surface TS3 of the drain region 42 in contact with the second supplementary isolation layer 72 is located is lower than the horizontal plane where the second top surface TS2 of the source region 41 in contact with the first supplementary isolation layer 71 is located, refer to Figure 4 It should be noted that the "horizontal plane" mentioned above is a plane parallel to the extension direction of the surface of the substrate 1, and the height direction mentioned above is a direction away from the substrate 1 upward and perpendicular to the substrate 1 in the figure.

[0058] In another exemplary embodiment of the present disclosure, referring to Figure 5As shown, the channel region 3 includes a deep surface layer 3a, which is in contact with the gate dielectric layer 5, and the first top surface TS1 of the channel region 3 is the top surface of the deep surface layer 3a. The deep surface layer 3a is doped with a third type of ions, and the third type of ions are the same type as the first type of ions doped in the source region 41 and / or the drain region 42, and are both N-type or P-type. In some embodiments, the first type of ions and the third type of ions are both N-type, and specifically, the N-type ions include ions of group V elements, such as ions of phosphorus, arsenic, antimony or bismuth. In an exemplary embodiment of the present disclosure, phosphorus ions are doped in the deep surface layer 3a. The concentration of the third type of ions doped in the channel region 3 is less than the concentration of the first type of ions doped in the source region 41 and / or the drain region 42. Since the deep surface layer 3a has the same doping type as the source region 41 and / or the drain region 43, it is beneficial for the channel region 3 to still form a conductive channel at a relatively long distance from the first top surface TS1, thereby making the transistor structure conductive and stable.

[0059] In yet another exemplary embodiment of the present disclosure, referring to Figure 6 As shown, the channel region 3 includes a shallow layer 3b and a deep layer 3a, the shallow layer 3b is located above the deep layer 3a and is in contact with the gate dielectric layer 5, and the first top surface TS1 of the channel region 3 is the top surface of the shallow layer 3b. Among them, the shallow layer 3b is doped with fourth-type ions, and the deep layer 3a is doped with fifth-type ions. The fourth-type ions are of opposite types to the first-type ions doped in the source region 41 and / or the drain region 42, and are N-type and P-type to each other. The fifth-type ions are of the same type as the first-type ions doped in the source region 41 and / or the drain region 42, and are both N-type or P-type. In some embodiments, the first-type ions and the fifth-type ions are both N-type, and the fourth-type ions are P-type. Specifically, the N-type ions include ions of group V elements, such as ions of phosphorus, arsenic, antimony or bismuth, and the P-type ions include ions of group III elements, such as ions of boron, aluminum, gallium or indium. In an exemplary embodiment of the present disclosure, phosphorus ions are doped in the deep surface layer 3a, and boron ions are doped in the shallow surface layer 3b. The concentrations of the fourth type ions and the fifth type ions doped in the channel region 3 are both less than the concentrations of the first type ions doped in the source region 41 and / or the drain region 42. Since the doping types of the shallow surface layer 3b and the deep surface layer 3a are opposite, the top surface of the deep surface layer 3a moves downward, so that when the transistor is in the working state, the channel (carrier channel) formed in the channel region 3 will be formed in the deep surface layer 3a to be further away from the contact interface between the channel region 3 and the gate dielectric layer 5.

[0060] In some embodiments, the semiconductor structure provided by the present disclosure further includes a contact 8, and the contact 8 may have a plurality of contacts, which are respectively inserted into the gate conductive layer 2, the source region 41, and the drain region 42. Specifically, as Figures 2 to 7As shown in any of the figures, the contact 8 located on the gate conductive layer 2 penetrates the isolation layer 6 and is inserted into the gate conductive layer 2, and is electrically connected to the gate conductive layer 2; the contact 8 located on the source region 41 penetrates the isolation layer 6 and the first supplementary isolation layer 71 and is inserted into the source region 41, and is electrically connected to the source region 41; the contact 8 located on the drain region 42 penetrates the isolation layer 6 and the second supplementary isolation layer 72 and is inserted into the drain region 42, and is electrically connected to the drain region 42. In some embodiments, the material of the contact 8 may be tungsten or copper and titanium nitride or tantalum nitride. In an exemplary embodiment of the present disclosure, the material of the contact 8 is tungsten and titanium nitride. The contact 8 is provided to transmit an electrical signal to or from a corresponding region.

[0061] The semiconductor structure provided by the present invention reduces the height of the source region and the drain region, that is, the top surfaces of the source region and the drain region are lower than the top surface of the channel region, so that when the transistor is in a working state, the channel (carrier channel) formed in the channel region is away from the contact interface between the channel region and the gate dielectric layer, thereby reducing the influence of the interface bound state / defect state (Dit) on the transistor on-current, thereby achieving a reduction in the transient noise of the transistor and improving the stability of the transistor output voltage. Further, it helps to improve the stability of the CIS output signal.

[0062] Based on the above semiconductor structure, the present disclosure also provides a method for manufacturing a semiconductor structure. FIG. 8A to FIG. 8K , a method for manufacturing a semiconductor structure includes: providing a substrate 1, such as Fig. 8A shown.

[0063] The material of the substrate 1 may be at least one of the following materials: semiconductor materials or III-V materials such as silicon, germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI). In an exemplary embodiment of the present disclosure, the substrate 1 is a P-type silicon substrate formed by doping a single crystal silicon material with a trace amount of III-group elements, such as boron, aluminum, gallium or indium.

[0064] Next, refer to Figure 8B As shown, an initial pad oxide layer 11' is formed on the top surface of the substrate 1 to protect the top surface of the substrate 1 from possible damage in the subsequent process flow. In some embodiments, the thickness of the initial pad oxide layer 11' ranges from 3 to 15 nm, for example, 3 nm, 4 nm, 5 nm, 6 nm, 8 nm, 10 nm, 12 nm, 14 nm, 15 nm.

[0065] In some embodiments, the deposition method of the initial pad oxide layer 11' can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), thermal oxidation growth method.

[0066] Then, a patterned first mask layer 12' is formed on the initial pad oxide layer 11'. Figure 8C As shown, with the first mask layer 12' as a mask, a first ion implantation A is performed on the surface of the substrate 1 on both sides of the first mask layer 12', and then annealing is performed to form an initial source region 41' and an initial drain region 42' on the surface of the substrate 1 on both sides of the first mask layer 12', and the surface of the substrate 1 covered by the first mask layer 12' serves as a channel region 3, the channel region 3 is located between the initial source region 41' and the initial drain region 42', and a first top surface of the channel region 3 is coplanar with the top surfaces of the initial source region 41' and the initial drain region 42'.

[0067] In some embodiments, the first mask layer 12' may be patterned by photolithography. Specifically, an initial mask material layer (not shown) and a photoresist mask layer (not shown) may be formed on the surface of the substrate 1, and the pattern of the channel region 3 may be formed in the photoresist mask layer by exposure and development, and then dry etching is performed to etch the initial mask material layer along the pattern to form a patterned first mask layer 12'. In other embodiments, the initial mask material layer is a photoresist mask layer (not shown), and after exposure and development, the patterned photoresist mask layer is the first mask layer 12'.

[0068] In some embodiments, the first ion implantation A is of N-type doping type, specifically, including ions of group V elements, such as ions of phosphorus, arsenic, antimony or bismuth. In an exemplary embodiment of the present disclosure, the first ion implantation A is doped with arsenic ions. In some embodiments, no doping is used in the channel region 3.

[0069] Then, refer to Fig.8DAs shown, the initial source region 41' and the initial drain region 42' are thinned. Specifically, in an exemplary embodiment of the present disclosure, the first mask layer 12' is continued to be used as a mask, and the initial pad oxide layer 11' and the initial source region 41' and the initial drain region 42' that are not covered by the first mask layer 12' are etched to remove part of the thickness, so as to obtain the pad oxide layer 11, the source region 41 and the drain region 42. In some embodiments, the initial pad oxide layer 11' located directly above the top surface of the initial source region 41' and the initial drain region 42' is completely removed, and only the initial pad oxide layer 11' on the first top surface of the channel region 3 is retained as the pad oxide layer 11. In some embodiments, the thickness of the etched portion of the initial source region 41' and the initial drain region 42' is in the range of 3-10nm, for example, it can be 3nm, 3.5nm, 4nm, 5nm, 6nm, 7.5nm, 8nm, 10nm.

[0070] In some embodiments, the etching method may include a combination of any one or more etching methods selected from the group consisting of selective plasma dry etching, selective wet etching, reactive ion etching (RIE), and vapor phase chemical etching.

[0071] Next, refer to Fig. 8E As shown, a supplementary isolation material layer 7 is formed to cover the surface of the substrate 1 , including the top surfaces of the source region 41 , the drain region 42 and the pad oxide layer 11 , and the exposed side surfaces of the channel region 3 .

[0072] In some embodiments, the material of the supplementary isolation material layer 7 is an insulating dielectric material, for example, at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0073] In other embodiments, the material of the supplementary isolation material layer 7 is a semiconductor dielectric material, such as doped silicon or germanium. Specifically, the supplementary isolation material layer 7 is doped with second-type ions during the deposition process. The second-type ions are opposite to the doping ions in the first ion implantation A, and are N-type and P-type. In some embodiments, the doping ions of the first ion implantation A are N-type, and the second-type ions are P-type. Specifically, the N-type ions include ions of group V elements, such as ions of phosphorus, arsenic, antimony or bismuth, and the P-type ions include ions of group III elements, such as ions of boron, aluminum, gallium or indium. In an exemplary embodiment of the present disclosure, the material of the supplementary isolation material layer 7 is polysilicon doped with boron ions.

[0074] In some embodiments, the deposition method of the supplementary isolation material layer 7 can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), thermal oxidation growth method.

[0075] Then, refer to Fig.8F As shown, after the supplementary isolation material layer 7 is formed, the surface of the substrate 1 is planarized to expose the first top surface of the channel region 3. Specifically, in an exemplary embodiment of the present disclosure, the first top surface of the channel region 3 is used as the plane where the stop layer is located, and the structure on the surface of the substrate 1 is planarized to remove all the film layers directly above the first top surface of the channel region 3 and the partial thickness of the supplementary isolation material layer 7 directly above the source region 41 and the drain region 42, and the remaining thickness of the supplementary isolation material layer 7 directly above the second top surface of the source region 41 and the third top surface of the drain region 42 corresponds to the first supplementary isolation layer 71 and the second supplementary isolation layer 72, respectively. In some embodiments, the top surface of the first supplementary isolation layer 71 and the top surface of the second supplementary isolation layer 72 are coplanar with the first top surface of the channel region 3 and parallel to the extension direction of the surface of the substrate 1.

[0076] In some embodiments, the planarization process may be a combination of one or more process methods including chemical mechanical polishing (CMP) or plasma dry etching.

[0077] Next, refer to Figure 8G As shown, after the first top surface of the channel region 3 is exposed by planarization, a gate dielectric material layer 5' and a gate conductive material layer 2' are sequentially formed, wherein the gate dielectric material layer 5' covers the top surface of the first supplementary isolation layer 71, the top surface of the second supplementary isolation layer 72 and the first top surface of the channel region 3, and the gate conductive material layer 2' covers the top surface of the gate dielectric material layer 5'. It should be noted that, in other embodiments, the gate dielectric material layer 5' can also be selectively formed only on the first top surface of the channel region 3.

[0078] In some embodiments, the material of the gate dielectric material layer 5' can be any one or more combinations of silicon oxide, hafnium oxide, zirconium oxide, and aluminum oxide. In an exemplary embodiment of the present disclosure, the material of the gate dielectric material layer 5' is silicon oxide. In some embodiments, the material of the gate conductive material layer 2' can be any one or more combinations of doped polysilicon, tungsten, and titanium nitride. In an exemplary embodiment of the present disclosure, the material of the gate conductive material layer 2' is doped polysilicon.

[0079] In some embodiments, the gate dielectric material layer 5' and the gate conductive material layer 2' may be formed by at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in situ water vapor growth (ISSG), thermal oxidation growth.

[0080] Next, if Figure 8H As shown, the gate conductive material layer 2' and the gate dielectric material layer 5' are patterned to form the gate conductive layer 2 and the gate dielectric layer 5. Specifically, the gate conductive material layer 2' and the gate dielectric material layer 5' are etched to remove all film layers located directly above the top surfaces of the first supplementary isolation layer 71 and the second supplementary isolation layer 72, and only the gate conductive material layer 2' and the gate dielectric material layer 5' located directly above the first top surface of the channel region 3 are retained as the gate conductive layer 2 and the gate dielectric layer 5, respectively.

[0081] In some embodiments, the gate conductive material layer 2' and the gate dielectric material layer 5' may be etched by photolithography. Specifically, a photoresist mask layer may be formed on the surface of the gate conductive material layer 2', and a pattern of the gate conductive layer 2 or the channel region 3 may be formed in the photoresist mask layer by exposure and development, and then dry etching is performed to etch the gate conductive material layer 2' and the gate dielectric material layer 5' along the pattern to form the gate conductive layer 2 and the gate dielectric layer 5. In some embodiments, before applying the photoresist mask layer, an anti-reflective layer and a hard mask layer (not shown) are also formed on the surface of the gate conductive material layer 2', and both are removed after the gate conductive layer 2 and the gate dielectric layer 5 are formed.

[0082] Then, if Figure 8IAs shown, an isolation layer 6 is formed to cover the exposed surfaces of the gate conductive layer 2 and the gate dielectric layer 5 and the top surfaces of the first supplementary isolation layer 71 and the second supplementary isolation layer 72. The first bottom surface of the isolation layer 6 is flush with the first top surface of the channel region 3.

[0083] In some embodiments, the material of the isolation layer 6 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride. In an exemplary embodiment of the present disclosure, the material of the isolation layer 6 is silicon oxide.

[0084] In some embodiments, the isolation layer 6 may be formed by at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in situ water vapor growth (ISSG), thermal oxidation growth.

[0085] Then, if Figure 8H As shown, a contact 8 is formed, and a plurality of contact members 8 are respectively inserted into the gate conductive layer 2, the source region 41, and the drain region 42. Specifically, the contact member 8 is formed to penetrate the isolation layer 6 and be inserted into the gate conductive layer 2, and is electrically connected to the gate conductive layer 2; the contact member 8 located on the source region 41 penetrates the isolation layer 6 and the first supplementary isolation layer 71 and is inserted into the source region 41, and is electrically connected to the source region 41; the contact member 8 located on the drain region 42 penetrates the isolation layer 6 and the second supplementary isolation layer 72 and is inserted into the drain region 42, and is electrically connected to the drain region 42.

[0086] In some embodiments, the material of the contact 8 may be tungsten or copper and titanium nitride or tantalum nitride. In an exemplary embodiment of the present disclosure, the material of the contact 8 is tungsten and titanium nitride.

[0087] In some embodiments, the method for forming the contact 8 is specifically to first form an interlayer dielectric layer (not shown) to cover the isolation layer 6, then use a photolithography process to etch a contact hole (not shown) in the interlayer dielectric layer to insert it into the corresponding film layer, and then fill the contact hole with a conductive material to form the contact 8. In some embodiments, the method for filling the conductive material can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering.

[0088] In other embodiments, Figure 8K As shown, before forming an interlayer dielectric layer (not shown) to cover the isolation layer 6, an isolation layer 9 is formed on the surface of the isolation layer 6. The isolation layer 9 at least covers the surface of the isolation layer 6 on the sidewalls of the gate conductive layer 2 and the gate dielectric layer 5, and also covers the surface of the isolation layer 6 on the top surface of the first supplementary isolation layer 71 and the second supplementary isolation layer 72. The isolation layer 9 is provided to further protect the gate dielectric layer 5, the channel region 3, and the source region 41 and the drain region 42 from being corroded by oxygen or water vapor in the environment.

[0089] In some embodiments, the material of the insulating layer 10 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride. In an exemplary embodiment of the present disclosure, the material of the insulating layer 9 is silicon nitride.

[0090] In another exemplary embodiment of the present disclosure, the source region 41 further has a protrusion 41a and the drain region 42 further has a protrusion 42a, and both protrusions 41a and 42a protrude toward the channel region 3, so that the minimum distance between the source region 41 and the drain region 42 is the distance from the protrusion 41a to the protrusion 42a.

[0091] In some embodiments, the method for making the protrusions 41a and 42a can refer to 9A to 9C As shown. Figure 8CAfter the first ion implantation A is performed on the surface of the substrate 1 on both sides of the first mask layer 12', and before annealing is performed, the process further includes: reducing at least the width dimension of the first mask layer 12' to form a [reduced first mask layer 12], using the [reduced first mask layer 12] as a mask, performing a second ion implantation B on the substrate 1 on both sides of the [reduced first mask layer 12], wherein the depth of the second ion implantation B is less than the depth of the first ion implantation A, and the ion doping type of the second ion implantation B is the same as the ion doping type of the first ion implantation A, and is both N-type or P-type. In some embodiments, the ion doping types of the first ion implantation A and the second ion implantation B are both N-type, and specifically, the N-type ions include ions of Group V elements, such as ions of phosphorus, arsenic, antimony, or bismuth. In an exemplary embodiment of the present disclosure, as Fig. 9A As shown, the first ion implantation A forms an initial first source region 41a' and an initial first drain region 42a' on the surface of the substrate 1 on both sides of the first mask layer 12, and the first ion implantation A adopts arsenic ion doping; the second ion implantation B forms an initial second source region 41b' and an initial second drain region 42b' on the surface of the substrate 1 on both sides of the first mask layer 12, and the second ion implantation B adopts phosphorus ion doping.

[0092] In some embodiments, in the direction toward the channel region 3 , the distance between the initial second source region 41 b ′ and the initial second drain region 42 b ′ is smaller than the distance between the initial first source region 41 a ′ and the initial first drain region 42 a ′.

[0093] In some embodiments, the width of the first mask layer 12 ′ may be reduced by using an ashing or wet etching process.

[0094] Next, refer to Fig. 9B As shown, annealing is performed so that the initial first source region 41a' and the initial second source region 41b' are diffused and merged to form the initial source region 41', and the initial first drain region 42a' and the initial second drain region 42b' are diffused and merged to form the initial drain region 42'.

[0095] Then, if Fig. 9CAs shown, the initial source region 41' and the initial drain region 42' are thinned. In an exemplary embodiment of the present disclosure, the initial pad oxide layer 11' and the initial source region 41' and the initial drain region 42' that are not covered by the [reduced first mask layer 12] are etched and removed at the same time to obtain a pad oxide layer 11, a source region 41 and a drain region 42, wherein the source region 41 and the drain region 42 respectively form protrusions 41a and 42a protruding toward the channel region 3. In some embodiments, the initial pad oxide layer 11' located directly above the top surfaces of the initial source region 41' and the initial drain region 42' is completely removed, and only the initial pad oxide layer 11' on the first top surface of the channel region 3 is retained as the pad oxide layer 11. In some embodiments, the thickness of the etched portions of the initial source region 41 ′ and the initial drain region 42 ′ is in the range of 3-10 nm, for example, 3 nm, 3.5 nm, 4 nm, 5 nm, 6 nm, 7.5 nm, 8 nm, 10 nm. In some embodiments, the second top surface of the source region 41 is flush with the third top surface of the drain region 42 .

[0096] In some embodiments, the etching method may include a combination of any one or more etching methods selected from the group consisting of selective plasma dry etching, selective wet etching, reactive ion etching (RIE), and vapor phase chemical etching.

[0097] In another exemplary embodiment of the present disclosure, referring to FIG. 10A to FIG. 10B , the initial pad oxide layer 11', the initial source region 41' and the initial drain region 42' are etched step by step to remove a portion of the thickness. Specifically, in some embodiments, such as Fig. 10AAs shown, a patterned second mask layer 13 is formed on the surface of the substrate 1 to cover the top surface of the initial pad oxide layer 11' located directly above the channel region 3 and the initial source region 41', exposing the top surface of the initial pad oxide layer 11' located directly above the initial drain region 42', and performing the first etching on the exposed portion to remove the entire initial pad oxide layer 11' located directly above the initial drain region 42' and a portion of the thickness of the initial drain region 42' to obtain a temporary pad oxide layer 11a and the drain region 42; then, the second mask layer 13 is removed. , then a patterned third mask layer 14 is formed on the surface of the substrate 1 to cover the top surface of the temporary pad oxide layer 11' located directly above the channel region 3 and the third top surface of the drain region 42, exposing the top surface of the temporary pad oxide layer 11a located directly above the initial source region 41', and the exposed portion is subjected to a second step of etching to remove all the temporary pad oxide layer 11a located directly above the initial source region 41' and a portion of the thickness of the initial source region 41' to obtain the pad oxide layer 11 and the source region 41; finally, the third mask layer 14 is removed. In some embodiments, the thickness of the etched portion of the initial source region 41' and the initial drain region 42' is in the range of 3-10nm, for example, 3nm, 3.5nm, 4nm, 5nm, 6nm, 7.5nm, 8nm, 10nm. In some embodiments, the third top surface of the drain region 42 is lower than the second top surface of the source region 41, and the bottom surface of the channel region 3 is an inclined surface inclined upward from the drain region toward the source region.

[0098] In other embodiments, the exposed areas of the patterned second mask layer 13 and the third mask layer 14 can be swapped, that is, the second mask layer 13 exposes the top surface of the initial pad oxide layer 11' located directly above the initial source region 41', and the third mask layer 14 exposes the top surface of the temporary pad oxide layer (not shown) located directly above the initial drain region 42'. Accordingly, the first etching step can first remove a portion of the thickness of the initial source region 41', and the second etching step can then remove a portion of the thickness of the initial drain region 42'.

[0099] In some embodiments, the materials and forming methods of the patterned second mask layer 13 and the third mask layer 14 may be the same as those of the patterned first mask layer 12 ′ in the aforementioned embodiments, and are not described repeatedly herein.

[0100] In some embodiments, the first etching step and the second etching step may include a combination of any one or more etching methods selected from the group consisting of selective plasma dry etching, selective wet etching, reactive ion etching (RIE), and vapor phase chemical etching.

[0101] In another exemplary embodiment of the present disclosure, referring to Fig.11As shown, after the initial source region 41' and the initial drain region 42' are formed, the initial source region 41' and the initial drain region 42' are thinned to form the source region 41 and the drain region 42, and a first supplementary isolation layer 71 is formed on the second top surface of the source region 41 and a second supplementary isolation layer 72 is formed on the third top surface of the drain region 42. Specifically, in the aforementioned embodiment, Figure 8C After the step, continue to use the first mask layer 12' as a mask to perform a third ion implantation C on the initial source region 41' and the initial drain region 42' to respectively form a first supplementary isolation layer 71 on the surface of the initial source region 41' and a second supplementary isolation layer 72 on the surface of the initial drain region 42'. The depth of the third ion implantation C is less than the depth of the first ion implantation A. The ion doping type of the third ion implantation C is opposite to the ion doping type of the first ion implantation A, and they are N-type and P-type to each other. Specifically, the doping ions of the first ion implantation A are N-type, and the doping ion type of the third ion implantation is P-type. Specifically, the N-type ions include ions of group V elements, such as ions of phosphorus, arsenic, antimony or bismuth, and the P-type ions include ions of group III elements, such as ions of boron, aluminum, gallium or indium. The thickness of the first supplementary isolation layer 71 and the second supplementary isolation layer 72 is the depth of the third ion implantation C. The remaining portion of the initial source region 41' after removing the first supplementary isolation layer 71 is used as the source region 41, and the remaining portion of the initial drain region 42' after removing the second supplementary isolation layer 72 is used as the drain region 42. In some embodiments, the thickness of the first supplementary isolation layer 71 and the second supplementary isolation layer 72 are both in the range of 3-10 nm, for example, 3 nm, 3.5 nm, 4 nm, 5 nm, 6 nm, 7.5 nm, 8 nm, 10 nm. In some embodiments, after performing the third ion implantation C, an annealing process is also performed.

[0102] In another exemplary embodiment of the present disclosure, referring to Fig. 12A and Fig. 12B As shown, after forming the source region 41 and the drain region 42, the process further includes: performing a fourth ion implantation D1 on the channel region 3. Specifically, as Fig. 12A As shown, the depth of the fourth ion implantation D1 is lower than the second top surface of the source region 41 and the third top surface of the drain region 42, and the ion doping type of the fourth ion implantation D1 is the same as the ion doping type of the first ion implantation A, which is N-type or P-type. In some embodiments, the ion doping types of the first ion implantation A and the fourth ion implantation D1 are both N-type, and specifically, the N-type ions include ions of group V elements, such as ions of phosphorus, arsenic, antimony, or bismuth.

[0103] In some embodiments, after the fourth ion implantation D1 is performed on the channel region 3, the method further includes: performing a fifth ion implantation D2 on the channel region 3. Specifically, Fig. 12BAs shown, the depth of the fifth ion implantation D2 is less than the depth of the fourth ion implantation D1, the ion doping type of the fifth ion implantation D2 is opposite to the ion doping type of the fourth ion implantation D1, and they are N-type and P-type to each other, and the ion doping type of the fifth ion implantation D2 is opposite to the ion doping type of the first ion implantation A, and they are N-type and P-type to each other. In some embodiments, the ion doping types of the first ion implantation A and the fourth ion implantation D1 are both N-type, and the ion doping type of the fifth ion implantation D2 is P-type, specifically, the N-type ions include ions of group V elements, such as ions of phosphorus, arsenic, antimony or bismuth, and the P-type ions include ions of group III elements, such as ions of boron, aluminum, gallium or indium.

[0104] In another exemplary embodiment of the present disclosure, referring to Fig.13 As shown, in some embodiments, Figure 8C After the first ion implantation A is performed on the surface of the substrate 1 on both sides of the first mask layer 12' and before annealing is performed, the method further includes: performing a sixth ion implantation A' on the surface of the substrate 1; after annealing, the initial source region 41' and the initial drain region 42' are formed to simultaneously form protrusions 41a and 42a protruding toward the channel region 3, and the protrusions 41a and 42a both protrude toward the channel region 3, so that the minimum distance between the source region 41 and the drain region 42 is the distance from the protrusion 41a to the protrusion 42a. Specifically, as Fig.13 As shown, with the first mask layer 12' as a mask, the sixth ion implantation A' is performed on the substrate 1 on both sides of the first mask layer 12', the implantation direction of the sixth ion implantation A' has an inclination angle toward the channel region 3, and the ion doping type of the sixth ion implantation A' is the same as the ion doping type of the first ion implantation A, both of which are N-type or P-type. In some embodiments, the ion doping types of the first ion implantation A and the sixth ion implantation A' are both N-type, and specifically, the N-type ions include ions of group V elements, such as ions of phosphorus, arsenic, antimony, or bismuth.

[0105] In other embodiments, the sixth ion implantation A' may replace the first ion implantation A to simultaneously form an initial source region 41' having a protrusion 41a and an initial drain region 42' having a protrusion 42a after annealing, wherein both the protrusions 41a and 42a protrude toward the channel region 3, so that the minimum distance between the source region 41 and the drain region 42 is the distance from the protrusion 41a to the protrusion 42a.

[0106] The semiconductor structure formed by the method for forming a semiconductor structure provided by the present disclosure has a transition layer of a stack of silicon germanium and boron-doped polysilicon in the conductive electrode plate formed on the upper electrode of the capacitor structure, and the boron-doped polysilicon layer is located on the surface of the silicon germanium layer. On the one hand, the silicon germanium layer can be protected from corrosion damage during the etching and cleaning process; on the other hand, its surface roughness is low and has low surface energy, which can obtain better hydrophobicity, enhance the adhesion of the photoresist in the subsequent process, and avoid the risk of photoresist falling off and breaking. In addition, the stacked structure of boron-doped polysilicon and silicon germanium, especially the sandwich structure (i.e., a silicon germanium layer is located between two boron-doped polysilicon layers), can effectively reduce the resistivity and improve the working performance of the storage device.

[0107] Based on the above semiconductor structure, the present disclosure also provides a semiconductor device, referring to Fig.14 As shown, it includes: a source follower transistor SF, the source follower transistor SF includes the transistor structure in the semiconductor structure of any of the aforementioned embodiments; a photoelectric conversion element PD, a floating diffusion area FD, a transfer transistor TG, a reset transistor RST and a selection transistor SEL, wherein the two source and drain electrodes of the transfer transistor are respectively connected to the photoelectric conversion element PD and the floating diffusion area FD, the floating diffusion area FD is connected to the gate of the source follower transistor SF, and is also connected to a source and drain of the reset transistor RST, and the selection transistor SEL is connected in series with the source of the source follower transistor SF.

[0108] In some embodiments, the photoelectric conversion element PD may adopt a photodiode for generating a charge proportional to the amount of light incident from the outside. The photoelectric conversion element PD may be coupled to a transfer transistor TG that transfers the generated and accumulated charge to the floating diffusion area FD. The floating diffusion area FD may adopt a capacitor, which is a region for converting the charge into a voltage and can store the charge cumulatively due to its parasitic capacitance. The transfer transistor TG may adopt a field effect transistor (MOSFET), one source and drain of the transfer transistor TG is connected to the photoelectric conversion element PD, and the other source and drain of the transfer transistor TG is connected to the floating diffusion area FD. The transfer transistor TG may be driven by a predetermined bias, for example, a transfer signal TX. The transfer transistor TG may transfer the charge generated by the photoelectric conversion element PD to the floating diffusion area FD according to the transfer signal TX. The source follower transistor SF may amplify the potential change of the floating diffusion area FD that receives the charge from the photoelectric conversion element PD, and may output the amplified change to the output line Vout. When the source follower transistor SF is turned on, the predetermined potential provided to the drain of the source follower transistor SF, for example, the power supply voltage VDD may be transferred to the drain of the selection transistor SEL. The selection transistor SEL may be a field effect transistor (MOSFET) for selecting the unit pixel to be read row by row. The selection transistor SEL may be driven by a selection line to which a predetermined bias voltage is applied, for example, a row selection signal RS. The reset transistor RST may be a field effect transistor (MOSFET) for periodically resetting the floating diffusion area FD. The reset transistor RST may be driven by a reset line to which a predetermined bias voltage is applied, for example, a reset signal RX. When the reset transistor RST is turned on by the reset signal RX, a predetermined potential provided to the drain of the reset transistor RST, for example, a power supply voltage VDD, may be transferred to the floating diffusion area FD.

[0109] The source follower transistor SF in the semiconductor device disclosed in the present invention adopts the transistor structure in the above embodiment, which reduces the transient noise of the output voltage of the source follower transistor during operation, is beneficial to improving the stability of the output signal Vout of the CIS device, thereby improving the performance of the product.

[0110] The present disclosure also provides an imaging system 500, referring to Fig.15 As shown, the imaging system 500 captures images using the image sensor 100 formed by the above-mentioned semiconductor structure or semiconductor device. Fig.15The imaging system 500 may be a portable electronic device such as a camera, a mobile phone, a tablet computer, a webcam, a video camera, a video surveillance system, an automotive imaging system, a video game system with imaging capabilities, or any other desired imaging system or device that captures digital image data. The camera module 300 may be used to convert incident light into digital image data. The camera module 300 may include a lens 200 and a corresponding image sensor 100. The lens 200 may include a fixed lens and / or an adjustable lens, and may include a microlens formed on an imaging surface of the image sensor 100. During an image capture operation, light from a scene may be focused onto the image sensor 100 through the lens 200. The image sensor 100 may include circuitry for converting analog pixel data into corresponding digital image data to be provided to the storage and processing circuit 400. If desired, the camera module 300 may be provided with an array of lenses 200 and an array of corresponding image sensors 100.

[0111] The storage and processing circuit 400 may include one or more integrated circuits, such as memory and processors (e.g., image processing circuits, microprocessors, storage devices such as random access memory and non-volatile memory, etc.), and may be implemented using components that are separate from and / or form part of the camera module 300 (e.g., circuits that form part of an integrated circuit that includes the image sensor 100 or within a module associated with the image sensor 100). Image data that has been captured by the camera module 300 may be processed and stored using the processing circuit 400 (e.g., using an image processing engine on the processing circuit 400, using an imaging mode selection engine on the processing circuit 400, etc.). The processed image data may be provided to an external device (e.g., a computer, an external display, or other device) using a wired and / or wireless communication path coupled to the processing circuit 400 as desired.

[0112] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A transistor structure, located on the surface of the substrate, the transistor structure comprising a channel region, a gate dielectric layer and a gate conductive layer located directly above the channel region, and a source region and a drain region located on both sides of the channel region, the channel region having a first top surface in contact with the gate dielectric layer, the source region having a second top surface, the drain region having a third top surface, and the source region and the drain region being doped with first type ions; Wherein, the second top surface and the third top surface are both lower than the first top surface.

2. The semiconductor structure according to claim 1, characterized in that: The source region and / or the drain region further has a protrusion, which protrudes toward the channel region, so that a minimum distance between the source region and the drain region is a distance from the protrusion of one to the other or the protrusion of the other.

3. The semiconductor structure according to claim 1, characterized in that: The third top surface of the drain region is not higher than the second top surface of the source region.

4. The semiconductor structure according to claim 1, characterized in that: Also includes: An isolation layer covers the surfaces of the gate conductive layer and the gate dielectric layer and is located above the source region and the drain region, wherein a first bottom surface of the isolation layer is flush with the first top surface of the channel region.

5. The semiconductor structure according to claim 4, characterized in that: Also includes: A first supplementary isolation layer, located between the isolation layer and the source region, the first supplementary isolation layer is in contact with a second top surface of the source region; a second supplementary isolation layer, located between the isolation layer and the drain region, the second supplementary isolation layer being in contact with a second top surface of the drain region; The materials of the first supplementary isolation layer and the second supplementary isolation layer are insulating dielectric materials or semiconductor dielectric materials.

6. The semiconductor structure according to claim 5, characterized in that: The material of the first supplementary isolation layer and the second supplementary isolation layer is a semiconductor dielectric material. The first supplementary isolation layer and the second supplementary isolation layer are doped with second type ions. The second type ions are of opposite types to the first type ions, and are N-type and P-type to each other.

7. The semiconductor structure according to claim 5, characterized in that: The thickness of the first supplementary isolation layer and the second supplementary isolation layer are both in the range of 3-10 nm.

8. The semiconductor structure according to claim 1, characterized in that: The channel region is doped with third type ions, and the third type ions are of the same type as the first type ions, both of which are N type or P type.

9. The semiconductor structure according to claim 1, characterized in that: The channel region includes a shallow layer and a deep layer, the shallow layer is located above the deep layer and is in contact with the gate dielectric layer, and the first top surface is the top surface of the shallow layer; Among them, the shallow layer is doped with fourth type ions, and the deep layer is doped with fifth type ions. The fourth type ions are of opposite types to the fifth type ions, which are N type and P type respectively. The fifth type ions are of the same type as the first type ions, which are both N type or P type.

10. The semiconductor structure according to any one of claims 1 to 9, characterized in that: Also includes: Contacts are inserted into the gate conductive layer, the source region, and the drain region, respectively.

11. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; Forming a channel region having a first top surface and an initial source region and an initial drain region on both sides of the channel region on the surface of the substrate, wherein the top surfaces of the initial source region and the initial drain region are coplanar with the first top surface; Thinning the initial source region and the initial drain region to obtain a source region having a second top surface and a drain region having a third top surface, wherein the second top surface and the third top surface are both lower than the first top surface; A gate dielectric layer and a gate conductive layer are sequentially formed directly above the channel region, the first top surface is in contact with the gate dielectric layer, and the source region, the drain region, the channel region, the gate dielectric layer and the gate conductive layer together constitute a transistor structure.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: A channel region having a first top surface and an initial source region and an initial drain region on both sides of the channel region are formed on the surface of the substrate, comprising: forming a first mask layer on the surface of the substrate; Using the first mask layer as a mask, first ion implantation is performed on the substrate at both sides of the first mask layer, and annealing is performed to form the initial source region and the initial drain region on the surface of the substrate at both sides of the first mask layer.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: After performing the first ion implantation and before performing the annealing, the method further includes: At least the width of the first mask layer is reduced, and the reduced first mask layer is used as a mask to perform a second ion implantation on the substrate on both sides of the reduced first mask layer, wherein the depth of the second ion implantation is less than the depth of the first ion implantation, and the ion doping type of the second ion implantation is the same as the ion doping type of the first ion implantation; After the annealing is performed, protrusions protruding toward the channel region are formed in the preliminary source region and the preliminary drain region.

14. The method for manufacturing a semiconductor structure according to claim 12 or 13, characterized in that: The initial source region and the initial drain region are thinned, comprising: using the first mask layer or the first mask layer after being reduced as a mask, etching the initial source region and the initial drain region to remove a portion of the thickness, so that the remaining thickness of the initial source region is used as the source region and the remaining thickness of the initial drain region is used as the drain region; The third top surface of the drain region is flush with the second top surface of the source region, or the third top surface of the drain region is lower than the second top surface of the source region.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: A first supplementary isolation layer is formed on the second top surface of the source region, and a second supplementary isolation layer is formed on the third top surface of the drain region, wherein the thickness of the first supplementary isolation layer and the second supplementary isolation layer is the same as the thickness of the portion of the initial source region and the initial drain region that is etched away.

16. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The initial source region and the initial drain region are thinned, comprising: using the first mask layer as a mask, performing a third ion implantation on the initial source region and the initial drain region to respectively form a first supplementary isolation layer on the surface of the initial source region and a second supplementary isolation layer on the surface of the initial drain region, wherein the depth of the third ion implantation is less than the depth of the first ion implantation, and the ion doping type of the third ion implantation is opposite to the ion doping type of the first ion implantation; The thickness of the first supplementary isolation layer and the second supplementary isolation layer is the depth of the third ion implantation. The remaining portion of the initial source region after removing the first supplementary isolation layer serves as the source region, and the remaining portion of the initial drain region after removing the second supplementary isolation layer serves as the drain region.

17. The method for manufacturing a semiconductor structure according to claim 16, characterized in that: After forming the source region and the drain region, the method further comprises: performing a fourth ion implantation on the channel region, wherein the depth of the fourth ion implantation is lower than the second top surface and the third top surface, and the ion doping type of the fourth ion implantation is the same as the ion doping type of the first ion implantation; or A fourth ion implantation and a fifth ion implantation are performed on the channel region, wherein the depth of the fourth ion implantation is lower than the second top surface and the third top surface, the depth of the fifth ion implantation is less than the depth of the fourth ion implantation, the ion doping type of the fourth ion implantation is the same as the ion doping type of the first ion implantation, and the ion doping type of the fifth ion implantation is opposite to the ion doping type of the first ion implantation.

18. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: After performing the first ion implantation and before performing the annealing, the method further includes: using the first mask layer as a mask, performing a sixth ion implantation on the substrate at both sides of the first mask layer, wherein the implantation direction of the sixth ion implantation has an inclination angle toward the channel region, and the ion doping type of the sixth ion implantation is the same as the ion doping type of the first ion implantation; After the annealing is performed, protrusions protruding toward the channel region are formed in the preliminary source region and the preliminary drain region.

19. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: After forming the gate dielectric layer and the gate conductive layer, the method further comprises: forming an isolation layer, covering the surfaces of the gate conductive layer and the gate dielectric layer, and being located above the source region and the drain region, wherein a first bottom surface of the isolation layer is flush with the first top surface of the channel region; Contacts are formed, the contacts being inserted into the gate conductive layer, the source region, and the drain region, respectively.

20. A semiconductor device, characterized in that: include: A source follower transistor, comprising the transistor structure in the semiconductor structure according to any one of claims 1 to 10; A photoelectric conversion element for generating electric charge by photoelectric conversion; A floating diffusion region connected to the gate conductive layer of the source follower transistor and used for storing the charge and generating a potential; a transfer transistor, connected to the photoelectric conversion element and the floating diffusion area respectively, and used for transferring the charge from the photoelectric conversion element to the floating diffusion area; A reset transistor connected to the floating diffusion region and used for resetting the potential of the floating diffusion region; A selection transistor connected in series with the source of the source follower transistor; The source follower transistor is used to respond to the change of the potential of the floating diffusion area, amplify the change of the potential to obtain a signal change, and output the signal change through the selection transistor.

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