P-channel enhanced gallium nitride transistor structure and manufacturing method thereof

Abstract

The invention discloses a P-channel enhanced gallium nitride transistor structure and a manufacturing method thereof, and relates to the technical field of integrated circuit manufacturing, the transistor structure comprises an epitaxial wafer, a gate dielectric layer, a second channel layer, a gate, a gate side wall, a source and a drain; the manufacturing method comprises the steps of 1, providing an epitaxial wafer, 2, depositing a gate dielectric layer and a gate, 3, oxidizing polycrystalline silicon, and removing a silicon nitride dielectric in a source / drain region, 4, carrying out secondary epitaxial growth of a second channel layer, 5, depositing to form a gate side wall and carrying out back etching, 6, depositing a source / drain metal layer, forming a source and a drain, and 5, carrying out back etching. 7, depositing an intermetallic dielectric layer, and then completing a back-end process; two-dimensional hole gas is formed on two sides of gate metal by using a secondary epitaxial process to serve as gate-source and gate-drain connection regions, and a small-size P-channel enhanced gallium nitride transistor is formed by combining a side wall process and a self-alignment process, so that the working voltage of a device is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a P-channel enhancement-type gallium nitride transistor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of GaN technology, all-GaN circuits are a promising development direction. All-GaN digital or mixed analog and digital circuits require both N-channel enhancement-mode GaN transistors and P-channel enhancement-mode transistor devices. A lot of research progress has been made in N-channel enhancement-mode GaN HEMT devices, but the preparation of P-channel enhancement-mode GaN transistor devices is still a challenging problem. Small-size P-channel enhancement-mode GaN devices are a difficult problem that must be solved in the preparation of high-density GaN digital circuits.

[0003] There is an urgent need to develop a small-sized, low-voltage P-channel enhancement-mode gallium nitride transistor device that can be used in all-gallium nitride digital / digital-analog hybrid integrated circuits. Summary of the invention

[0004] In order to overcome the above technical problems, an object of the present invention is to provide a P-channel enhancement-mode gallium nitride transistor structure and a manufacturing method thereof.

[0005] The purpose of the present invention can be achieved through the following technical solutions:

[0006] A P-channel enhancement-mode gallium nitride transistor structure, comprising:

[0007] An epitaxial wafer including a first channel layer;

[0008] A gate dielectric layer, formed above the first channel layer;

[0009] A second channel layer is formed on both sides of the gate dielectric layer;

[0010] A gate, formed above the gate dielectric layer;

[0011] Gate sidewalls are formed on both sides of the gate and connected to the second channel layer;

[0012] The source and the drain are formed on the second channel layer and are located outside the gate sidewalls on both sides.

[0013] As a further solution of the present invention: the epitaxial wafer includes a substrate, a nucleation layer is arranged above the substrate, a buffer layer is arranged above the nucleation layer, a high resistance layer is arranged above the buffer layer, a barrier layer is arranged above the high resistance layer, and a first channel layer is arranged above the barrier layer.

[0014] As a further solution of the present invention: the bottoms of the second channel layers on both sides are connected to the first channel layer, the inner ends of the second channel layers are connected to the gate dielectric layer and the gate sidewalls, and the source and the drain are connected to the second channel layers.

[0015] As a further solution of the present invention: the nucleation layer is a gallium nitride layer or an aluminum nitride layer, the buffer layer is an Al x GaN layer, where 0 < x < 1, the high-resistance layer is a gallium nitride layer doped with iron or carbon, the barrier layer is an Al GaN layer, and the first channel layer is an InGaN layer with a thickness of 5 - 15 nm.

[0016] As a further solution of the present invention: the gate dielectric layer is a silicon nitride layer with a thickness of 5 - 20 nm, and the second channel layer is a Mg-doped P-type GaN channel layer with a thickness of 50 - 100 nm.

[0017] As a further solution of the present invention: the gate is a polysilicon layer with a thickness of 500 - 1000 nm, and the gate sidewall is a single-layer silicon dioxide or a multi-layer structure of silicon dioxide / silicon nitride with a thickness of 200 - 500 nm.

[0018] As a further solution of the present invention: both the source and the drain are Pt / Al or Ni / Al stacked structures.

[0019] As a further solution of the present invention: a manufacturing method of a P-channel enhancement-mode gallium nitride transistor structure for manufacturing the above-mentioned P-channel enhancement-mode gallium nitride transistor structure, including the following steps:

[0020] Step 1: Provide or prepare an epitaxial wafer;

[0021] Step 2: Deposit silicon nitride on the first channel layer to form a gate dielectric layer, then deposit polysilicon to form a gate, and then perform photolithography on the gate pattern and etch the polysilicon to form polysilicon gate bars;

[0022] Step 3: Oxidize the polysilicon to form a silicon dioxide layer with a certain thickness on the outer layer of the gate, and then use a wet etching process to remove the silicon nitride dielectric in the source-drain region;

[0023] Step 4: Selectively perform secondary epitaxial growth of the second channel layer in the source-drain region;

[0024] Step 5: Deposit a sidewall dielectric layer to form a gate sidewall, and then etch back to the top of the second channel layer and the gate;

[0025] Step 6: Deposit a source-drain metal layer, use a planarization process to remove the source-drain metal layer on the upper part of the gate, perform annealing treatment to form a source-drain ohmic contact, and then form a source and a drain;

[0026] Step 7: After step 6, an intermetallic dielectric layer is deposited, and then the rear-end via and metal interconnection processes are completed to finally form a P-channel enhancement-mode gallium nitride transistor device.

[0027] As a further solution of the present invention: the epitaxial wafer is formed by providing a substrate, and epitaxially growing a core layer, a buffer layer, a high resistance layer, a barrier layer and a first channel layer in sequence from bottom to top on the surface of the substrate.

[0028] As a further solution of the present invention: the epitaxial wafer is purchased from outside or prefabricated.

[0029] As a further solution of the present invention: a method for manufacturing a P-channel enhancement-mode gallium nitride transistor structure, characterized in that the method is used to manufacture the above-mentioned P-channel enhancement-mode gallium nitride transistor structure, comprising the following steps:

[0030] Step 1: providing or preparing an epitaxial wafer;

[0031] Step 2: depositing silicon nitride on the first channel layer to form a gate dielectric layer, then depositing polysilicon to form a gate, then photolithography the gate pattern, and etching the polysilicon to form a polysilicon gate strip;

[0032] Step 3: Oxidize the polysilicon to form a silicon oxide layer of a certain thickness on the outer layer of the gate, and then use a wet etching process to remove the silicon nitride dielectric in the source and drain regions;

[0033] Step 4: selectively performing secondary epitaxial growth on the source and drain regions to form a second channel layer;

[0034] Step 5: depositing a sidewall dielectric layer to form a gate sidewall, and then etching back to the barrier layer and the top of the gate;

[0035] Step 6: depositing source and drain metal layers, removing the source and drain metal layers on the gate by a planarization process, and performing annealing to form source and drain ohmic contacts, thereby forming source and drain electrodes;

[0036] Step 7: After step 6, an intermetallic dielectric layer is deposited, and then the rear-end via and metal interconnection processes are completed to finally form a P-channel enhancement-mode gallium nitride transistor device.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] The present invention uses polysilicon as the gate metal, and uses a secondary epitaxial process to form a two-dimensional hole gas (2DHG) on both sides of the gate metal as the gate-source and gate-drain access regions, which can form an enhanced P-channel device, and combines the sidewall process and the self-alignment process to form a small-sized P-channel enhancement-type gallium nitride transistor (the gate, source, and drain are all separated by the sidewall spacer. Since the sidewall is relatively thin, the gate-source and gate-drain spacing can be very small, and the spacing is only controlled by the film thickness, and the repeatability of the device structure is relatively high), reducing the device operating voltage, and further improving the circuit density. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The present invention will be further described below in conjunction with the accompanying drawings.

[0040] Figure 1 is a schematic diagram of the structure of a transistor manufactured by the method of Embodiment 2 of the present invention;

[0041] Figure 2 It is a schematic diagram of the structure of the epitaxial wafer of the present invention;

[0042] Figure 3 is a schematic structural diagram of forming a gate dielectric layer and a gate in step 2 of embodiment 2 of the present invention;

[0043] Figure 4 It is a schematic diagram of the structure of forming a silicon oxide layer and etching back to the first channel layer in step 3 of the second embodiment of the present invention;

[0044] Figure 5 It is a schematic structural diagram of the second channel layer secondary epitaxial growth in step 4 of the second embodiment of the present invention;

[0045] Figure 6 It is a schematic diagram of the structure of forming the gate sidewall and etching back to the second channel layer in step five of the second embodiment of the present invention;

[0046] Figure 7 It is a schematic diagram of the structure of forming gate sidewalls and etching back to the barrier layer in step five of embodiment four of the present invention.

[0047] In the figure: 1. substrate; 2. nucleation layer; 3. buffer layer; 4. high resistance layer; 5. barrier layer; 6. first channel layer; 7. gate dielectric layer; 8. gate; 9. silicon oxide layer; 10. second channel layer; 11. gate sidewall; 12. source; 13. drain. DETAILED DESCRIPTION

[0048] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts belong to the scope of protection of the present invention.

[0049] Embodiment 1

[0050] As Figure 1 shown, the present invention provides a P-channel enhancement-mode gallium nitride transistor structure, which includes an epitaxial wafer. A gate dielectric layer 7 is provided in the middle above the epitaxial wafer. Second channel layers 10 are provided on both sides of the gate dielectric layer 7. A gate 8 is provided above the gate dielectric layer 7. Gate sidewalls 11 are provided on both sides of the gate 8. The gate sidewalls 11 on both sides are connected to the second channel layer 10, and a source electrode 12 and a drain electrode 13 are correspondingly provided outside the gate sidewalls 11 on both sides. The source electrode 12 and the drain electrode 13 are formed on the second channel layer 10.

[0051] Preferably, the above-mentioned epitaxial wafer includes a substrate 1, a nucleation layer 2, a buffer layer 3, a high-resistance layer 4, a barrier layer 5, and a first channel layer 6. A nucleation layer 2 is provided above the substrate 1, a buffer layer 3 is provided above the nucleation layer 2, a high-resistance layer 4 is provided above the buffer layer 3, a barrier layer 5 is provided above the high-resistance layer 4, and a first channel layer 6 is provided above the barrier layer 5. And the above-mentioned gate dielectric layer 7 is located in the middle above the first channel layer 6. The second channel layers 10 on both sides are connected to the first channel layer 6, and the inner ends of the second channel layers 10 are connected to the gate dielectric layer 7 and the gate sidewalls 11.

[0052] Preferably, the above-mentioned source electrode 12 and drain electrode 13 are connected to the second channel layer 10.

[0053] Preferably, the above-mentioned substrate 1 can be a silicon substrate, a silicon carbide substrate, a sapphire substrate, a diamond substrate, etc. In this embodiment, the substrate 1 is a silicon substrate. By using silicon as the substrate, heteroepitaxy of gallium nitride materials can be realized on a large-size wafer, saving the epitaxial cost per unit size.

[0054] Preferably, the above-mentioned nucleation layer 2 can be selected as a gallium nitride layer or an aluminum nitride layer; the above-mentioned buffer layer 3 can be an Al X GaN layer, where 0 < x < 1; the above-mentioned high-resistance layer 4 can be a gallium nitride layer doped with iron or carbon.

[0055] Preferably, the above-mentioned barrier layer 5 is an AlGaN layer, and the first channel layer 6 is an InGaN layer with a thickness of 5-15 nm;

[0056] Preferably, the gate dielectric layer 7 is a high-temperature silicon nitride layer, and the film thickness of the gate dielectric layer 7 is set according to the device performance requirements, ranging from 5 to 20 nm;

[0057] Preferably, the second channel layer 10 is a Mg-doped P-type GaN channel layer with a thickness of 50 to 100 nm;

[0058] Preferably, the above-mentioned gate 8 is a polysilicon layer with a thickness of 500 to 1000 nm, and in-situ doping is performed as required; the above-mentioned gate sidewall 11 can be a single layer of silicon dioxide or a multilayer structure of silicon dioxide / silicon nitride with a thickness of 200 to 500 nm; the above-mentioned source 12 and drain 13 are both source and drain metal layers, and the source and drain metal layers can adopt a Pt (or Ni) / Al stacked structure.

[0059] In this embodiment, InGaN with a relatively narrow bandgap width is used as the channel layer, and GaN / AlGaN with a wider bandgap are used on both sides to form a sandwich structure. Since the band gap of InGaN is smaller than that of AlGaN and GaN, and the valence band difference between InGaN and AlGaN is larger, holes can be more effectively confined in the InGaN channel, and the density and hole mobility of the two-dimensional hole gas can be improved; and a certain amount of doped P-type GaN is secondary epitaxially grown on the unintentionally doped InGaN, so that a certain amount of holes can be shared to enter the two-dimensional hole gas, thereby realizing the separation of doped impurities and carriers, and also improving the concentration and mobility of holes, thereby increasing the output current of the device and improving the driving capability of the device.

[0060] Embodiment 2

[0061] like Figure 1-Figure 6 As shown, the present invention provides a method for manufacturing a P-channel enhancement-mode gallium nitride transistor structure, the manufacturing method comprising the following steps:

[0062] Step 1: preparing an epitaxial wafer. The epitaxial wafer is formed by providing a substrate 1 and sequentially epitaxially growing a nucleation layer 2, a buffer layer 3, a high resistance layer 4, a barrier layer 5 and a first channel layer 6 on the surface of the substrate 1 from bottom to top;

[0063] Step 2: depositing high-temperature silicon nitride on the first channel layer 6 to form a gate dielectric layer 7, wherein the deposition thickness of the gate dielectric layer 7 is set according to performance requirements, ranging from 5 to 20 nm, and then depositing polysilicon to form a gate 8, wherein the deposition thickness of the polysilicon is 500 to 1000 nm, and in-situ doping is performed according to actual requirements, and then photolithography of the gate pattern is performed, and the polysilicon is etched to form a polysilicon gate strip;

[0064] Step 3: Oxidize the polysilicon to form a silicon oxide layer 9 of a certain thickness on the outer layer of the gate 8, with a thickness of 5 to 20 nm, and then use a wet etching process to remove the silicon nitride dielectric in the source and drain regions (areas other than the bottom of the gate 8);

[0065] Step 4: selectively epitaxially grow the second channel layer 10 in the source and drain regions, with a growth thickness in the range of 50 to 100 nm;

[0066] Step 5: depositing a sidewall dielectric layer to form a gate sidewall 11. The sidewall dielectric layer may be a single layer of silicon dioxide or a multilayer structure of silicon dioxide / silicon nitride, with a total thickness of about 200 to 500 nm. Then, etching back to the position of the second channel layer 10 close to the InGaN channel layer and the top of the gate 8;

[0067] Step 6: deposit source and drain metal layers (Pt or Ni / Al stacked structures may be used), remove the source and drain metal layers on the gate 8 by a planarization process (such as photoresist reflow-etch back planarization, or CMP technology), anneal, form source and drain ohmic contacts, and then form a source 12 and a drain 13;

[0068] Step 7: After step 6, an intermetallic dielectric layer is deposited, and then the rear-end via and metal interconnection processes are completed to finally form a P-channel enhancement-mode gallium nitride transistor device.

[0069] Embodiment 3

[0070] The difference between this embodiment and embodiment 2 is that the epitaxial wafers in this embodiment are purchased from outside (customized according to the process requirements such as the epitaxial wafer structure in embodiment 2), or are prefabricated using the method of step one in embodiment 2 before the manufacturing process, thereby shortening the overall production process (the integrated process is carried out in sections and simultaneously), shortening the actual process time, and improving the efficiency of production and manufacturing.

[0071] Embodiment 4

[0072] like Figure 7 As shown, the difference between this embodiment and the second or third embodiment is that in step five of this embodiment, after depositing the sidewall dielectric layer to form the gate sidewall 11, the sidewall dielectric layer is etched back to the top of the barrier layer 5 and the gate 8, and the other steps are completely the same.

[0073] The present invention uses polysilicon as gate metal and forms two-dimensional hole gas (2DHG) as gate-source and gate-drain access regions on both sides of the gate metal using a secondary epitaxial process, thereby forming an enhanced P-channel device.

[0074] The P-channel enhancement-mode gallium nitride transistor device formed by the manufacturing method of the present invention has a gate dielectric layer 7. During the manufacturing process of the transistor, the gate dielectric layer 7 can effectively block the direct attack of the etching process on the InGaN surface, thereby avoiding the process problem of etching damage on the InGaN surface at the gate 8, and the semiconductor interface at the gate 8 is good, which can improve the reliability of the device.

[0075] The length of the gate 8 of the present invention can be made into tens of nanometers, which reduces the capacitance between the gate 8 and the InGaN channel, thereby reducing the switching time of the transistor and increasing the operating frequency, so that a device with a higher operating frequency can be obtained;

[0076] The present invention can adjust the device threshold voltage by regulating the polysilicon doping concentration in the gate 8 and the InGaN channel thickness, thereby reducing the device operating voltage.

[0077] The present invention uses polysilicon as the gate metal, which can ensure the performance while taking into account the thickness of the gate 8, and combines the sidewall process and the self-alignment process to form a small-sized P-channel enhancement-type gallium nitride transistor, thereby reducing the device operating voltage and further improving the circuit density.

[0078] In the present invention, the ohmic contact is formed by using metal and a certain doped P-type GaN (or metal and Al GaN), and the ohmic contact is smaller.

[0079] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, and a specific direction structure and operation, and therefore, cannot be understood as a limitation on the present invention. In addition, "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0080] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0081] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A P-channel enhancement-mode gallium nitride transistor structure, characterized in that: include: An epitaxial wafer comprising a first channel layer (6); A gate dielectric layer (7) formed above the first channel layer (6); A gate (8) formed above the gate dielectric layer (7); A second channel layer (10) is formed on both sides of the gate dielectric layer (7); Gate sidewalls (11) are formed on both sides of the gate (8) and are connected to the second channel layer (10); The source electrode (12) and the drain electrode (13) are formed on the second channel layer (10) and are located outside the gate sidewalls (11) on both sides.

2. A P-channel enhancement-mode gallium nitride transistor structure according to claim 1, characterized in that: The epitaxial wafer comprises a substrate (1), a nucleation layer (2) is arranged above the substrate (1), a buffer layer (3) is arranged above the nucleation layer (2), a high resistance layer (4) is arranged above the buffer layer (3), a barrier layer (5) is arranged above the high resistance layer (4), and a first channel layer (6) is arranged above the barrier layer (5).

3. A P-channel enhancement-mode gallium nitride transistor structure according to claim 2, characterized in that: The bottom of the second channel layer (10) is connected to the first channel layer (6), the inner end of the second channel layer (10) is connected to the gate dielectric layer (7) and the gate sidewall (11), and the source (12) and the drain (13) are connected to the second channel layer (10).

4. A P-channel enhancement-mode gallium nitride transistor structure according to claim 2, characterized in that: The nucleation layer (2) is a gallium nitride layer or an aluminum nitride layer, and the buffer layer (3) is an Al x GaN layer, where 0 < x < 1. The high-resistance layer (4) is a gallium nitride layer doped with iron or carbon. The barrier layer (5) is an AlGaN layer. The first channel layer (6) is an InGaN layer with a thickness of 5 to 15 nm.

5. The P-channel enhancement-mode gallium nitride transistor structure according to claim 1, characterized in that: The gate dielectric layer (7) is a silicon nitride layer with a thickness of 5 to 20 nm, and the second channel layer (10) is a Mg-doped P-type GaN channel layer with a thickness of 50 to 100 nm.

6. A P-channel enhancement-mode gallium nitride transistor structure according to claim 1, characterized in that: The gate (8) is a polysilicon layer with a thickness of 500-1000 nm, and the gate sidewall (11) is a silicon dioxide single layer or a silicon dioxide / silicon nitride multilayer structure with a thickness of 200-500 nm.

7. The P-channel enhancement-mode gallium nitride transistor structure according to claim 1, characterized in that: The source electrode (12) and the drain electrode (13) are both Pt / Al or Ni / Al stacked layer structures.

8. A method for manufacturing a P-channel enhancement-mode gallium nitride transistor structure, characterized in that: The method for manufacturing a P-channel enhancement-mode gallium nitride transistor structure according to any one of claims 1 to 7 comprises the following steps: Step 1: providing or preparing an epitaxial wafer; Step 2: depositing silicon nitride on the first channel layer (6) to form a gate dielectric layer (7), then depositing polysilicon to form a gate (8), then photolithography of the gate pattern, and etching the polysilicon to form a polysilicon gate strip; Step 3: oxidize the polysilicon to form a silicon oxide layer (9) on the outer layer of the gate (8), and then use a wet etching process to remove the silicon nitride dielectric in the source and drain regions; Step 4: selectively performing secondary epitaxial growth on the source and drain regions. Step 5: depositing a sidewall dielectric layer to form a gate sidewall (11), and then etching back to the second channel layer (10) and the top of the gate (8); Step 6: depositing a source and drain metal layer, removing the source and drain metal layer on the gate (8) by a planarization process, and performing an annealing process to form a source and drain ohmic contact, thereby forming a source electrode (12) and a drain electrode (13); Step 7: deposit an intermetallic dielectric layer, and then complete the rear-end through-hole and metal interconnection process to finally form a P-channel enhancement-mode gallium nitride transistor device.

9. The method for manufacturing a P-channel enhancement-mode gallium nitride transistor structure according to claim 8, characterized in that: The epitaxial wafer preparation method comprises: providing a substrate (1), and epitaxially growing a nucleus layer (2), a buffer layer (3), a high resistance layer (4), a barrier layer (5) and a first channel layer (6) in sequence from bottom to top on the surface of the substrate (1).

10. A method for manufacturing a P-channel enhancement-mode gallium nitride transistor structure, characterized in that: The method for manufacturing a P-channel enhancement-mode gallium nitride transistor structure according to any one of claims 1 to 7 comprises the following steps: Step 1: providing or preparing an epitaxial wafer; Step 2: depositing silicon nitride on the first channel layer (6) to form a gate dielectric layer (7), then depositing polysilicon to form a gate (8), then photolithography of the gate pattern, and etching the polysilicon to form a polysilicon gate strip; Step 3: oxidize the polysilicon to form a silicon oxide layer (9) on the outer layer of the gate (8), and then use a wet etching process to remove the silicon nitride dielectric in the source and drain regions; Step 4: selectively performing secondary epitaxial growth on the source and drain regions. Step 5: depositing a sidewall dielectric layer to form a gate sidewall (11), and then etching back to the top of the barrier layer (5) and the gate (8); Step 6: depositing a source and drain metal layer, removing the source and drain metal layer on the gate (8) by a planarization process, and performing an annealing process to form a source and drain ohmic contact, thereby forming a source electrode (12) and a drain electrode (13); Step 7: deposit an intermetallic dielectric layer, and then complete the rear-end through-hole and metal interconnection process to finally form a P-channel enhancement-mode gallium nitride transistor device.

Images