Semiconductor device

Abstract

A semiconductor device capable of switching a connection ground of a back gate contact region between a source region and a drain region is provided. A semiconductor device (1, 151, 161, 201) is provided with: a semiconductor chip (2) having a first main surface (3) and a second main surface (4) facing the first main surface (3); a first conductivity-type first drain region (21) formed in a surface layer portion of the first main surface (3); a back gate region (16) of a second conductivity type, which is formed in a surface layer portion of the first main surface (3) so as to be spaced apart from the first drain region (21); a source region (23) of the first conductivity type, which is formed at a surface layer portion of the back gate region (16) so as to be spaced inward from a peripheral edge (61-64) of the back gate region (16); a back gate contact region (24) of a second conductivity type, which is formed in a surface layer portion of the back gate region (16) so as to be electrically isolated from the source region (23); and a gate electrode (20) facing the channel region (53) in the back gate region (16), the gate electrode (20) being formed between peripheral edges (61-64) of the back gate region (16) and the source region (23).

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] Patent Document 1 discloses a semiconductor device including a p-type silicon substrate and an n-channel LDMOS formed on the silicon substrate.

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] Patent Document 1: Japanese Patent Application Publication No. 2023-017388 Summary of the invention

[0006] Embodiments of the present disclosure provide a semiconductor device capable of switching a destination of a back gate contact region between a source region and a drain region.

[0007] According to an embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor chip having a first main surface and a second main surface opposite to the first main surface; a first drain region of a first conductivity type, formed in a surface portion of the first main surface; a back gate region of a second conductivity type, formed in a surface portion of the first main surface, spaced apart from the first drain region; a source region of a first conductivity type, formed in a surface portion of the back gate region, spaced inwardly from a periphery of the back gate region; a back gate contact region of a second conductivity type, formed in a surface portion of the back gate region, electrically isolated from the source region; and a gate electrode facing a channel region, formed in the back gate region between the periphery of the back gate region and the source region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure.

[0009] Figure 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 is a view showing an example of a planar layout of an impurity diffusion region in the LDMOS region.

[0011] Figure 3 is a view showing an example of a planar shape of a field insulating film in the LDMOS region.

[0012] Figure 4 Is Figure 3 An enlarged view of the portion enclosed by the middle dotted line IV.

[0013] Figure 5is a view showing an example of a planar shape of a gate electrode in the LDMOS region.

[0014] Figure 6 It is a cross-sectional view taken along the line VI-VI shown in FIG5.

[0015] Figure 7 Is Figure 6 An enlarged view of the portion enclosed by the dashed line VII.

[0016] Figure 8 A circuit diagram of a semiconductor device.

[0017] Fig. 9 is a graph showing a relationship between a fourth width of the back gate contact region in the second direction and an on-state breakdown voltage of the semiconductor device.

[0018] Fig. 10A is shown corresponding to Figure 7 A view of a portion of the manufacturing process of a semiconductor device.

[0019] Fig. 10B It is shown Fig. 10A view of the next step.

[0020] Fig. 10C It is shown Fig. 10B view of the next step.

[0021] Fig. 10D It is shown Fig. 10C view of the next step.

[0022] Fig.10E It is shown Fig. 10D view of the next step.

[0023] Fig.10F It is shown Fig.10E view of the next step.

[0024] Figure 10G It is shown Fig.10F view of the next step.

[0025] Fig. 10H Shows Figure 10G view of the next step.

[0026] Fig.10I It is shown Fig. 10H view of the next step.

[0027] Fig.10J It is shown Fig.10I view of the next step.

[0028] Figure 10K It is shown Fig.10Jview of the next step.

[0029] Fig.10L Shows Figure 10K view of the next step.

[0030] Figure 10M Shows Fig.10L view of the next step.

[0031] Fig.10N Shows Figure 10M view of the next step.

[0032] Fig.11 is shown corresponding to Figure 4 FIG. 1 is a view of a first variation of the planar structure of the semiconductor device, the portion surrounded by the dashed line XI.

[0033] Fig.12 is corresponding to Fig.11 FIG. 2 is a view of a second variation of the planar structure of a semiconductor device.

[0034] Fig.13 is corresponding to Figure 7 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other cases, well-known methods, procedures, systems, and components are not described in detail in order to avoid unnecessarily obscuring aspects of the various embodiments.

[0036] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present disclosure.

[0038] The semiconductor device 1 includes a semiconductor chip 2 formed into a rectangular parallelepiped shape. The semiconductor chip 2 forms the outer shape of the semiconductor device 1 and has a structure in which, for example, a single crystal semiconductor material is formed into a chip shape (rectangular parallelepiped shape). The semiconductor chip 2 is made of a semiconductor material such as Si or SiC. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and a first side surface 5 to a fourth side surface 8 connecting the first main surface 3 and the second main surface 4. The first side surface 5 to the fourth side surface 8 include a first side surface 5, a second side surface 6, a third side surface 7 and a fourth side surface 8. The third side surface 7 and the fourth side surface 8 extend in a first direction X and face each other in a second direction Y orthogonal to the first direction X. The first side surface 5 and the second side surface 6 extend in a second direction Y and face each other in the first direction X.

[0039] In a plan view (hereinafter referred to as "top view") when viewed from a third direction Z (the normal direction of the first main surface 3 and the second main surface 4), the first main surface 3 and the second main surface 4 are formed into a quadrilateral / square shape. The first main surface 3 can also be referred to as a device surface on which a functional device is formed. The second main surface 4 can also be referred to as a non-device surface on which no functional device is formed. A plurality of device regions 9 are formed on the first main surface 3. The number and arrangement of the device regions 9 are arbitrary. The plurality of device regions 9 may include functional devices formed by using the surface portion of the first main surface 3. The functional device may include, for example, at least one selected from the group of semiconductor switching devices, semiconductor rectifier devices, and passive devices. The functional device may include, for example, a circuit network obtained by combining at least two selected from the group of semiconductor switching devices, semiconductor rectifier devices, and passive devices.

[0040] The semiconductor switching device may include, for example, at least one selected from the group of a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET). The semiconductor rectifying device may include, for example, at least one selected from the group of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include, for example, at least one selected from the group of a resistor, a capacitor, and an inductor.

[0041] Figure 2 is a view showing an example of a planar layout of an impurity diffusion region in the LDMOS region 11 . Figure 3 is a view showing an example of the planar shape of the field insulating film 19 in the LDMOS region 11 . Figure 4 Is Figure 3 An enlarged view of the portion enclosed by the middle dotted line IV. Figure 5 is a view showing an example of the planar shape of the gate electrode 20 in the LDMOS region 11 .

[0042] Figure 6 is along Figure 5 A cross-sectional view taken along line VI-VI is shown. Figure 7 Is Figure 6 The enlarged view of the portion surrounded by the dotted line VII is shown in FIG. Figures 1 to 7 The structure of the LDMOS region 11 is specifically described, in which lateral double diffused MOSFETs (LDMOSFETs) 10 as examples of functional devices are formed in a plurality of device regions 9 .

[0043] The LDMOSFET 10 includes a first p-type region 12, a second p-type region 13, a buried region 14, a first well region (well region) 15, a back gate region 16, a drift region 17, a second well region 18, a field insulating film 19, a gate electrode 20, a first drain region 21, a second drain region 22, a source region 23, a back gate contact region 24, a first impurity region 25, a second impurity region 26, an interlayer insulating film 27, a drain wiring 28, a first drain contact 29, a second drain contact 30, a source wiring 31, a source contact 32, a back gate wiring 33 and a back gate contact 34.

[0044] Reference Figure 6 and Figure 7 The first p-type region 12 is formed on the surface of the second main surface 4 of the semiconductor chip 2. The first p-type region 12 is a p-type (second conductivity type) impurity region. The first p-type region 12 is formed on the entire surface of the second main surface 4 and is exposed from the second main surface 4 and the first side surface 5 to the fourth side surface 8 (see Figure 1 ).

[0045] The p-type impurity concentration of the first p-type region 12 may be 1.0×10 13 cm -3 Above and 1.0×10 15 cm -3 The thickness of the first p-type region 12 may be 100 μm or more and 500 μm or less. The first p-type region 12 may have a structure in which a p-type epitaxial layer (Si epitaxial layer) is stacked on a p-type semiconductor substrate formed on the second main surface 4 side. The first p-type region 12 may be a p-type semiconductor substrate. Because the first p-type region 12 has a relatively low impurity concentration, it may be referred to as a p-type region.

[0046] Reference Figure 6 and Figure 7The second p-type region 13 is formed on the surface of the first main surface 3 of the semiconductor chip 2. The second p-type region 13 is a p-type impurity region. The second p-type region 1 is formed on the entire surface of the first main surface 3 and is exposed from the first main surface 3 and the first side surface 5 to the fourth side surface 8 (see Figure 1 ). For example, the thickness of the second p-type region 13 is less than the thickness of the first p-type region 12. The thickness of the second p-type region 13 may be greater than or equal to 5 μm and less than or equal to 20 μm. In the present embodiment, the second p-type region 13 may be a p-type epitaxial layer. The p-type impurity concentration of the second p-type region 13 may be the same as the p-type impurity concentration of the first p-type region 12. The p-type impurity concentration of the second p-type region 13 may be 1.0×10 13 cm -3 Above and 1.0×10 15 cm -3 Since the second p-type region 13 has a relatively low impurity concentration, it may also be referred to as a p-type region.

[0047] The second p-type region 13 is insulated and separated into a plurality of regions by an element isolation structure (eg, element isolation well, deep trench isolation (DTI), shallow trench isolation (STI), etc.) not shown. The element isolation structure divides the semiconductor chip 2 into a plurality of device regions 9 . Figures 2 to 7 It is shown that the second p-type region 13 of the LDMOS region 11 is formed among a plurality of separated second p-type regions 13 .

[0048] Reference Figure 2 The second p-type region 13 includes a p-type inner region 13A and a ring-shaped p-type outer region 13B, which surrounds the side of the p-type inner region 13A and contacts the element isolation structure. The back gate region 16, the drift region 17, etc. are formed in the p-type inner region 13A.

[0049] Reference Figure 6 and Figure 7 , the buried region 14 is an n-type (first conductivity type) region (B / L layer) buried between the first p-type region 12 and the p-type inner region 13A. Specifically, the buried region 14 extends along the first main surface 3 in a layered manner to cross the boundary between the first p-type region 12 and the p-type inner region 13A (i.e., the second p-type region 13). Although not shown, the buried region 14 has a quadrilateral shape when viewed from above. The buried region 14 is electrically connected to the first p-type region 12 and the second p-type region 13. The thickness of the buried region 14 may be greater than 0.1 μm and less than 5 μm. The n-type impurity concentration of the buried region 14 may be 1.0×10 16 cm -3 Above and 1.0×10 20 cm -3The n-type impurity concentration of the buried region 14 may be higher than the n-type impurity concentration of the drift region 17 . The n-type impurity concentration of the buried region 14 may be the same as the n-type impurity concentration of the drift region 17 .

[0050] Reference Figure 2 , Figure 6 and Figure 7 The first well region 15 is an n-type impurity region formed in the surface layer portion of the second p-type region 13. The first well region 15 is formed in a ring shape in a plan view. Figure 2 , the first well region 15 may be formed into a quadrangular ring shape extending long in the first direction X in a top view. The first well region 15 overlaps with the periphery of the buried region 14 in a top view. The bottom of the first well region 15 reaches the buried region 14. The depth of the first well region 15 is the same in the entire circumferential direction. The periphery of the buried region 14 contacts the entire circumferential area of ​​the first well region 15 from below.

[0051] The n-type impurity concentration of the first well region 15 may be 1.0×10 16 cm -3 Above and 1.0×10 20 cm -3 The n-type impurity concentration of the first well region 15 may be higher than the n-type impurity concentration of the drift region 17 . The n-type impurity concentration of the first well region 15 may be the same as the n-type impurity concentration of the drift region 17 .

[0052] Reference Figure 2 , Figure 6 and Figure 7 , the annular first well region 15 surrounds the side of the p-type inner region 13A in the second p-type region 13. Since the bottom of the first well region 15 reaches the buried region 14, the p-type inner region 13A is surrounded by the n-type region including the buried region 14 and the first well region 15 in the first direction X, the second direction Y, and the third direction Z. As a result, the p-type inner region 13A is electrically isolated from the p-type outer region 13B and the first p-type region 12 by the n-type region including the buried region 14 and the first well region 15.

[0053] Reference Figure 6 and Figure 7 The back gate region 16 is a region in the LDMOS region 11 to which the back gate voltage of the LDMOSFET 10 is applied. The back gate region 16 is a p-type back gate region and is formed in the surface layer portion of the p-type inner region 13A. The depth of the bottom of the back gate region 16 is smaller than the depth of the bottom of the first well region 15. The depth of the bottom of the back gate region 16 is smaller than the depth of the bottom of the drift region 17.

[0054] Reference Figure 2 , Figure 3 and Figure 6 , the back gate region 16 is formed into an elliptical shape extending long in the first direction X in a plan view. The back gate region 16 has a first periphery 61 and a second periphery 62 extending linearly spaced from each other in the first direction X. The back gate region 16 has a third periphery 63 and a fourth periphery 64 connecting the first periphery 61 and the second periphery 62. The third periphery 63 and the fourth periphery 64 face each other in the first direction X. The third periphery 63 and the fourth periphery 64 are formed into an arc shape bulging outward in the first direction X.

[0055] Reference Figure 6 and Figure 7 , the back gate region 16 includes a low concentration portion (second portion) 36 formed on the periphery of the back gate region 16. The low concentration portion 36 is formed on the entire circumferential area of ​​the back gate region 16. The low concentration portion 36 is formed on the periphery of the back gate region 16 except for the vicinity of the bottom. The low concentration portion 36 is formed in an elliptical ring shape along the periphery (first periphery 61 to fourth periphery 64) of the back gate region 16. The outer peripheral portion of the low concentration portion 36 is in contact with the drift region 17 on the entire circumferential area of ​​the back gate region 16. The p-type impurity concentration of the back gate region 16 may be, for example, 1.0×10 15 cm -3 Above and 5.0×10 16 cm -3 The depth of the bottom of the low-concentration portion 36 is the same as the depth of the bottom of the drift region 17 which will be described below.

[0056] Reference Figure 6 and Figure 7 , the portion of the back gate region 16 other than the low concentration portion 36 is a high concentration portion (first portion) 35. The p-type impurity concentration of the high concentration portion 35 may be, for example, 1.0×10 16 cm -3 Above and 5.0×10 17 cm -3 the following.

[0057] Reference Figure 6 and Figure 7 The drift region 17 is formed in the surface layer of the p-type inner region 13A. The drift region 17 is an n-type drift region. The n-type impurity concentration of the drift region 17 may be, for example, 5.0×10 15 cm -3 Above and 5.0×10 17 cm -3 The depth of the bottom of the drift region 17 is less than the depth of the bottom of the first well region 15. The depth of the bottom of the drift region 17 is greater than the depth of the bottom of the back gate region 16. The second width W of the drift region 17 is 2smaller than the first width W of the back gate region 16 1 .

[0058] Reference Figure 2 The drift region 17 surrounds the back gate region 16 in a plan view. The drift region 17 may be formed in an elliptical ring shape extending long in a plan view along the first direction X. The inner periphery 17A of the drift region 17 contacts the periphery (the first periphery 61 to the fourth periphery 64) of the back gate region 16 over the entire circumference.

[0059] Reference Figure 6 and Figure 7 The second well region 18 is a p-type impurity region formed in the surface layer of the second p-type region 13. The p-type impurity concentration of the second well region 18 may be, for example, 1.0×10 16 cm -3 Above and 5.0×10 17 cm -3 The p-type impurity concentration of the second well region 18 is the same as the p-type impurity concentration of the high concentration portion 35 of the second well region 18. The p-type impurity concentration of the second well region 18 may be higher than the p-type impurity concentration of the high concentration portion 35. The p-type impurity concentration of the second well region 18 may be lower than the p-type impurity concentration of the high concentration portion 35.

[0060] Reference Figure 2 , the second well region 18 may be formed in a quadrilateral annular shape extending long in the first direction X when viewed from above. The second well region 18 surrounds the drift region 17 when viewed from above. The second well region 18 is formed spaced apart from the drift region 17 in both the first direction X and the second direction Y when viewed from above. The second well region 18 is surrounded by the first well region 15 when viewed from above. The second well region 18 is formed spaced apart from the first well region 15 in both the first direction X and the second direction Y when viewed from above. Although not shown, the second well region 18 may be formed in an elliptical annular shape extending long in the first direction X when viewed from above.

[0061] Reference Figure 2 and Figure 3 A field insulating film 19 is formed on the first main surface 3 of the semiconductor chip 2. The field insulating film 19 covers the first main surface 3. For the sake of clarity, the field insulating film 19 is Figure 3 Indicated by hatching. Figure 3 The non-hatched region in is a region not covered by the field insulating film 19. The field insulating film 19 may be, for example, a LOCOS oxide film formed by selectively oxidizing the surface of the second p-type region 13 (the first main surface 3).

[0062] Reference Figure 3The field insulating film 19 has a first opening 41, a second opening 42, a third opening 43, and a fourth opening 44. The first opening 41 is formed in an elliptical shape extending long in the first direction X in a plan view. The first opening 41 exposes a portion of the drift region 17 (the first drain region 21). The second opening 42 is formed in an elliptical shape extending long in the first direction X in a plan view. The second opening 42 exposes a portion of the first well region 15 (the second drain region 22).

[0063] Reference Figure 3 , the third opening portion 43 is formed in an elliptical shape. The third opening portion 43 exposes a portion of the back gate region 16 (the back gate contact region 24). The fourth opening portion 44 extends long in the first direction X in a plan view, and is formed in an elliptical ring shape surrounding the third opening portion 43 in a plan view. The fourth opening portion 44 exposes the back gate region 16 and the drift region 17. The opening width of the elliptical ring-shaped fourth opening portion 44 is greater than the opening width of the elliptical third opening portion 43.

[0064] Reference Figure 3 , the first opening 41 may be formed in a pair so as to sandwich the third opening 43 and the fourth opening 44 in the second direction Y. The second opening 42 may be formed in a pair so as to sandwich the first opening 41, the third opening 43 and the fourth opening 44 in the second direction Y. The first opening 41, the second opening 42 and the third opening 43 may be formed in a quadrilateral shape extending long in the first direction X in a plan view.

[0065] Reference Figure 6 and Figure 7 The first drain region 21 is formed in the surface layer of the drift region 17. The first drain region 21 may have a higher n-type impurity concentration than the drift region 17. The n-type impurity concentration of the first drain region 21 may be, for example, 1.0×10 16 cm -3 Above and 5.0×10 17 cm -3 the following.

[0066] Reference Figure 4 The first drain region 21 is exposed from the field insulating film 19 at the first opening 41. The first drain region 21 has a first side portion 21A and a second side portion 21B extending in the first direction X while being spaced apart from each other. The first drain region 21 has a third side portion 21C and a fourth side portion 21D connecting the first side portion 21A and the second side portion 21B (see Figure 3 ). The third side portion 21C and the fourth side portion 21D are formed in an arc shape bulging outward along the first direction X. In a plan view, the first to fourth side portions 21A to 21D may all be arranged inside the outer periphery of the drift region 17 .

[0067] Reference Figure 6 and Figure 7 The second drain region 22 is formed in the surface layer of the first well region 15. The second drain region 22 may have a higher n-type impurity concentration than the first well region 15. The n-type impurity concentration of the second drain region 22 may be, for example, 1.0×10 16 cm -3 Above and 5.0×10 17 cm -3 the following.

[0068] Reference Figure 4 The second drain region 22 is exposed from the field insulating film 19 at the second opening 42. The second drain region 22 has a first side portion 22A and a second side portion 22B extending along the first direction X and spaced apart from each other. The second drain region 22 has a third side portion 22C and a fourth side portion 22D connecting the first side portion 22A and the second side portion 22B (see Figure 3 ). The third side portion 22C and the fourth side portion 22D are formed in an arc shape bulging outward along the first direction X. In a plan view, the first to fourth side portions 22A to 22D may all be arranged inside the outer periphery of the first well region 15 .

[0069] Reference Figure 5 A gate electrode 20 is formed on the first main surface 3 of the semiconductor chip 2. For the sake of clarity, the gate electrode 20 is Figure 5 . For example, the gate electrode 20 may include a conductive material such as polysilicon or aluminum. The gate electrode 20 is formed in a ring shape when viewed from above. The gate electrode 20 may include a pair of first portions 51 facing each other in the second direction Y, and a second portion 52 connecting the pair of first portions 51 to each other. In the present embodiment, the first portion 51 is formed in a straight line shape extending parallel to each other along the first direction X, and the second portion 52 is formed in an arc shape bulging outward in the first direction X. An opening portion 50 is formed in the central portion of the gate electrode 20 separated by a pair of first portions 51 and a pair of second portions 52. The opening portion 50 is formed in an elliptical shape extending along the first direction X when viewed from above. The opening portion 50 exposes a portion of the back gate region 16. Specifically, the opening portion 50 exposes the source region 23 and the back gate contact region 24 as a whole.

[0070] Reference Figure 7 The region in the back gate region 16 that the gate electrode 20 faces is the channel region 53 of the LDMOSFET 10. The formation of a channel in the channel region 53 is controlled by the gate electrode 20. The thickness of the gate electrode 20 may be, for example, 0.1 μm or more and 0.4 μm or less. When a channel is formed in the back gate region 16, the gate electrode 20 provides a threshold voltage (VTH ).

[0071] Reference Figure 7 A gate insulating film 54 is formed between the gate electrode 20 and the first main surface 3. The gate insulating film 54 may be, for example, silicon oxide (SiO 2 The thickness of the gate insulating film 54 can be, for example, not less than 0.2 nm and not more than 100 nm.

[0072] Reference Figure 7 The gate electrode 20 may integrally include an annular control portion 55 on the side (inside) of the opening portion 50 and an annular field plate portion 56 on the outside compared to the control portion 55. The control portion 55 of the gate electrode 20 sequentially covers the back gate region 16 (channel region 53) and the drift region 17 from the inside to the outside via the gate insulating film 54. On the drift region 17, the field plate portion 56 of the gate electrode 20 is formed on the field insulating film 19.

[0073] Reference Figure 7 , a side wall structure 57 is formed on the side of the gate electrode 20. The side wall structure 57 is formed on both the inner side (the side of the opening 50) and the outer side of the gate electrode 20.

[0074] Reference Figure 7 A silicide layer 60 is formed on the first main surface 3 except for the portion where the gate insulating film 54 is formed. Therefore, the silicide layer 60 may be a compound containing silicon (Si) and a transition metal such as titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt) or tungsten (W).

[0075] Reference Figure 7 The source region 23 and the back gate contact region 24 are formed on the surface of the back gate region 16. The source region 23 has a strip shape extending along the first direction X. The source region 23 is an n-type impurity region. The n-type impurity concentration of the source region 23 may be, for example, 1.0×10 16 cm -3 Above and 5.0×10 17 cm -3 The source region 23 may have a higher n-type impurity concentration than the drift region 17. The source region 23 includes a pair of source regions 23 sandwiching the back gate contact region 24 in the second direction Y.

[0076] Reference Figure 4 The source region 23 has a first side portion 23A and a second side portion 23B extending along the first direction X and spaced apart from each other. The source region 23 has a third side portion 23C and a fourth side portion 23D connecting the first side portion 23A and the second side portion 23B (see Figure 3). The third side portion 23C and the fourth side portion 23D are formed into an arc shape that bulges outward in the first direction X. The first side portion 23A to the fourth side portion 23D are all arranged inward from the periphery (the first periphery 61 to the fourth periphery 64) of the back gate region 16 when viewed from above. That is, the source region 23 is formed in the surface portion of the back gate region 16, spaced inward from the periphery (the first periphery 61 to the fourth periphery 64) of the back gate region 16.

[0077] The third width W of each source region 23 in the second direction Y 3 The third width W is not less than 0.8 μm and not more than 1.0 μm. 3 The source regions 23 may be constant over the entire region in the first direction X. Both ends of the pair of source regions 23 may be aligned in the first direction X. Each source region 23 may be formed in a quadrilateral shape extending long in the first direction X in a plan view.

[0078] Reference Figure 4 The back gate contact region 24 is exposed from the field insulating film 19 in the third opening 43. The back gate contact region 24 has a strip shape extending along the first direction X. The back gate contact region 24 is formed adjacent to the source region 23. The back gate contact region 24 is a p-type impurity region. The back gate contact region 24 may have a higher p-type impurity concentration than the back gate region 16. The p-type impurity concentration of the back gate contact region 24 may be, for example, 1.0×10 19 cm -3 Above and 2.0×10 20 cm -3 the following.

[0079] Reference Figure 4 The back gate contact region 24 has a first side portion 24A and a second side portion 24B extending along the first direction X and spaced apart from each other. The back gate contact region 24 has a third side portion 24C and a fourth side portion 24D connecting the first side portion 24A and the second side portion 24B (see Figure 3 ). The third side portion 24C and the fourth side portion 24D are formed into an arc shape that bulges outward in the first direction X. The first side portion 24A to the fourth side portion 24D are all arranged inward from the periphery (the first periphery 61 to the fourth periphery 64) of the back gate region 16 in a plan view. That is, the back gate contact region 24 is formed in the surface layer portion of the back gate region 16, spaced inward from the periphery (the periphery 61 to the fourth periphery 64) of the back gate region 16.

[0080] Reference Figure 7 , the fourth width W of the back gate contact region 24 in the second direction Y 4 The fourth width W is not less than 0.6 μm and not more than 0.8 μm. 4 Less than the third width W3 (W 4 <W 3 ). The fourth width W 4 Can be equal to or greater than the third width W 3 (W 4 ≥W 3 ). The fourth width W 4 The thickness may be constant over the entire region in the first direction X. The back gate contact region 24 may be formed in a quadrilateral shape extending long in the first direction X in a plan view.

[0081] Reference Figure 4 and Figure 7 The back gate contact region 24 and the source region 23 are electrically isolated by the field insulating film 19 in the surface portion of the back gate region 16. The back gate contact region 24 and the source region 23 are adjacent to each other and are spaced apart from each other in the second direction Y. Figure 4 , a first interval W between the back gate contact region 24 and the source region 23 in the second direction Y 11 The first region W is not less than 0.8 μm and not more than 1.0 μm. 11 Greater than the fourth region W 4 (W 11 >W 4 ). The first interval W 11 Can be equal to or less than the fourth width W 4 (W 11 ≤W 4 ).

[0082] Reference Figure 2 and Figure 7 The first impurity region 25 is a p-type impurity region. The first impurity region 25 is formed on the second main surface 4 side relative to the back gate region 16. The first impurity region 25 overlaps with the back gate region 16 in a plan view. Figure 7 As shown, the first impurity region 25 may be in contact with the back gate region 16. Although not shown, the first impurity region 25 may be spaced apart from the back gate region 16 in the depth direction (so as to be close to the second main face 4).

[0083] The p-type impurity concentration of the first impurity region 25 may be, for example, 1.0×10 15 cm -3 Above and 5.0×10 1 6 cm -3 The p-type impurity concentration of the first impurity region 25 may be the same as the p-type impurity concentration of the high concentration portion 35 of the back gate region 16. The p-type impurity concentration of the first impurity region 25 may be lower than the p-type impurity concentration of the high concentration portion 35. The p-type impurity concentration of the first impurity region 25 may be higher than the p-type impurity concentration of the high concentration portion 35.

[0084] Reference Figure 2 and Figure 7 , the first impurity region 25 is formed in an elliptical shape extending long in the first direction X in a plan view. The first impurity region 25 has a first periphery 71 and a second periphery 72 extending linearly in the first direction X while being spaced apart from each other. The first impurity region 25 has a third periphery 73 and a fourth periphery 74 connecting the first periphery 71 and the second periphery 72. The third periphery 73 and the fourth periphery 74 face each other in the first direction X. The third periphery 73 and the fourth periphery 74 are formed in an arc shape bulging outward in the first direction X. The first periphery 71, the second periphery 72, the third periphery 73 and the fourth periphery 74 of the first impurity region 25 are spaced apart inward from the first periphery 61, the second periphery 62, the third periphery 63 and the fourth periphery 64 of the back gate region 16, respectively.

[0085] Reference Figure 2 and Figure 7 , the first impurity region 25 is not formed in the region facing the gate electrode 20 in the depth direction (third direction Z). That is, the first impurity region 25 is not formed in the region facing the channel region 53 in the depth direction (third direction Z).

[0086] Reference Figure 7 The depth of the bottom of the first impurity region 25 is less than the depth of the bottom of the first well region 15. The first impurity region 25 is in contact with the high concentration portion 35 of the back gate region 16. The first impurity region 25 is not in contact with the low concentration portion 36 of the back gate region 16.

[0087] Reference Figure 7 , the second impurity region 26 is a p-type region. The second impurity region 26 is formed on the second main surface 4 side relative to the second well region 18. Although not shown, the second impurity region 26 overlaps with the second well region 18 when viewed from above. Although not shown, the second impurity region 26 has a quadrilateral ring shape. The second impurity region 26 may be in contact with the second well region 18. Although not shown, the second impurity region 26 may be formed to be spaced apart from the second well region 18 in the depth direction (so as to be close to the second main surface 4).

[0088] The p-type impurity concentration of the second impurity region 26 may be, for example, 1.0×10 15 cm -3 Above and 5.0×10 16 cm -3The p-type impurity concentration of the second impurity region 26 is the same as the p-type impurity concentration of the second well region 18. The depth of the bottom of the second impurity region 26 is the same as the depth of the bottom of the first impurity region 25. The inner peripheral end of the second impurity region 26 is spaced outward from the inner peripheral end of the second well region 18. The outer peripheral end of the second impurity region 26 is spaced inward from the outer peripheral end of the second well region 18.

[0089] Reference Figure 6 The second impurity region 26 is formed to surround the sides of the first impurity region 25. In other words, the second impurity region 26 faces the first impurity region 25 while being spaced apart from each other in the first direction X and the second direction Y.

[0090] Reference Figure 6 and Figure 7 An interlayer insulating film 27 is formed on the first main surface 3 of the semiconductor chip 2. The interlayer insulating film 27 covers the gate electrode 20. The interlayer insulating film 27 is made of, for example, silicon oxide (SiO 2 ), Silicon Nitride (SiN 2 ) etc. In the present embodiment, the interlayer insulating film 27 is formed of a single layer film of silicon oxide, but may be formed of a plurality of interlayer insulating films 27 .

[0091] Reference Figure 7 A drain wiring 28 is formed on the interlayer insulating film 27. The drain wiring 28 is electrically connected to the first drain region 21 and the second drain region 22 via the first drain contact 29 and the second drain contact 30, respectively. Figure 4 and Figure 7 , the first drain contact 29 is formed to penetrate the interlayer insulating film 27 at a position overlapping with the first drain region 21 in a plan view. More specifically, the first drain contact 29 is electrically connected to the first drain region 21 via the silicide layer 60. The first drain contact 29 may include a plurality of first drain contacts 29 arranged along the first direction X. Although not shown, the first drain contact 29 may be one first drain contact 29 that is long along the first direction X.

[0092] Reference Figure 4 and Figure 7 The second drain contact 30 is formed to penetrate the interlayer insulating film 27 at a position overlapping with the second drain region 22 when viewed from above. More specifically, the second drain contact 30 is electrically connected to the second drain region 22 via the silicide layer 60. The second drain contact 30 may include a plurality of second drain contacts 30 arranged along the first direction X. Although not shown, the second drain contact 30 may be one second drain contact 30 that is long along the first direction X.

[0093] Reference Figure 7, a source wiring 31 is formed on the interlayer insulating film 27. The source wiring 31 is electrically connected to the source region 23 via a source contact 32. Figure 4 and Figure 7 The source contact 32 is formed to penetrate the interlayer insulating film 27 at a position overlapping with the source region 23 in a plan view. More specifically, the source contact 32 is electrically connected to the source region 23 via the silicide layer 60. The source contact 32 includes a plurality of source contacts 32 arranged along the first direction X.

[0094] Reference Figure 7 A back gate wiring 33 is formed on the interlayer insulating film 27. The back gate wiring 33 is electrically connected to the back gate contact region 24 via a back gate contact 34. Figure 4 and Figure 7 The back gate contact 34 is formed to penetrate the interlayer insulating film 27 at a position overlapping with the back gate contact region 24 in a plan view. More specifically, the back gate contact 34 is electrically connected to the back gate contact region 24 via the silicide layer 60. The back gate contact 34 may include a plurality of back gate contacts 34 arranged along the first direction X.

[0095] Reference Figure 4 , a plurality of source contacts 32 connected to one source region 23 are aligned with a plurality of source contacts 32 connected to another source region 23 in the first direction X. The source contacts 32 and the back gate contacts 34 are electrically isolated. The source contacts 32 and the back gate contacts 34 may be aligned with the drain contacts (the first drain contacts 29 and the second drain contacts 30) in the first direction X.

[0096] Although the drain wiring 28, the source wiring 31, and the back gate wiring 33 are made of aluminum (Al) in the present embodiment, they may be made of other conductive materials such as copper (Cu), etc. The drain wiring 28, the source wiring 31, and the back gate wiring 33 may be referred to as a drain conductive layer, a source conductive layer, and a back gate conductive layer, respectively.

[0097] Although the first drain contact 29, the second drain contact 30, the source contact 32, and the back gate contact 34 are made of tungsten (W) in the present embodiment, they may be made of other conductive materials such as aluminum (Al), copper (Cu), etc. In this case, it goes without saying that a barrier film such as TiN may be used.

[0098] Furthermore, although not shown, a gate contact mechanically and electrically connected to the gate electrode 20 is buried in the interlayer insulating film 27. The gate contact is electrically isolated from the first drain contact 29, the second drain contact 30, the source contact 32, and the back gate contact 34.

[0099] As described above, in the LDMOSFET 10 , the source region 23 and the back gate contact region 24 are formed to be electrically isolated from each other. Therefore, the connection ground of the back gate contact region 24 can be switched between the source region 23 and the first drain region 21 .

[0100] Figure 8 2 is a circuit diagram of a semiconductor chip 2. The semiconductor chip 2 includes an LDMOSFET 10 and two body diodes 88. The semiconductor chip 2 includes a source terminal electrode 81, a drain terminal electrode 82, a back gate terminal electrode 83, and a gate terminal electrode 84. The source terminal electrode 81, the drain terminal electrode 82, the back gate terminal electrode 83, and the gate terminal electrode 84 are formed on the outer surface of the semiconductor chip 2. The source wiring 31 of the LDMOSFET 10 (see Figure 7 ) is electrically connected to the source terminal electrode 81. The source terminal electrode 81 may also be referred to as an output terminal. The drain wiring 28 (see Figure 7 ) is electrically connected to the drain terminal electrode 82. The drain terminal electrode 82 may also be referred to as an input terminal. The back gate wiring 33 (see Figure 7 ) is electrically connected to the back gate terminal electrode 83. A gate wiring (not shown) of the LDMOSFET 10 is electrically connected to the gate terminal electrode 84. The above-mentioned gate contact is electrically connected to the gate wiring.

[0101] A first switch 85 is arranged between the source terminal electrode 81 and the back gate terminal electrode 83. A second switch 86 is arranged between the drain terminal electrode 82 and the back gate terminal electrode 83. The opening and closing of the first switch 85 and the second switch 86 are switched by the drive circuit 87. The connection ground of the back gate terminal electrode 83 is selectively switched between the source terminal electrode 81 and the drain terminal electrode 82 by the first switch 85 and the second switch 86. When the LDMOSFET 10 is in the on state, the first switch 85 is in the off state and the second switch 86 is in the off state. That is, the connection ground of the back gate terminal electrode 83 is the drain terminal electrode 82. When the LDMOSFET 10 is in the off state, the first switch 85 is in the closed state and the second switch 86 is in the off state. That is, the connection ground of the back gate terminal electrode 83 is the source terminal electrode 81.

[0102] Two body diodes 88 are formed in the path connecting the source terminal electrode 81 and the drain terminal electrode 82. The two body diodes 88 realize the overcurrent prevention function and the reverse current prevention function. Regardless of whether the connection ground of the back gate terminal electrode 83 is the source terminal electrode 81 or the drain terminal electrode 82, the current flows through the two body diodes 88. That is, the semiconductor chip 2 can realize the overcurrent prevention function and the reverse current prevention function in the on state of the LDMOSFET 10 and the off state of the LDMOSFET 10.

[0103] In this embodiment, one semiconductor chip 2 realizes both the overcurrent prevention function and the reverse current prevention function. Therefore, compared with the case of using a total of two chips (one having an overcurrent prevention function and the other having a reverse current prevention function), the size of the substrate on which the semiconductor chip 2 is arranged can be reduced.

[0104] Furthermore, in the case where both the LDMOSFET for the overcurrent prevention function and the LDMOSFET for the reverse current prevention function are to be mounted on one chip, there is a risk that the chip size may increase.

[0105] In contrast, in the present embodiment, only one LDMOSFET 10 is formed on one semiconductor chip 2. Therefore, the chip size of the semiconductor chip 2 can be reduced compared to the case where both the LDMOSFET for the overcurrent prevention function and the LDMOSFET for the reverse current prevention function are mounted on one chip.

[0106] In the semiconductor device described in Patent Document 1, the source region and the back gate contact region are electrically connected to the same source wiring. That is, the semiconductor device described in Patent Document 1 adopts a butt-jointed structure of the source and the back gate. In this type of semiconductor device, a decrease in the on-state breakdown voltage is suppressed.

[0107] In contrast, in the present embodiment, the source region 23 and the back gate contact region 24 are formed to be electrically separated from each other so as to realize the overcurrent prevention function and the reverse current prevention function in one semiconductor chip 2. That is, a structure is adopted in which the source and the back gate are separated from each other. Since the back gate and the source are separated from each other, there is a concern that the on-state breakdown voltage of the semiconductor chip 2 (semiconductor device 1) will be reduced.

[0108] Fig. 9 24 is a fourth width W of the back gate contact region 24 in the second direction. 4 The graph is a graph showing the relationship between the on-state breakdown voltage of the semiconductor device 1. Fig. 9 In FIG. 1 , the lower limit of the allowable value of the on-state breakdown voltage is shown by a dotted line.

[0109] The on-state breakdown voltage of the semiconductor device 1 depends on the fourth width W of the back gate contact region 24. 4 .from Fig. 9 It can be seen that when the fourth width W 4 When the thickness is 0.4 μm or more and 0.6 μm or less, the on-state breakdown voltage of the semiconductor device 1 can be maintained high. As a result, even when the semiconductor device 1 has a structure in which the source and the back gate are separated from each other, a decrease in the on-state breakdown voltage can be suppressed.

[0110] Furthermore, in the present embodiment, the p-type first impurity region 25 is formed below the back gate region 16. By forming a p-type impurity region having a relatively high concentration below the back gate region 16, it is possible to suppress a decrease in the on-state breakdown voltage of the semiconductor device 1. On the other hand, the concentration of the surface portion of the back gate region 16 remains unchanged. Therefore, while suppressing the influence on the element characteristics of the semiconductor device 1, it is possible to suppress a decrease in the on-state breakdown voltage of the semiconductor device 1.

[0111] Furthermore, as described above, the first impurity region 25 is not formed in the region facing the channel region 53 in the depth direction (third direction Z). If the first impurity region 25 is also formed in the region facing the channel region 53 in the depth direction, there is a threshold voltage (V TH ) will thereby deteriorate. Therefore, in the present embodiment, the first impurity region 25 is not formed in a region facing the channel region 53 in the depth direction.

[0112] FIG. 10A to FIG. 10N 1 is a diagram showing a part of the manufacturing process of the semiconductor device 1 in process order. FIG. 10A to FIG. 10N Corresponds to Figure 7 .

[0113] First, refer to Fig. 10A , prepare a semiconductor wafer 101. The semiconductor wafer 101 is used as a substrate for the semiconductor chip 2 (see Figure 6 and Figure 7 ). The semiconductor wafer 101 is a p-type wafer. The semiconductor wafer 101 corresponds to the first p-type region 12 of the semiconductor device 1 (see Figure 6 and Figure 7 ).

[0114] Next, refer to Fig. 10B , a hard mask (not shown) having an opening is arranged, the opening corresponding to the buried region 14 to be formed (see Figure 6 and Figure 7 ) region, and n-type impurities are selectively introduced into the surface portion of the semiconductor wafer 101 through a hard mask. As a result, an introduction portion 102 is formed in the surface portion of the semiconductor wafer 101. Examples of n-type impurities may include P (phosphorus), As (arsenic), and the like.

[0115] Next, refer to Fig. 10C , an epitaxial layer 103 is formed by epitaxially growing silicon on the semiconductor wafer 101. By forming the epitaxial layer 103, a semiconductor wafer structure 111 including a second p-type region 13 is formed. The epitaxial layer 103 corresponds to the second p-type region 13. The n-type impurities introduced into the introduction portion 102 in the main surface of the semiconductor wafer 101 diffuse into the p-type epitaxial layer 103, thereby forming a buried region 14. The semiconductor wafer structure 111 has a first wafer main surface 112 on one side and a second wafer main surface 113 on the opposite side. The first wafer main surface 112 and the second wafer main surface 113 correspond to the first main surface 3 and the second main surface 4 of the semiconductor chip 2, respectively (see Figure 6 and Figure 7 Next, a sacrificial insulating film 114 is formed on the first wafer main surface 112. The sacrificial insulating film 114 may be, for example, silicon oxide (SiO 2 )membrane.

[0116] Next, refer to Fig. 10D , a p-type first impurity region 25 and a p-type second impurity region 26 are formed.

[0117] Specifically, p-type impurities are selectively introduced into the first wafer main surface 112 via the resist mask RM. Examples of p-type impurities (first impurities) may include B (boron), Al (aluminum), etc. The opening OP of the resist mask RM corresponds to the region where the p-type first impurity region 25 and the p-type second impurity region 26 are to be formed. The opening OP of the resist mask RM includes an elliptical first opening OP1 (corresponding to the first impurity region 25) and a ring-shaped second opening OP2 (corresponding to the second impurity region 26) surrounding the side of the opening. After the p-type impurities are introduced, the resist mask RM is removed from the semiconductor wafer structure 111. Next, the introduced p-type impurities are diffused by heat treating the semiconductor wafer structure 111. As a result, the p-type first impurity region 25 and the p-type second impurity region 26 are formed.

[0118] As described above, the pattern of the opening OP of the resist mask RM has an elliptical first opening OP1 and an annular second opening OP2. If the pattern of the opening OP of the resist mask RM has only the first opening OP1, there is a risk that the periphery of the first opening OP1 will be pulled by the surrounding resist and expand outward. Therefore, there is a risk that the outer periphery of the first impurity region 25 formed by using the first opening OP1 may shift outward from its intended position. In this case, there is a risk that the outer periphery of the first impurity region 25 is set in the region facing the channel region 53 in the depth direction (third direction Z).

[0119] In contrast, in the present embodiment, since the second opening OP2 is formed in the resist mask RM, no outward pulling force acts on the periphery of the first opening OP1. Therefore, the periphery of the first opening OP1 does not expand outward. As a result, the outer periphery of the first impurity region 25 does not shift from its intended position. Therefore, it is possible to reliably prevent the outer periphery of the first impurity region 25 from facing the channel region 53 in the depth direction (third direction Z).

[0120] Next, refer to Fig.10E A first well region 15 , a back gate region 16 , a drift region 17 , and a second well region 18 are formed on the surface portion of the first wafer main surface 112 .

[0121] Specifically, n-type impurities are implanted into the surface portion of the first wafer main surface 112 by ion implantation via the sacrificial insulating film 114, thereby forming the first well region 15. The bottom of the first well region 15 reaches the buried region 14. By forming the ring-shaped first well region 15, the second p-type region 13 is divided into a p-type inner region 13A and a p-type outer region 13B. The p-type inner region 13A is surrounded by the n-type region including the buried region 14 and the first well region 15 in the first direction X, the second direction Y, and the third direction Z. As a result, the p-type inner region 13A is electrically isolated from the p-type outer region 13B and the first p-type region 12 by the n-type region including the buried region 14 and the first well region 15.

[0122] Furthermore, the back gate region 16 and the second well region 18 are formed on the surface of the first wafer main surface 112. Specifically, p-type impurities are implanted into the surface of the first wafer main surface 112 through the sacrificial insulating film 114 by ion implantation, thereby forming the back gate region 16 and the second well region 18.

[0123] Next, the drift region 17 is formed on the surface of the first wafer main surface 112. Specifically, n-type impurities are implanted into the surface of the first wafer main surface 112 by ion implantation via the sacrificial insulating film 114, thereby forming the drift region 17. The bottom of the drift region 17 does not reach the buried region 14.

[0124] In the ion implantation for forming the drift region 17, the n-type impurity is introduced up to the region on the inner side than the inner periphery 17A of the drift region 17. As a result, the inner periphery 17A of the drift region 17 can be reliably connected to the back gate region 16. By introducing the n-type impurity up to the region on the inner side than the inner periphery 17A of the drift region 17, the p-type impurity in the peripheral portion of the back gate region 16 is reduced. As a result, the low concentration portion 36 is formed in the peripheral portion of the back gate region 16. Since the dose of the p-type impurity is smaller than the dose of the n-type impurity, the peripheral portion of the back gate region 16 maintains the p-type impurity region.

[0125] The formation order of the first well region 15, the back gate region 16, the drift region 17, and the second well region 18 may be changed appropriately. For example, the back gate region 16 may be formed first, and then the drift region 17 may be formed. Alternatively, for example, the drift region 17 may be formed first, and then the first well region 15 may be formed.

[0126] Next, refer to Fig.10F A hard mask (not shown) is formed on the sacrificial insulating film 114, and the sacrificial insulating film 114 is selectively removed by etching through the hard mask, thereby forming an opening 115. Next, a field insulating film 19 is formed by thermally oxidizing the surface portion of the first wafer main surface 112 exposed through the opening 115 of the sacrificial insulating film 114. Thereafter, the sacrificial insulating film 114 is removed.

[0127] Next, refer to Figure 10G , a gate insulating film 54 is formed on the first wafer main surface 112. For example, the gate insulating film 54 may be formed by thermally oxidizing the surface layer of the first wafer main surface 112 exposed through the first opening 41, the second opening 42, the third opening 43, and the fourth opening 44 of the field insulating film 19 into a film-like shape of silicon oxide (SiO 2 )membrane.

[0128] Next, refer to Fig. 10H On the first wafer main surface 112, a gate electrode 20 is formed in a manner covering the gate insulating film 54 and the field insulating film 19 (see Figure 6 and Figure 7 ) is a substrate electrode 116 of a substrate. In the present embodiment, the substrate electrode 116 is made of conductive polysilicon. The substrate electrode 116 can be formed by, for example, a CVD method.

[0129] Next, refer to Fig.10I , by etching through a hard mask (not shown) having a predetermined pattern, the unnecessary portion of the substrate electrode 116 is removed. As a result, the gate electrode 20 is formed. The etching may be, for example, dry etching (e.g., RIE method) or wet etching. Thereafter, the gate insulating film 54 exposed from the gate electrode 20 is removed, so that the back gate region 16 is exposed from the opening portion 50, and the first well region 15 is exposed from the first opening portion 41 of the field insulating film 19.

[0130] Next, refer to Fig.10J, a base insulating film 117 serving as a base of the sidewall structure 57 is sequentially formed on the first wafer main surface 112. The base insulating film 117 can be formed by, for example, a CVD method. Next, unnecessary portions of the base insulating film 117 are removed by etching back. As a result, the sidewall structure 57 is formed by the base insulating film 117 remaining on the inner side and the outer side of the gate electrode 20.

[0131] Next, refer to Figure 10K , the first drain region 21 and the second drain region 22 are formed on the surface of the drift region 17 and the first well region 15, respectively. In addition, the source region 23, the back gate contact region 24, the first drain region 21 and the second drain region 22 are formed on the surface of the back gate region 16. In this embodiment, ion implantation is performed by using the sidewall structure 57 and the field insulating film 19 as a hard mask, and n-type impurities and p-type impurities are implanted into the surface of the back gate region 16 to form the source region 23 and the back gate contact region 24. That is, the source region 23 and the back gate contact region 24 are formed in self-alignment with the periphery of the sidewall structure 57 of the gate electrode 20 and the periphery of the third opening 43, respectively. By using the field insulating film 19 as a hard mask, ion implantation is performed, and n-type impurities are implanted into the surface of the drift region 17 to form the first drain region 21. That is, the first drain region 21 is formed in self-alignment with the periphery of the first opening 41 of the field insulating film 19. By performing ion implantation using the field insulating film 19 as a hard mask, n-type impurities are implanted into the surface layer of the first well region 15 to form the second drain region 22. That is, the second drain region 22 is formed in self-alignment with the periphery of the second opening 42 of the field insulating film 19.

[0132] Next, refer to Fig.10L , forming the silicide layer 60. To form the silicide layer 60, first, the above transition metal is deposited on the second p-type region 13 and the gate electrode 20, and then heat treatment is performed. The exposed portions (silicon) of the second p-type region 13 and the gate electrode 20 react with the transition metal to form the silicide layer 60.

[0133] Next, refer to Figure 10M , an interlayer insulating film 27 is formed on the first wafer main surface 112. The interlayer insulating film 27 can be formed by, for example, a CVD method.

[0134] Next, refer to Fig.10N, a first drain contact 29, a second drain contact 30, a source contact 32, and a back gate contact 34 are formed on the interlayer insulating film 27 by etching through a hard mask (not shown) having a predetermined pattern, forming a metal film by a CVD method, and etching unnecessary metal films. Next, a base wiring film serving as a base for a plurality of wirings is formed on the interlayer insulating film 27, and is patterned to form a drain wiring 28, a source wiring 31, and a back gate wiring 33. Thereafter, the semiconductor wafer structure 111 is cut, and a plurality of semiconductor chips 2 are cut out. The semiconductor device 1 is manufactured through the above steps.

[0135] Although embodiments of the disclosure have been described, the disclosure may be implemented in other forms.

[0136] like Fig.11 In the semiconductor device 151 shown, the back gate contacts 34 and the source contacts 32 may be arranged to be offset from each other in a plan view along the first direction X. Even in this case, a plurality of back gate contacts 34 connected to one source region 23 may be aligned in the first direction X with a plurality of back gate contacts 34 connected to another source region 23 .

[0137] In addition, as in Fig.12 In the semiconductor device 161 shown in FIG. 1 , the back gate contact 34 may have a straight line shape extending along the first direction X, rather than a dot shape (quadrilateral shape). Fig.12 As shown, the source contact 32 may have a straight line shape extending along the first direction X, rather than a dot shape (quadrilateral shape).

[0138] Fig.13 is corresponding to Figure 7 FIG. 2 is a schematic cross-sectional view of a semiconductor device 201 according to another embodiment of the present disclosure. Fig.13 Components identical to those described above are denoted by the same reference numerals, and description thereof will be omitted.

[0139] Semiconductor device 201 and Figure 1 to 10N The semiconductor device 1 of the illustrated embodiment is different in that the second well region 18 and the second impurity region 26 are eliminated. The outer periphery 17B of the drift region 17 is in contact with the first well region 15 over the entire circumferential region of the drift region 17. Since the first well region 15 is in electrical contact with the drift region 17, the first well region 15 has the same potential as the drift region 17. Therefore, in the semiconductor device 201, no drain contact region (corresponding to Figure 1 to 10N A second drain contact 30 in the illustrated embodiment).

[0140] According to another embodiment of the present disclosure, a semiconductor device 201 can be implemented as Figures 1 to 10N The same operation and effects as described in the illustrated embodiment.

[0141] In the above embodiments, an example in which the first conductivity type is n-type and the second conductivity type is p-type has been described, but the first conductivity type may be p-type and the second conductivity type may be n-type. The specific configuration in this case can be obtained by replacing the n-type region with the p-type region and the p-type region with the n-type region in the above description and the drawings.

[0142] As described above, the embodiments of the present disclosure are illustrative in all aspects, should not be considered restrictive, and are intended to include changes in all aspects.

[0143] The following features can be extracted from the description and drawings of the present disclosure. In the following, alphanumeric characters in brackets represent corresponding components in the above-described embodiments, but they are not intended to limit the scope of each clause to the embodiments.

[0144] [Additional Note 1-1]

[0145] A semiconductor device (1, 151, 161, 201), comprising:

[0146] A semiconductor chip (2) having a first main surface (3) and a second main surface (4) opposite to the first main surface (3);

[0147] A first drain region (21) of a first conductivity type, formed on a surface portion of the first main surface (3);

[0148] A back gate region (16) of a second conductivity type is formed on a surface portion of the first main surface (3) and is spaced apart from the first drain region (21);

[0149] A source region (23) of the first conductivity type is formed on the surface of the back gate region (16) and is spaced inward from the periphery (61 to 64) of the back gate region (16);

[0150] A back gate contact region (24) of a second conductivity type is formed on a surface portion of the back gate region (16) so as to be electrically isolated from the source region (23); and

[0151] A gate electrode (20) facing the channel region (53) is formed in the back gate region (16) between the periphery (61 to 64) of the back gate region (16) and the source region (23).

[0152] According to the above configuration, the source region (23) and the back gate contact region (24) are formed to be electrically isolated from each other. Therefore, the connection ground of the back gate contact region (24) can be switched between the source region (23) and the first drain region (21).

[0153] [Additional Notes 1-2]

[0154] The semiconductor device (1, 151, 161, 201) described in Supplement 1-1, wherein the back gate region (16) has a strip shape extending in the first direction (X) along the first main surface (3), and

[0155] The source region (23) and the back gate contact region (24) are formed to be spaced apart from each other in a second direction (Y) intersecting the first direction (X).

[0156] [Notes 1-3]

[0157] The semiconductor device (1, 151, 161, 201) described in Supplement 1-2, wherein the source region (23) and the back gate contact region (24) have a strip shape extending along the first direction (X).

[0158] [Notes 1-4]

[0159] The semiconductor device (1, 151, 161, 201) described in Supplement 1-3, wherein the width (W) of the back gate contact region (24) in the second direction (Y) is 4 ) is greater than or equal to 0.6 μm and less than or equal to 0.8 μm.

[0160] [Notes 1-5]

[0161] The semiconductor device (1, 151, 161, 201) described in Supplement 1-3 or 1-4, wherein the source region (23) includes a pair of source regions (23) formed in a manner of sandwiching a back gate contact region (24) in the second direction (Y).

[0162] [Appendix 1-6]

[0163] A semiconductor device (1, 151, 161, 201) as described in any one of Notes 1-1 to 1-5, wherein the source region (23) and the back gate contact region (24) are electrically isolated from each other by a field insulating film (19) at the surface of the back gate region (16).

[0164] [Appendix 1-7]

[0165] The semiconductor device (1, 151, 161, 201) according to any one of Annexes 1-1 to 1-6, further comprising:

[0166] An interlayer insulating film (27) covering the first main surface (3);

[0167] A back gate wiring (33) formed on the interlayer insulating film (27);

[0168] a source wiring (31) which is a wiring different from the back gate wiring (33) and is formed on the interlayer insulating film (27);

[0169] a back gate contact (34) penetrating the interlayer insulating film (27) and connecting the back gate region (16) and the back gate wiring (33); and

[0170] The source contact (32) penetrates the interlayer insulating film (27) and connects the source region (23) and the source wiring (31).

[0171] [Appendix 1-8]

[0172] The semiconductor device (1, 151, 161, 201) described in any one of Notes 1-1 to 1-7 further includes: a first impurity region (25) of the second conductivity type formed below the back gate region (16).

[0173] [Appendix 1-9]

[0174] The semiconductor device (1, 151, 161, 201) described in Supplementary Notes 1-8, wherein the first impurity region (25) is formed in a manner not to face the channel region (53) in the depth direction (Z).

[0175] [Notes 1-10]

[0176] A semiconductor device (1, 151, 161, 201) as described in Note 1-8 or 1-9, wherein the periphery (71 to 74) of the first impurity region (25) is formed to be spaced inward from the periphery (61 to 64) of the back gate region (16) in the direction along the first main surface (3).

[0177] [Appendix 1-11]

[0178] The semiconductor device (1, 151, 161, 201) according to any one of Supplementary Notes 1-8 to 1-10, wherein the first impurity region (25) is in contact with the back gate region (16).

[0179] [Appendix 1-12]

[0180] The semiconductor device (1, 151, 161) described in any one of Supplementary Notes 1-8 to 1-11 further includes: a second impurity region (26) of a second conductivity type, formed in a manner surrounding the side of the first impurity region (25).

[0181] [Appendix 1-13]

[0182] The semiconductor device (1, 151, 161, 201) according to any one of Annexes 1-1 to 1-12 further includes: a drift region (17) of a first conductivity type formed on a surface portion of the first main surface (3),

[0183] The first drain region (21) is formed in the surface portion of the drift region (17).

[0184] [Appendix 1-14]

[0185] The semiconductor device (1, 151, 161, 201) described in Notes 1 to 13, wherein the back gate region (16) includes: a first portion (35) in which a source region (23) and a back gate contact region (24) are formed; and a second portion (36) formed at a position closer to the drift region (17) than the first portion and having a lower second conductive type impurity concentration than the first portion (35).

[0186] [Note 1-15]

[0187] The semiconductor device (1, 151, 161, 201) described in Supplement 1-13 or 1-14 further includes:

[0188] A well region (15) of the first conductivity type has a ring shape when viewed from above and is a region on the side of a first region (13A) formed with a back gate region (16) and a drift region (17) on the surface of the first main surface (3); and

[0189] The buried region (14) covers the entire lower portion of the first region (13A),

[0190] The well region (15) and the buried region (14) electrically isolate the first region (13A) from the second region (12, 13A), and the second region is another region in the surface layer portion of the first main surface (3).

[0191] Although certain embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present disclosure. In fact, the embodiments described herein may be embodied in various other forms. In addition, various omissions, substitutions, and changes may be made to the forms of the embodiments described herein without departing from the spirit of the present disclosure. The attached claims and their equivalents are intended to cover these forms or modifications that fall within the scope and spirit of the present disclosure.

[0192] 1: Semiconductor devices

[0193] 2: Semiconductor chips

[0194] 3: First main surface

[0195] 4: Second main surface

[0196] 5: First side

[0197] 6: Second side

[0198] 7: The third side

[0199] 8: The fourth side

[0200] 9: Device area

[0201] 11: LDMOS area

[0202] 12: First p-type region

[0203] 13: Second p-type region

[0204] 13A: p-type inner region

[0205] 13B: p-type outer region

[0206] 14: Buried Area

[0207] 15: First well region

[0208] 16: Back gate area

[0209] 17: Drift Zone

[0210] 17A: Inner circumference

[0211] 17B: Outer periphery

[0212] 18: Second well region

[0213] 19: Field insulation film

[0214] 20: Gate electrode

[0215] 21: First drain region

[0216] 21A: First side

[0217] 21B: Second side

[0218] 21C: Third side

[0219] 21D: Fourth side

[0220] 22: Second drain region

[0221] 22A: First side

[0222] 22B: Second side

[0223] 22C: Third side

[0224] 22D: Fourth side

[0225] 23: Source region

[0226] 23A: First side

[0227] 23B: Second side

[0228] 23C: Third side

[0229] 23D: Fourth side

[0230] 24: Back gate contact area

[0231] 24A: First side

[0232] 24B: Second side

[0233] 24C: Third side

[0234] 24D: Fourth side

[0235] 25: First impurity region

[0236] 26: Second impurity region

[0237] 27: Interlayer insulation film

[0238] 28: Drain wiring

[0239] 29: First drain contact

[0240] 30: Second drain contact

[0241] 31: Source wiring

[0242] 32: Source contact

[0243] 33: Back gate wiring

[0244] 34: Back gate contact

[0245] 35: High concentration part (Part 1)

[0246] 36: Low concentration part (part 2)

[0247] 41: First opening

[0248] 42: Second opening

[0249] 43: The third opening

[0250] 44: Fourth opening

[0251] 50: Opening

[0252] 51: Part 1

[0253] 52: Part 2

[0254] 53: Channel area

[0255] 54: Gate insulation film

[0256] 55: Control Department

[0257] 56: Field board

[0258] 57: Sidewall structure

[0259] 60: Silicide layer

[0260] 61: First perimeter

[0261] 62: Second perimeter

[0262] 63: Third perimeter

[0263] 64: Fourth perimeter

[0264] 71: First perimeter

[0265] 72: Second perimeter

[0266] 73: Third perimeter

[0267] 74: Fourth perimeter

[0268] 81: Source terminal electrode

[0269] 82: Drain terminal electrode

[0270] 83: Back gate terminal electrode

[0271] 84: Gate terminal electrode

[0272] 85: First switch

[0273] 86: Second switch

[0274] 87: Driving circuit

[0275] 88: Body diode

[0276] 101: Semiconductor Wafer

[0277] 102: Introduction

[0278] 103: Epitaxial layer

[0279] 111: Semiconductor wafer structure

[0280] 112: Main surface of the first wafer

[0281] 113: Second wafer main surface

[0282] 114: Sacrificial insulation film

[0283] 115: Opening

[0284] 116: Base electrode

[0285] 117: Base insulation film

[0286] 151: Semiconductor devices

[0287] 161: Semiconductor devices

[0288] 201: Semiconductor devices

[0289] OP: Opening

[0290] OP1: First opening

[0291] OP2: Second opening

[0292] RM: Resist Mask

[0293] W 1 : First interval

[0294] W 2 : Second width

[0295] W 3 : Third width

[0296] W 4 : Fourth width

[0297] W 11 : First interval

[0298] X: First direction

[0299] Y: Second direction

[0300] Z: The third direction (depth direction)

Claims

1. A semiconductor device, comprising: A semiconductor chip having a first main surface and a second main surface opposite to the first main surface; A first drain region of a first conductivity type, formed on a surface portion of the first main surface; A back gate region of a second conductivity type is formed on a surface portion of the first main surface and is spaced apart from the first drain region; A source region of the first conductivity type is formed at a surface portion of the back gate region and is spaced inward from a periphery of the back gate region; The back gate contact region of the second conductivity type is formed at a surface portion of the back gate region to be electrically isolated from the source region; and A gate electrode facing the channel region is formed in the back gate region between the periphery of the back gate region and the source region.

2. The semiconductor device according to claim 1, wherein The back gate region has a strip shape extending in a first direction along the first main surface, and The source region and the back gate contact region are formed to be spaced apart from each other in a second direction intersecting the first direction.

3. The semiconductor device according to claim 2, wherein: The source region and the back gate contact region have a strip shape extending along the first direction.

4. The semiconductor device according to claim 3, wherein: The width of the back gate contact region in the second direction is greater than or equal to 0.6 μm and less than or equal to 0.8 μm.

5. The semiconductor device according to claim 3, wherein: The source region includes a pair of source regions formed so as to sandwich the back gate contact region in the second direction.

6. The semiconductor device according to claim 1, wherein The source region and the back gate contact region are electrically isolated from each other by a field insulating film at a surface portion of the back gate region.

7. The semiconductor device according to any one of claims 1 to 6, further comprising: an interlayer insulating film covering the first main surface; a back gate wiring formed on the interlayer insulating film; a source wiring which is a wiring different from the back gate wiring and is formed on the interlayer insulating film; a back gate contact penetrating the interlayer insulating film and connecting the back gate region and the back gate wiring; and A source contact penetrates the interlayer insulating film and connects the source region and the source wiring.

8. The semiconductor device according to claim 1, further comprising: A first impurity region of a second conductivity type is formed below the back gate region.

9. The semiconductor device according to claim 8, wherein: The first impurity region is formed so as not to face the channel region in a depth direction.

10. The semiconductor device according to claim 8, wherein The periphery of the first impurity region is formed to be spaced inward from the periphery of the back gate region in a direction along the first main surface.

11. The semiconductor device according to any one of claims 8 to 10, wherein: The first impurity region is in contact with the back gate region.

12. The semiconductor device according to any one of claims 8 to 10, further comprising: The second impurity region of the second conductivity type is formed so as to surround the side of the first impurity region.

13. The semiconductor device according to any one of claims 1 to 6 and 8 to 10, further comprising: a drift region of a first conductivity type formed on a surface portion of the first main surface, Wherein, the first drain region is formed in a surface portion of the drift region.

14. The semiconductor device according to claim 13, wherein: The back gate region comprises: a first portion in which the source region and the back gate contact region are formed; and The second portion is formed at a position closer to the drift region than the first portion and has a lower second conductivity type impurity concentration than the first portion.

15. The semiconductor device according to claim 13, further comprising: A well region of the first conductivity type has a ring shape in a plan view and is a region on the side of the first region where the back gate region and the drift region are formed on the surface portion of the first main surface; and a buried region covering the entire lower portion of the first region, The well region and the buried region electrically isolate the first region from a second region, which is another region in the surface layer portion of the first main surface.

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