An asymmetric trench SiC MOSFET device with low resistance and miller capacitance

Abstract

The application relates to a novel asymmetric trench SiC MOSFET device with low resistance and Miller capacitance, and belongs to the technical field of semiconductor devices. The device comprises a substrate, a drift region formed on one surface of the substrate, an N-CSL formed on the surface of the drift region, a low-barrier diode formed on one side of the surface of the N-CSL, a second P-well formed on the other side of the surface of the N-CSL, a trench gate and an auxiliary trench gate formed on the surface of the low-barrier diode and located on both sides of the low-barrier diode, a P-base formed on the surface of the N-CSL and located between the second P-well and the trench gate, a source N+ region formed on the surface of the P-base and located between the second P-well and the trench gate, a source electrode formed on the top of the device, and a drain electrode formed on the other surface of the substrate. The application can reduce the specific on-resistance of the device, reduce the Miller capacitance and gate charge of the device, and improve the switching speed of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device technology and relates to a novel asymmetric trench SiC MOSFET device with low resistance and Miller capacitance. Background Art

[0002] Power semiconductor devices serve as switches, drivers, and rectifiers. Power SiC MOSFETs offer excellent characteristics such as high switching frequency, high input impedance, and excellent thermal stability. Energy-saving and advanced power SiC MOSFETs are becoming a key cornerstone of my country's information industry and efficiency economy. Power SiC MOSFETs are widely used in daily life and across various industries. They are found wherever modern electronic chips are found, and are a crucial component in their safe, efficient, and accurate processing of information. With the continuous optimization of semiconductor technology and processes, power devices are required to exhibit not only excellent static characteristics but also improved dynamic characteristics, leading to higher requirements for switching speed and switching losses.

[0003] In recent years, with the continuous improvement of SiC MOSFET's electrical characteristics, manufacturing technology, and reliability, the unipolar conduction characteristics of SiC MOSFETs have given them superior switching characteristics and lower switching losses compared to Si bipolar power devices. This makes SiC MOSFETs a promising alternative to Si IGBTs in high-frequency applications. As a commonly used field-effect transistor in electronic devices, the on-resistance of SiC MOSFETs is crucial to circuit performance. On-resistance determines conduction losses, but reducing the specific on-resistance reduces the device's breakdown voltage; increasing the device's breakdown voltage increases the specific on-resistance. Summary of the Invention

[0004] In view of this, the object of the present invention is to provide an asymmetric trench SiC MOSFET device with low resistance and Miller capacitance, so as to reduce the device's specific on-resistance, reduce the device's feedback capacitance and gate charge, and improve the device's switching speed.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A novel asymmetric trench SiC MOSFET device with low resistance and Miller capacitance, comprising:

[0007] N+ substrate;

[0008] N-Drift formed on the first surface of the N+ substrate;

[0009] N-CSL formed on the N-Drift surface;

[0010] A P-type low-barrier diode formed on one side of the N-CSL surface;

[0011] a second P-well formed on the other side of the N-CSL surface;

[0012] A trench gate and an auxiliary trench gate formed on the surface of the low barrier diode and located on both sides of the low barrier diode;

[0013] A P-base formed on the surface of the N-CSL and located between the second P-well and the trench gate;

[0014] A source N+ region formed on the P-base surface and located between the second P-well and the trench gate;

[0015] a source electrode formed on top of the device; and

[0016] A drain electrode is formed on the second surface of the N+ substrate.

[0017] Furthermore, the low barrier diode includes: a first P-well formed on one side of the N-CSL surface, a P-Channel formed on the surface of the first P-well and located between the trench gate and the auxiliary trench gate, and a source P+ region formed on the surface of the P-Channel and located between the trench gate and the auxiliary trench gate.

[0018] The trench gate disconnects the source P+ region from the first P-well by depleting the P-channel, so that the first P-well is in a floating state, increasing the potential of the first P-well, and thus reducing the on-resistance of the device.

[0019] Furthermore, the trench gate and the auxiliary trench gate are surrounded by a first oxide layer and a second oxide layer, respectively. By increasing the thickness of the first oxide layer and the second oxide layer on the side adjacent to the P-Channel, the gate-source capacitance C introduced by the auxiliary trench gate can be reduced. gs .

[0020] Furthermore, by reducing the width of the N-CSL to reduce the coupling area between the device gate and drain, the gate-drain capacitance of the device, ie, the Miller capacitance, can be reduced, and the gate charge of the device can also be reduced.

[0021] The beneficial effects of the present invention are as follows: The present invention proposes an asymmetric trench SiC MOSFET device with low resistance and Miller capacitance, integrating a P-type low-barrier diode on the basis of a conventional asymmetric trench SiC MOSFET device. Based on this integrated P-type low-barrier diode, when the device is forward-conducting, with the drain connected to a positive voltage and the gate connected to a 15V positive voltage, the P-channel is depleted and pinched off, disconnecting the P+ source region from the P-well, floating the P-well and increasing the P-well potential, thereby reducing the device's specific on-resistance. Furthermore, by reducing the JFET width (i.e., the width of the N-CSL) between the first and second P-wells, thereby reducing the gate-drain coupling area, the device's Miller capacitance and gate charge can be reduced, thereby improving the device's switching speed.

[0022] Other advantages, objects, and features of the present invention will be described in part in the following description and, in part, will be apparent to those skilled in the art upon examination of the following description or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below with reference to the accompanying drawings, in which:

[0024] Figure 1 The overall structure of a SiC MOSFET device provided by one embodiment of the present invention;

[0025] Figure 2 A comparison of the output characteristic curves of the SiC MOSFET of the present invention and the traditional asymmetric trench SiC MOSFET when the gate voltage is 15 V in forward conduction, and a diagram of the first quadrant working mechanism of the SiC MOSFET of the present invention;

[0026] Figure 3 The total current density distribution diagram of C-ATMOS and LR-ATMOS during forward conduction;

[0027] Figure 4 The comparison diagram of the breakdown characteristic curves of the two devices is shown in Figure 2.

[0028] Figure 5 The breakdown electric field distribution of two SiC MOSFETs;

[0029] Figure 6 The effect of NCSL on the breakdown voltage (BV) and specific on-resistance (Ron,sp) of two SiC MOSFETs is shown;

[0030] Figure 7 The influence of different CSL region widths on the breakdown voltage, on-resistance and Qgd of LR-ATMOS;

[0031] Figure 8 Graph showing capacitance comparison between the SiC MOSFET of the present invention and a conventional asymmetric trench SiC MOSFET;

[0032] Figure 9 A comparison diagram of gate charge characteristics of the SiC MOSFET of the present invention and the traditional asymmetric trench SiC MOSFET;

[0033] Figure 10 : The switching characteristic curves of the SiC MOSFET of the present invention and the traditional asymmetric trench SiC MOSFET;

[0034] Figure 11 A comparison chart of switching losses between the SiC MOSFET of the present invention and the traditional asymmetric trench SiC MOSFET;

[0035] Figure 12 Schematic diagram of the main process flow of the SiC MOSFET device of the present invention.

[0036] Figure numerals: 1-gate, 2-source, 3-drain, 4-trench gate, 5-auxiliary trench gate, 6-first oxide layer, 7-second oxide layer, 8-source N+ region, 9-source P+ region, 10-P-base, 11-P-channel, 12-first P-well, 13-second P-well, 14-N-CSL, 15-N-Drift, 16-N+SUB. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention by means of specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0038] Among them, the accompanying drawings are only for illustrative purposes and represent only schematic diagrams rather than actual pictures, and should not be understood as limiting the present invention. In order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the dimensions of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the accompanying drawings.

[0039] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "back", etc. indicating directions or positional relationships, they are based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0040] like Figure 1 As shown, an asymmetric trench SiC MOSFET device with low resistance and Miller capacitance provided by an embodiment of the present invention is composed of a gate 1, a source 2, a drain 3, a trench gate 4, an auxiliary trench gate 5, a first oxide layer 6, a second oxide layer 7, a source N+ region 8, a source P+ region 9, a P-base 10, a P-channel 11, a first P-well 12, a second P-well 13, an N-CSL 14, an N-Drift 15, and an N+SUB 16.

[0041] The trench gate 4 , the auxiliary trench gate 5 , the source P+ region 9 , the P-channel 11 and the first P-well 12 form a P-type low-barrier diode.

[0042] The source P+ region 9 is located on the upper surface of the P-channel 11 and is connected to the source 2. Its thickness is 0.25 and its width is 0.2 , doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 20 cm -3 The first P-well 12 is located on the lower surface of the P-channel 11 and has a thickness of 0.95 , with a width of 1.3 , doped with P-type impurity aluminum (AL) with a doping concentration of 2.5×10 17 cm -3 The source P+ region 9, P-channel 11 and the first P-well 12 are arranged vertically to form a P-type low barrier diode, and the thickness of P-channel 11 is 0.5 , with a width of 0.2 The trench gate 4 and the auxiliary trench gate 5 are respectively located on both sides of the source P+ region 9, the P-channel 11 and the first P-well 12. The lower surface of the trench gate 4 and the auxiliary trench gate 5 are adjacent to the first P-well 12, and the thickness is 1.0 , with widths of 0.85 , 0.55 , PolySi is doped with N-type impurity phosphorus (P) with a doping concentration of 4×10 16 cm -3 .

[0043] Gate 1 is connected to trench gate 4, auxiliary trench gate 5, and trench gate 4. Trench gate 4 and auxiliary trench gate 5 are located within first oxide layer 6 and second oxide layer 7, respectively. The right side of first oxide layer 6, adjacent to the P-channel, is 80 nm thick. The left side of second oxide layer 7, adjacent to the P-channel, is also 80 nm thick. The remaining thicknesses of the first and second oxide layers are both 50 nm.

[0044] The source 2 is connected to the source N+ region 8, the source P+ region 9 and the second P-well 13, and is located on the upper surface of the source N+ region 8, the source P+ region 9 and the second P-well 13. The thickness of the source N+ region 8 is 0.25 , with a width of 0.8 , doped with N-type impurity nitrogen (Ni) with a doping concentration of 1×10 20 cm -3 ; The thickness of the second P-well 13 is 1.7 , with a width of 0.8 , doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 19 cm -3 .

[0045] Drain 3 is connected to N+SUB16 and is located on the lower surface of N+SUB16. The thickness of N+SUB16 is 5 , with a width of 3.2 , doped with N-type impurity nitrogen (Ni) with a doping concentration of 1×10 20 cm -3 ;

[0046] In addition, in the device, the source N+ region 8, P-base 10, second P-well 13, N-CSL 14, N-Drift 15, and N+SUB 16. The source N+ region 8 is located on the upper surface of P-base 10, and the left surface of the source N+ region 8 and P-base 10 is adjacent to the right surface of the second P-well 13, and the right surface is adjacent to the left surface of the first oxide layer 6. The thickness of the source N+ region 8 is 0.25 , with a width of 0.8 , doped with N-type impurity nitrogen (Ni) with a doping concentration of 1×10 20 cm -3N-CSL14 is located between the first and second P-well on both sides, with its lower surface adjacent to the upper surface of N-Drift15. The thickness of N-CSL14 is 1.7 , with a width of 3.2 , doped with N-type impurity nitrogen (Ni) with a doping concentration of 2.5×10 16 cm -3 The upper surface of N-Drift15 is located on the lower surface of N-CSL14, and the lower surface of N-Drift15 is located on the upper surface of N+SUB16. The thickness of N-Drift15 is 1.7 , with a width of 3.2 , doped with N-type impurity nitrogen (Ni) with a doping concentration of 7×10 15 cm -3 .

[0047] In another embodiment of the present invention, a simulation test is performed on the proposed SiC MOSFET device to verify the excellent performance of the device proposed in the present invention, as follows:

[0048] like Figure 2 As shown in FIG, a comparison of the output characteristic curves of the SiC MOSFET device of the present invention and the conventional asymmetric trench SiC MOSFET device when the gate voltage is 15 V in forward conduction, as well as the first quadrant working mechanism of the SiC MOSFET device of the present invention, can be seen that the device of the present invention has better output characteristics than the conventional asymmetric trench SiC MOSFET device.

[0049] like Figure 3 As shown, the total current density distribution of C-ATMOS and the device of the present invention during the forward conduction process. Figure 3 It can be seen that compared with the traditional asymmetric trench SiC MOSFET device, the device of the present invention still has a larger conduction path even when the WCSL is small. In the J-FET region, the current width of the device of the present invention is 0.64 , the current width of the traditional asymmetric trench SiC MOSFET is 0.68 This difference is attributed to the integration of a P-type low-barrier diode. When the gate is connected to a positive voltage of 15 V, the P-channel is depleted, disconnecting the source P+ region connected to the source from the second P-well, floating the second P-well and increasing its potential. As a result, the depletion region width is reduced, the JFET resistance is reduced, and the current flowing into the N-Drift is increased. Therefore, compared with traditional asymmetric trench SiC MOSFETs, the device of the present invention has a lower specific on-resistance.

[0050] like Figure 4As shown in FIG, a comparison of the breakdown characteristic curves of the two devices is shown. The two devices exhibit similar BV characteristics. Figure 4 The hole density distribution of the device of the present invention under blocking conditions is also shown. Since the gate is connected to 0 V under blocking conditions, the lightly doped P-channel cannot be depleted. Therefore, the source P+ region is normally connected to the second P-well, so that the second P-well is grounded, which can effectively deplete the drift region and show good BV characteristics.

[0051] like Figure 5 Figure 2 shows the breakdown electric field distribution of two SiC MOSFETs. The maximum breakdown electric field for both devices is at the P-well, and the gate oxide electric field of the SiC MOSFET is less than 3 MV / cm, which helps enhance the long-term reliability of the gate oxide. Because the N-CSL of the device of the present invention is smaller than that of traditional asymmetric trench SiC MOSFETs, the peak electric field near the trench bottom of the device of the present invention is smaller than that of traditional asymmetric trench SiC MOSFETs, resulting in better device reliability.

[0052] like Figure 6 The concentration of N-CSL is shown in CSL ) on the breakdown voltage (BV) and specific on-resistance (Ron,sp) of two SiC MOSFETs. Figure 6 It can be seen that with the increase of N-CSL concentration, the on-resistance tends to decrease and the BV tends to decrease.

[0053] like Figure 7 As shown, different N-CSL widths (W CSL ) on the breakdown voltage, on-resistance and Qgd of LR-ATMOS. Figure 7 It can be seen that with the W CSL With the increase of , the BV and on-resistance of the device show a downward trend, and Qgd shows an upward trend.

[0054] like Figure 8 The figure shows the capacitance comparison curve of the SiC MOSFET device of the present invention and the traditional asymmetric trench SiC MOSFET. It can be seen that the input capacitance (Ciss) and output capacitance (Coss) of the SiC MOSFET device proposed by the present invention are slightly lower than those of the traditional asymmetric trench SiC MOSFET device. In addition, the feedback capacitance (Crss or C gd ) is significantly smaller than that of the conventional asymmetric trench SiC MOSFET device. The C extracted from the device of the present invention and the conventional asymmetric trench SiC MOSFET device at Vds=400 V is gd 10.98 and 24.45 pF / cm respectively2 This is because the narrower W CSL Reduces the capacitive coupling between the gate and the source-drain, resulting in C gd Therefore, the HF-FOM value (Ron,sp×C gd ) is 58.3% lower than that of traditional asymmetric trench SiC MOSFET devices.

[0055] like Figure 9 The figure shows a comparison of the gate charge characteristics of the SiC MOSFET device of the present invention and the conventional asymmetric trench SiC MOSFET device. Figure 9 A test circuit is also inserted. Figure 9 It can be seen from the figure that the gate charge (Q gd ) and the total gate charge (V gs = 0~15 V) are 67.7 nC / cm 2 and 920 nC / cm 2 , lower than the 90.3 nC / cm of traditional asymmetric trench SiC MOSFET devices 2 and 970 nC / cm 2 . Figure 9 As can be seen from the figure, after the plateau period, the gate charge of the SiC MOSFET device of the present invention is also significantly lower than that of the traditional asymmetric trench SiC MOSFET device. This is because the gate current in this stage is mainly C gs The SiC MOSFET device of the present invention cuts off the P-channel connecting the P-well to the source, making the P-well in a floating state. The C gs It also decreases.

[0056] like Figure 10 , which are the switching characteristic curves of the SiC MOSFET device of the present invention and the traditional asymmetric trench SiC MOSFET device. Figure 10 A test circuit is also inserted. It can be seen that since the SiC MOSFET of the present invention has a lower gate charge, the SiC MOSFET proposed in the present invention has better switching characteristics and can reduce switching losses.

[0057] like Figure 11 As shown in FIG11 , the switching loss comparison of the SiC MOSFET device of the present invention and the conventional asymmetric trench SiC MOSFET device is shown. As can be seen from FIG11 , the switching loss of the device of the present invention is reduced by 15% (from 2.40 mJ / cm 2 down to 2.04 mJ / cm2 ).

[0058] The following table compares the relevant parameters of the device of the present invention and the traditional asymmetric trench SiC MOSFET device.

[0059] Table 1

[0060]

[0061] In another embodiment of the present invention, a process flow of the device of the present invention is provided. Considering the feasibility of the process, most of the process steps are compatible with the general manufacturing process of the traditional asymmetric trench SiC MOSFET device. Figure 12 As shown in FIG. , the main process flow of the device proposed in this embodiment includes: epitaxial growth, N+ source and P well implantation, trench etching, P base implantation, isolation oxidation, gate oxidation, polysilicon gate deposition, and metallization. The difference is that in the process flow of this embodiment, the gate trench requires multiple steps of polysilicon gate deposition, trenching, and gate oxidation.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should all be included in the scope of the claims of the present invention.

Claims

1. An asymmetric trench SiC MOSFET device with low resistance and Miller capacitance, characterized in that: The device includes: N+ substrate; N-Drift formed on the first surface of the N+ substrate; N-CSL formed on the surface of the N-Drift; a P-type low-barrier diode formed on one side of the N-CSL surface; a second P-well formed on the other side of the N-CSL surface; A trench gate and an auxiliary trench gate formed on the surface of the P-type low barrier diode and located on both sides of the P-type low barrier diode; A P-base formed on the surface of the N-CSL and located between the second P-well and the trench gate; A source N+ region formed on the surface of the P-base and located between the second P-well and the trench gate; a source electrode formed on top of the device; and a drain electrode formed on the second surface of the N+ substrate; The P-type low barrier diode includes: a first P-well formed on one side of the N-CSL surface; a P-Channel formed on the surface of the first P-well and located between the trench gate and the auxiliary trench gate; and a source P+ region formed on the surface of the P-Channel and located between the trench gate and the auxiliary trench gate.

2. The SiC MOSFET device according to claim 1, wherein: The trench gate and the auxiliary trench gate are surrounded by a first oxide layer and a second oxide layer respectively.

3. The SiC MOSFET device according to claim 2, wherein: The gate-source capacitance C introduced by the auxiliary trench gate is reduced by increasing the thickness of the first oxide layer and the second oxide layer on the side adjacent to the P-Channel. gs .

4. The SiC MOSFET device according to claim 1, wherein By reducing the width of the N-CSL, the coupling area between the device gate and the drain is reduced, thereby reducing the gate-drain capacitance of the device, that is, the Miller capacitance.

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