Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. In an embodiment, a method includes receiving a workpiece including a first transistor and a second transistor formed over a first side of a substrate; forming a first multilayer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure includes a first plurality of metal lines and a first plurality of vias; forming a source / drain contact directly under the source / drain feature of the first transistor after forming the first MLI structure; and forming a second MLI structure under the source / drain contact and under a second side of the substrate opposite the first side, where the second MLI structure includes a second plurality of metal lines and a second via having a thickness greater than a thickness of one of the first plurality of vias.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be formed using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Such scaling down has also increased the complexity of processing and manufacturing ICs. For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or a portion of a gate structure disposed on more than one side of a channel region. As examples of multi-gate devices, fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors have become popular and are promising candidates for high-performance and low-leakage applications. FinFETs have an elevated channel surrounded by a gate on more than one side (e.g., the gate surrounds the top and sidewalls of a "fin" formed of semiconductor material extending from a substrate). A gate-all-around (GAA) transistor has a gate structure that extends partially or completely around a channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor may be formed of nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region has also been given some alternative names for GAA transistors, such as nanosheet transistors or nanowire transistors.

[0004] As the size of multi-gate devices decreases, it becomes increasingly challenging to pack all contact features on one side of the substrate. To reduce the packing density, the wiring features may be partially moved to the back side of the substrate. Such wiring features may include backside superpower rails (SPRs) and / or backside contacts. Although existing backside superpower rails (SPRs) are generally sufficient for their intended purpose, not all aspects of the backside superpower rails are satisfactory. Summary of the invention

[0005] An embodiment of the present invention provides a method for forming a semiconductor structure, including: receiving a workpiece, the workpiece including a first transistor and a second transistor formed on a first side of a substrate; forming a first multilayer interconnect structure on the first side of the substrate, wherein the first multilayer interconnect structure includes a first plurality of metal lines and a first plurality of through holes; after forming the first multilayer interconnect structure, forming a source / drain contact directly below the source / drain feature of the first transistor; and forming a second multilayer interconnect structure below the source / drain contact and below a second side of the substrate, the second side being opposite to the first side, wherein the second multilayer interconnect structure includes a second plurality of metal lines and a second through hole, wherein the thickness of the second through hole is greater than the thickness of a through hole in the first plurality of through holes.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, including: receiving a workpiece, the workpiece including a first plurality of transistors located in a first area above a substrate and a second plurality of transistors located in a second area; and forming a power delivery network under the substrate to provide power signals to the first plurality of transistors and the second plurality of transistors, wherein the power delivery network includes a first portion and a second portion, the first portion having a first number of conductive features electrically coupled to the first plurality of transistors, and the second portion having a second number of conductive features electrically coupled to the second plurality of transistors, wherein the first number is less than the second number.

[0007] An embodiment of the present invention provides a semiconductor structure including: a first transistor, including: a plurality of nanostructures, a gate structure, wrapped around each of the plurality of nanostructures; and a first source / drain feature and a second source / drain feature, coupled to each of the plurality of nanostructures; a first source / drain contact, disposed under the first source / drain feature; a first metal line, located in a first dielectric layer and electrically coupled to the first source / drain contact, the first metal line being disposed under the first source / drain contact and in direct contact with the first source / drain contact; a multilayer dielectric structure, disposed under the first dielectric layer; a first through hole, extending through the multilayer dielectric structure and in direct contact with the first metal line; and a second metal line, located in a second dielectric layer and in direct contact with the first through hole, the second dielectric layer being disposed under the multilayer dielectric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A flow chart is shown of a method for forming a semiconductor structure having a backside power delivery network (PDN) according to one or more aspects of the present disclosure.

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 A workpiece according to one or more aspects of the present disclosure is shown in Figure 1 Partial cross-sectional views during various stages of fabrication of the method are shown.

[0011] Fig.18 According to one or more aspects of the present disclosure, Fig.17 A partial top view of features of a workpiece taken along lines AA and BB is shown in FIG.

[0012] Fig.23 and Fig.24 A partial cross-sectional view illustrating an alternative structure of a workpiece according to one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0013] The following disclosure provides a plurality of different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are merely examples and are not intended to limit the present disclosure. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly in contact with each other, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in different embodiments. Such repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations.

[0014] In addition, for ease of description, the present disclosure may use spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. to describe the relationship between one component or feature and another component or features. In addition to the orientation shown in the drawings, the spatially relative terms are also intended to cover different orientations of the components in use or operation. The components can be oriented in other orientations (rotated 90 degrees or other orientations), and the spatially relative terms used in the present disclosure can also be interpreted accordingly.

[0015] In addition, as understood by those of ordinary skill in the art, when "about," "approximate," and similar terms are used to describe a number or a range of numbers, the terms are intended to encompass numbers that are within a reasonable range to account for variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing features having the properties associated with the number, a number or range of numbers encompasses a reasonable range that includes the number being described, such as within + / - 10% of the number being described. For example, a material layer having a thickness of "about 5 nanometers" may encompass a range of sizes from 4.25 nanometers to 5.75 nanometers, where the manufacturing tolerance associated with depositing the material layer is known to those of ordinary skill in the art to be + / - 15%. Further still, the present disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purposes of brevity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0016] IC manufacturing process flows can generally be divided into three categories: front-end-of-line (FEOL) processes, middle-end-of-line (MEOL) processes, and back-end-of-line (BEOL) processes. FEOL processes generally include processes associated with making IC devices such as transistors. For example, FEOL processes may include forming isolation features, gate structures, and source / drain features. Source / drain features may refer to source or drain individually or collectively depending on the context. MEOL processes generally include processes associated with making contacts for various conductive features of IC devices (e.g., gate vias for gate structures and / or source / drain contacts for source / drain features). BEOL processes generally include processes associated with making multi-layer interconnect structures that interconnect various IC features made by FEOL processes and MEOL processes, thereby enabling the IC device to operate. Features made by FEOL processes may be referred to as FEOL features. Features made by MEOL processes may be referred to as MEOL features. Features made by BEOL processes may be referred to as BEOL features.

[0017] In some existing chip structures, MEOL features (e.g., source / drain contacts, contact vias of transistors) are formed on the front side of a substrate and connect the source / drain features of the transistors to BEOL features (e.g., multi-layer interconnect structures) also disposed on the front side of the substrate. As the size of IC devices decreases, the close proximity between the source / drain contacts and the gate vias can reduce the process margin for forming these conductive features and can increase the parasitic capacitance between these conductive features. To alleviate these problems, some IC chips (e.g., super power rail (SPR) chips) can implement backside source / drain contacts that pass through the substrate to contact the source / drain features, and form power rails on the back side of the substrate that contact the backside source / drain contacts. Since implementing an SPR structure relieves the crowding of the contacts, SPR chips require a current solution to improve the performance of the power delivery network (PDN) for advanced technology nodes. The PDN is a structure that delivers power and ground voltages from conductive pad locations to various components (e.g., transistors) of the chip. However, conductive features in the PDN (e.g., backside metal lines and backside vias) may be formed to have small dimensions and may include materials with high resistivity (e.g., titanium nitride), resulting in a large current-resistance (IR) drop during power delivery. When the voltage at the transistor drops, the transistor becomes slower and this may adversely affect circuit timing. For some SPR chips including devices to be implemented in high-power applications, such a large IR drop may change the timing or even directly cause functional failures. A large IR drop may also force the use of a voltage source with a higher voltage potential, which may be more difficult to implement or more expensive. A large IR drop may also make the device more susceptible to voltage source noise.

[0018] The present disclosure provides a semiconductor structure with reduced current-resistance (IR) drop and a method for forming the same. In one embodiment, after forming MEOL features and BEOL features on the front side of a transistor and after forming a backside source / drain contact below the transistor, a power delivery network electrically coupled to the transistor is formed below the backside source / drain contact. A portion of the power delivery network includes a dielectric via disposed vertically between two metal lines and is configured to provide a power delivery path to a device to be implemented in a high power application. Compared to a power delivery network formed by a backside multi-layer interconnect structure and without a dielectric via, the power delivery network of the present disclosure has reduced parasitic resistance and thus provides reduced IR drop during power delivery.

[0019] The various aspects of the present disclosure will now be described in more detail with reference to the various figures. In this regard, Figure 1 1 is a flow chart showing a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. Figures 2 to 24 Elaboration method 100, Figures 2 to 24 is a partial cross-sectional view or a partial top view of a workpiece 200 at different stages of fabrication according to an embodiment of method 100. Method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown therein. Additional steps may be provided before method 100, during method 100 and / or after method 100, and some of the steps described may be replaced, deleted or moved for additional embodiments of the method. For the sake of brevity, not all steps are described in detail herein. Since workpiece 200 will be fabricated into semiconductor structure 200 at the end of the fabrication process, workpiece 200 may be referred to as semiconductor structure 200 as the context requires. For the avoidance of doubt, Figures 2 to 24 The X, Y and Z directions are perpendicular to each other and Figures 2 to 24 Throughout this disclosure, unless otherwise specified, the same reference numerals refer to the same features.

[0020] Reference Figure 1 and Figure 2 The method 100 includes a block 102 at which a workpiece 200 is received. The workpiece 200 includes a substrate 202 having a top surface 202t and a bottom surface 202b opposite the top surface 202t. In one embodiment, the substrate 202 is a bulk silicon substrate (i.e., includes bulk single crystal silicon). In various embodiments, the substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof, or other suitable materials. In some alternative embodiments, the substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 202 may include a plurality of doped regions (e.g., N-type doped wells, P-type doped wells). Each of the N-type doped wells may be doped with an N-type dopant (e.g., phosphorus, arsenic, other N-type dopants, or a combination thereof). Each of the P-type doped wells may be doped with a P-type dopant (e.g., boron, indium, other P-type dopants, or a combination thereof). Each of the various doped regions may be formed by performing an ion implantation process, a diffusion process, other suitable doping processes, or a combination thereof.

[0021] The workpiece 200 also includes a number of transistors 300 formed in and / or on the top surface 202t of the substrate 202. In the present embodiment, the number of transistors 300 are formed in the first region 200A of the workpiece 200, and the number of transistors 300 are formed in the second region 200B of the workpiece 200. When the manufacturing process is completed, the first region 200A of the workpiece 200 can be implemented in high power applications (e.g., central processing unit (CPU), graphics processing unit (GPU)), and the second region 200B of the workpiece 200 can be implemented in low power applications.

[0022] In the present embodiment, each of the transistors 300 is a GAA transistor. Figure 2 , and an exemplary structure of transistor 300 is enlarged and shown in FIG. Transistor 300 includes a number of channel layers 305 stacked in a vertical direction along the Z axis. Each of the channel layers 305 may include Si, Ge, SiC, SiGe, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof. In the present embodiment, each of the channel layers 305 includes Si in the form of a nanosheet, a nanowire (e.g., a nanowire with a hexagonal cross section), a nanorod (e.g., a nanorod with a square cross section or a circular cross section), or other suitable configurations. In some embodiments, transistor 300 includes two to ten channel layers 305. Of course, the present disclosure is not limited to such configurations, and the number of channel layers 305 can be tuned according to the design requirements of semiconductor structure 200.

[0023] The transistor 300 also includes a source / drain feature 308 coupled to the channel layer 305. The transistor 300 can be an N-type transistor or a P-type transistor, and accordingly, the source / drain feature 308 can be an N-type source / drain feature or a P-type source / drain feature. Exemplary N-type source / drain features can include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and can be doped in-situ by introducing an N-type dopant (e.g., phosphorus, arsenic, or antimony) during an epitaxial process or ex-situ using a junction implant process. Exemplary P-type source / drain features may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be doped in-situ by introducing a P-type dopant (e.g., boron or gallium) during the epitaxy process or ex-situ using a junction implantation process. In some embodiments, each of the source / drain features 308 may be a multilayer structure including an undoped semiconductor layer, a lightly doped semiconductor layer, and a heavily doped semiconductor layer.

[0024] The transistor 300 also includes a gate structure 310 wrapped around each of the channel layers 305 and located on each of the channel layers 305. The gate structure 310 includes at least a high-k gate dielectric layer (not separately labeled) and a metal gate electrode (not separately labeled) located on the high-k gate dielectric layer. The high-k gate dielectric layer may include silicon oxynitride, aluminum silicon oxide, a high-k dielectric material (e.g., hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate), other suitable dielectric materials, or combinations thereof. Although not shown, each metal gate electrode may include a bulk conductive layer. The bulk conductive layer may include Cu, W, Ru, Co, Al, Ti, Ta, other suitable metals, or combinations thereof. In some examples, each gate structure may include one or more work function metal layers of the same conductivity type or different conductivity types. Examples of work function metal layers may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi 2 、TaSi 2 、NiSi 2 , Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials or combinations thereof. Each gate structure may also include additional material layers, such as an interface layer, a barrier layer, a cap layer, other suitable material layers or combinations thereof.

[0025] The transistor 300 also includes top spacers 312a and 312b and an inner spacer 312c disposed on the sidewalls of the gate structure 310, wherein the top spacers 312a and 312b are disposed on the topmost channel layer 305 and the inner spacer 312c is disposed in the space between two channel layers 305 stacked in the vertical direction. In some embodiments, the top spacers 312a and 312b may include silicon oxide, silicon oxycarbide, silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or other suitable dielectric materials. The inner spacer 312c may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. In some embodiments, the transistor 300 also includes a dielectric cap layer 314 formed on the gate structure 310. The top spacers 312a and 312b also extend along the sidewall surface of the dielectric cap layer 314. In some other embodiments, the dielectric cap layer 314 may be formed on and in direct contact with both the gate structure 310 and the top spacers 312a and 312b.

[0026] The transistor 300 also includes a contact etch stop layer (CESL) 316 and an interlayer dielectric (ILD) layer 318 disposed over the source / drain features 308 and adjacent to the sidewalls of the top spacers 312a and 312b. The CESL 316 may include silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be formed by an atomic layer deposition (ALD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. After depositing the CESL 316, the ILD layer 318 may be deposited over the source / drain features 308 by a PECVD process or another suitable deposition technique. The ILD layer 318 may include, for example, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials).

[0027] Still refer to Figure 1 and Figure 2 , the method 100 includes block 104, at which source / drain contacts, source / drain contact vias, and gate vias are formed over the top surface 202t (or front side) of the substrate 202. In an exemplary process, a patterned mask layer (not shown) is formed over the transistor 300, and an etching process may be performed while using the patterned mask layer as an etching mask to remove portions of the ILD layer 318 and portions of the CESL 316, thereby forming a source / drain contact opening exposing the source / drain feature 308. A silicide layer 322 and a source / drain contact 320 are then formed in the source / drain contact opening. The source / drain contact 320 is electrically coupled to the source / drain feature 308 via the silicide layer 322. Since the source / drain contacts 320 are formed on the front side of the substrate 202, the source / drain contacts 320 may be referred to as front side source / drain contacts 320. The front side source / drain contacts 320 may include any suitable conductive material, such as Cu, W, Ru, Co, Al, Ti, Ta, other suitable metals, or combinations thereof. Each source / drain contact 320 may also include a barrier layer, which may include any suitable material, such as Ti, Ta, TiN, TaN, other suitable materials, or combinations thereof. The silicide layer 322 may include nickel silicide, titanium silicide, cobalt silicide, other suitable silicides, or combinations thereof.

[0028] After forming the front side source / drain contacts 320, an etch stop layer 324 and a dielectric layer 326 are formed over the transistor 300. The composition and formation of the etch stop layer 324 and the dielectric layer 326 may be similar to the composition and formation of the CESL 316 and the ILD layer 318, respectively, and are not described again for the sake of brevity. A source / drain contact via (e.g., source / drain contact via 328) is formed over the front side source / drain contacts 320, and a gate via (e.g., gate via 330) is formed over the gate structure 310 of the transistor 300. The composition and formation of the source / drain contact via (e.g., source / drain contact via 328) and the gate via (e.g., gate via 330) may be similar to the composition and formation of the front side source / drain contacts 320. In the present disclosure, the front side MEOL features (e.g., front side source / drain contacts 320, gate vias 330, source / drain contact vias 328) and the associated dielectric layer (e.g., dielectric layer 326) may be collectively referred to as the contact layer 204. It is understood that the contact layer 204 includes a plurality of gate vias 330 electrically coupled to corresponding gate structures 310, a plurality of front side source / drain contacts 320 electrically coupled to corresponding source / drain features 308, and a plurality of source / drain contact vias 328 electrically coupled to corresponding front side source / drain contacts 320.

[0029] Reference Figure 1 and Figures 3 to 6 The method 100 includes block 106, at which a multi-layer interconnect (MLI) structure 220 is formed on the front side of the substrate 202 (on the Figure 6 When completed, the multi-layer interconnect structure 220 may include multiple interconnect layers, which include interconnect components (such as metal lines) and vias that interconnect different metal lines from different interconnect layers in a vertical direction.

[0030] exist Figure 3In the illustrated embodiment, after forming the contact layer 204, a metal 0 interconnect layer M0 (as the bottommost interconnect layer of the multi-layer interconnect structure 220) is formed on the contact layer 204. The metal 0 interconnect layer M0 may be referred to as an M0 layer. Forming the M0 layer includes forming a dielectric layer 206d on the front side of the substrate 202 (including on the transistor 300). The dielectric layer 206d may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, the dielectric layer 206d may include a dielectric material such as silicon oxide or silicon nitride. In other embodiments, the dielectric layer 206d may include a polymer material. In some embodiments, the dielectric layer 206d is a two-layer structure and includes an interlayer dielectric layer formed on an etch stop layer.

[0031] One or more etching processes may be performed to form a number of trenches in the dielectric layer 206d, and one or more deposition processes may be performed to fill the trenches with a conductive material. The deposition process may include CVD, PVD, ALD, or a combination thereof. For example, a first deposition process may be performed to conformally deposit a barrier layer 206b on the workpiece 200 (including in the trenches). The barrier layer 206b may include Ti, Ta, TiN, or TaN. A second deposition process may then be performed to form a metal fill layer 206f on the barrier layer 206b that substantially fills the remainder of the trenches. A planarization process (e.g., a chemical mechanical polishing (CMP) process) may then be performed to remove excess portions of the barrier layer 206b and the metal fill layer 206f located outside the trenches and on the dielectric layer 206d, thereby forming a metal line 206m in the dielectric layer 206d. In one embodiment, the metal fill layer 206f includes copper. In other embodiments, the metal filling layer 206f may include cobalt, ruthenium, tungsten, aluminum, or a combination thereof.

[0032] Now refer to Figures 3 to 5After forming the M0 layer, a metal 1 interconnect layer M1 of a multi-layer interconnect structure 220 is formed on the M0 layer. The metal 1 interconnect layer M1 may be referred to as the M1 layer. The M1 layer includes a metal line 208m embedded in a dielectric layer 208d. In some embodiments, the dielectric layer 208d is a double-layer structure and includes an interlayer dielectric layer formed on an etch stop layer. The workpiece 200 also includes a via 1 interconnect layer V1 formed between the M0 layer and the M1 layer. The via 1 interconnect layer V1 may be referred to as the V1 layer. The V1 layer includes a number of vias 208v embedded in the dielectric layer 208d and configured to electrically connect the metal line 206m of the M0 layer and the metal line 208m of the M1 layer. A dual damascene process may be used to form the via 208v in the V1 layer and the metal line 208m in the M1 layer. The via 208v has a width W1 (in Figure 4 In an exemplary process, Figure 3 As shown in FIG. 1 , one or more deposition processes (eg, CVD, PVD, ALD) may be performed to form a dielectric layer 208d on the M0 layer (including on the top surface of the metal line 206m). Thereafter, as shown in FIG. Figure 4 As shown, one or more etching processes may be performed on the workpiece 200 to etch a number of trenches 208t in the dielectric layer 208d. Figure 4 As shown in FIG. 1 , at least one of the trenches 208t includes a lower portion and an upper portion, and the width spanned by the upper portion is greater than the width spanned by the lower portion. Referring now to FIG. Figure 5 . A barrier layer 208b is conformally deposited over the workpiece 200 (including in the trench 208t), and then a metal fill layer 208f is deposited over the barrier layer 208b and in the trench 208t. A planarization process may be applied to the workpiece 200 to remove excess portions of the barrier layer 208b and the metal fill layer 208f, thereby forming a metal line 208m in the M1 layer and a via 208v in the V1 layer. The composition and formation of the barrier layer 208b and the metal fill layer 208f may be similar to the composition and formation of the barrier layer 206b and the metal fill layer 206f, and are not described again for the sake of brevity. In the present disclosure, the metal line 208m and the via 208v located below the metal line 208m are formed by a dual damascene process, and the metal line 208m and the via 208v are part of the overall conductive feature. The portion of the integral conductive feature formed in the lower portion of the trench 208t is referred to as a via 208v, and the portion of the integral conductive feature formed in the upper portion of the trench 208t is referred to as a metal line 208m.

[0033] like Figure 6As shown in , after forming the M1 layer and the V1 layer, more interconnect layers (e.g., metal 2 interconnect layer M2, via 2 interconnect layer V2, metal 3 interconnect layer M3, via 3 interconnect layer V3, metal 4 interconnect layer M4, via 4 interconnect layer V4, metal 5 interconnect layer M5, and via 5 interconnect layer V5) are formed on the M0 layer to complete the manufacture of the multi-layer interconnect structure 220. The metal 2 interconnect layer M2, the metal 3 interconnect layer M3, the metal 4 interconnect layer M4, and the metal 5 interconnect layer M5 may be referred to as the M2 layer, the M3 layer, the M4 layer, and the M5 layer, respectively. The via 2 interconnect layer V2, the via 3 interconnect layer V3, the via 4 interconnect layer V4, and the via 5 interconnect layer V5 may be referred to as the V2 layer, the V3 layer, the V4 layer, and the V5 layer, respectively. The M2 layer and the V2 layer, the M3 layer and the V3 layer, the M4 layer and the V4 layer, and the M5 layer and the V5 layer may be formed in a manner similar to that of the M1 layer and the V1 layer, respectively. For example, the M2 layer and the V2 layer, the M3 layer and the V3 layer, the M4 layer and the V4 layer, and the M5 layer and the V5 layer may be formed by forming a dielectric layer and then performing a dual damascene process to form metal lines and vias in the dielectric layer, respectively. For simplicity, the dielectric layers of the multi-layer interconnect structure 220 may be referred to individually or collectively as dielectric layers 208d. The metal lines formed at the M2 layer, the M3 layer, the M4 layer, and the M5 layer may be referred to as metal lines 210m, metal lines 212m, metal lines 214m, metal lines 216m, and metal lines 218m, respectively. The vias formed at the V2 layer, the V3 layer, the V4 layer, and the V5 layer may be referred to as vias 210v, 212v, 214v, 216v, and 218v, respectively. It should be understood that Figure 6 The number of interconnect layers of the multilayer interconnect structure 220 shown in FIG. 2 is only an example, and the multilayer interconnect structure 220 may include any suitable number of interconnect layers. Since the multilayer interconnect structure 220 is formed on the front side of the transistor 300, the multilayer interconnect structure 220 may also be referred to as a front-side interconnect structure 220.

[0034] Reference Figure 1 and Figure 7, the method 100 includes block 108, where the workpiece 200 is bonded to a carrier substrate 222. In some embodiments, the carrier substrate 222 may be bonded to the workpiece 200 by fusion bonding, by using an adhesive layer, or a combination thereof. In some cases, the carrier substrate 222 may include a semiconductor material (e.g., silicon), sapphire, glass, a polymeric material, or other suitable material. In the present embodiment, the carrier substrate 222 is bonded to the front-side interconnect structure 220 using an adhesive layer 224. Once the carrier substrate 222 is bonded to the front-side interconnect structure 220 of the workpiece 200, the workpiece 200 may be flipped (not shown) and the workpiece 200 may be planarized from the bottom surface 202b of the substrate 202 to reduce the thickness of the substrate 202, thereby facilitating the formation of features under the transistor 300. All processes implemented to form features under the back side of the transistor 300 are performed while the workpiece 200 is flipped. However, for the sake of brevity, all positional relationships throughout the present disclosure are described in a manner that does not take into account the flipping of the substrate 202 .

[0035] Reference Figure 1 and Figure 8 , the method 100 includes block 110, at which one or more source / drain contacts 340 are formed below the bottom of the transistor 300. The portion of the workpiece 200 including the source / drain contacts 340 is enlarged for ease of illustration. In an exemplary process, after the substrate 202 is thinned, a patterned mask layer (not shown) may be formed below the bottom surface 202b of the substrate 202 to cover portions of the substrate 202. An etching process may be performed while using the patterned mask layer as an etching mask to remove portions of the substrate 202 that are not covered by the patterned mask layer, thereby forming a source / drain contact opening extending from the back side of the substrate 202 through the substrate 202 to expose a bottom surface of at least one source / drain feature 308 or a plurality of source / drain features 308 of the transistor 300. The source / drain contact openings formed under the back side of the transistor may be referred to as backside source / drain contact openings, and the source / drain contacts 340 to be formed in the backside source / drain contact openings may be referred to as backside source / drain contacts 340 .

[0036] After forming the back side source / drain contact opening, a dielectric barrier layer 336 may be conformally deposited and then etched back to cover only the sidewalls of the back side source / drain contact opening while exposing the source / drain features 308. In some embodiments, the dielectric barrier layer 336 may include silicon nitride or other suitable materials. The dielectric barrier layer 336 extends along the substrate 202 and is disposed directly below the source / drain features 308.

[0037] The operation at block 110 also includes forming a silicide layer 338 in the back side source / drain contact opening to reduce the contact resistance between the source / drain feature 308 and the back side source / drain contact 340 to be formed. The silicide layer 338 may include titanium silicide, tantalum silicide, nickel silicide, cobalt silicide, or tungsten silicide. After forming the silicide layer 338, the back side source / drain contact 340 may be formed in the back side source / drain contact opening. The back side source / drain contact 340 may include aluminum, rhodium, ruthenium, copper, iridium, or tungsten. The back side source / drain contact 340 is electrically coupled to the source / drain feature through the silicide layer 338. In other words, the silicide layer 338 is sandwiched between the source / drain feature 308 and the back side source / drain contact 340.

[0038] Reference Figure 1 and Fig. 9 The method 100 includes block 112, at which a backside metal 0 interconnect layer BM0 is formed below the bottom surface 202b of the substrate 202. Fig. 9In the illustrated embodiment, after forming the backside source / drain contacts 340, a backside metal-0 interconnect layer BM0 (as the topmost interconnect layer of the backside multi-layer interconnect (MLI) structure 260) is formed below the backside source / drain contacts 340. The backside metal-0 interconnect layer BM0 may be referred to as a BM0 layer. The BM0 layer is part of the backside MLI structure 260 and is therefore also part of the power delivery network (PDN) 270. Forming the BM0 layer includes forming a dielectric layer 226d below the back side of the substrate 202. The dielectric layer 226d may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process. In some embodiments, the dielectric layer 226d may include a dielectric material such as silicon oxide or silicon nitride. In other embodiments, the dielectric layer 226d may include a polymer material. One or more etching processes may then be performed to form a number of trenches in the dielectric layer, thereby exposing the bottom surface of the backside source / drain contact 340. Thereafter, one or more deposition processes may be performed to fill the trenches with a conductive material. The deposition process may include CVD, PVD, ALD, or a combination thereof. For example, a first deposition process may be performed to conformally deposit a barrier layer 226b in the trench. The barrier layer 226b may include Ti, Ta, TiN, or TaN. A second deposition process may then be performed to form a metal fill layer 226f that substantially fills the remainder of the trench. A planarization process (e.g., a chemical mechanical polishing (CMP) process) may then be performed to remove excess portions of the barrier layer 226b and the metal fill layer 226f outside the trench, thereby forming a metal line 226m in the dielectric layer 226d. In one embodiment, the metal fill layer 226f includes copper. In other embodiments, the metal fill layer 226f may include cobalt, ruthenium, tungsten, aluminum, or a combination thereof. Each of the metal lines 226m is in direct contact with one or more backside source / drain contacts 340. It should be noted that the backside source / drain contacts 340 are formed in both the first region 200A and the second region 200B. For ease of description, the metal line 226m formed in the second region 200B may be referred to as a metal line 226m, and the metal line 226m formed in the first region 200A may be referred to as a metal line 226m'.

[0039] Reference Figure 1 and Fig.13 , method 100 includes block 114, at which an additional backside interconnect layer is formed below the BM0 layer. Referring now to Figures 10 to 12After forming the BM0 layer, a backside metal 1 interconnect layer BM1 of the backside MLI structure 260 is formed under the BM0 layer. The backside metal 1 interconnect layer BM1 may be referred to as the BM1 layer. The BM1 layer includes a metal line 228m embedded in the dielectric layer 228d and the second region 200B. The workpiece 200 also includes a backside via 1 interconnect layer BV1 formed between the BM0 layer and the BM1 layer. The backside via 1 interconnect layer BV1 may be referred to as the BV1 layer. The BV1 layer includes a number of backside vias 228v embedded in the dielectric layer 228d and the second region 200B and configured to electrically couple the metal line 226m of the BM0 layer to the metal line 228m of the BM1 layer. A dual damascene process may be used to form the vias 228v in the BV1 layer and the metal line 228m in the BM1 layer. In an exemplary process, as Fig.10 As shown in FIG. 1 , one or more deposition processes (eg, CVD, PVD, ALD, etc.) may be performed to form a dielectric layer 228d below the BMO layer (including below the bottom surface of the metal line 226m). Thereafter, as shown in FIG. Fig.11 As shown, one or more etching processes may be performed on the workpiece 200 to etch a number of trenches 228t in the dielectric layer 228d. In the present embodiment, the trenches 228t are formed in the second region 200B but not in the first region 200A. Fig.11 As shown in FIG. 1 , at least one of the grooves 228t includes a lower portion and an upper portion, and the width of the upper portion is smaller than the width of the lower portion. Fig.12 . A barrier layer 228b is conformally deposited under the workpiece 200 (including in the trench 228t), and then a metal fill layer 228f is deposited to fill the trench 228t. A planarization process may be applied to the workpiece 200 to remove excess portions of the barrier layer 228b and the metal fill layer 228f, thereby forming a metal line 228m in the BM1 layer and a via 228v in the BV1 layer. The composition and formation of the barrier layer 228b and the metal fill layer 228f may be similar to the composition and formation of the barrier layer 206b and the metal fill layer 206f, and are not described again for the sake of brevity. In the present disclosure, the metal line 228m and the via 228v are formed by a dual damascene process, and the metal line 228m and the via 228v are part of the overall conductive feature. The portion of the overall conductive feature formed in the upper portion of the trench 228t is referred to as a via 228v, and the portion of the overall conductive feature formed in the lower portion of the trench 228t is referred to as a metal line 228m. It should be noted that the metal line 228m and the via 228v are formed in the second region 200B and not in the first region 200A.

[0040] Still refer to Figure 1 and Fig.13The operation in block 114 also includes forming more backside interconnect layers of the backside MLI structure 260 below the substrate 202. Fig.13 In the illustrated embodiment, after the BM1 layer and the BV1 layer are formed, more backside interconnect layers are formed under the BM0 layer, such as the backside via 2 interconnect layer BV2, the backside metal 2 interconnect layer BM2, the backside via 3 interconnect layer BV3, and the backside metal 3 interconnect layer BM3. The backside metal 2 interconnect layer BM2 and the backside metal 3 interconnect layer BM3 may be referred to as the BM2 layer and the BM3 layer, respectively. The backside via 2 interconnect layer BV2 and the backside via 3 interconnect layer BV3 may be referred to as the BV2 layer and the BV3 layer, respectively. The BM2 layer and the BV2 layer, the BM3 layer and the BV3 layer may be formed in a manner similar to that of the BM1 layer and the BV1 layer, respectively. For example, the BM2 layer and the BV2 layer may be formed by forming a dielectric layer 230d and then performing a dual damascene process to form metal lines and vias in the dielectric layer 230d; the BM3 layer and the BV3 layer may be formed by forming a dielectric layer 232d and then performing a dual damascene process to form metal lines and vias in the dielectric layer 232d. The metal lines formed at the BM2 layer and the BM3 layer may be referred to as metal lines 230m and metal lines 232m, respectively. The vias formed at the BV2 layer and the BV3 layer may be referred to as vias 230v and vias 232v, respectively. The metal lines 230m, 232m and the vias 230v, 232v are all formed in the second region 200B and not in the first region 200A. It should be understood that Fig.13 The number of interconnect layers of the backside MLI structure 260 shown in FIG. 2 is merely an example, and the backside MLI structure 260 may include any suitable number of interconnect layers.

[0041] Reference Figure 1 and Fig.14 , the method 100 includes block 116, at which a first dielectric layer 234d1 is formed below the BM3 layer. The first dielectric layer 234d1 may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, the first dielectric layer 234d1 may include a dielectric material such as silicon oxide or silicon nitride. In other embodiments, the first dielectric layer 234d1 may include a polymer material.

[0042] Reference Figure 1 and Figures 15 to 18, the method 100 includes block 118, at which a via 238 is formed in the first region 200A coupled to the metal line 226m' in the first region 200A. In an exemplary process, a mask layer (e.g., a hard mask layer and / or a photoresist layer) may be formed under the first dielectric layer 234d1, and then the mask layer may be patterned to form an opening that exposes a portion of the first dielectric layer 234d1 directly under the metal line 226m' in the first region 200A, while the first dielectric layer 234d1 covers other features in both the first region 200A and the second region 200B. Referring to Fig.15 , an etching process is performed while using a patterned mask layer (not shown) as an etching mask to remove portions of the dielectric layers 228d, 230d, 232d, and 234d1 exposed by the openings of the patterned mask layer to form trenches 236 in the first region 200A. That is, the trenches 236 extend through the dielectric layers 228d, 230d, 232d, and 234d1 and expose at least a portion of the bottom surface of the metal line 226m' formed in the first region 200A.

[0043] Reference Figure 16 to Figure 17 After forming the trench 236, a via 238 is formed in the trench 236. Since the via 238 extends through the dielectric layers 228d, 230d, 232d, and 234d, the via 238 may be referred to as a through dielectric via (TDV) 238 or a through oxide via (TOV) 238 when the dielectric layers 228d, 230d, 232d, and 234d are formed of oxide. In an exemplary process, as shown in FIG. Fig.16 As shown in FIG. 1 , a seed layer (or barrier layer) 238b is conformally deposited to partially fill the trench 236. The seed layer 238b may include titanium nitride (TiN) or other suitable materials. After the seed layer 238b is deposited, a metal filling layer 238f is formed to fill the rest of the trench 236. The metal filling layer 238f may include copper, cobalt, ruthenium, tungsten, aluminum, or a combination thereof. In one embodiment, the metal filling layer 238f includes copper. In one embodiment, the copper-based metal filling layer 238f is formed by electrochemical plating. Fig.17, a planarization process may be performed to remove excess portions of the metal fill layer 238f and the seed layer 238b outside the trench 236, thereby providing a planar bottom surface for the TDV 238. After the planarization process is performed, the bottom surface of the TDV 238 in the first region 200A is substantially coplanar with the bottom surface of the first dielectric layer 234d1. The TDV 238 has a thickness T1 that is greater than the thickness T2 of any of the vias in the MLI structure 220. In one embodiment, the thickness T1 is also greater than the thickness T3 of any of the vias in the MLI structure 260. In some embodiments, the thickness T1 is also greater than the thickness T4 of any of the metal lines (e.g., metal line 226m') in the MLI structure 260.

[0044] Fig.18 An exemplary partial top view of a TDV 238 in the first region 200A and an exemplary partial top view of a via (eg, via 228v) in the second region 200B are shown. In this embodiment, the top view of the TDV 238 is taken along Fig.17 AA shown in FIG. 2 , and the top view of the via hole (eg, via hole 228v) in the second region 200B is taken along the line AA shown in FIG. Fig.17 In this embodiment, as shown in FIG. Fig.18 As shown in , when viewed from the top within the same area (e.g., the product of length W3 and width W3), since the width W3 spanned by the TDV 238 is greater than the width W2 of each of the vias 228v, the first region 200A includes only one TDV 238, and the second region 200B includes a number of vias 228v. That is, the density of the conductive features of the second region 200B is greater than the density of the conductive features in the first region 200A. In some embodiments, in order to effectively reduce the IR drop, the ratio of the width W3 to the width W2 is greater than 10. In some embodiments, the width of one or more of the vias of the MLI structure 220 is substantially equal to the width W1. In the present embodiment, the shape of the top view of the TDV 238 is substantially a circular shape, and the shape of the top view of the via 228v is substantially a rectangular shape. It should be understood that the shapes of the top views of the TDV 238 and the via 228v may include other shapes, such as a circular shape, a square shape, and / or a rectangular shape.

[0045] Reference Figure 1 and Fig.19 The method 100 includes block 120, where a second dielectric layer 234d2 is formed below the first dielectric layer 234d1 at block 120. The formation and composition of the second dielectric layer 234d2 may be similar to the formation and composition of the first dielectric layer 234d1, and will not be described again for the sake of brevity. The first dielectric layer 234d1 and the second dielectric layer 234d2 may be collectively referred to as a dielectric layer 234d.

[0046] Reference Figure 1 and Figure 20 to Figure 21 , the method 100 includes block 122, at which a metal line 242m is formed below the TDV 238 and in the first region 200A, and at least one metal line 234m and a via 234v are formed below the metal line 232m and in the second region 200B. In the present embodiment, after forming the second dielectric layer 234d2, a trench 239a is formed in the first region 200A (at Fig. 20 238) to expose the bottom surface of the TDV 238, and form one or more trenches 239b (in the second region 200B) Fig. 20 2 (shown in FIG. 2 ) to expose the bottom surface of the metal line 232m. The trench 239a formed in the first region 200A and the trench 239b formed in the second region 200B may be formed simultaneously or sequentially in any order. In the present embodiment, the trench 239a extends through the second dielectric layer 234d2 to expose the TDV 238, and the trench 239b extends through both the first dielectric layer 234d1 and the second dielectric layer 234d2 to expose the bottom surface of the metal line 232m. That is, the trench 239a and the trench 239b have different depths.

[0047] Reference Fig.21 After forming the trenches 239a and 239b, a metal line 242m is formed in the trench 239a to directly contact the TDV 238, and a metal line 234m and a via 234v are formed in the trench 239b to directly contact the metal line 232m. In an exemplary process, a barrier layer 242b is conformally deposited and then a metal filling layer 242f is deposited to fill the remaining portions of the trenches 239a and 239b. In one embodiment, the barrier layer 242b may include titanium nitride, and the metal filling layer 242f may include copper. A CMP process may then be performed to remove excess portions of the barrier layer 242b and the metal filling layer 242f disposed outside the trenches 239a and 239b. The bottom surface of the metal line 242m is coplanar with the bottom surface of the metal line 234m in the second region 200B, and the top surface of the metal line 242m may be above, below, or coplanar with the top surface of the metal line 234m in the second region 200B. In one embodiment, the thickness of the metal line 242m is different from the thickness of the metal line 234m. In one embodiment, the metal line 234m and the second dielectric layer 234d2 may be collectively referred to as the backside interconnect layer BM4 (or BM4 layer) of the backside MLI structure 260, and the via 234v and the first dielectric layer 234d1 may be collectively referred to as the backside interconnect layer BV4 (or BV4 layer) of the backside MLI structure 260.

[0048] While the MLI structure 220, adhesive layer 224, and carrier substrate 222 are located on the front side of the substrate 202, a power delivery network (PDN) 270 is formed on the back side of the substrate 202. The PDN 270 is a structure that delivers power and ground voltages from conductive pad locations to various components (e.g., transistors 300) of the workpiece 200. In this embodiment, the PDN 270 includes metal lines and vias of the MLI structure 260 formed in the second region 200B. The PDN 270 also includes metal lines 226m', metal lines 242m, and TDVs 238 formed in the first region 200A. Electrical connections to the PDN 270 (and to the rest of the workpiece 200) can be obtained through conductive bumps 252 (e.g., solder balls) located on the back side of the PDN 270.

[0049] Reference Figure 1 and Fig. 22 , the method 100 includes block 124, at which further processes are performed. Such further processes may include forming a first protection structure 244 under the metal lines 234m and 242m, forming a bonding pad 246 (e.g., an aluminum pad) extending through the first protection structure 244 to electrically couple to the metal lines 234m and 242m. Such further processes may also include forming a second protection structure 248 under the first protection structure 244, forming an underbump metal (UBM) 250 extending through the second protection structure 248 to electrically couple to the bonding pad 246, and forming a solder ball 252 under the UBM 250. The solder ball 252 may be configured as an input / output (I / O) connector. Such further processes may also include bonding the workpiece 200 to another IC chip or a printed circuit board (PCB).

[0050] In the above embodiment, the TDV 238 is formed after forming metal lines (e.g., metal lines 228m, 230m, and 232m) and vias (e.g., vias 228v, 230v, 232v) in the second region 200B that are laterally adjacent to the TDV 238 in the first region 200A. In some other implementations, the TDV 238 may be formed before forming the metal lines and vias in the second region 200B.

[0051] In the present disclosure, compared to the second conductive path (represented by dotted line 255b) between the back source / drain contact 340 and the solder ball 252 in the second region 200B formed by a number of metal lines (e.g., metal lines 226m, 228m, 230m, 232m, 234m) and a number of vias (e.g., vias 228v, 230v, 232v, 234v) disposed between the number of metal lines, the first conductive path (represented by dotted line 255a) between the back source / drain contact 340 and the solder ball 252 in the first region 200A includes two metal lines (e.g., metal lines 226m' and 242m) and TDV 238. That is, the number of barrier layers in the first conductive path (represented by the dotted line 255a) of the first region 200A is much less than the number of barrier layers in the second conductive path (represented by the dotted line 255b) of the second region 200B. The reduction of barrier layers in the conductive path 255a will reduce the parasitic resistance and thus reduce the IR drop in the conductive path 255a of the first region 200A. That is, due to the presence of the TDV 238, the IR drop caused by the portion of the PDN 270 located in the first region 200A is less than the IR drop caused by the portion of the PDN 270 located in the second region 200B.

[0052] In the above embodiments, compared to the second conductive path (represented by dashed line 255b), the first conductive path (represented by dashed line 255a) can be considered as replacing all metal lines and vias disposed between the uppermost metal line (e.g., metal line 226m) and the lowermost metal line (e.g., metal line 234m) of the backside MLI structure 260 with TDV 238. In some other implementations, only some portions of these metal lines and vias are replaced by TDV 238. For example, in Fig.23 In the illustrated embodiment, the first conductive path 255a includes not only the TDV 238', but also the metal line 232m and the via 234v. The TDV 238' is in direct contact with the metal line 226m'. Fig.24 In the illustrated embodiment, the first conductive path 255a includes not only the TDV 238″, but also the metal line 228m and the via 228v. The TDV 238″ is in direct contact with the metal line 242m. The TDV 238′ and the TDV 238″ are similar to the TDV 238, except for their sizes. The degree to which the IR drop is improved can be flexibly adjusted by configuring the number of metal lines and vias in the first conductive path 255a, such as Figure 22 to Figure 24 This is represented by the embodiment shown in FIG.

[0053] In the above embodiments, the metal lines and vias (e.g., via 228v and metal line 228m) in the MLI structures 220 and 260 are formed by implanting a dual damascene process. Other processes may also be used to form the metal lines and vias. For example, a metal line (e.g., metal line 228m) may be formed after forming a via (e.g., via 228v), and the metal filling layer of the metal line is separated from the metal filling layer of the conductive feature by a barrier layer of the metal line.

[0054] Embodiments of the present disclosure provide various advantages. The disclosed method provides a power delivery network with reduced IR drop. In one embodiment, the power delivery network includes a first portion having a dielectric through-via disposed between a topmost interconnect layer of an MLI structure and a bottommost interconnect layer of the MLI structure. The power delivery network also includes a second portion having a number of metal lines and vias disposed between the topmost interconnect layer and the bottommost interconnect layer of the MLI structure. Forming the dielectric through-via reduces the parasitic resistance of the power delivery network and thus reduces IR drop during power delivery.

[0055] The present disclosure provides many different embodiments. A semiconductor structure and a method for making the same are disclosed herein. In one exemplary embodiment, the present disclosure is about a method. The method includes: receiving a workpiece, the workpiece including a first transistor and a second transistor formed on a first side of a substrate; forming a first multilayer interconnect structure on the first side of the substrate, wherein the first multilayer interconnect structure includes a first plurality of metal lines and a first plurality of through holes; after forming the first multilayer interconnect structure, forming a source / drain contact directly under the source / drain feature of the first transistor; and forming a second multilayer interconnect structure under the source / drain contact and under the second side of the substrate, the second side being opposite to the first side, wherein the second multilayer interconnect structure includes a second plurality of metal lines and a second through hole, wherein the thickness of the second through hole is greater than the thickness of a through hole in the first plurality of through holes.

[0056] In some embodiments, the one through hole in the first plurality of through holes spans a first width, the second through hole spans a second width, and a ratio of the second width to the first width is greater than 10. In some embodiments, the second through hole is disposed between and in direct contact with two metal lines in the second plurality of metal lines in a vertical direction, and one of the two metal lines in the second plurality of metal lines is in direct contact with the source / drain contact. In some embodiments, the forming of the second multi-layer interconnect structure may include: depositing a first dielectric layer under the second side of the substrate; forming a first trench in the first dielectric layer to expose a bottom surface of the source / drain contact; forming one metal line in the second plurality of metal lines in the first trench; depositing a second dielectric layer under the first dielectric layer; depositing a third dielectric layer under the second dielectric layer; forming a second trench extending through the second dielectric layer and the third dielectric layer, the second trench exposing a portion of the one metal line in the second plurality of metal lines; forming the second through hole in the second trench; and forming another metal line in the second plurality of metal lines under the second through hole. In some embodiments, the forming of the second via may include: forming a barrier layer in the second trench; forming a conductive material to fill the remaining portion of the second trench; and performing a planarization process to remove a portion of the barrier layer and a portion of the conductive material disposed under the third dielectric layer. The method may also include: after the forming of the second multi-layer interconnect structure, forming a conductive pad directly contacting the second via under the second via; and forming a solder bump under the conductive pad. In some embodiments, the second transistor may include: a plurality of nanostructures disposed on the substrate; a gate structure wrapped around each of the plurality of nanostructures and located on each of the plurality of nanostructures; and a source feature and a drain feature coupled to the plurality of nanostructures. In some embodiments, the forming of the source / drain contacts may include: reducing the thickness of the substrate; forming an opening extending through the substrate to expose the bottom surface of the source / drain feature; forming a dielectric liner pad extending along the sidewall surface of the opening; forming a silicide layer in the opening in direct contact with the source / drain feature; and depositing a conductive material in the opening. The method may also include: forming a plurality of source / drain contacts and a plurality of gate vias on the first side of the substrate before forming the first multi-layer interconnect structure. In some embodiments, the thickness of the second via may be greater than the thickness of a metal line in the second plurality of metal lines.

[0057] In another exemplary aspect, the disclosure relates to a method. The method includes receiving a workpiece, the workpiece including a first plurality of transistors located in a first region and a second plurality of transistors located in a second region over a substrate, and forming a power delivery network under the substrate to provide power signals to the first plurality of transistors and the second plurality of transistors, wherein the power delivery network includes a first portion and a second portion, the first portion having a first number of conductive features electrically coupled to the first plurality of transistors, the second portion having a second number of conductive features electrically coupled to the second plurality of transistors, wherein the first number is less than the second number.

[0058] In some embodiments, the method may also include: before forming the power delivery network, forming gate vias electrically coupled to the gate structures of the first plurality of transistors and the gate structures of the second plurality of transistors on the gate structures of the first plurality of transistors and the gate structures of the second plurality of transistors; forming source / drain contacts electrically coupled to the source / drain features of the first plurality of transistors and the source / drain features of the second plurality of transistors through a silicide layer on the source / drain features of the first plurality of transistors and the source / drain features of the second plurality of transistors; and forming an interconnect structure on the workpiece, the interconnect structure comprising metal lines and vias embedded in a dielectric layer and located above the gate vias and the source / drain contacts. The method may also include: before forming the power delivery network, thinning the thickness of the substrate from the back side of the substrate; forming a first trench and a second trench extending through the substrate, the first trench exposing the bottom surface of the source / drain features of the first plurality of transistors, and the second trench exposing the bottom surface of the source / drain features of the second plurality of transistors; forming a silicide layer in the first trench and the second trench; and forming a first source / drain contact in the first trench and a second source / drain contact in the second trench, wherein the power delivery network is disposed directly below the first source / drain contact and the second source / drain contact. In some embodiments, the forming of the power delivery network may include: depositing a first dielectric layer; forming a first metal line and a first via in the first dielectric layer and in the second region; depositing a second dielectric layer below the first dielectric layer; forming a second metal line and a second via in the second dielectric layer and in the second region; depositing a third dielectric layer below the second dielectric layer; forming a third metal line and a third via in the third dielectric layer and in the second region; forming an opening extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer, wherein the opening is formed in the first region; and forming a via in the opening, wherein the first portion of the power delivery network may include the via, and the second portion of the power delivery network may include the first metal line and the first via, the second metal line and the second via, and the third metal line and the third via. In some embodiments, the via may have a diameter greater than a diameter of a via of the second portion of the power delivery network. In some embodiments, forming the power delivery network may include: depositing an insulating layer below the via; forming a metal line opening extending through the insulating layer to expose a bottom surface of the via; and forming a metal line in the metal line opening.

[0059] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first transistor, the first transistor including: a plurality of nanostructures; a gate structure wrapped around each of the plurality of nanostructures; and a first source / drain feature and a second source / drain feature coupled to each of the plurality of nanostructures. The semiconductor structure also includes: a first source / drain contact disposed under the first source / drain feature; a first metal line disposed in a first dielectric layer and electrically coupled to the first source / drain contact, the first metal line disposed under the first source / drain contact and in direct contact with the first source / drain contact; a multi-layer dielectric structure disposed under the first dielectric layer; a first via extending through the multi-layer dielectric structure and in direct contact with the first metal line; and a second metal line disposed in a second dielectric layer and in direct contact with the first via, the second dielectric layer disposed under the multi-layer dielectric structure.

[0060] In some embodiments, the semiconductor structure may also include: a second source / drain contact disposed on the second source / drain feature; and a multi-layer interconnect structure disposed on the second source / drain contact. The semiconductor structure may also include a multi-layer interconnect structure disposed under the first source / drain contact and including a plurality of metal lines and a plurality of vias, wherein the multi-layer dielectric structure is a part of the multi-layer interconnect structure. In some embodiments, the thickness of the first via is greater than the thickness of the first metal line.

[0061] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: receiving a workpiece comprising a first transistor and a second transistor formed on a first side of a substrate; forming a first multi-layer interconnect structure on the first side of the substrate, wherein the first multi-layer interconnect structure comprises a first plurality of metal lines and a first plurality of vias; After forming the first multi-layer interconnect structure, forming a source / drain contact directly beneath the source / drain features of the first transistor; as well as forming a second multi-layer interconnect structure below the source / drain contacts and below a second side of the substrate, the second side being opposite to the first side, wherein the second multi-layer interconnect structure includes a second plurality of metal lines and second vias, The thickness of the second through hole is greater than the thickness of a through hole in the first plurality of through holes.

2. The method for forming a semiconductor structure according to claim 1, wherein: The one through-hole in the first plurality of through-holes spans a first width, the second through-hole spans a second width, and a ratio of the second width to the first width is greater than ten.

3. The method for forming a semiconductor structure according to claim 1, wherein: The second via is disposed between and in direct contact with two metal lines of the second plurality of metal lines in a vertical direction, and one of the two metal lines of the second plurality of metal lines is in direct contact with the source / drain contact.

4. The method for forming a semiconductor structure according to claim 1, wherein: The forming of the second multi-layer interconnect structure comprises: depositing a first dielectric layer beneath the second side of the substrate; forming a first trench in the first dielectric layer to expose a bottom surface of the source / drain contact; forming a metal line of the second plurality of metal lines in the first trench; depositing a second dielectric layer beneath the first dielectric layer; depositing a third dielectric layer below the second dielectric layer; forming a second trench extending through the second dielectric layer and the third dielectric layer, the second trench exposing a portion of the one metal line of the second plurality of metal lines; forming the second through hole in the second trench; and Another metal line of the second plurality of metal lines is formed under the second via.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: The forming of the second through hole comprises: forming a barrier layer in the second trench; forming a conductive material to fill the remaining portion of the second trench; and A planarization process is performed to remove a portion of the barrier layer and a portion of the conductive material disposed under the third dielectric layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the second multi-layer interconnect structure, forming a conductive pad directly contacting the second through hole under the second through hole; as well as A solder bump is formed beneath the conductive pad.

7. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the second via is greater than a thickness of a metal line in the second plurality of metal lines.

8. A method for forming a semiconductor structure, comprising: receiving a workpiece comprising a first plurality of transistors located in a first region and a second plurality of transistors located in a second region over a substrate; as well as forming a power delivery network beneath the substrate to provide power signals to the first plurality of transistors and the second plurality of transistors, wherein the power delivery network includes a first portion having a first number of conductive features electrically coupled to the first plurality of transistors and a second portion having a second number of conductive features electrically coupled to the second plurality of transistors, Wherein the first number is smaller than the second number.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: Also includes: Before forming the power delivery network, forming gate vias on gate structures of the first plurality of transistors and gate structures of the second plurality of transistors to be electrically coupled to the gate structures of the first plurality of transistors and the gate structures of the second plurality of transistors; forming source / drain contacts over source / drain features of the first plurality of transistors and source / drain features of the second plurality of transistors and electrically coupled to the source / drain features of the first plurality of transistors and the source / drain features of the second plurality of transistors through a silicide layer; and An interconnect structure is formed on the workpiece, the interconnect structure including metal lines and vias embedded in a dielectric layer and located above the gate vias and the source / drain contacts.

10. A semiconductor structure comprising: A first transistor comprising: Multiple nanostructures, a gate structure surrounding each of the plurality of nanostructures; and a first source / drain feature and a second source / drain feature coupled to each of the plurality of nanostructures; a first source / drain contact disposed below the first source / drain feature; A first metal line, located in the first dielectric layer and electrically coupled to the first source / drain contact, wherein the first metal line is disposed below the first source / drain contact and directly contacts the first source / drain contact; A multi-layer dielectric structure disposed below the first dielectric layer; a first through hole extending through the multi-layer dielectric structure and directly contacting the first metal line; and The second metal line is located in a second dielectric layer and directly contacts the first through hole. The second dielectric layer is disposed under the multi-layer dielectric structure.

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