Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The method comprises the steps that an initial semiconductor structure is provided, the initial semiconductor structure comprises a silicon substrate provided with at least one first transistor and at least one second transistor, the line width of a first grid electrode of the first transistor is larger than or equal to 40 nm, and the line width of a second grid electrode of the second transistor is smaller than 40 nm; at least forming a first metal silicide layer on the top of the first source electrode and the top of the first drain electrode, wherein the first metal silicide layer is a CoSi2 layer; and at least forming a second metal silicide layer on the top of the second source electrode and the top of the second drain electrode, wherein the second metal silicide layer is a NiSi layer. According to the invention, the metal silicide film layers made of different materials are formed in the transistors with different line widths as the contact regions, so that the overall contact resistance of the subsequent transistors and the metal wires is reduced, the small line width effect and the film layer agglomeration defect caused by high temperature are avoided, and the electrical performance of the device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As the integration of semiconductor components becomes higher and higher, the circuit size gradually becomes smaller, and the contact area provided in the layout for connecting individual components with the contact structure becomes smaller and smaller. Especially in high-density memory cells, such as dynamic random access memory devices (DRAM), the depth of the contact structure required to reach increases, and the current flowing becomes smaller. In this case, the parameter of contact resistance becomes more important in the electrical properties of the component.

[0003] In order to speed up the operation of components, and taking into account factors such as wiring miniaturization and thermal resistance, the industry now generally performs a silicidation process at the connection between the metal wire and the source / drain and the gate to form metal silicides such as cobalt silicide to reduce contact resistance. This can reduce the energy loss of the device and improve the current transmission efficiency, which has a direct effect on improving the performance of the device. The application of metal silicides in semiconductor devices has greatly promoted the development of semiconductor technology.

[0004] At present, the formation process of metal silicide in the device is usually to form a metal film layer on the surface of the silicon-based material at the connection between the source / drain and the gate, and to promote the silicidation reaction between the metal film layer and the silicon-based material through a heat treatment process to generate metal silicide. However, the process conditions, device line width and the composition of the metal layer will affect the performance of the metal silicide, and the three also have mutual influences. For example, cobalt silicide is more suitable for high-temperature process, but it is subject to boundary inhibition in small line width devices and it is difficult to form a molecular structure with a small resistance value; in small line width devices, nickel silicon can form a molecular structure with a small resistance value at a relatively low temperature, but it will generate a molecular structure with a higher resistance value under high temperature conditions, which is difficult to be applied to high temperature processes. The existing semiconductor manufacturing method is difficult to balance the influence of the process conditions, device line width and the composition of the metal layer on the performance of the metal silicide, and it is impossible to form a metal silicide film layer with a small resistance value.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In view of this, a semiconductor device and a manufacturing method thereof are provided, by which a metal silicide film layer with a low resistivity can be formed, thereby effectively reducing the contact resistance of the device and improving the performance of the device.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0008] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising:

[0009] Providing an initial semiconductor structure, the initial semiconductor structure comprising a silicon substrate, at least one first transistor and at least one second transistor formed on the silicon substrate, the first transistor comprising a first gate, a first source and a first drain, the second transistor comprising a second gate, a second source and a second drain, the line width of the first gate being greater than or equal to 40 nm, and the line width of the second gate being less than 40 nm;

[0010] forming a first metal silicide layer at least on the top of the first source electrode and the top of the first drain electrode, wherein the first metal silicide layer is a CoSi2 layer;

[0011] A second metal silicide layer is formed at least on the top of the second source and the top of the second drain, and the second metal silicide layer is a NiSi layer.

[0012] In an exemplary embodiment of the present disclosure, the material of the first gate is polysilicon, and the method for manufacturing the semiconductor device includes:

[0013] A first metal silicide layer is formed on the top of the first gate, the top of the first source, and the top of the first drain, and the first metal silicide layer is a CoSi2 layer.

[0014] In an exemplary embodiment of the present disclosure, the material of the second gate is polysilicon, and the method for manufacturing the semiconductor device includes:

[0015] A second metal silicide layer is formed on the top of the second gate, the top of the second source, and the top of the second drain, and the second metal silicide layer is a NiSi layer.

[0016] In an exemplary embodiment of the present disclosure, the method of forming the first metal silicide layer includes:

[0017] Covering the entire surface of the initial semiconductor structure with a first protective material layer;

[0018] Performing patterning on the first protective material layer to form a first protective layer, wherein the first protective layer at least exposes the first source electrode and the first drain electrode;

[0019] forming a first metal layer, wherein the first metal layer conformally covers the initial semiconductor structure having the first protective layer, and the first metal layer is a Co metal layer;

[0020] The first metal layer is subjected to a first heat treatment to diffuse Co in the first metal layer into the silicon substrate, so as to form a first sub-metal silicide layer at least on the top of the first source and the top of the first drain.

[0021] In an exemplary embodiment of the present disclosure, after forming the first sub-metal silicide layer, the method includes:

[0022] The first sub-metal silicide layer is subjected to a second heat treatment to transform the first sub-metal silicide layer into the first metal silicide layer, wherein the resistivity of the first metal silicide layer is less than the resistivity of the first sub-metal silicide layer.

[0023] In an exemplary embodiment of the present disclosure, after forming the first sub-metal silicide layer and before converting the first sub-metal silicide layer into the first metal silicide layer, the method further includes: removing the remaining unreacted first metal layer.

[0024] In an exemplary embodiment of the present disclosure, after forming the first metal layer and before performing the first heat treatment, the method further includes:

[0025] A first covering film is formed, wherein the first covering film conformally covers the surface of the first metal layer.

[0026] In an exemplary embodiment of the present disclosure, the forming of the second metal silicide layer includes:

[0027] Covering the entire surface of the initial semiconductor structure or the surface after the first metal silicide layer is formed on the initial semiconductor structure with a second protective material layer;

[0028] Performing patterning on the second protective material layer to form a second protective layer, wherein the second protective layer at least exposes the second source electrode and the second drain electrode;

[0029] forming a second metal layer, wherein the second metal layer conformally covers the initial semiconductor structure having the second protective layer or the initial semiconductor structure after the first metal silicide layer is formed, and the second metal layer is a Ni metal layer;

[0030] The second metal layer is subjected to a first sub-heat treatment to diffuse Ni in the second metal layer into the silicon substrate, so as to form a second sub-metal silicide layer on at least the top of the second source and the top of the second drain.

[0031] In an exemplary embodiment of the present disclosure, after forming the second sub-metal silicide layer, the method further includes:

[0032] The second sub-metal silicide layer is subjected to a second sub-heat treatment, wherein the temperature of the second sub-heat treatment is higher than the temperature of the first sub-heat treatment, so that the second sub-metal silicide layer is converted into the second metal silicide layer, wherein the resistivity of the second metal silicide layer is less than the resistivity of the second sub-metal silicide layer.

[0033] In an exemplary embodiment of the present disclosure, after forming the second sub-metal silicide layer and before converting the second sub-metal silicide layer into the second metal silicide layer, the method further includes: removing the remaining unreacted second metal layer.

[0034] In an exemplary embodiment of the present disclosure, after forming the second metal layer and before performing the first sub-heat treatment, the method further includes:

[0035] A second covering film is formed, wherein the second covering film conformally covers the surface of the second metal layer.

[0036] In an exemplary embodiment of the present disclosure, the second covering film includes at least one of platinum, ruthenium, iridium, rhodium, and palladium.

[0037] According to another aspect of the present disclosure, a semiconductor device is provided. The device is manufactured using the above manufacturing method. The semiconductor device includes:

[0038] Silicon substrate;

[0039] at least one first transistor, the first transistor being formed on the silicon substrate, the first transistor comprising a first gate, a first source, a first drain and a first metal silicide layer, the first metal silicide layer being at least located on the top of the first source and the top of the first drain, and the first metal silicide layer being a CoSi2 layer;

[0040] at least one second transistor, the second transistor being formed on the silicon substrate, the second transistor comprising a second gate, a second source, a second drain and a second metal silicide layer, the second metal silicide layer being at least located on the top of the second source and the top of the second drain, and the second metal silicide layer being a NiSi layer;

[0041] The line width of the first gate is greater than or equal to 40 nm, and the line width of the second gate is less than 40 nm.

[0042] In an exemplary embodiment of the present disclosure, each of the first transistors and each of the second transistors are independently selected from a PMOS transistor or an NMOS transistor.

[0043] The present invention provides a method for manufacturing a semiconductor device, wherein a first transistor and a second transistor having different line widths are formed on a silicon substrate, wherein the line width of the first transistor is greater than or equal to 40 nm, and the line width of the second transistor is less than 40 nm, that is, the first transistor is a large line width device, and the second transistor is a small line width device, and a first metal silicide film layer is formed at a contact position between the source / drain of the first transistor and the metal line, wherein the first metal silicide film layer is a CoSi2 layer, and a second metal silicide film layer is formed at a contact position between the source / drain of the second transistor and the metal line, wherein the second metal silicide film layer is a NiSi layer. By forming a low-resistance CoSi2 layer as a contact area on a transistor with a larger line width, and forming a low-resistance NiSi layer as a contact area on a transistor with a smaller line width, on the one hand, the influence of boundary inhibition on the diffusion of metal ions is overcome, and at the same time, the agglomeration defects caused by high temperature are avoided, and the small line width effect is overcome; on the other hand, the formed semiconductor device is not affected by high temperature in subsequent processes and has strong applicability; thirdly, the metal silicide film layer formed in the device is uniform and has a small resistance, which is conducive to reducing contact resistance, improving the current transmission efficiency of the device, and thus improving the overall performance of the device.

[0044] The semiconductor device provided by the present invention includes a first transistor and a second transistor with different line widths. A first metal silicide layer is formed at the contact position between the source / drain of the first transistor and the metal line, and the first metal silicide layer is a CoSi2 layer. A second metal silicide layer is formed at the contact position between the source / drain of the second transistor and the metal line, and the second metal silicide layer is a NiSi layer. Metal silicide contact areas with different components are formed on transistors with different line widths, so that the overall resistivity of the metal silicide film layer in the device is small, the contact resistance is small, and it is suitable for a variety of process steps, and the overall performance of the device is good.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0047] Figure 1 The present invention discloses a flow chart of a method for manufacturing a semiconductor device in an exemplary embodiment.

[0048] Figure 2It is a schematic structural diagram of a semiconductor device in which a first protective material layer is formed in an exemplary embodiment of the present disclosure.

[0049] Figure 3 It is a schematic structural diagram of a semiconductor device for forming a first patterned photoresist layer in an exemplary embodiment of the present disclosure.

[0050] Figure 4 It is a schematic structural diagram of a semiconductor device in which a first protection layer is formed in an exemplary embodiment of the present disclosure.

[0051] Figure 5 It is a schematic structural diagram of a semiconductor device with a first protective layer in an exemplary embodiment of the present disclosure.

[0052] Figure 6 It is a schematic structural diagram of a semiconductor device in which a first metal layer is formed in an exemplary embodiment of the present disclosure.

[0053] Figure 7 It is a schematic structural diagram of a semiconductor device in which a first covering film is formed in an exemplary embodiment of the present disclosure.

[0054] Figure 8 It is a schematic structural diagram of a semiconductor device in which a first metal silicide layer is formed in an exemplary embodiment of the present disclosure.

[0055] Fig. 9 It is a schematic structural diagram of a semiconductor device in which a second protective material layer is formed in an exemplary embodiment of the present disclosure.

[0056] Fig.10 It is a schematic structural diagram of a semiconductor device for forming a second patterned photoresist layer in an exemplary embodiment of the present disclosure.

[0057] Fig.11 It is a schematic structural diagram of a semiconductor device in which a second protection layer is formed in an exemplary embodiment of the present disclosure.

[0058] Fig.12 It is a schematic structural diagram of a semiconductor device with a second protective layer in an exemplary embodiment of the present disclosure.

[0059] Fig.13 It is a schematic structural diagram of a semiconductor device in which a second metal layer is formed in an exemplary embodiment of the present disclosure.

[0060] Fig.14 It is a schematic structural diagram of a semiconductor device in which a second covering film is formed in an exemplary embodiment of the present disclosure.

[0061] Fig.15 It is a schematic structural diagram of a semiconductor device in which a second metal silicide layer is formed in an exemplary embodiment of the present disclosure.

[0062] The reference numerals are described as follows:

[0063] 100, silicon substrate; 210, first transistor; 211, first gate; 212, first source; 213, first drain; 220, second transistor; 221, second gate; 222, second source; 223, second drain; 310, first protective layer; 311, first protective material layer; 320, second protective layer; 321, second protective material layer; 410, first metal silicide layer; 420, second metal silicide layer; 510, first metal layer; 520, second metal layer; 610, first covering film; 620, second covering film; 810, first patterned photoresist layer; 820, second patterned photoresist layer. DETAILED DESCRIPTION

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0065] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0066] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0067] In the related art, in semiconductor structures, metal silicide is usually one of the indispensable film layers in semiconductor devices due to its characteristics of reducing contact resistance, improving thermal stability, and improving device performance. When it is used as a contact material between a metal wire and the source / drain / gate in a transistor, it can significantly reduce contact resistance and improve current conductivity, which is crucial to improving the overall electrical performance of the device. In addition, the metal silicide film layer has good thermal stability and is not easy to decompose or degrade in high-temperature processes. It also plays an important role in the semiconductor process. Therefore, it is necessary to ensure the formation of a uniform and low-resistance metal silicide film layer.

[0068] At present, commonly used metal silicides include titanium silicide (TiSi2), tungsten silicide (WSi2), cobalt disilicide (CoSi2) and nickel silicon (NiSi), etc. Each has its own characteristics and applicable scenarios when forming a metal silicide layer and being used in semiconductors.

[0069] In deep submicron and nanoscale processes, cobalt disilicide (CoSi2) and nickel silicon (NiSi) are often used. For nickel-containing silicide, the molecular component of its low-resistance phase is NiSi, and the molecular structure of the high-resistance phase is Ni2Si and NiSi2. In the process of forming nickel-containing silicide, for devices with larger line widths, NiSi can be formed at a lower temperature. When the temperature is further increased, silicon ions will further combine with nickel ions to form NiSi2 with a larger resistance value. Therefore, nickel-containing silicide is not suitable for large line width devices and high-temperature processes at the same time; for cobalt-containing silicide, the molecular component of its low-resistance phase is C oSi2, the molecular structure of the high-resistance phase is Co2Si and CoSi. In the process of forming cobalt-containing silicide, for devices with smaller line widths, Co2Si and CoSi are formed at lower temperatures. In order to transform the cobalt silicide from a low-resistance phase to a high-resistance phase, the temperature needs to be further increased to promote the further combination of silicon ions with cobalt ions. However, due to the line width effect, silicon ions cannot continue to diffuse in the part of the film layer close to the surface, causing this part of the film layer to remain in the high-resistance phase. As the temperature continues to rise, the film layer will also agglomerate and produce agglomeration defects. Therefore, cobalt-containing silicide is not suitable for small line width devices and low-temperature processes at the same time.

[0070] In the present disclosure, line width refers to the geometric dimensions of each structure in a semiconductor device, which may include a gate, a source, a drain, and other structures such as contact holes. For example, the line width of a gate may refer to the width between one side wall and the other side wall of the gate, and the line width of a source and a drain may refer to the width of the source and drain in the cross section of the device in a direction parallel to the silicon substrate. The width may be the maximum width dimension, the minimum width dimension, or the average width dimension, and the line width may be measured based on one of the above three dimensions.

[0071] It should be noted that the large line width, relatively large line width, small line width and relatively small line width provided in the present disclosure are all relative sizes and do not limit the actual size within the device. The line width in the present disclosure can be of various sizes such as micron level, submicron level, deep submicron level, nanometer level, subnanometer level, etc. The comparison between sizes can be of the same size level or of different size levels, and can be specifically divided according to the actual structure of the device.

[0072] In the present disclosure, 40nm is used as a boundary to define the size of the device line width, wherein when the gate line width of the device is greater than or equal to 40nm, the device is a large line width device, and when the gate line width of the device is less than 40nm, the device is a small line width device. For the semiconductor device provided in the present disclosure, the sizes of the gate and the source and drain can be consistent or approximately consistent, that is, after determining the gate size, the source and drain sizes can be confirmed. However, it should be noted that with the development of the process, the defined size of the device line width may be different from the size provided above, but it should be considered that the manufacturing method provided in the present disclosure is equally applicable.

[0073] Based on this, the present disclosure provides a method for manufacturing a semiconductor device, such as Figure 1 As shown, the manufacturing method includes: steps S10 to S30.

[0074] Wherein, step S10: providing an initial semiconductor structure, the initial semiconductor structure comprising a silicon substrate, at least one first transistor and at least one second transistor formed on the silicon substrate, the first transistor comprising a first gate, a first source and a first drain, the second transistor comprising a second gate, a second source and a second drain, the line width of the first gate being greater than or equal to 40 nm, and the line width of the second gate being less than 40 nm;

[0075] Step S20: forming a first metal silicide layer at least on the top of the first source electrode and the top of the first drain electrode, wherein the first metal silicide layer is a CoSi2 layer;

[0076] Step S30: forming a second metal silicide layer at least on the top of the second source and the top of the second drain, wherein the second metal silicide layer is a NiSi layer.

[0077] It should be understood that the order of forming the first metal silicide layer and the second metal silicide layer is not specific (i.e., the order of step S20 and step S30 is not specific), that is, the first metal silicide layer can be formed first and then the second metal silicide layer, or the second metal silicide layer can be formed first and then the first metal silicide layer, but it should be noted that before forming the metal silicide layer at the target position, it is necessary to cover the other non-target positions with a protective film. Therefore, the order of forming the first metal silicide layer and the second metal silicide layer will affect the design of the corresponding protective film layer.

[0078] In some embodiments, the first gate and / or the second gate are both polysilicon gates, and the above step S20 further includes forming a first metal silicide layer on top of the first gate, and / or the step S30 further includes forming a second metal silicide layer on top of the second gate. It should be understood that if the first gate and the second gate are both metal gates, it is not necessary to design a metal silicide contact layer.

[0079] The manufacturing method of the semiconductor device provided by the present disclosure forms a first transistor and a second transistor with different line widths on a silicon substrate, wherein the line width of the first transistor is greater than or equal to 40nm, and the line width of the second transistor is less than 40nm, and forms a first metal silicide film layer, i.e., a CoSi2 layer, at least at the contact position between the source and drain of the first transistor and the metal line, and forms a second metal silicide film layer, i.e., a NiSi layer, at least at the contact position between the source and drain of the second transistor and the metal line. By forming a CoSi2 layer on a transistor with a larger line width and a NiSi layer on a transistor with a smaller line width, the line width effect is overcome and agglomeration defects caused by high temperature are avoided; the formed metal silicide film layer structure is not affected by high temperature in subsequent processes and has strong applicability; the metal silicide film layer formed in the device is uniform and has a small resistance value, which is conducive to reducing contact resistance, improving the current transmission efficiency of the device, and thus improving the overall performance of the device.

[0080] The following will describe in detail the various steps of the method for manufacturing a semiconductor device according to the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0081] In the embodiment provided in the present disclosure, the first gate and the second gate are both polysilicon gates. Figure 2 As shown, in step S10 , an initial semiconductor structure is provided. The initial semiconductor structure includes a silicon substrate 100 , on which at least one first transistor 210 and at least one second transistor 220 are formed.

[0082] Among them, the silicon substrate 100 can be a semiconductor substrate, for example, it can be a silicon (Si) substrate, a silicon germanium (Ge Si) substrate, SOI (Silicon On Insulator) or SOS (Silicon-on-Sapphire). In some embodiments, the semiconductor substrate can also be a substrate including other element semiconductors or compound semiconductors, for example, silicon carbide (SiC) and the like. The embodiments provided in the present disclosure are described by taking the silicon substrate 100 as a substrate mainly including silicon (Si) elements as an example. Of course, for other types of silicon substrates 100, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the scope of protection of the present disclosure.

[0083] The first transistor 210 can be independently selected as a PMOS (Positive-channel Metal-Oxide-Semiconductor Field-Effect Transistor) device or an NMOS (N-Metal-Oxide-Semiconductor Field-Effect Transistor) device. Each first transistor 210 and each second transistor 220 can be independently selected as a PMOS transistor or an NMOS transistor. The specific number and type of the first transistor 210 and the second transistor 220 can be selected according to the actual design requirements of the device.

[0084] When the first transistor 210 or the second transistor 220 is an NMOS transistor, the silicon substrate 100 can be a P-type silicon substrate, and an N-type well or an N-type isolation region is formed on the silicon substrate 100; two high-concentration N-type regions are formed in the N-type well by ion implantation or diffusion process to form a source or a drain.

[0085] When the first transistor 210 or the second transistor 220 is a PMOS transistor, the silicon substrate 100 may be a P-type silicon substrate, an epitaxial layer is formed on the silicon substrate 100, and the epitaxial layer may be N-type; an N-type well or an N-type isolation region is formed in the epitaxial layer by ion implantation or diffusion process; two high-concentration P-type regions are formed in the N-type well by ion implantation or diffusion process to form a source or a drain. If the transistor is a PMOS transistor, it can be understood that the silicon substrate 100 proposed in this article includes an epitaxial layer required to form a PMOS transistor.

[0086] This disclosure Figure 2 In the embodiment shown, the initial semiconductor structure includes two first transistors 210, one of which is an NMOS transistor and the other is a PMOS transistor, and the initial semiconductor structure also includes two second transistors 220, both of which are NMOS transistors. However, it should be understood that when the type and number of transistors change, the embodiments provided in the present disclosure can be adaptively modified or adjusted to obtain the manufacturing method provided in the present disclosure.

[0087] It should be noted that in the embodiment provided in the present disclosure, the number of the first transistor 210 and the second transistor 220 is not limited to: Figure 2The embodiment shown is limited, wherein the number of the first transistor 210 is at least one, and the number of the second transistor 220 is at least one. When the number of the first transistor 210 and the second transistor 220 are both multiple, the multiple first transistors 210 and the multiple second transistors 220 can be arranged alternately and spaced. Of course, the first area and the second area can also be defined on the silicon substrate 100 according to the type and function of the device, wherein the first area is used to form the multiple first transistors 210, and the second area is used to form the multiple second transistors 220. The number and arrangement of the first transistor 210 and the second transistor 220 can be adaptively adjusted according to the actual design requirements of the device.

[0088] Among them, the first transistor 210 includes a first gate 211, a first source 212 and a first drain 213, and the first source 212 and the first drain 213 are respectively located on both sides of the first gate 211. The first source 212 and the first drain 213 are respectively located on both sides of the second gate 221, which means that the edges of the first source 212 and the first drain 213 are respectively adjacent to the outer edges of the side walls of the first gate 211, that is, there is no gap or the gap is very small and can be ignored between the first source 212 and the first drain 213 and the outer edge of the first gate 211.

[0089] Among them, the line width of the first gate 211 is greater than or equal to 40nm, and the first transistor 210 formed thereby can be considered as a large line width device. Correspondingly, the line width of the first source 212 and the line width of the first drain 213 are also greater than or equal to 40nm. That is, after determining the line width of the first gate 211, the line width of the first source 212 and the line width of the first drain 213 can be determined accordingly.

[0090] The first gate 211 may include a gate oxide layer, a gate layer and a gate protection layer, and the gate oxide layer is formed on the silicon substrate 100. The gate oxide layer may be a silicon dioxide (SiO2) or other high-K dielectric material layer, such as one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3) or yttrium oxide (Y2O3). It may be formed by one or more of methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE) or plasma enhanced chemical vapor deposition (PECVD). The specific formation method may be adaptively selected and adjusted according to the material and other characteristics of the gate oxide layer.

[0091] The gate layer is formed on the gate oxide layer. The gate layer can be polysilicon (poly). It can be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALE), sputtering, photolithography or etching, but it should be noted that with the development of semiconductor technology, the gate layer of the present disclosure can also be made of non-metallic materials other than polysilicon, and in order to reduce the contact resistance between the non-metallic gate layer and the metal wire when the non-metallic gate layer forms an electrical connection with the metal wire, the manufacturing method of the present disclosure can also be used to form a metal silicide in the contact area between the gate layer and the metal wire.

[0092] The gate protection layer is formed on the side wall of the gate layer. The gate protection layer may include at least one insulating layer and at least one passivation layer formed in sequence along the side wall direction away from the gate layer. Of course, the gate protection layer may also be formed by one insulating layer or one passivation layer according to the actual structural requirements of the device. If there are multiple insulating layers and passivation layers, the multiple insulating layers and the multiple passivation layers are alternately distributed on the side wall of the gate in sequence along the side wall direction away from the gate layer. In the embodiments of the present disclosure, the gate protection layer is a multi-layer structure as an example for explanation.

[0093] The insulating layer in the gate protection layer may be silicon dioxide (SiO2) or other high dielectric constant material layer, such as one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3) or yttrium oxide (Y2O3). It may be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The specific formation method may be adaptively selected and adjusted according to the material and other characteristics of the insulating layer.

[0094] The passivation layer can be made of materials such as silicon nitride (Si3N4), which can be formed by methods such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Of course, the material of the passivation layer can also be formed by other materials and process methods according to the actual structural requirements of the device.

[0095] Each second transistor 220 includes a second gate 221, a second source 222 and a second drain 223, wherein the second source 222 and the second drain 223 are respectively located on both sides of the second gate 221. The second gate 221 has the same or substantially the same structure as the first gate 211, and the second gate 221 will not be described in detail herein.

[0096] Among them, the line width of the second gate 221 is less than 40nm, and the second transistor 220 formed thereby can be considered as a small line width device. Correspondingly, the line width of the second source 222 and the line width of the second drain 223 are also less than 40nm. That is, after determining the line width of the second gate 221, the line width of the second source 222 and the line width of the second drain 223 can be determined accordingly.

[0097] In some embodiments, the line width of the first gate 211 is greater than the line width of the second gate 221, the line width of the first source 212 is greater than the line width of the second source 222, and the line width of the first drain 213 is greater than the line width of the second drain 223, so as to ensure that the overall line width of the first transistor 210 is greater than the overall line width of the second transistor 220. In the same semiconductor device, transistors with different line widths are formed to enrich the functions of the semiconductor device and improve the applicability and practicality of the device.

[0098] In the embodiment provided by the present disclosure, the semiconductor device further includes an isolation structure (not shown in the figure), which is formed in the silicon substrate 100 and is located between two adjacent transistors. Adjacent transistors or transistors and other devices or regions can be electrically isolated by the isolation structure, which can be a shallow trench isolation structure, and the distribution form of the semiconductor structure and the distance between adjacent transistors can be selected according to the actual design requirements of the device.

[0099] The method for forming the isolation structure on the silicon substrate 100 may include: defining an area for forming the isolation structure on the silicon substrate 100 by photolithography, and etching a shallow trench in the defined area by dry or wet etching; filling the shallow trench with an insulating material, such as silicon oxide (SiO2), to form an isolation film layer in the shallow trench; and then performing a planarization process to expose the surface of the silicon substrate 100. The number of the isolation structure is at least one, and when the number is multiple, the multiple isolation structures may be distributed in an array on the silicon substrate 100. By providing the isolation structure on the silicon substrate 100, current leakage between devices can be effectively prevented, and the performance and reliability of the device can be improved.

[0100] In the embodiments provided in the present disclosure, if dry etching is adopted, one or more of reactive ion etching (RIE), ion beam etching (IBE), plasma etching (Plasma Etching), deep reactive ion etching (DRIE), electron cyclotron resonance etching (ECR) or inductively coupled plasma etching (ICP) may be adopted; if wet etching is adopted, one or more of isotropic etching (Isotropic Etching), anisotropic etching (Anisotropic Etching), selective etching (Selective Etching), chemical mechanical etching (Chemical Mechanical Etching), alkaline etching (Alkaline Etching) or acidic etching (Acidic Etching) may be adopted, and an appropriate etching method may be selected according to parameters such as the material, thickness and properties of the film layer.

[0101] In the embodiments provided in the present disclosure, Figure 8 As shown, in step S20 , a first metal silicide layer 410 is formed at least on the top of the first source 212 and the top of the first drain 213 , and the first metal silicide layer 410 is a CoSi 2 layer.

[0102] Among them, Figures 2 to 8 As shown in the figure, in this embodiment, the preparation sequence is to first form the first metal silicide layer 410 and then form the second metal silicide layer 420. Forming the first metal silicide layer 410 includes: covering the entire surface of the initial semiconductor structure with a first protective material layer 311, such as Figure 2 As shown; the first protective material layer 311 is patterned to form a first protective layer 310, and the first protective layer 310 at least exposes the first source 212 and the first drain 213.

[0103] Specifically, patterning the first protective material layer 311 may include: forming a first patterned photoresist layer 810 on the surface of the first protective material layer 311, such as Figure 3 As shown; using the first patterned photoresist layer 810 as a mask, the first protective material layer 311 is etched, as shown Figure 4 As shown; then remove the first patterned photoresist layer, as shown Figure 5 As shown, a first protection layer 310 is formed.

[0104] The first protective layer 310 is obtained by etching the first protective material layer 311. Therefore, the first protective layer 310 and the first protective material layer 311 are made of the same material. The first protective material layer 311 can be prepared using materials such as silicon nitride (Si3N4) and can be formed using one or more methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD).

[0105] In order to further form a protective isolation effect on the second transistor 220, the isolation structure and the two side walls of the first gate 211, and avoid damage or destruction to the second transistor 220, the isolation structure and the two side walls of the first gate 211 when processing the first transistor 210, it is necessary to make the first protective material layer 311 expose the top of the first source 212, the top of the first drain 213 and the top of the first gate 211 while covering the isolation structure, the second transistor 220 and the two side walls of the first gate 211. Therefore, a first patterned photoresist layer 810 is formed on the first protective material layer 311, and the first patterned photoresist layer 810 covers the second transistor 220, the isolation structure on the silicon substrate 100 and the two side walls of the first gate 211. The first protective material layer 311 is etched using the first patterned photoresist layer 810 as a mask to form a first protective layer 310 exposing the top of the first source 212, the top of the first drain 213 and the top of the first gate 211. The first protective material layer 311 may be etched by dry etching or wet etching.

[0106] The first patterned photoresist layer 810 may be made of photoresist, and the first patterned photoresist layer 810 may be removed by ashing, wet process, etc. For example, a chemical solution such as potassium hydroxide, tetramethylammonium hydroxide, sulfuric acid or nitric acid may be used to remove the photoresist to expose the surface of the first protective layer 310. Of course, the specific removal process of the first patterned photoresist layer 810 may be adaptively adjusted to avoid damage to the first protective layer 310.

[0107] The first protective layer 310 exposes at least the first source 212 and the first drain 213, and may also expose the first gate 211 according to the position requirements for forming the first metal silicide layer 410. In this embodiment, the first protective material layer 311 exposes the top of the first source 212, the top of the first drain 213, and the top of the first gate 211.

[0108] Among them, Figure 6As shown, forming a first metal silicide layer 410 also includes: forming a first metal layer 510, the first metal layer 510 is conformally covered on the initial semiconductor structure having the first protective layer 310, and the first metal layer 510 is a Co metal layer; performing a first heat treatment on the first metal layer 510 to diffuse the cobalt ions in the first metal layer 510 into the silicon substrate 100 to form a first sub-metal silicide layer on the top of the first source 212, the top of the first drain 213 and the top of the first gate 211.

[0109] In order to avoid the influence of external impurities on the first metal layer 510, especially to avoid the oxidation of the first metal layer 510 by oxygen, as shown in FIG. Figure 7 As shown, after forming the first metal layer 510, the formation method may further include: forming a first covering film 610, and the first covering film 610 is conformally covered on the surface of the first metal layer 510. The first covering film 610 may be one or more of materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), etc., which may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) and the like. The specific material and formation process of the first covering film 610 may be adaptively selected and adjusted according to the device process design. Taking the first covering film 610 as titanium nitride (TiN) as an example, the thickness of the first covering film 610 may be 5nm to 15nm, for example, the thickness may be 5nm, 8nm, 10nm, 13nm, 15nm, etc.

[0110] The first metal layer 510 is subjected to a first heat treatment to diffuse Co in the first metal layer 510 into the corresponding silicon substrate and the gate layer of the first gate 211, so as to form a first sub-metal silicide layer on the top of the first source 212, the top of the first drain 213, and the top of the first gate 211. The first heat treatment may include a first intermediate heat treatment and a second intermediate heat treatment.

[0111] The first intermediate heat treatment includes: at a temperature of 250°C to 410°C, using Co in the first metal layer 510 as a diffusion source, so that Co is doped into the first source 212, the first drain 213 and the first gate 211, and dicobaltized silicon (Co2Si) is formed in the first source 212, the first drain 213 and the first gate 211, especially at the exposed positions of the first source 212, the first drain 213 and the first gate 211, the concentration of Co is higher, and more dicobaltized silicon (Co2Si) is formed.

[0112] The second intermediate heat treatment includes: at a temperature of 410°C to 700°C, Co continues to act as a diffusion source and further diffuses into the first source 212, the first drain 213 and the first gate 211, forming cobaltized silicon (CoSi) in the first source 212, the first drain 213 and the first gate 211. After the first heat treatment, dicobaltized silicon (Co2Si) and cobaltized silicon (CoSi) can exist in the first sub-metal silicide layer at the same time, and the resistivity of dicobaltized silicon (Co2Si) and cobaltized silicon (CoSi) are both high, and the resistance value of the formed first sub-metal silicide is also large. The temperature range of the first intermediate heat treatment and the second intermediate heat treatment in the above-mentioned first heat treatment is only shown as an exemplary embodiment. In the actual heat treatment process, the above-mentioned temperature range does not have a strict limit and can be adaptively adjusted according to the actual process requirements.

[0113] The first sub-metal silicide layer may include dicobalt silicon (Co2Si) and cobalt silicon (CoSi), and the thickness of the first sub-metal silicide layer may be 5nm to 30nm, for example, 5nm, 8nm, 15nm, 20nm, 22nm, 25nm, 29nm or 30nm, etc. The thickness of the first sub-metal silicide layer formed is different according to the ratio between dicobalt silicon (Co2Si) and cobalt silicon (CoSi) in the first sub-metal silicide layer. In this embodiment, the thickness of the first sub-metal silicide layer refers to the size of the film layer in the direction perpendicular to the silicon substrate 100.

[0114] In order to form the first metal silicide layer 410 with a smaller resistance, after forming the first sub-metal silicide layer, the method further includes: performing a second heat treatment on the first sub-metal silicide layer to transform the first sub-metal silicide layer into the first metal silicide layer 410, such as Figure 8 As shown, the resistivity of the first metal silicide layer 410 is less than the resistivity of the first sub-metal silicide layer.

[0115] As the temperature of the heat treatment further increases, such as when the temperature increases to greater than 700°C, at this time, the Si in the device diffuses into the first sub-metal silicide layer as a diffusion source. Since the first transistor 210 has a larger line width, Si will not be inhibited by the boundary on ion diffusion. Therefore, the formed dicobalt silicon (Co2Si) and cobalt silicon (CoSi) continue to combine with Si to form cobalt disilicide (CoSi2). The resistivity of cobalt disilicide (CoSi2) is smaller than that of dicobalt silicon (Co2Si) and cobalt silicon (CoSi). The resistance value of cobalt disilicide (CoSi2) is small, which can effectively reduce the contact resistance and improve the overall electrical performance of the device.

[0116] The temperature of the second heat treatment is greater than the temperature of the first heat treatment. Specifically, the temperature of the second heat treatment may be greater than 700°C, such as 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C or even higher. The time of the second heat treatment may also be different according to the temperature within the temperature conditions. The second heat treatment time may be in the nanosecond to millisecond range. For example, under high temperature conditions, the treatment time may be appropriately shortened; under low temperature conditions, the treatment time may be appropriately increased.

[0117] Among them, the first metal silicide layer 410 may include cobalt disilicide (CoSi2), and the thickness of the first metal silicide layer 410 may be 15nm to 55nm. For example, the thickness may be 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, etc., and its thickness may be adjusted according to the requirements of the device.

[0118] After forming the first sub-metal silicide layer and before the first sub-metal silicide layer is converted into the first metal silicide layer 410, the method further includes removing the remaining unreacted first metal layer 510. The remaining first metal layer 510 can be removed by wet chemical etching, dry etching, mechanical polishing, laser etching, electrochemical etching, etc. The specific process can be selected according to the actual process design requirements.

[0119] Before removing the remaining unreacted first metal layer 510, the method further includes: removing the first covering film 610. Taking TiN as an example, wet etching, dry etching, chemical mechanical polishing or laser stripping can be used, and the specific method can be selected according to the actual process design requirements.

[0120] In the present disclosure, embodiments are provided, such as Fig.12 As shown, in step S30 , a second metal silicide layer 420 is formed on the top of the second source 222 , the top of the second drain 223 , and the top of the second gate 221 , and the second metal silicide layer 420 is a NiSi layer.

[0121] Among them, Figures 9 to 12As shown, forming a second metal silicide layer 420 includes: covering the surface of the initial semiconductor structure or the surface after forming the first metal silicide layer on the initial semiconductor structure with a second protective material layer 321; patterning the second protective material layer 321 to form a second protective layer 320, and the second protective layer 320 exposes the second source 222, the second drain 223 and the top of the second gate 221.

[0122] In order to further form a protective isolation effect on the first transistor 210 on which the first metal silicide layer 410 has been formed, and to avoid damage or destruction to the two side walls of the first transistor 210 and the second gate 221 when processing the second transistor 220, it is necessary to make the second protective material layer 321 expose the top of the second source 222, the top of the second drain 223, and the top of the second gate 221 while covering other positions. Therefore, a second patterned photoresist layer 820 is formed on the second protective material layer 321, and the second patterned photoresist layer 820 covers the first transistor 210 and the isolation structure. The second protective material layer 321 is etched using the second patterned photoresist layer 820 as a mask to form a second protective layer 320 that exposes the top of the second source 222, the top of the second drain 223, and the top of the second gate 221. The second protective material layer 321 can be etched by dry etching or wet etching.

[0123] Specifically, the method for forming the second protective layer 320 may include: forming a second protective material layer 321, the second protective material layer 321 conformally covers the surface of the initial semiconductor structure or the initial semiconductor structure after the first metal silicide layer is formed, such as Fig. 9 As shown; a second patterned photoresist layer 820 is formed on the surface of the second protective material layer 321, as Fig.10 As shown; using the second patterned photoresist layer 820 as a mask, the second protective material layer 321 is etched, as shown Fig.11 As shown; then remove the second patterned photoresist layer 820, as Fig.12 As shown, a second protection layer 320 is formed.

[0124] The second protective layer 320 is obtained by etching the second protective material layer 321. Therefore, the second protective layer 320 and the second protective material layer 321 are made of the same material. The second protective material layer 321 can be prepared using materials such as silicon nitride (Si3N4) and can be formed using one or more methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD).

[0125] The second protective layer 320 exposes at least the second source 222 and the second drain 223 in the second transistor 220, and may also expose the second gate 221 according to the position requirements for forming the second metal silicide layer 420. In this embodiment, the second protective layer 320 exposes the top of the second source 222, the top of the second drain 223, and the top of the second gate 221.

[0126] It should be noted that before forming the second protective layer 320, the first protective layer 310 can be removed first; or the second protective layer 320 can include the first protective layer 310, and when the second protective layer 320 is etched, the first protective layer 310 covering the second transistor 220 is also etched to form a second protective layer 320 that exposes the surface of the second transistor 220 and covers the surface of the first transistor 210. The processing process of the first protective layer 310 can be selected according to the process design requirements.

[0127] The second patterned photoresist layer 820 can be made of photoresist, and the removal of the second patterned photoresist layer 820 can also be done by ashing, wet processing, etc. The removal process can be the same or substantially the same as the removal process of the first patterned photoresist layer 810, and will not be described in detail here.

[0128] In some embodiments, the second protection layer 320 is also made of silicon nitride material.

[0129] Among them, the formation Fig.15 The method for forming the second metal silicide layer 420 shown in the figure also includes: forming a second metal layer 520, the second metal layer 520 conformally covering the initial semiconductor structure having the second protective layer 320 or the initial semiconductor structure after forming the first metal silicide layer, the second metal layer 520 is a Ni metal layer, such as Fig.13 As shown; the second metal layer 520 is subjected to a first sub-heat treatment so that the Ni in the second metal layer 520 diffuses into the corresponding silicon substrate and the gate layer of the second gate 221 to form a second sub-metal silicide layer on the top of the second source 222, the top of the second drain 223 and the top of the second gate 221.

[0130] Among them, Fig.14As shown, after forming the second metal layer 520, the method further includes: forming a second covering film 620, and the second covering film 620 is conformally covered on the surface of the second metal layer 520. The second covering film 620 may include at least one of platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), and palladium (Pd). For example, the second covering film 620 includes platinum (Pt), and the platinum (Pt) in the second covering film 620 can be used as a catalyst to promote the reaction between nickel and silicon and increase the reaction rate; the second covering film 620 can also prevent impurity metals or other impurities from diffusing into the silicon substrate 100, and accurately control the formation of nickel-silicon compounds; the second covering film 620 also helps to improve the interface characteristics between the second metal layer 520 and the second transistor 220, and form a stable interface morphology.

[0131] The second covering film 620 can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD) and the thickness thereof can be 5 nm to 90 nm. The specific thickness and forming method of the second covering film 620 can be adjusted according to process requirements and design objectives.

[0132] After forming the second sub-metal silicide layer, the method further includes: performing a second sub-heat treatment on the second sub-metal silicide layer, the temperature of the second sub-heat treatment being higher than the temperature of the first sub-heat treatment, so as to convert the second sub-metal silicide layer into a second metal silicide layer 420, wherein the resistivity of the second metal silicide layer 420 is less than the resistivity of the second sub-metal silicide layer.

[0133] Among them, the first sub-heat treatment includes: at a temperature of 200℃~300℃, using Ni in the second metal layer 520 as a diffusion source, so that Ni is doped into the second gate 221, the second source 222 and the second drain 223, and nickel disilazer (Ni2Si) is formed in the second gate 221, the second source 222 and the second drain 223.

[0134] Since the resistivity of the formed second sub-metal silicide layer is relatively large, in order to further obtain the second metal silicide layer 420 with a lower resistivity, it is further necessary to perform a second sub-heat treatment on the second sub-metal silicide layer, wherein the temperature of the second sub-heat treatment is higher than the temperature of the first sub-heat treatment, and the second sub-heat treatment includes: at a temperature of 400°C to 700°C, using Si as a diffusion source, so that Si is doped into the second sub-metal silicide layer, and nickel silicon (NiSi) is formed in the second gate 221, the second source 222 and the second drain 223, that is, the second sub-metal silicide layer is converted into the second metal silicide layer 420. Since the resistivity of nickel silicon (NiSi) is lower than the resistivity of nickel silicon (Ni2Si), and the second metal silicide layer 420 is mainly composed of NiSi, the resistivity of the second metal silicide layer 420 is less than the resistivity of the second sub-metal silicide layer.

[0135] As the temperature of the heat treatment continues to rise, such as when the temperature rises to greater than 700°C, in the second transistor 220, due to its smaller line width, the boundary of the device inhibits ion diffusion. Even if the temperature continues to rise, the silicon ions in the silicon substrate 100 cannot continue to diffuse toward the surfaces of the second gate 221, the second source 222, and the second drain 223. That is, nickel disilicide (NiSi2) with a larger resistance cannot be formed at the second gate 221, the second source 222, and the second drain 223. In particular, near the surfaces of the second gate 221, the second source 222, and the second drain 223, the second metal silicide layer 420 exists in the form of nickel silicon (NiSi) with a low resistance phase, forming a second metal silicide layer 420 with a smaller resistance. The second metal silicide layer 420 is not affected by high temperature, thereby providing a good structural foundation for the subsequent formation of transistors.

[0136] Among them, the second metal silicide layer 420 may include nickel silicon (NiSi), and its thickness may be 10nm to 60nm, for example, it may be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc., and its thickness may be adjusted according to the requirements of the device.

[0137] After forming the second sub-metal silicide layer and before converting the second sub-metal silicide layer into the second metal silicide layer 420, the method further includes: removing the remaining unreacted second metal layer 520. The method for removing the second metal layer 520 is similar to the method for removing the first metal layer 510, and will not be described in detail here.

[0138] Before removing the remaining unreacted second metal layer 520, the method further includes: removing the second covering film 620. Taking the second covering film 620 as Pt as an example, wet etching, dry etching, chemical mechanical polishing or laser stripping can be used, and the specific method can be selected according to the actual process design requirements.

[0139] In order to promote the uniformity and stability of the second metal silicide layer 420, after forming the second metal silicide layer 420, the method includes: further heat treatment of the second metal silicide layer 420, the temperature of the further heat treatment is higher than the temperature of the second sub-heat treatment. The temperature of the further heat treatment can be greater than 700°C, for example, it can be 700°C, 800°C, 900°C, 1000°C, 1100°C or even higher, and the further heat treatment can be a high temperature annealing process to repair the lattice damage in the film layer, form a better lattice structure in the film layer, and obtain a better transistor.

[0140] After forming the second metal silicide layer 420, the method further includes: forming a second protective film (not shown in the figure), the second protective film conformally covering the surface of the target semiconductor structure. The second protective film can be formed of materials such as silicon nitride (Si3N4).

[0141] The present invention provides a method for manufacturing a semiconductor device, by forming at least one first transistor 210 and at least one second transistor 220 with different line widths on a silicon substrate 100, wherein the first transistor 210 is a device with a large line width and the second transistor 220 is a device with a small line width, and forming a first metal silicide film layer at the contact position between the source / drain / gate of the first transistor 210 and the metal line, and forming a second metal silicide film layer at the contact position between the source / drain / gate of the second transistor 220 and the metal line, and by forming a CoSi2 layer in the transistor with a larger line width and a NiSi layer in the transistor with a smaller line width, the small line width effect is overcome and agglomeration defects caused by high temperature are avoided; the formed metal silicide film layer structure is not affected by high temperature in subsequent processes and has strong applicability; the metal silicide film layer formed in the device is uniform and has a small resistance value, which is beneficial to reducing contact resistance, improving the current transmission efficiency of the device, and thus improving the overall performance of the device.

[0142] It should be noted that, although the steps of the method for manufacturing a semiconductor device in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0143] The present disclosure also provides a semiconductor device, such as Fig.15 As shown, the semiconductor device is manufactured by the above manufacturing method, and the semiconductor device includes: a silicon substrate 100 , at least one first transistor 210 and at least one second transistor 220 .

[0144] Among them, the first transistor 210 is formed on the silicon substrate 100, and the first transistor 210 includes a first gate 211, a first source 212, a first drain 213 and a first metal silicide layer 410, and the first metal silicide layer 410 is respectively located on the top of the first gate 211, the first source 212 and the first drain 213, and the first metal silicide layer 410 is a CoSi2 layer; the second transistor 220 is formed on the silicon substrate 100, and the second transistor 220 includes a second gate 221, a second source 222, a second drain 223 and a second metal silicide layer 420, and the second metal silicide layer 420 is respectively located on the top of the second gate 221, the second source 222 and the second drain 223, and the second metal silicide layer 420 is a NiSi layer; wherein the line width of the first gate 211 is greater than or equal to 40nm, and the line width of the second gate 221 is less than 40nm.

[0145] In the embodiment provided in the present disclosure, each first transistor 210 and each second transistor 220 are independently selected to be a PMOS device or an NMOS device.

[0146] Among them, the specific structure and formation process of the first transistor 210 and the second transistor 220 are the same or substantially the same as those of the embodiment provided by the above-mentioned manufacturing method, and are not repeated here.

[0147] The semiconductor device provided by the present invention includes a first transistor 210 and a second transistor 220 with different line widths, wherein a first metal silicide layer 410 is formed at the contact position between the source / drain / gate of the first transistor 210 and the metal line, and the first metal silicide layer 410 is a CoSi2 layer, and a second metal silicide layer 420 is formed at the contact position between the source / drain / gate of the second transistor 220 and the metal line, and the second metal silicide layer 420 is a NiSi layer. Metal silicide contacts with different components are formed in transistors with different line widths, so that the overall resistivity of the metal silicide film layer in the device is small, the contact resistance is small, and it is suitable for a variety of process steps, and the overall performance of the device is good.

[0148] The semiconductor device provided by the present disclosure can be applied to dynamic random access memory (DRAM), static random access memory (SRAM), flash memory (Flash Memory), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), etc. Of course, it can also be applied to other storage devices not listed, which are not listed here.

[0149] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing an initial semiconductor structure, the initial semiconductor structure comprising a silicon substrate, at least one first transistor and at least one second transistor formed on the silicon substrate, the first transistor comprising a first gate, a first source and a first drain, the second transistor comprising a second gate, a second source and a second drain, the line width of the first gate being greater than or equal to 40 nm, and the line width of the second gate being less than 40 nm; forming a first metal silicide layer at least on the top of the first source electrode and the top of the first drain electrode, wherein the first metal silicide layer is a CoSi2 layer; A second metal silicide layer is formed at least on the top of the second source and the top of the second drain, and the second metal silicide layer is a NiSi layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the first gate is polysilicon, and the manufacturing method of the semiconductor device includes: A first metal silicide layer is formed on the top of the first gate, the top of the first source, and the top of the first drain, and the first metal silicide layer is a CoSi2 layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the second gate is polysilicon, and the manufacturing method of the semiconductor device includes: A second metal silicide layer is formed on the top of the second gate, the top of the second source, and the top of the second drain, and the second metal silicide layer is a NiSi layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The method of forming a first metal silicide layer comprises: Covering the entire surface of the initial semiconductor structure with a first protective material layer; Performing patterning on the first protective material layer to form a first protective layer, wherein the first protective layer at least exposes the first source electrode and the first drain electrode; forming a first metal layer, wherein the first metal layer conformally covers the initial semiconductor structure having the first protective layer, and the first metal layer is a Co metal layer; The first metal layer is subjected to a first heat treatment to diffuse Co in the first metal layer into the silicon substrate, so as to form a first sub-metal silicide layer at least on the top of the first source and the top of the first drain.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: After forming the first sub-metal silicide layer, the method comprises: The first sub-metal silicide layer is subjected to a second heat treatment to transform the first sub-metal silicide layer into the first metal silicide layer, wherein the resistivity of the first metal silicide layer is less than the resistivity of the first sub-metal silicide layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: After forming the first sub-metal silicide layer and before converting the first sub-metal silicide layer into the first metal silicide layer, the method further includes: removing the remaining unreacted first metal layer.

7. The method for manufacturing a semiconductor device according to claim 4, wherein: After forming the first metal layer and before performing the first heat treatment, the method further includes: A first covering film is formed, wherein the first covering film conformally covers the surface of the first metal layer.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of the second metal silicide layer comprises: Covering the entire surface of the initial semiconductor structure or the surface after the first metal silicide layer is formed on the initial semiconductor structure with a second protective material layer; Performing patterning on the second protective material layer to form a second protective layer, wherein the second protective layer at least exposes the second source electrode and the second drain electrode; forming a second metal layer, wherein the second metal layer conformally covers the initial semiconductor structure having the second protective layer or the initial semiconductor structure after the first metal silicide layer is formed, and the second metal layer is a Ni metal layer; The second metal layer is subjected to a first sub-heat treatment to diffuse Ni in the second metal layer into the silicon substrate, so as to form a second sub-metal silicide layer on at least the top of the second source and the top of the second drain.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: After forming the second sub-metal silicide layer, the method further comprises: The second sub-metal silicide layer is subjected to a second sub-heat treatment, wherein the temperature of the second sub-heat treatment is higher than the temperature of the first sub-heat treatment, so that the second sub-metal silicide layer is converted into the second metal silicide layer, wherein the resistivity of the second metal silicide layer is less than the resistivity of the second sub-metal silicide layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: After forming the second sub-metal silicide layer and before converting the second sub-metal silicide layer into the second metal silicide layer, the method further includes: removing the remaining unreacted second metal layer.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: After forming the second metal layer and before performing the first sub-heat treatment, the method further includes: A second covering film is formed, wherein the second covering film conformally covers the surface of the second metal layer.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The material of the second covering film includes at least one of platinum, ruthenium, iridium, rhodium and palladium.

13. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 12, characterized in that: include: Silicon substrate; at least one first transistor, the first transistor being formed on the silicon substrate, the first transistor comprising a first gate, a first source, a first drain and a first metal silicide layer, the first metal silicide layer being at least located on the top of the first source and the top of the first drain, and the first metal silicide layer being a CoSi2 layer; at least one second transistor, the second transistor being formed on the silicon substrate, the second transistor comprising a second gate, a second source, a second drain and a second metal silicide layer, the second metal silicide layer being at least located on the top of the second source and the top of the second drain, and the second metal silicide layer being a NiSi layer; The line width of the first gate is greater than or equal to 40 nm, and the line width of the second gate is less than 40 nm.

14. The semiconductor device according to claim 13, characterized in that Each of the first transistors and each of the second transistors are independently selected from a PMOS transistor or an NMOS transistor.

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