Display substrate and display panel

Abstract

The invention discloses a display substrate and a display panel. The display substrate comprises a substrate, a first insulating layer, a semiconductor layer, a second insulating layer, a metal layer and a third insulating layer which are sequentially stacked, wherein the semiconductor layer and the metal layer are partial structures of a thin film transistor in the display substrate, the display substrate further comprises at least one groove, the groove is at least located in one side of the thin film transistor, and the groove penetrates through the first insulating layer and the second insulating layer. And the third insulating layer is also filled in the groove and is attached to the substrate in the groove. Through the design, the metal layer and the semiconductor layer in the thin film transistor can be prevented from being invaded by external water vapor or free ions.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display panel. Background Art

[0002] As a key semiconductor device, thin film transistors (TFT) have been widely used in the field of modern electronic technology. Especially in flat panel display technologies, such as liquid crystal display (LCD) and organic electroluminescence display (OLED), with the development of various new display technologies, the performance requirements for thin film transistors are getting higher and higher, especially in terms of stability. Through the development of new materials, design optimization, improvement of manufacturing processes and improvement of packaging technology, future thin film transistors will be more adaptable to increasingly stringent application requirements, thereby expanding their application scope and depth in the global electronics market.

[0003] Since the metal layer and semiconductor layer in the current thin film transistor are easily invaded by external water vapor or free ions, which leads to the degradation of the device characteristics of the thin film transistor, how to prevent the metal layer and semiconductor layer in the thin film transistor from being invaded by external water vapor or free ions is an important research direction that needs to be studied in the current display field. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a display substrate and a display panel to prevent the metal layer and the semiconductor layer in the thin film transistor from being invaded by external water vapor or free ions.

[0005] An embodiment of the present application discloses a display substrate, which includes a base, a first insulating layer, a semiconductor layer, a second insulating layer, a metal layer and a third insulating layer, wherein the first insulating layer is arranged on the base, the semiconductor layer is arranged on a side of the first insulating layer away from the base, the second insulating layer is arranged on a side of the semiconductor layer away from the first insulating layer, the metal layer is arranged on a side of the second insulating layer away from the semiconductor layer, and the third insulating layer is arranged on the metal layer; wherein the semiconductor layer and the metal layer are partial structures of a thin film transistor in the display substrate, the display substrate also includes at least one groove, the groove is at least located on one side of the thin film transistor, and the groove runs through the first insulating layer and the second insulating layer, and the third insulating layer is also filled in the groove and adheres to the base in the groove.

[0006] Optionally, the display substrate also includes a first dam structure, which is arranged between the second insulating layer and the third insulating layer and adjacent to the groove; wherein the first dam structure is composed of an insulating material, and the bonding force between the first dam structure and the second insulating layer is greater than the bonding force between the first dam structure and the third insulating layer.

[0007] Optionally, the display substrate also includes a second dam structure, the second dam structure is arranged between the second insulating layer and the third insulating layer, and the groove is located between the first dam structure and the second dam structure; wherein the first dam structure and the second dam structure are formed by the same process.

[0008] Optionally, an area of ​​the first dam structure in contact with the second insulating layer is larger than an area of ​​the first dam structure in contact with the third insulating layer, and an area of ​​the second dam structure in contact with the second insulating layer is larger than an area of ​​the second dam structure in contact with the third insulating layer.

[0009] Optionally, in the thickness direction of the substrate, the cross-section of the first dam structure is trapezoidal, the width of the side of the first dam structure in contact with the second insulating layer is 2.8um-3.2um, the width of the side of the first dam structure in contact with the third insulating layer is 1.5um-2.5um, and the height of the first dam structure is 0.5um-0.8um.

[0010] Optionally, the material of the first dam structure is the same as that of the second insulating layer, and different from that of the third insulating layer; and / or, a rate of forming the first dam structure is higher than a rate of forming the third insulating layer.

[0011] Optionally, the display substrate also includes a third dam structure, which is located between the first insulating layer and the second insulating layer, arranged in parallel with the semiconductor layer, and the third dam structure is also located between the semiconductor layer and the groove; wherein the third dam structure is composed of an insulating material, and the bonding force between the third dam structure and the first insulating layer is greater than the bonding force between the third dam structure and the second insulating layer.

[0012] Optionally, in the thickness direction of the substrate, the cross-section of the groove is an inverted trapezoid, the bottom width of the groove is 0.5um-1um, the top width of the groove is 1um-2um, and the height of the groove is 0.5um-1.5um.

[0013] Optionally, the display substrate includes a plurality of grooves, wherein the grooves are arranged in the display area of ​​the display substrate, corresponding one-to-one to the thin film transistors, and the grooves are arranged around the corresponding thin film transistors; or, the grooves are arranged in the non-display area of ​​the display substrate, surrounding the display area of ​​the display substrate; or, the grooves are arranged on both sides of the display substrate and are located in the length direction of the metal layer.

[0014] The embodiment of the present application further discloses a display panel, which includes the display substrate as described above.

[0015] The beneficial effect of the embodiment of the present application is that since external water vapor or free ions will penetrate from the joint between the film layers in the display substrate, the metal layer and the semiconductor layer in the thin film transistor are invaded by harmful substances such as water vapor or free ions, thereby affecting the device characteristics of the thin film transistor. The embodiment of the present application adds a groove that penetrates the first insulating layer and the second insulating layer in the display substrate, and fills the third insulating layer in the groove, so that the external water vapor or free ions and other harmful substances invade from the joint between the third insulating layer and the second insulating layer, or from the joint between the second insulating layer and the first insulating layer. Since the harmful substances cannot penetrate the film layer, the harmful substances can only invade around the surface of the third insulating layer in the groove toward the third metal layer and the semiconductor layer, resulting in a longer invasion path of the harmful substances, thereby achieving the purpose of slowing down or even blocking the invasion and penetration of harmful substances such as water vapor or free ions into the metal layer and the semiconductor layer in the thin film transistor, thereby ensuring the device characteristics of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0017] Figure 1 is a schematic diagram of a display panel provided in an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of a display substrate provided in an embodiment of the present application;

[0019] Figure 3 is a schematic diagram of a display substrate provided in one implementation manner of an embodiment of the present application;

[0020] Figure 4 is a schematic diagram of a display substrate provided in another embodiment of the present application;

[0021] Figure 5 is a schematic diagram of a display substrate provided in another embodiment of the present application;

[0022] Figure 6 is a schematic diagram of a display substrate provided in another embodiment of the present application;

[0023] Figure 7 is a schematic diagram of a display substrate based on a groove design provided in an embodiment of the present application;

[0024] Figure 8 is a schematic diagram of a display substrate based on a second insulating layer design provided in an embodiment of the present application;

[0025] Fig. 9 It is a process flow chart of a display substrate provided in an embodiment of the present application.

[0026] Among them, 10, display panel; 20, display substrate; 100, thin film transistor; 110, base; 120, gate; 130, first insulating layer; 140, semiconductor layer; 150, second insulating layer; 151, first insulating medium layer; 152, second insulating medium layer; 160, metal layer; 170, third insulating layer; 180, organic insulating layer; 190, pixel definition layer; 200, first dam structure; 300, second dam structure; 400, third dam structure; 500, fourth dam structure; 600, groove. DETAILED DESCRIPTION

[0027] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0028] In addition, unless otherwise clearly specified or limited, "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internally connected between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0029] like Figure 1As shown, an embodiment of the present application provides a display panel, and the display panel 10 may be a liquid crystal display panel (Liquid Crystal Display, LCD), or an organic light-emitting semiconductor display panel (Organic Electroluminescence Display, OLED) or other types of display panels. When the display panel 10 is a liquid crystal display panel, the liquid crystal display panel includes an array substrate and a color filter substrate that are relatively arranged, and a liquid crystal layer arranged between the array substrate and the color filter substrate. At this time, the display substrate 20 is an array substrate, and the display substrate 20 has pixel units arranged in an array, each pixel unit is connected to a corresponding thin film transistor, and the drain of the thin film transistor is connected to the pixel electrode of the pixel unit, and the pixel electrode of the corresponding pixel unit is energized through the thin film transistor; in some liquid crystal display panels, the display substrate 20 also has an integrated gate drive circuit (Gate on Array, GOA), and the GOA circuit also has multiple thin film transistors, and the thin film transistor acts as a switch to control the transmission of the scanning signal. As shown in FIG. Figure 2 As shown, when the display panel 10 is an organic light-emitting semiconductor display panel, the display substrate 20 includes pixel units arranged in an array and a cover plate located on the pixel units, each pixel unit is correspondingly provided with a plurality of thin film transistors, and the activation of the light-emitting unit is controlled by the plurality of thin film transistors.

[0030] The embodiment of the present application further provides a display substrate 20 , which can be used in a liquid crystal display panel, an organic light-emitting semiconductor display panel, or other types of display panels.

[0031] like Figure 2As shown, the display substrate 20 includes a base 110, a first insulating layer 130, a semiconductor layer 140, a second insulating layer 150, a metal layer 160 and a third insulating layer 170, wherein the first insulating layer 130 is disposed on the base 110, the semiconductor layer 140 is disposed on a side of the first insulating layer 130 away from the base 110, the second insulating layer 150 is disposed on a side of the semiconductor layer 140 away from the first insulating layer 130, and the metal layer 160 is disposed on a side of the second insulating layer 150 away from the semiconductor layer 140 on one side of the thin film transistor 100, and the third insulating layer 170 is arranged on the metal layer 160; wherein the semiconductor layer 140 and the metal layer 160 are partial structures of the thin film transistor 100 in the display substrate 20, and the display substrate 20 also includes at least one groove 600, the groove 600 is at least located on one side of the thin film transistor, and the groove 600 passes through the first insulating layer 130 and the second insulating layer 150, and the third insulating layer 170 is also filled in the groove 600, and is adhered to the substrate 110 in the groove 600.

[0032] Among them, the metal layer 160 is the source and drain, the semiconductor layer 140 can be composed of a metal oxide semiconductor, or can be composed of polycrystalline silicon or other types of semiconductor materials, and the source and drain are also connected to the semiconductor layer 140 through vias, respectively. The thin film transistor 100 also includes a gate 120, and the thin film transistor 100 can be a top gate structure or a bottom gate structure. When the thin film transistor 100 is a bottom gate structure, the gate 120 is arranged between the substrate 110 and the first insulating layer 130; when the thin film transistor 100 is a top gate structure, the gate 120 is arranged above the semiconductor layer 140.

[0033] Since external water vapor or free ions may penetrate from the joints between the film layers in the display substrate 20 , the metal layer 160 and the semiconductor layer 140 in the thin film transistor 100 may be invaded by harmful substances such as water vapor or free ions, thereby affecting the device characteristics of the thin film transistor 100 . In the embodiment of the present application, a groove 600 penetrating the first insulating layer 130 and the second insulating layer 150 is added to the display substrate 20, and the third insulating layer 170 is filled in the groove 600, so that harmful substances such as external water vapor or free ions invade from the bonding point between the third insulating layer 170 and the second insulating layer 150, or invade from the bonding point between the second insulating layer 150 and the first insulating layer 130. Since the harmful substances cannot penetrate the film layer, the harmful substances can only invade around the surface of the third insulating layer 170 in the groove 600 toward the third metal layer 160 and the semiconductor layer 140, resulting in a longer invasion path of the harmful substances, thereby achieving the purpose of slowing down or even blocking the invasion of harmful substances such as water vapor or free ions and penetrating into the metal layer 160 and the semiconductor layer 140 in the thin film transistor 100, thereby ensuring the device characteristics of the thin film transistor 100.

[0034] As an implementation method, Figure 3 As shown, the display substrate 20 also includes a first dam structure 200, which is arranged between the second insulating layer 150 and the third insulating layer 170, adjacent to the groove 600, and located on the side of the groove 600 away from the metal layer 160, that is, located on the outside of the groove 600; wherein the first dam structure 200 is composed of insulating material, and the bonding force between the first dam structure 200 and the second insulating layer 150 is greater than the bonding force between the first dam structure 200 and the third insulating layer 170.

[0035] Figure 3 The direction of the arrow in the figure represents the route of harmful substances such as water vapor or free ions invading from the joint between the third insulating layer 170 and the second insulating layer 150 toward the metal layer 160. It can be seen from the figure that due to the existence of the first dam structure 200 and the large bonding force between the first dam structure 200 and the second insulating layer 150, the harmful substances invading from the joint between the third insulating layer 170 and the second insulating layer 150 toward the metal layer 160 can only invade along the two sides and the top of the first dam structure 200, but cannot invade from the joint between the first dam structure 200 and the second insulating layer 150, thereby increasing the invasion path of harmful substances. This embodiment combines the two designs of the first dam structure 200 and the groove 600 to greatly slow down or even block the invasion and penetration of harmful substances such as water vapor or free ions into the source and drain of the thin film transistor 100.

[0036] In this embodiment, the material of the first dam structure 200 is the same as that of the second insulating layer 150, and is different from that of the third insulating layer 170. For example, the materials of the first dam structure 200 and the second insulating layer 150 are both silicon oxide, while the material of the third insulating layer 170 is silicon nitride or aluminum oxide; through the above design, since the adsorption effect between the same materials is better, the bonding force between the first dam structure 200 and the second insulating layer 150 is greater than the bonding force between the first dam structure 200 and the third insulating layer 170.

[0037] Alternatively, in this embodiment, the rate of forming the first dam structure 200 is higher than the rate of forming the third insulating layer 170. Since the slower the film forming rate during the film formation, the higher the density of the film layer, and the better the contact effect with the underlying film layer, through the above design, the bonding force between the first dam structure 200 and the second insulating layer 150 is higher than the bonding force between the first dam structure 200 and the third insulating layer 170.

[0038] Of course, this embodiment can also simultaneously satisfy that the material of the first dam structure 200 is the same as the material of the second insulating layer 150, and different from the material of the third insulating layer 170; and the rate of film formation of the first dam structure 200 is higher than the rate of film formation of the third insulating layer 170, so as to further improve the bonding force between the first dam structure 200 and the second insulating layer 150.

[0039] In this embodiment, the area of ​​the first dam structure 200 that is in contact with the second insulating layer 150 is larger than the area of ​​the first dam structure 200 that is in contact with the third insulating layer 170. This facilitates process design, and on the other hand, the upslope and downslope terrain on the side of the first dam structure 200 is used to guide harmful substances such as water vapor or free ions to prevent the harmful substances from accumulating at the bottom of the first dam structure 200, resulting in excessive accumulation of harmful substances, thereby breaking the bonding force between the first dam structure 200 and the second insulating layer 150.

[0040] In this embodiment, in the thickness direction of the substrate 110, the cross section of the first dam structure 200 is a trapezoid, the width of the first dam structure 200 on the side in contact with the second insulating layer 150 is 2.8-3.2um, the width of the first dam structure 200 on the side in contact with the third insulating layer 170 is 1.5-2.5um, and the height of the first dam structure 200 is 0.5-0.8um. ​​Through the above design, after the first dam structure 200 is added to the display substrate 20, while avoiding increasing the overall thickness of the display substrate 20, the first dam structure 200 can also ensure the blocking effect of harmful substances such as water vapor or free ions.

[0041] In other embodiments, the first dam structure 200 may not be a trapezoid, but a triangle or a polygon; and the area of ​​the first dam structure 200 that is in contact with the second insulating layer 150 may be smaller than or equal to the area of ​​the first dam structure 200 that is in contact with the third insulating layer 170. The first dam structure 200 can block harmful substances such as water vapor or free ions by adopting these designs.

[0042] Of course, in other embodiments, the first dam structure 200 may also be disposed between the metal layer 160 and the trench 600 , and located inside the trench 600 .

[0043] As another embodiment, Figure 4 As shown, this embodiment Figure 3 On the basis of the implementation method, a second dam structure 300 is additionally provided, and the second dam structure 300 is also arranged between the second insulating layer 150 and the third insulating layer 170, and the first dam structure 200 and the second dam structure 300 are respectively located on both sides of the groove 600; and, like the first dam structure 200, the bonding force between the second dam structure 300 and the second insulating layer 150 is greater than the bonding force between the second dam structure 300 and the third insulating layer 170.

[0044] In this embodiment, by adding the second dam structure 300 , the invasion path of harmful substances such as water vapor or free ions is further prolonged, thereby effectively protecting the source and drain structures.

[0045] In this embodiment, the first dam structure 200 and the second dam structure 300 are formed by the same process. The shape and process design of the second dam structure 300 can be specifically referred to the description of the first dam structure 200 in the previous embodiment, and will not be repeated here.

[0046] As another embodiment, Figure 5 As shown, the display substrate 20 also includes a third dam structure 400, which is located between the first insulating layer 130 and the second insulating layer 150, and is arranged in parallel with the semiconductor layer 140, and the third dam structure 400 is also located between the semiconductor layer 140 and the groove 600, that is, located on the inner side of the groove 600; wherein the third dam structure 400 is composed of an insulating material, and the bonding force between the third dam structure 400 and the first insulating layer 130 is greater than the bonding force between the third dam structure 400 and the second insulating layer 150.

[0047] In this embodiment, a third dam structure 400 is provided between the first insulating layer 130 and the second insulating layer 150. Due to the existence of the third dam structure 400 and the greater bonding force between the third dam structure 400 and the first insulating layer 130, harmful substances invading the semiconductor layer 140 from the joint between the first insulating layer 130 and the second insulating layer 150 can only invade along the two sides and the top of the third dam structure 400, but cannot invade from the joint between the first dam structure 200 and the first insulating layer 130, thereby increasing the invasion path of harmful substances. In this embodiment, the combination of the third dam structure 400 and the groove 600 greatly slows down or even blocks the invasion and penetration of harmful substances such as water vapor or free ions into the active layer in the thin film transistor 100.

[0048] In some embodiments, the third dam structure 400 may also be located outside the trench 600 .

[0049] It should be noted that this embodiment is based on Figure 4 On the basis of the corresponding embodiment, a third dam structure 400 is further added, so that the semiconductor layer 140 and the source and drain of the thin film transistor 100 each have a multi-layer protection structure.

[0050] Of course, in some embodiments, the display substrate 20 may only have the third dam structure 400 without the first dam structure 200 and the second dam structure 300; or, the display substrate 20 may only have the third dam structure 400 and the first dam structure 200; or, the display substrate 20 may only have the third dam structure 400 and the second dam structure 300.

[0051] As another embodiment, Figure 6 As shown, the display substrate 20 is a bottom gate structure, the gate 120 is located between the substrate 110 and the first insulating layer 130, and the display substrate 20 also includes a fourth dam structure 500, the fourth dam structure 500 is located between the substrate 110 and the first insulating layer 130, and is arranged in parallel with the gate 120, and the fourth dam structure 500 is also located between the gate 120 and the groove 600, and is located on the inner side of the groove 600; wherein the bonding force between the fourth dam structure 500 and the substrate 110 is greater than the bonding force between the fourth dam structure 500 and the first insulating layer 130.

[0052] In this embodiment, a fourth dam structure 500 is provided between the substrate 110 and the first insulating layer 130. Due to the existence of the fourth dam structure 500 and the large bonding force between the fourth dam structure 500 and the substrate 110, harmful substances invading the gate 120 from the joint between the substrate 110 layer and the first insulating layer 130 can only invade along the two sides and the top of the fourth dam structure 500, but cannot invade from the joint between the first dam structure 200 and the first substrate 110, thereby increasing the invasion path of harmful substances. This embodiment combines the fourth dam structure 500 and the groove 600 to greatly slow down or even block the invasion and penetration of harmful substances such as water vapor or free ions into the gate 120 in the thin film transistor 100.

[0053] In this embodiment, the substrate 110 is made of glass, and the fourth dam structure 500 and the substrate 110 are an integrated structure.

[0054] In some embodiments, the fourth dam structure 500 may also be located outside the trench 600 .

[0055] like Figure 7 As shown, in some embodiments, in the thickness direction of the substrate 110, the cross section of the groove 600 is an inverted trapezoid. Compared with the solution of making the groove 600 into a rectangle, the inverted trapezoid has inclined surfaces on both sides, so the path for harmful substances such as external water vapor or free ions to invade the inside of the thin film transistor 100 along the side of the inverted trapezoid is longer. Specifically, the bottom width of the groove 600 is 0.5-1um, the top width of the groove 600 is 1-2um, and the height of the groove 600 is 0.5-1.5um.

[0056] like Figure 8 As shown, in some embodiments, the second insulating layer 150 includes a first insulating dielectric layer 151 and a second insulating dielectric layer 152, the first insulating dielectric layer 151 is arranged on a side of the semiconductor layer 140 away from the first insulating layer 130, and the second insulating dielectric layer 152 is arranged on a side of the first insulating dielectric layer 151 away from the semiconductor layer 140; and, after the first insulating dielectric layer 151 is deposited by chemical vapor deposition, it is annealed at a temperature of 300-450°C and an annealing time of 45-75 minutes. This design promotes the movement and coupling of ions and defects inside the first insulating dielectric layer 151, promotes the volatilization of excess elements, and reduces surface defects.

[0057] In some embodiments, the display substrate 20 includes a plurality of grooves 600, which are annular in shape. The grooves 600 are arranged in the display area of ​​the display substrate 20, corresponding one to the thin film transistors 100, and the grooves 600 are arranged around the corresponding thin film transistors 100 to block harmful substances such as water vapor or free ions from all directions; at the same time, the first dam structure 200, the second dam structure 300, the third dam structure 400 and the fourth dam structure 500 can also be annular structures, which are arranged around the corresponding thin film transistors 100 to enhance the blocking effect of each thin film transistor on harmful substances such as water vapor or free ions.

[0058] In some embodiments, the grooves 600 are disposed on both sides of the display substrate 20 and in the length direction of the metal layer 160 to prevent harmful substances such as external water vapor or free ions from invading from the end of the metal layer 160. At the same time, the first dam structure 200, the second dam structure 300, the third dam structure 400 and the fourth dam structure 500 can also be disposed only in the extension direction of the metal layer 160.

[0059] In some embodiments, the groove 600 is located in the non-display area of ​​the display substrate 20. The groove 600 may be one or more than one groove 600, which are arranged to surround the display area of ​​the entire display substrate 20. Meanwhile, the first dam structure 200, the second dam structure 300, the third dam structure 400 and the fourth dam structure 500 are also arranged to surround the display area of ​​the display panel 10.

[0060] In some embodiments, the groove 600 is located in the non-display area of ​​the display substrate 20 and surrounds the entire GOA circuit. Meanwhile, the first dam structure 200 , the second dam structure 300 , the third dam structure 400 and the fourth dam structure 500 also surround the GOA circuit of the display substrate 20 .

[0061] like Fig. 9 As shown, the embodiment of the present application further provides a specific process technology of the above-mentioned display substrate 20, taking the display substrate 20 as a bottom gate structure, and the display substrate 20 only having the first dam structure 200 and the second dam structure 300 as an example, the specific steps are as follows:

[0062] A bottom gate electrode layer is deposited on a glass substrate by magnetron sputtering. The bottom gate electrode layer can be set to a single layer, double layer, or multi-layer metal alloy or a single metal or a conductive oxide element, including but not limited to Cu, Mo, Al, Ti, Nb, Mg, Co, W, In and other materials; then the bottom gate electrode layer is patterned by coating, exposure, development and etching (dry or wet etching) to obtain a gate 120.

[0063] After the gate 120 is manufactured, a first insulating layer 130 is formed on the surface of the gate 120 by chemical vapor deposition or atomic layer deposition. The first insulating layer 130 includes but is not limited to a film layer combination of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In the embodiment of the present application, the first insulating layer 130 is a composite film layer composed of at least two of the above-mentioned film layers, and the first insulating layer 130 close to the gate 120 is one of the two film layers of silicon nitride and silicon oxynitride, and the film layer away from the gate 120 is one of the two film layers of aluminum oxide and silicon oxide.

[0064] After the first insulating layer 130 is manufactured, an amorphous metal oxide semiconductor layer 140 is deposited on the surface of the first insulating layer 130 by magnetron sputtering. In the present embodiment, the metal oxide semiconductor material adopts a metal oxide material with certain semiconductor properties (the elements contained in the material include but are not limited to In, Ga, Zn, O and rare earth elements, and the In element content of the material is different from the monomer content of other metal elements) to achieve device characteristics with higher mobility; then an annealing process is performed, the annealing temperature is 260-450°C, the annealing time is 45-90min, and a patterned metal oxide semiconductor is formed by coating, exposure, development, wet etching, and peeling to obtain the semiconductor layer 140.

[0065] After the semiconductor layer 140 is completed, the first insulating dielectric layer 151 is deposited by chemical vapor deposition. The first insulating dielectric layer 151 includes but is not limited to one or more films of silicon oxide, aluminum oxide, and silicon nitride materials, and a layer close to the semiconductor layer 140 is one of the dense silicon oxide or aluminum oxide films. Then, annealing treatment is performed at an annealing temperature of 300-450°C and an annealing time of 45-75 minutes.

[0066] After the first insulating dielectric layer 151 is completed, the second insulating dielectric layer 152 is formed by chemical vapor deposition or atomic layer deposition. The second insulating dielectric layer 152 includes but is not limited to a film layer combination of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The second insulating dielectric layer 152 is a composite film layer composed of at least two of the above film layers, and a layer of the second insulating dielectric layer 152 close to the first insulating dielectric layer 151 is one of a silicon oxide or aluminum oxide film layer.

[0067] After the second insulating dielectric layer 152 is manufactured, an insulating layer is formed by chemical vapor deposition or atomic layer deposition. The insulating layer includes but is not limited to a film layer combination of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The insulating layer can be one of the above-mentioned film layers or a composite film layer composed of two or more. Then, a pattern is formed by coating, developing, etching, and stripping to form a first dam structure 200 and a second dam structure 300.

[0068] Then, the semiconductor layer 140 is perforated by coating, developing, etching, and stripping, and the perforations are made to the surface of the semiconductor layer 140. Then, an ion implantation device is used to implant doping into the semiconductor layer 140 exposed by the perforations. The process gas used includes but is not limited to BF 3 , Ar, He and other gases.

[0069] Then, the metal layer 160 is deposited by magnetron sputtering deposition. The metal layer 160 can use a single layer, double layer, or multi-layer single metal or alloy or conductive oxide (single metal and alloy elements include but are not limited to Cu, Mo, Al, Ti, Nb, Mg, Co, W, In, and O). If it is a double layer or multi-layer structure, the lower metal in the metal layer 160 is consistent with the gate 120 metal to reduce the potential difference caused by material differences. Then, the coating, development, and etching stripping are performed to pattern the source and drain.

[0070] Then, holes are punched to the substrate 110 to form a patterned groove 600 structure, so that the path of water vapor and free ions is extended. The number of grooves 600 is not limited, and can be single or multiple. The groove 600 is an inverted trapezoidal structure with a bottom width of 0.5-1 μm, a top width of 1-2 μm, and a height of 0.5-1.5 μm, or a double trapezoidal stacked structure.

[0071] Next, a third insulating layer 170 is deposited by chemical vapor deposition. The third insulating layer 170 includes but is not limited to a thin film of silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, and may be a composite layer of the above-mentioned multiple film layers.

[0072] Subsequently, an organic insulating layer 180 is formed on the third insulating layer 170 as needed, and a planarization process is performed, followed by coating, development and etching to form a perforated structure of the organic insulating layer 180 and the third insulating layer 170 .

[0073] Finally, a pixel definition layer 190 is formed by magnetron sputtering. The film material is a single layer, double layer, or multi-layer single metal or alloy or oxide (the single metal, alloy, or oxide elements include but are not limited to Cu, Mo, Al, Ti, Nb, Mg, Co, W, In, O, Zn, and Ga). The layer is then coated, developed, and etched for graphic processing. After an annealing treatment at a temperature of 200-280°C and a time of 25-45 minutes, the preparation of the display substrate 20 is completed.

[0074] Of course, the thin film transistor 100 may also use a polycrystalline high-mobility oxide semiconductor material as the semiconductor layer 140, or use a stacked metal semiconductor oxide material with different mobilities as the semiconductor layer 140, so as to ensure the stability of the device while maintaining the high mobility of the thin film transistor 100 device.

[0075] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A display substrate, characterized in that: include: substrate; A first insulating layer, disposed on the substrate; A semiconductor layer, disposed on a side of the first insulating layer away from the substrate; A second insulating layer is disposed on a side of the semiconductor layer away from the first insulating layer; A metal layer, disposed on a side of the second insulating layer away from the semiconductor layer; a third insulating layer, disposed on the metal layer; Among them, the semiconductor layer and the metal layer are partial structures of the thin film transistor in the display substrate, and the display substrate also includes at least one groove, the groove is located on at least one side of the thin film transistor, and the groove passes through the first insulating layer and the second insulating layer, and the third insulating layer is also filled in the groove and adheres to the substrate in the groove.

2. The display substrate according to claim 1, wherein: The display substrate further includes a first dam structure, which is disposed between the second insulating layer and the third insulating layer and adjacent to the groove; The first dam structure is made of insulating material, and the bonding force between the first dam structure and the second insulating layer is greater than the bonding force between the first dam structure and the third insulating layer.

3. The display substrate according to claim 2, wherein: The display substrate further includes a second dam structure, the second dam structure is disposed between the second insulating layer and the third insulating layer, and the groove is located between the first dam structure and the second dam structure; The first dam structure and the second dam structure are formed by the same process.

4. The display substrate according to claim 2, wherein: An area of ​​the first dam structure in contact with the second insulating layer is larger than an area of ​​the first dam structure in contact with the third insulating layer.

5. The display substrate according to claim 4, wherein: In the thickness direction of the substrate, the cross-section of the first dam structure is trapezoidal, the width of the side of the first dam structure that is in contact with the second insulating layer is 2.8um-3.2um, the width of the side of the first dam structure that is in contact with the third insulating layer is 1.5um-2.5um, and the height of the first dam structure is 0.5um-0.8um.

6. The display substrate according to claim 2, wherein: The material of the first dam structure is the same as the material of the second insulating layer, and different from the material of the third insulating layer; and / or The first dam structure is formed at a higher rate than the third insulating layer.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The display substrate also includes a third dam structure, which is located between the first insulating layer and the second insulating layer, arranged in parallel with the semiconductor layer, and the third dam structure is also located between the semiconductor layer and the groove; wherein the third dam structure is composed of an insulating material, and the bonding force between the third dam structure and the first insulating layer is greater than the bonding force between the third dam structure and the second insulating layer.

8. The display substrate according to claim 1, wherein: In the thickness direction of the substrate, the cross section of the groove is an inverted trapezoid, the bottom width of the groove is 0.5um-1um, the top width of the groove is 1um-2um, and the height of the groove is 0.5um-1.5um.

9. The display substrate according to claim 1, wherein: The display substrate comprises a plurality of grooves, the grooves are arranged in the display area of ​​the display substrate, corresponding to the thin film transistors one by one, and the grooves are arranged around the corresponding thin film transistors; or The groove is disposed in the non-display area of ​​the display substrate and surrounds the display area of ​​the display substrate; or The grooves are arranged on both sides of the display substrate and are located in the length direction of the metal layer.

10. A display panel, characterized in that: Comprising the display substrate as described in any one of claims 1-9.

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