Back contact cell with specific contact layer and preparation method thereof

Abstract

The present application provides a back-contact battery with a specific contact layer and a preparation method thereof. The back-contact battery with a specific contact layer includes a silicon wafer, a first semiconductor layer and a second semiconductor layer; the silicon wafer has a backlight surface and a light-receiving surface; the first semiconductor layer and the second semiconductor layer are alternately arranged on the backlight surface; the first semiconductor layer at least includes an N-type doped polysilicon layer, the N-type doped polysilicon layer includes a hydrogen-doped N-type polysilicon layer and a deuterium-doped N-type polysilicon layer, and the second semiconductor layer at least includes a P-type doped amorphous silicon layer, the P-type doped amorphous silicon layer includes a hydrogen-doped P-type amorphous silicon layer and a deuterium-doped P-type amorphous silicon layer. The present application can greatly improve the surface density and stability of the first semiconductor layer and the second semiconductor layer, prevent the surfaces of the two semiconductor layers from being naturally oxidized or corroded by the solution during the manufacturing process, thereby reducing the contact resistance between the first semiconductor layer and the second semiconductor layer and the transparent conductive layer, and improving the FF of the battery.

Description

Technical Field

[0001] The present application relates to the technical field of back contact batteries, and in particular to a back contact battery with a specific contact layer and a preparation method thereof. Background Art

[0002] The FF of a solar cell, namely Fill Factor, is an important parameter that describes the performance of a solar cell. It is one of the key indicators that determine the conversion efficiency of the cell. Currently, the FF of back-contact cells still needs to be improved.

[0003] FF is affected by many factors, and the size of contact resistance is one of the important factors. When the contact resistance is large, the current will be hindered when passing through the contact interface, causing the operating voltage of the solar cell to drop, which in turn affects its FF. Therefore, reducing the contact resistance is one of the effective ways to improve FF.

[0004] In the existing back-contact solar cell process, the first semiconductor layer and the second semiconductor layer usually include a hydrogen-doped silicon layer manufactured by the reaction of hydrogen and silane. However, under this conventional choice, the surface density and stability of the first semiconductor layer and the second semiconductor layer need to be improved. The surfaces of the two semiconductor layers are easily naturally oxidized or corroded by the solution during the process, which increases the contact resistance between the first semiconductor layer and the second semiconductor layer and the transparent conductive layer, and seriously reduces the FF of the battery. Summary of the invention

[0005] In view of this, the purpose of the present application is to provide a back contact battery with a specific contact layer and a preparation method thereof, so as to at least solve the problem of excessively high contact resistance between the first semiconductor layer and the second semiconductor layer and the transparent conductive layer in the prior art, thereby improving the FF of the battery.

[0006] In the first aspect, the present application provides a back-contact battery with a specific contact layer, including a silicon wafer, a first semiconductor layer and a second semiconductor layer; the silicon wafer has a backlight surface and a light-receiving surface; the first semiconductor layer and the second semiconductor layer are alternately arranged on the backlight surface; the first semiconductor layer at least includes an N-type doped polycrystalline silicon layer, the N-type doped polycrystalline silicon layer includes a hydrogen-doped N-type polycrystalline silicon layer and a deuterium-doped N-type polycrystalline silicon layer arranged in sequence, and the second semiconductor layer at least includes a P-type doped amorphous silicon layer, the P-type doped amorphous silicon layer includes a hydrogen-doped P-type amorphous silicon layer and a deuterium-doped P-type amorphous silicon layer arranged in sequence.

[0007] In some preferred embodiments of the present invention, the ratio of phosphorus doping concentration to deuterium doping concentration in the deuterium-doped N-type polysilicon layer is 1:1-200, and the ratio of boron doping concentration to deuterium doping concentration in the deuterium-doped P-type amorphous silicon layer is 1:5-900.

[0008] In some preferred embodiments of the present invention, the first semiconductor layer further comprises a tunneling silicon oxide layer, and the thickness of the tunneling silicon oxide layer is 1-2 nm.

[0009] In some preferred embodiments of the present invention, the total thickness of the N-type doped polysilicon layer is 80-150 nm, the thickness ratio of the hydrogen-doped N-type polysilicon layer to the deuterium-doped N-type polysilicon layer is 1:0.1-0.7; the thickness of the hydrogen-doped N-type polysilicon layer is 70-140 nm, and the hydrogen doping concentration is 1*10 20 -5*10 22 cm -3 , the phosphorus doping concentration is 1*10 19 -9*10 20 cm -3 The thickness of the deuterium-doped N-type polysilicon layer is 10-50nm, and the deuterium doping concentration of the deuterium-doped N-type polysilicon layer is 1*10 20 -5*10 22 cm -3 , the phosphorus doping concentration is 1*10 19 -9*10 20 cm -3 .

[0010] In some preferred embodiments of the present invention, the second semiconductor layer further comprises an intrinsic hydrogenated amorphous silicon layer, and the thickness of the intrinsic hydrogenated amorphous silicon layer is 3-9 nm.

[0011] In some preferred embodiments of the present invention, the total thickness of the P-type doped amorphous silicon layer is 8-15 nm, the thickness ratio of the hydrogen-doped P-type amorphous silicon layer to the deuterium-doped P-type amorphous silicon layer is 1:0.3-1; the thickness of the hydrogen-doped P-type amorphous silicon layer is 4-10.5 nm, and the hydrogen doping concentration is 3*10 20 -6*10 22 cm -3 , the boron doping concentration is 1*10 18 -7*10 19 cm -3 The thickness of the deuterium-doped P-type amorphous silicon layer is 2.4-7.5 nm, and the deuterium doping concentration of the deuterium-doped P-type amorphous silicon layer is 5*10 20 -9*10 22 cm -3 , the boron doping concentration is 1*10 18 -9*10 19 cm -3 .

[0012] In some preferred embodiments of the present invention, a second semiconductor opening region is provided between adjacent first semiconductor layers, and both ends of the second semiconductor layer located in the second semiconductor opening region extend toward the surface of the adjacent first semiconductor layer by a preset distance and overlap with it to form an overlapping region.

[0013] In some preferred embodiments of the present invention, the back-contact battery with a specific contact layer also includes a conductive film layer, which is laid on the first semiconductor layer and the second semiconductor layer. The thickness of the conductive film layer is 40-80nm. The material of the conductive film layer is an indium oxide-based film doped with one or a combination of tin, tungsten, titanium and zinc, or a zinc oxide-based film doped with one or a combination of aluminum and boron. The conductive film layer is provided with an insulating groove at the position of each overlapping area, and the width of the insulating groove is 20-100μm.

[0014] In some preferred embodiments of the present invention, the back-contact battery with a specific contact layer also includes a metal electrode, which is arranged in the first semiconductor opening region and the second semiconductor opening region; the first semiconductor opening region is arranged in a portion outside the overlapping region on the first semiconductor layer, and the width of the first semiconductor opening region is 150-350μm, and the width of the second semiconductor opening region is 400-600μm.

[0015] In some preferred embodiments of the present invention, the back-contact battery with a specific contact layer also includes a third semiconductor layer, which is laid on the light-receiving surface of the silicon wafer. The third semiconductor layer includes a passivation layer and an anti-reflection layer arranged in sequence, and the passivation layer is one or a combination of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, an oxide layer and a doped oxide layer; the anti-reflection layer is one or a combination of a silicon nitride layer, a silicon oxynitride layer and an oxide layer.

[0016] In a second aspect, the present application provides a method for preparing a back contact battery having a specific contact layer, comprising the following steps:

[0017] S1, provide double-sided polished silicon wafers;

[0018] S2. Depositing a first semiconductor layer and a mask layer on the backlight surface of the silicon wafer in sequence, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer arranged in sequence, and the N-type doped polysilicon layer comprises a hydrogen-doped N-type polysilicon layer and a deuterium-doped N-type polysilicon layer arranged in sequence;

[0019] S3, performing a first etching opening on the backlight surface obtained in S2 to form second semiconductor opening regions arranged at intervals;

[0020] S4, removing the first semiconductor layer remaining in the second semiconductor opening region by texturing, and forming a textured surface on the light-receiving surface of the silicon wafer and the second semiconductor opening region, and then removing the mask layer outside the second semiconductor opening region on the backlight side of the silicon wafer during the cleaning process of the textured surface;

[0021] S5, forming a passivation layer and an anti-reflection layer on the light-receiving surface of the silicon wafer;

[0022] S6, removing the wrap-around coating produced by the deposition on the backlight surface of the silicon wafer in S5 and cleaning the second semiconductor opening area again;

[0023] S7. Depositing a second semiconductor layer on the backlight side of the silicon wafer, the second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous silicon layer arranged in sequence, and the P-type doped amorphous silicon layer comprises a hydrogen-doped P-type amorphous silicon layer and a deuterium-doped P-type amorphous silicon layer arranged in sequence.

[0024] In some preferred embodiments of the present invention, in S2, the first semiconductor layer and the mask layer are sequentially deposited by PECVD and annealed in an annealing furnace at 800-950° C. for 30-90 min. The deposition temperature is 350-550° C. The specific deposition conditions are as follows:

[0025] Preferably, when depositing the hydrogen-doped N-type polysilicon layer, the gas flow rate of silane is 1000-3000sccm, the gas flow rate of phosphine is 1000-2500sccm, the gas flow rate of hydrogen is 3000-9000sccm, the pressure is 300-450 Pa, the power is 5-20KW, the time is 800-2500 seconds, and the composition of phosphine is 2-8% PH3 and 92-98% H2;

[0026] Preferably, when depositing the deuterium-doped N-type polysilicon layer, the gas flow rate of silane is 1000-3000sccm, the gas flow rate of phosphine is 1000-2500sccm, the gas flow rate of deuterium gas is 1000-9000sccm, the pressure is 300-450 Pa, the power is 5-20KW, the time is 300-1300 seconds, and the composition of phosphine is 2-8% PH3 and 92-98% H2;

[0027] Preferably, when depositing the tunneling silicon oxide layer, the gas flow rate of laughing gas is 8000-12000sccm, the pressure is 100-300 Pa, the power is 3-20KW, and the time is 20-100 seconds;

[0028] Preferably, when depositing the mask layer, the gas flow rate of silane is 1000-2000sccm, the gas flow rate of nitrogen is 2000-10000sccm, the pressure is 200-300 Pa, the power is 3-20KW, and the time is 300-800 seconds; wherein the mask layer is at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, and the thickness of the mask layer is 50-100nm.

[0029] In some preferred embodiments of the present invention, in S7, the second semiconductor layer is deposited by PECVD, and the specific deposition conditions are as follows:

[0030] Preferably, when depositing the hydrogen-doped P-type amorphous silicon layer, the gas flow rate of silane is 300-1000sccm, the gas flow rate of diborane or trimethylborane is 200-2000sccm, the gas flow rate of hydrogen is 1500-10000sccm, the temperature is 160-300°C, the gas pressure is 200-600pa, the power is 300-1500w, the time is 90-210 seconds, the composition of diborane is 2-8% B2H6 and 92-98% H2, and the composition of trimethylborane is 2-8% TMB and 92-98% H2;

[0031] Preferably, when depositing the deuterium-doped P-type amorphous silicon layer, the gas flow rate of silane is 300-1000 sccm, the gas flow rate of diborane or trimethylborane is 200-2000 sccm, the gas flow rate of deuterium gas is 1500-10000 sccm, the temperature is 160-300°C, the gas pressure is 200-600 Pa, the power is 300-1500 W, the time is 27-105 seconds, the composition of diborane is 2-8% B2H6 and 92-98% H2, and the composition of trimethylborane is 2-8% TMB and 92-98% H2;

[0032] Preferably, when depositing the intrinsic hydrogenated amorphous silicon layer, the gas flow rate of silane is 300-2000 sccm, the gas flow rate of hydrogen is 1500-10000 sccm, the temperature is 160-300° C., the gas pressure is 200-600 Pa, the power is 300-1500 W, and the time is 20-120 seconds.

[0033] In some preferred embodiments of the present invention, in S4, the texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%-5%, the mass percentage of the texturing additive is 0.5%-1%, the texturing time is 8-30 minutes, and the texturing temperature is 75°C-85°C;

[0034] In some preferred embodiments of the present invention, in S4, the cleaning solution is an HF solution, the mass percentage of HF acid is 0.5%-5%, the mass percentage of deionized water is 95%-99.5%, the processing temperature is 20°C-30°C, and the removal time is 60-500s.

[0035] In some preferred embodiments of the present invention, the method for preparing a back contact battery further comprises:

[0036] S8, performing a second etching opening on the second semiconductor layer to form first semiconductor opening regions that are alternately arranged with and spaced from the second semiconductor opening regions;

[0037] S9, depositing a conductive film layer on the backlit surface obtained in S8;

[0038] S10, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove;

[0039] S11 , forming metal electrodes in the first semiconductor opening region and the second semiconductor opening region respectively.

[0040] In some preferred embodiments of the present invention, the method for preparing a back contact battery further comprises at least one of the following methods:

[0041] Preferably, in S3, the first etching opening is performed by mask etching or laser, the laser is ultraviolet or green laser, and the pulse width is less than 10ns;

[0042] Preferably, in S6, the removal cleaning solution is an HF solution, the mass percentage of HF acid is 1%-10%, the mass percentage of deionized water is 90%-99%, the treatment temperature is 20°C-30°C, and the removal time is 30-500s;

[0043] Preferably, in S8, the second etching opening is performed by laser, the laser is ultraviolet or green laser, and the pulse width is less than 10ns;

[0044] Preferably, in S9, the conductive film layer is deposited by PVD or RPD;

[0045] Preferably, in S10, the third etching opening is performed by mask etching or laser etching, and the resistance between the first semiconductor layer and the second semiconductor layer after etching is greater than 1KΩ;

[0046] Preferably, in S11, the metal electrode is formed by using screen printing technology.

[0047] The beneficial effects that this application can achieve are:

[0048] 1. In the existing back contact solar cell process, the doping layer is usually a hydrogen-doped silicon layer made by the reaction of hydrogen and silane. However, the present application adopts the above technical solution, in particular, the first semiconductor layer at least includes an N-type doped polysilicon layer, the N-type doped polysilicon layer includes a hydrogen-doped N-type polysilicon layer and a deuterium-doped N-type polysilicon layer, and the second semiconductor layer at least includes a P-type doped amorphous silicon layer, the P-type doped amorphous silicon layer includes a hydrogen-doped P-type amorphous silicon layer and a deuterium-doped P-type amorphous silicon layer. The applicant creatively doped a certain proportion of deuterium gas into the first semiconductor outer layer and the second semiconductor outer layer respectively, so that the deuterium gas reacted with silane, replacing the conventional reaction of hydrogen and silane. The deuterium element replaced the original hydrogen element, so that the original unstable silicon-hydrogen bond formed a silicon-deuterium bond with good stability. Since the silicon-deuterium bond has a high bond energy, it is not easy to break and is not easily corroded by hydroxide or fluoride ions in the solution. Therefore, the film layer is not easy to oxidize, which greatly improves the surface density and stability of the first semiconductor layer and the second semiconductor layer, prevents the two semiconductor layers from naturally oxidizing or being corroded by the solution during the manufacturing process, thereby reducing the contact resistance between the first semiconductor layer and the second semiconductor layer and the transparent conductive layer, and improving the FF of the battery.

[0049] 2. Based on the above technical scheme, the preparation method of the present application can effectively control the thickness ratio between the hydrogen-doped N-type polysilicon layer and the deuterium-doped N-type polysilicon layer, and between the hydrogen-doped P-type amorphous silicon layer and the deuterium-doped P-type amorphous silicon layer by reasonably controlling the reaction conditions of the doping reaction, which is beneficial to taking into account both the stability of the film layer and the conductivity of the film layer; at the same time, it can also effectively control the deuterium doping concentration ratio in the deuterium-doped N-type polysilicon layer and the deuterium-doped P-type amorphous silicon layer, which is beneficial to taking into account both the oxidation resistance and conductivity of the two film layers, and is beneficial to improving the carrier transport performance of the two film layers and improving FF. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 A schematic structural diagram of a back contact battery with a specific contact layer of the present application is shown.

[0052] Description of reference numerals:

[0053] 1. Silicon wafer; 2. Tunneling silicon oxide layer; 3. N-type doped polysilicon layer; 3.1. Hydrogen-doped N-type polysilicon layer; 3.2. Deuterium-doped N-type polysilicon layer; 5. Passivation layer; 6. Anti-reflection layer; 7. Intrinsic hydrogenated amorphous silicon layer; 8. P-type doped amorphous silicon layer; 8.1. Hydrogen-doped P-type amorphous silicon layer; 8.2. Deuterium-doped P-type amorphous silicon layer; 9. Conductive film layer; 10. Metal electrode. DETAILED DESCRIPTION

[0054] The term "comprising" in the specification and claims of the present application and the drawings is synonymous with "including", "containing" or "characterized by", and is inclusive or open-ended, and does not exclude additional undescribed elements or method steps. "Comprising" is a technical term used in the claim language, meaning that the elements are present, but other elements may also be added and still form a structure or method within the scope of the claim.

[0055] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. The term "about" in this application means to include a small change (up to + / -10%) from the stated value.

[0056] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0057] In the present invention, the area close to the silicon substrate is referred to as the inner part, and the area far from the silicon substrate is referred to as the outer part.

[0058] In the first aspect, the present application provides a back-contact battery with a specific contact layer, including a silicon wafer, a first semiconductor layer and a second semiconductor layer; the silicon wafer has a backlight surface and a light-receiving surface; the first semiconductor layer and the second semiconductor layer are alternately arranged on the backlight surface; the first semiconductor layer at least includes an N-type doped polycrystalline silicon layer, the N-type doped polycrystalline silicon layer includes a hydrogen-doped N-type polycrystalline silicon layer and a deuterium-doped N-type polycrystalline silicon layer, and the second semiconductor layer at least includes a P-type doped amorphous silicon layer, the P-type doped amorphous silicon layer includes a hydrogen-doped P-type amorphous silicon layer and a deuterium-doped P-type amorphous silicon layer.

[0059] It should be noted that the P-type doped amorphous silicon layer can also be set as a silicon layer of other structures such as a P-type doped microcrystalline silicon layer, but it is preferably a P-type doped amorphous silicon layer because the amorphous silicon layer has excellent passivation effect, high carrier transmission efficiency and collection efficiency, and good interface contact effect. At the same time, it can be adapted to the PECVD process in the preparation method of the present application, has excellent process compatibility, low cost, high efficiency, and is easy for large-scale production.

[0060] In some preferred embodiments of the present invention, the ratio of the phosphorus doping concentration to the deuterium doping concentration of the deuterium-doped N-type polysilicon layer is 1:1-200, specifically 1:1, 1:10, 1:50, 1:100, 1:150, 1:200 and any value therebetween. The ratio of the boron doping concentration to the deuterium doping concentration in the deuterium-doped P-type amorphous silicon layer is 1:5-900, specifically 1:5, 1:50, 1:100, 1:300, 1:500, 1:700, 1:900 and any value therebetween. By controlling the deuterium doping concentration ratio in the deuterium-doped N-type polysilicon layer and the deuterium-doped P-type amorphous silicon layer, it is beneficial to take into account the antioxidant performance and conductive performance of the two film layers, improve the carrier transport performance of the two film layers, and improve FF.

[0061] In some preferred embodiments of the present invention, the first semiconductor layer also includes a tunneling silicon oxide layer having a thickness of 1-2 nm. The advantage of using the tunneling silicon oxide layer as the passivation layer of the first semiconductor layer in combination with the deuterium-doped layer is that it improves the passivation effect while improving the solution resistance stability of the film layer.

[0062] In some preferred embodiments of the present invention, the total thickness of the N-type doped polysilicon layer is 80-150 nm;

[0063] The thickness ratio of the hydrogen-doped N-type polysilicon layer to the deuterium-doped N-type polysilicon layer is 1:0.1-0.7, and can specifically be 1:0.1, 1:0.3, 1:0.5, 1:0.7 and any value therebetween.

[0064] The thickness of the hydrogen-doped N-type polysilicon layer is 70-140 nm, and can be 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, and any value therebetween.

[0065] The hydrogen doping concentration is 1*10 20 -5*10 22 cm -3 , which can be 1*10 20 cm -3 , 5*10 20 cm -3 , 1*10 21 cm -3, 5*10 21 cm -3 , 1*10 22 cm -3 , 5*10 22 cm -3 and any values ​​in between.

[0066] Phosphorus doping concentration is 1*10 19 -9*10 20 cm -3 ; Specifically, it can be 1*10 19 cm -3 , 5*10 19 cm -3 , 1*10 20 cm -3 , 5*10 20 cm -3 ,9*10 20 cm -3 and any values ​​in between.

[0067] The thickness of the deuterium-doped N-type polysilicon layer is 10-50 nm, and can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, and any value therebetween.

[0068] The deuterium doping concentration of the deuterium-doped N-type polysilicon layer is 1*10 20 -5*10 22 cm -3 , which can be 1*10 20 cm -3 , 5*10 20 cm -3 , 1*10 21 cm -3 , 5*10 21 cm -3 , 1*10 22 cm -3 , 5*10 22 cm -3 and any values ​​in between.

[0069] Phosphorus doping concentration is 1*10 19 -9*10 20 cm -3 Specifically, it can be 1*10 19 cm -3 , 5*10 19 cm -3 , 1*10 20 cm -3 , 5*10 20 cm -3 ,9*10 20 cm-3 and any values ​​in between.

[0070] The deuterium element replaces the original hydrogen element, so that the original unstable silicon-hydrogen bond forms a stable silicon-deuterium bond. Since the silicon-deuterium bond has a high bond energy, it is not easy to break and is not easily corroded by hydroxide or fluoride ions in the solution. Therefore, the film layer is not easy to oxidize. At the same time, controlling the thickness ratio between the hydrogen-doped N-type polysilicon layer and the deuterium-doped N-type polysilicon layer, and the doping concentrations of hydrogen and deuterium in the hydrogen-doped N-type polysilicon layer and the deuterium-doped N-type polysilicon layer is beneficial to improving the stability of the film layer and the conductivity of the film layer.

[0071] In some preferred embodiments of the present invention, the second semiconductor layer also includes an intrinsic hydrogenated amorphous silicon layer, and the thickness of the intrinsic hydrogenated amorphous silicon layer is 3-9nm; the advantage of using the intrinsic hydrogenated amorphous silicon layer as the passivation layer of the second semiconductor layer in combination with the deuterium-doped layer is that it improves the passivation effect of the film layer while improving the conductivity of the film layer.

[0072] In some preferred embodiments of the present invention, the total thickness of the P-type doped amorphous silicon layer is 8-15 nm.

[0073] The thickness ratio of the hydrogen-doped P-type amorphous silicon layer to the deuterium-doped P-type amorphous silicon layer is 1:0.3-1, and can specifically be 1:0.3, 1:0.5, 1:0.7, 1:1, and any value therebetween.

[0074] The thickness of the hydrogen-doped P-type amorphous silicon layer is 4-10.5 nm, and can be 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 10.5 nm and any value therebetween.

[0075] The hydrogen doping concentration is 3*10 20 -6*10 22 cm -3 , specifically 3*10 20 cm -3 , 6*10 20 cm -3 , 1*10 21 cm -3 , 3*10 21 cm -3 , 6*10 21 cm -3 , 1*10 22 cm -3 , 3*10 22 cm -3 , 6*10 22 cm -3 and any values ​​in between.

[0076] Boron doping concentration is 1*10 18 -7*1019 cm -3 , which can be 1*10 18 cm -3 , 5*10 18 cm -3 , 1*10 19 cm -3 ,7*10 19 cm -3 and any values ​​in between.

[0077] The thickness of the deuterium-doped P-type amorphous silicon layer is 2.4-7.5 nm, and can be 2.4 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 7.5 nm, and any value therebetween.

[0078] The deuterium doping concentration of the deuterium-doped P-type amorphous silicon layer is 5*10 20 -9*10 22 cm -3 , specifically it can be 5*10 20 cm -3 , 1*10 21 cm -3 , 5*10 21 cm -3 , 1*10 22 cm -3 , 5*10 22 cm -3 ,9*10 22 cm -3 and any values ​​in between.

[0079] Boron doping concentration is 1*10 18 -9*10 19 cm -3 , which can be 1*10 18 cm -3 , 5*10 18 cm -3 , 1*10 19 cm -3 , 5*10 19 cm -3 ,9*10 19 cm -3 and any values ​​in between.

[0080] The deuterium element replaces the original hydrogen element, so that the originally unstable silicon-hydrogen bond forms a stable silicon-deuterium bond. Since the silicon-deuterium bond has a high bond energy, it is not easy to break and is not easily corroded by hydroxide or fluoride ions in the solution. Therefore, the film layer is not easy to oxidize. At the same time, controlling the thickness ratio between the hydrogen-doped P-type polysilicon layer and the deuterium-doped P-type polysilicon layer, and the doping concentrations of hydrogen and deuterium in the hydrogen-doped P-type polysilicon layer and the deuterium-doped P-type polysilicon layer is beneficial to improving the stability of the film layer and the conductivity of the film layer.

[0081] In some preferred embodiments of the present invention, a second semiconductor opening region is provided between adjacent first semiconductor layers, and both ends of the second semiconductor layer located in the second semiconductor opening region extend toward the surface of the adjacent first semiconductor layer by a preset distance and overlap with it to form an overlapping region.

[0082] It should be noted that the stacking of the first semiconductor layer and the second semiconductor layer to form an overlapping region is only a preferred solution in the present application. The arrangement of the first semiconductor layer and the second semiconductor layer of the back contact battery of the present application also includes but is not limited to forming an interdigitated arrangement.

[0083] In some preferred embodiments of the present invention, the back-contact battery with a specific contact layer also includes a conductive film layer, which is laid on the first semiconductor layer and the second semiconductor layer. The thickness of the conductive film layer is 40-80nm. The material of the conductive film layer is an indium oxide-based film doped with one or a combination of tin, tungsten, titanium and zinc, or a zinc oxide-based film doped with one or a combination of aluminum and boron. The conductive film layer is provided with an insulating groove at the position of each overlapping area, and the width of the insulating groove is 20-100μm.

[0084] In some preferred embodiments of the present invention, the back contact battery with a specific contact layer further includes a metal electrode, which is disposed in the first semiconductor opening region and the second semiconductor opening region; the first semiconductor opening region is disposed in a portion outside the overlapping region on the first semiconductor layer, the width of the first semiconductor opening region is 150-350 μm, and the width of the second semiconductor opening region is 400-600 μm. Specifically, the first semiconductor opening region is formed by the gap between two adjacent second semiconductor layers and the bottom surface of the first semiconductor layer, and is located between the two adjacent overlapping regions.

[0085] In some preferred embodiments of the present invention, the back contact cell with a specific contact layer further includes a third semiconductor layer, which is laid on the light-receiving surface of the silicon wafer. The third semiconductor layer includes a passivation layer and an anti-reflection layer arranged in sequence, and the passivation layer is one or a combination of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, an oxide layer, and a doped oxide layer; the anti-reflection layer is one or a combination of a silicon nitride layer, a silicon oxynitride layer, and an oxide layer. Reasonable arrangement of the passivation layer and the anti-reflection layer on the light-receiving surface of the silicon wafer can significantly improve the photoelectric conversion efficiency and stability of the solar cell. The passivation layer can reduce the recombination rate of photogenerated carriers, improve the stability and reliability of the silicon wafer, and thus extend the service life of the battery. The anti-reflection layer can reduce the reflection loss of light, improve the absorption rate and penetration rate of light, so that more light can enter the silicon wafer and be converted into electrical energy, thereby improving the conversion efficiency of the battery.

[0086] In a second aspect, the present application provides a method for preparing a back contact battery having a specific contact layer, comprising the following steps:

[0087] S1, provide double-sided polished silicon wafers;

[0088] S2. Depositing a first semiconductor layer and a mask layer on the backlight side of the silicon wafer, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer, and the N-type doped polysilicon layer comprises a hydrogen-doped N-type polysilicon layer and a deuterium-doped N-type polysilicon layer;

[0089] S3, performing a first etching opening on the backlight surface obtained in S2 to form second semiconductor opening regions arranged at intervals;

[0090] S4, removing the first semiconductor layer remaining in the second semiconductor opening region by texturing, and forming a textured surface on the light-receiving surface of the silicon wafer and the second semiconductor opening region, and then removing the mask layer outside the second semiconductor opening region on the backlight side of the silicon wafer during the cleaning process of the textured surface;

[0091] S5, forming a passivation layer and an anti-reflection layer on the light-receiving surface of the silicon wafer;

[0092] S6, removing the wrap-around coating produced by the deposition on the backlight surface of the silicon wafer in S5 and cleaning the second semiconductor opening area again;

[0093] S7. Depositing a second semiconductor layer on the backlight side of the silicon wafer, wherein the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous silicon layer, wherein the P-type doped amorphous silicon layer includes a hydrogen-doped P-type amorphous silicon layer and a deuterium-doped P-type amorphous silicon layer.

[0094] In some preferred embodiments of the present invention, in S2, the first semiconductor layer and the mask layer are sequentially deposited by PECVD and annealed in an annealing furnace at 800-950°C for 30-90 min, and the deposition temperature is 350-550°C;

[0095] Preferably, when depositing the hydrogen-doped N-type polysilicon layer, the gas flow rate of silane is 1000-3000 sccm, specifically 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm, 3000 sccm and any value therebetween.

[0096] The gas flow rate of phosphine is 1000-2500 sccm, and specifically can be 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm and any value therebetween.

[0097] The gas flow rate of hydrogen is 3000-9000 sccm, specifically 3000 sccm, 5000 sccm, 7000 sccm, 9000 sccm and any value therebetween.

[0098] The pressure is 300-450 Pa, the power is 5-20KW, and the time is 800-2500 seconds, specifically 800s, 1300s, 1800s, 2300s, 2500s and any value therebetween.

[0099] The composition of phosphine is 2-8% PH3 and 92-98% H2; the advantage of using the above pressure and power is that the doping concentration and film uniformity can be better controlled.

[0100] Preferably, when depositing the deuterium-doped N-type polysilicon layer, the gas flow rate of silane is 1000-3000 sccm, specifically 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm, 3000 sccm and any value therebetween.

[0101] The gas flow rate of phosphine is 1000-2500 sccm, and specifically can be 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm and any value therebetween.

[0102] The gas flow rate of deuterium gas is 1000-9000 sccm, and specifically can be 1000 sccm, 3000 sccm, 5000 sccm, 7000 sccm, 9000 sccm and any value therebetween.

[0103] The pressure is 300-450 Pa, the power is 5-20KW, and the time is 300-1300 seconds, specifically 300s, 400s, 500s, 600s, 700s, 800s, 900s, 1000s, 1100s, 1200s, 1300s and any value therebetween.

[0104] The composition of phosphine is 2-8% PH3 and 92-98% H2; the advantage of using the above pressure and power is that the doping concentration and film density can be better controlled.

[0105] Preferably, when depositing the tunneling silicon oxide layer, the gas flow rate of nitrous oxide is 8000-12000 sccm, the pressure is 100-300 Pa, the power is 3-20 KW, and the time is 20-100 seconds.

[0106] Preferably, when depositing the mask layer, the gas flow rate of silane is 1000-2000sccm, the gas flow rate of nitrogen is 2000-10000sccm, the pressure is 200-300 Pa, the power is 3-20KW, and the time is 300-800 seconds; wherein the mask layer is at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, and the thickness of the mask layer is 50-100nm.

[0107] Reasonable control of deposition conditions can adjust the thickness of the tunneling silicon oxide layer, improve the passivation level, and be more conducive to improving the conversion efficiency of the battery; the thickness of the mask layer can be adjusted to effectively protect the first semiconductor layer; the thickness ratio between the hydrogen-doped N-type polysilicon layer and the deuterium-doped N-type polysilicon layer can be effectively controlled, which is beneficial to taking into account both the stability of the film layer and the conductivity of the film layer; at the same time, the deuterium doping concentration ratio in the deuterium-doped N-type polysilicon layer can also be effectively controlled, which is beneficial to taking into account both the anti-oxidation performance and the conductivity of the film layer, and is beneficial to improving the carrier transport performance of the film layer and improving FF.

[0108] In some preferred embodiments of the present invention, in S7, the second semiconductor layer is deposited by PECVD;

[0109] Preferably, when depositing the hydrogen-doped P-type amorphous silicon layer, the gas flow rate of silane is 300-1000 sccm, specifically 300 sccm, 500 sccm, 700 sccm, 1000 sccm and any value therebetween.

[0110] The gas flow rate of diborane or trimethylborane is 200-2000 sccm, and specifically can be 200 sccm, 500 sccm, 1000 sccm, 1500 sccm, 2000 sccm and any value therebetween.

[0111] The gas flow rate of hydrogen is 1500-10000 sccm, specifically 1500 sccm, 3000 sccm, 4500 sccm, 6000 sccm, 7500 sccm, 10000 sccm and any value therebetween.

[0112] The temperature is 160-300°C, the air pressure is 200-600 Pa, the power is 300-1500 W, and the time is 90-210 seconds, specifically 90s, 120s, 150s, 180s, 210s and any value therebetween.

[0113] The composition of diborane is 2-8% B2H6 and 92-98% H2, and the composition of trimethylborane is 2-8% TMB and 92-98% H2; the advantage of using the above pressure and power is that the doping concentration and film uniformity can be better controlled.

[0114] Preferably, when depositing the deuterium-doped P-type amorphous silicon layer, the gas flow rate of silane is 300-1000 sccm, specifically 300 sccm, 500 sccm, 700 sccm, 1000 sccm and any value therebetween.

[0115] The gas flow rate of diborane or trimethylborane is 200-2000 sccm, and specifically can be 200 sccm, 500 sccm, 1000 sccm, 1500 sccm, 2000 sccm and any value therebetween.

[0116] The gas flow rate of deuterium gas is 1500-10000 sccm, specifically 1500 sccm, 3000 sccm, 4500 sccm, 6000 sccm, 7500 sccm, 10000 sccm and any value therebetween.

[0117] The temperature is 160-300°C, the air pressure is 200-600 Pa, the power is 300-1500 W, and the time is 27-105 seconds, specifically 27 seconds, 50 seconds, 80 seconds, 105 seconds, and any value therebetween.

[0118] The composition of diborane is 2-8% B2H6 and 92-98% H2, and the composition of trimethylborane is 2-8% TMB and 92-98H2; the advantage of using the above pressure and power is that the doping concentration and film density can be better controlled.

[0119] Preferably, when depositing the intrinsic hydrogenated amorphous silicon layer, the gas flow rate of silane is 300-2000 sccm, the gas flow rate of hydrogen is 1500-10000 sccm, the temperature is 160-300° C., the gas pressure is 200-600 Pa, the power is 300-1500 W, and the time is 20-120 seconds.

[0120] Reasonable control of deposition conditions can adjust the thickness of the intrinsic hydrogenated amorphous silicon layer, improve the passivation level, and be more conducive to improving the conversion efficiency of the battery; the thickness ratio between the hydrogen-doped P-type amorphous silicon layer and the deuterium-doped P-type amorphous silicon layer can be effectively controlled, which is beneficial to taking into account both the stability of the film layer and the conductivity of the film layer; at the same time, the deuterium doping concentration ratio in the deuterium-doped P-type amorphous silicon layer can also be effectively controlled, which is beneficial to taking into account both the anti-oxidation performance and the conductivity of the film layer, and is beneficial to improving the carrier transport performance of the film layer and improving FF.

[0121] In some preferred embodiments of the present invention, in S4, the texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%-5%, the mass percentage of the texturing additive is 0.5%-1%, the texturing time is 8-30 minutes, and the texturing temperature is 75°C-85°C; reasonable setting of the texturing conditions can optimize the light trapping performance and improve the battery efficiency.

[0122] In some preferred embodiments of the present invention, in S4, the cleaning solution is an HF solution, the mass percentage of HF acid is 0.5%-5%, the mass percentage of deionized water is 95%-99.5%, the processing temperature is 20°C-30°C, and the removal time is 60-500s. Reasonable setting of cleaning conditions can remove organic matter, particulate matter, metal ions and other impurities on the surface of the silicon wafer, reduce the recombination loss of carriers at the junction interface, and thus improve the quality of the battery.

[0123] In some preferred embodiments of the present invention, the method for preparing a back contact battery further comprises:

[0124] S8, performing a second etching opening on the second semiconductor layer to form first semiconductor opening regions that are alternately arranged with and spaced from the second semiconductor opening regions;

[0125] S9, depositing a conductive film layer on the backlit surface obtained in S8;

[0126] S10, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove;

[0127] S11 , forming metal electrodes in the first semiconductor opening region and the second semiconductor opening region respectively.

[0128] In some preferred embodiments of the present invention, the method for preparing a back contact battery further comprises at least one of the following methods:

[0129] Preferably, in S3, the first etching opening can be performed by laser or mask etching, as long as the second semiconductor opening region can be formed. The laser is ultraviolet or green laser, and the pulse width is less than 10ns;

[0130] Preferably, in S6, the removal cleaning solution is an HF solution, the mass percentage of HF acid is 1%-10%, the mass percentage of deionized water is 90%-99%, the treatment temperature is 20°C-30°C, and the removal time is 30-500s;

[0131] Preferably, in S8, the second etching opening can be performed by laser, as long as the first semiconductor opening region can be formed. The laser is ultraviolet or green laser, and the pulse width is less than 10ns;

[0132] Preferably, in S9, the conductive film layer is deposited by physical vapor deposition (PVD) or activated plasma deposition (RPD);

[0133] Preferably, in S10, the third etching opening is performed by mask etching or laser etching, as long as an insulating groove can be formed. After etching, the resistance between the first semiconductor layer and the second semiconductor layer is greater than 1KΩ;

[0134] Preferably, in S11, a screen printing technique is used to form the metal electrode, and the metal electrode is located in the first semiconductor opening region and the second semiconductor opening region.

[0135] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0136] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0137] Example 1

[0138] like Figure 1 As shown, a back contact battery with a specific contact layer is prepared by the following manufacturing method:

[0139] S1, provide double-sided polished silicon wafer 1:

[0140] Double-sided polishing and cleaning of N-type single crystal silicon wafers.

[0141] S2. Depositing a first semiconductor layer and a mask layer on the backlit surface of the silicon wafer 1, the first semiconductor layer comprises a tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 3, and the N-type doped polysilicon layer 3 comprises a hydrogen-doped N-type polysilicon layer 3.1 and a deuterium-doped N-type polysilicon layer 3.2:

[0142] The thickness of the tunneling silicon oxide layer 2 is 1.2 nm; the total thickness of the N-type doped polysilicon layer 3 is 120 nm, the thickness ratio of the hydrogen-doped N-type polysilicon layer 3.1 to the deuterium-doped N-type polysilicon layer 3.2 is 1:0.41; the thickness of the hydrogen-doped N-type polysilicon layer 3.1 is 85 nm, and the hydrogen doping concentration is 3*10 21 cm -3 , the phosphorus doping concentration is 2*10 20 cm -3 The thickness of the deuterium-doped N-type polysilicon layer 3.2 is 35 nm, and the deuterium doping concentration of the deuterium-doped N-type polysilicon layer 3.2 is 3*10 22 cm -3 , the phosphorus doping concentration is 3*10 20 cm -3 , the thickness of the mask layer is 70nm.

[0143] The ratio of the phosphorus doping concentration to the deuterium doping concentration of the deuterium-doped N-type polysilicon layer 3.2 is 1:100.

[0144] The first semiconductor layer and the mask layer are formed by sequentially depositing by PECVD and annealing in an annealing furnace at 910°C for 80 minutes. The deposition temperature is 450°C.

[0145] When depositing the hydrogen-doped N-type polysilicon layer 3.1, the gas flow rate of silane is 1800 sccm, the gas flow rate of phosphine is 1600 sccm, the gas flow rate of hydrogen is 4500 sccm, the pressure is 350 Pa, the power is 8 KW, the time is 1900 seconds, and the composition of phosphine is 2% PH3 and 98% H2;

[0146] When the deuterium-doped N-type polysilicon layer 3.2 is deposited, the gas flow rate of silane is 1800 sccm, the gas flow rate of phosphine is 1800 sccm, the gas flow rate of deuterium gas is 6000 sccm, the pressure is 400 Pa, the power is 10.2 KW, and the time is 850 seconds; the composition of phosphine is 2% PH3 and 98% H2;

[0147] When depositing the tunneling silicon oxide layer 2, the gas flow rate of nitrous oxide is 9000 sccm, the pressure is 230 Pa, the power is 8 kW, and the time is 45 seconds;

[0148] When depositing the mask layer, the gas flow rate of silane is 1200 sccm, the gas flow rate of nitrogen is 6800 sccm, the pressure is 250 Pa, the power is 10.5 KW, and the time is 530 seconds.

[0149] S3, performing a first etching opening on the backlight surface obtained in S2 to form second semiconductor opening regions arranged at intervals;

[0150] The width W2 of the second semiconductor opening region is 540 μm.

[0151] S4, removing the first semiconductor layer remaining in the second semiconductor opening region by texturing, and forming a textured surface on the light-receiving surface of the silicon wafer and the second semiconductor opening region, and then removing the mask layer outside the second semiconductor opening region on the backlight side of the silicon wafer during the cleaning process of the textured surface;

[0152] The texturing liquid is a mixture of potassium hydroxide, texturing additives and water, in which the mass percentage of potassium hydroxide is 4% and the mass percentage of texturing additives is 0.8%. The texturing time is 12 minutes and the texturing temperature is 80°C;

[0153] The cleaning solution is HF solution, the mass percentage of HF acid is 2%, the mass percentage of deionized water is 98%, the processing temperature is 25°C, and the removal time is 120s;

[0154] S5, forming a passivation layer 5 and an anti-reflection layer 6 on the light-receiving surface of the silicon wafer 1:

[0155] The passivation layer 5 is an intrinsic amorphous silicon layer, and the anti-reflection layer 6 is a silicon nitride layer.

[0156] S6, removing the plating layer deposited on the backlight surface of the silicon wafer 1 in S5 and cleaning the second semiconductor opening area again:

[0157] The removal cleaning solution uses HF solution, the mass percentage of HF acid is 2%, the mass percentage of deionized water is 98%, the treatment temperature is 25°C, and the removal time is 120s;

[0158] S7, depositing a second semiconductor layer on the backlight side of the silicon wafer 1, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer 7 and a P-type doped amorphous silicon layer 8, the P-type doped amorphous silicon layer 8 includes a hydrogen-doped P-type amorphous silicon layer 8.1 and a deuterium-doped P-type amorphous silicon layer 8.2:

[0159] The thickness of the intrinsic hydrogenated amorphous silicon layer 7 is 7 nm, the total thickness of the P-type doped amorphous silicon layer 8 is 13 nm, the thickness ratio of the hydrogen-doped P-type amorphous silicon layer 8.1 to the deuterium-doped P-type amorphous silicon layer 8.2 is 1:0.625; the thickness of the hydrogen-doped P-type amorphous silicon layer 8.1 is 8 nm, and the hydrogen doping concentration is 1.2*10 21 cm -3 , the boron doping concentration is 4.2*10 19 cm -3 The thickness of the deuterium-doped P-type amorphous silicon layer 8.2 is 5 nm, and the deuterium doping concentration of the deuterium-doped P-type amorphous silicon layer is 5*10 22 cm -3 , the boron doping concentration is 6.2*10 19 cm -3 .

[0160] The ratio of the doping concentration of boron to the doping concentration of deuterium in the deuterium-doped P-type amorphous silicon layer 8.2 is 1:806.

[0161] The second semiconductor layer is deposited by PECVD, and the specific deposition conditions are as follows:

[0162] When depositing the hydrogen-doped P-type amorphous silicon layer 8.1, the gas flow rate of silane is 450 sccm, the gas flow rate of diborane is 500 sccm, the gas flow rate of hydrogen is 5500 sccm, the temperature is 190°C, the gas pressure is 350 Pa, the power is 800 W, the time is 150 seconds, and the composition of diborane is 2% B2H6 and 98% H2;

[0163] When depositing the deuterium-doped P-type amorphous silicon layer 8.2, the gas flow rate of silane is 400 sccm, the gas flow rate of diborane is 450 sccm, the gas flow rate of deuterium gas is 6500 sccm, the temperature is 200°C, the gas pressure is 450 Pa, the power is 900 W, the time is 90 seconds, and the composition of diborane is 2% B2H6 and 98% H2.

[0164] When the intrinsic hydrogenated amorphous silicon layer 7 is deposited, the gas flow rate of silane is 500 sccm, the gas flow rate of hydrogen is 5000 sccm, the temperature is 205° C., the gas pressure is 250 Pa, the power is 1200 W, and the time is 60 seconds.

[0165] S8, performing a second etching opening on the second semiconductor layer to form first semiconductor opening regions that are alternately arranged with and spaced from the second semiconductor opening regions:

[0166] The width W1 of the first semiconductor opening region is 230 μm.

[0167] S9, depositing a conductive film layer 9 on the backlight surface obtained in S8;

[0168] The thickness of the conductive film layer 9 is 60 nm, and the material of the conductive film layer 9 is a tin-doped indium oxide-based thin film.

[0169] S10, performing a third etching opening on a portion of the conductive film layer 9 located between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove;

[0170] The width W3 of the insulating groove is 90 μm, and the resistance between the first semiconductor layer and the second semiconductor layer after etching is greater than 1 KΩ.

[0171] S11 , forming metal electrodes 10 in the first semiconductor opening region and the second semiconductor opening region respectively.

[0172] Example 2

[0173] The method of Example 1 is followed, except that the ratio of the phosphorus doping concentration to the deuterium doping concentration of the deuterium-doped N-type polysilicon layer 3.2 is 1:25. The process parameters that need to be adjusted to meet this doping concentration ratio are: reducing the gas flow rate of the deuterium gas to 1500 sccm in S2.

[0174] Example 3

[0175] The method of Example 1 is referred to, except that the ratio of the boron doping concentration to the deuterium doping concentration in the deuterium-doped P-type amorphous silicon layer 8.2 is 1:205. The process parameters that need to be adjusted to meet this doping concentration ratio are: in S7, the gas flow rate of the deuterium gas is reduced to 1650 sccm.

[0176] Example 4

[0177] The method of Example 1 is referred to, except that the thickness ratio of the hydrogen-doped N-type polysilicon layer 3.1 to the deuterium-doped N-type polysilicon layer 3.2 is 1:0.2, and the process parameters that need to be adjusted to meet this thickness are: in S2, the deposition time of the deuterium-doped N-type polysilicon layer 3.2 is shortened to 420 seconds.

[0178] Example 5

[0179] The method of Example 1 is referred to, except that the thickness ratio of the hydrogen-doped P-type amorphous silicon layer 8.1 to the deuterium-doped P-type amorphous silicon layer 8.2 is 1:0.3, and the process parameters that need to be adjusted to meet this thickness are: in S7, the deposition time of the deuterium-doped P-type amorphous silicon layer 8.2 is shortened to 43 seconds.

[0180] Example 6

[0181] The method of Example 1 is followed, except that the hydrogen doping concentration of the hydrogen-doped N-type polysilicon layer is 1*10 20 cm -3 , the phosphorus doping concentration is 5*10 19 cm-3 ; The deuterium doping concentration of the deuterium-doped N-type polysilicon layer is 7*10 21 cm -3 , the phosphorus doping concentration is 8*10 19 cm -3 , the process parameters that need to be adjusted to meet the doping concentration are: when depositing the hydrogen-doped N-type polysilicon layer 3.1, the gas flow rate of silane is 1800sccm, the gas flow rate of phosphine is 1000sccm, the gas flow rate of hydrogen is 3000sccm, the pressure is 300 Pa, the power is 6KW, the time is 1900 seconds, and the composition of phosphine is 2% PH3 and 98% H2;

[0182] When depositing the deuterium-doped N-type polysilicon layer 3.2, the gas flow rate of silane is 1800sccm, the gas flow rate of phosphine is 1050sccm, the gas flow rate of deuterium is 3500sccm, the pressure is 310 Pa, the power is 5.2KW, and the time is 850 seconds; the composition of phosphine is 2% PH3 and 98% H2.

[0183] Example 7

[0184] The method of Example 1 is followed, except that the hydrogen doping concentration of the hydrogen-doped P-type amorphous silicon layer is 5*10 20 cm -3 , the boron doping concentration is 8.2*10 18 cm -3 ; The deuterium doping concentration of the deuterium-doped P-type amorphous silicon layer is 9*10 21 cm -3 , the boron doping concentration is 9.1*10 18 cm -3 , the process parameters that need to be adjusted to meet the doping concentration are: when depositing the hydrogen-doped P-type amorphous silicon layer 8.1, the gas flow rate of silane is 450 sccm, the gas flow rate of diborane is 250 sccm, the gas flow rate of hydrogen is 3500 sccm, the temperature is 190°C, the gas pressure is 300 Pa, the power is 700 W, the time is 150 seconds, and the composition of diborane is 2% B2H6 and 98% H2;

[0185] When depositing the deuterium-doped P-type amorphous silicon layer 8.2, the gas flow rate of silane is 400 sccm, the gas flow rate of diborane is 280 sccm, the gas flow rate of deuterium gas is 4500 sccm, the temperature is 200°C, the gas pressure is 400 Pa, the power is 800 W, the time is 90 seconds, and the composition of diborane is 2% B2H6 and 98% H2.

[0186] Comparative Example 1

[0187] The method of Example 1 is referred to, except that the deuterium-doped N-type polysilicon layer 3.2 and the deuterium-doped P-type amorphous silicon layer 8.2 are not formed.

[0188] Comparative Example 2

[0189] The method of Example 1 is referred to, except that the deuterium-doped N-type polysilicon layer 3.2 is not formed and only the deuterium-doped P-type amorphous silicon layer 8.2 is formed.

[0190] Comparative Example 3

[0191] The method of Example 1 is referred to, except that only the deuterium-doped N-type polysilicon layer 3.2 is formed and the deuterium-doped P-type amorphous silicon layer 8.2 is not formed.

[0192] Test Case

[0193] The back contact cells obtained in the above-mentioned embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The performance indicators of each embodiment and comparative example were converted using embodiment 1 as a reference benchmark, the data of embodiment 1 was normalized benchmark 1, and other examples were converted based on embodiment 1, such as the battery conversion efficiency of comparative example 1 / battery conversion efficiency of embodiment 1 was 0.941.

[0194] Table 1

[0195]

[0196] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can greatly improve the surface density and stability of the first semiconductor layer and the second semiconductor layer, prevent the two semiconductor layers from natural oxidation or corrosion by the solution during the process, thereby reducing the contact resistance between the first semiconductor layer and the second semiconductor layer and the conductive film layer, improving the FF of the battery, and improving the battery conversion efficiency.

[0197] Furthermore, according to Examples 1 and 2-7, it can be seen that the preferred solution of the present invention can effectively reduce the contact resistance between the first semiconductor layer and the second semiconductor layer and the conductive film layer, further improve the FF of the battery, and improve the battery conversion efficiency.

[0198] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A back contact battery with a specific contact layer, comprising: A silicon wafer, wherein the silicon wafer has a backlight surface and a light-receiving surface; A first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are alternately arranged on the backlight surface; The invention is characterized in that the first semiconductor layer at least comprises an N-type doped polysilicon layer, the N-type doped polysilicon layer comprises a hydrogen-doped N-type polysilicon layer and a deuterium-doped N-type polysilicon layer arranged in sequence, and the second semiconductor layer at least comprises a P-type doped amorphous silicon layer, the P-type doped amorphous silicon layer comprises a hydrogen-doped P-type amorphous silicon layer and a deuterium-doped P-type amorphous silicon layer arranged in sequence; The first semiconductor layer further comprises a tunneling silicon oxide layer, and the thickness of the tunneling silicon oxide layer is 1-2 nm; The total thickness of the N-type doped polysilicon layer is 80-150nm, the thickness ratio of the hydrogen-doped N-type polysilicon layer to the deuterium-doped N-type polysilicon layer is 1:0.1-0.7; the thickness of the hydrogen-doped N-type polysilicon layer is 70-140nm, and the hydrogen doping concentration is 1*10 20 -5*10 22 cm -3 , the phosphorus doping concentration is 1*10 19 -9*10 20 cm -3 The thickness of the deuterium-doped N-type polysilicon layer is 10-50 nm, and the deuterium doping concentration of the deuterium-doped N-type polysilicon layer is 1*10 20 -5*10 22 cm -3 , the phosphorus doping concentration is 1*10 19 -9*10 20 cm -3 ; The second semiconductor layer further comprises an intrinsic hydrogenated amorphous silicon layer, and the thickness of the intrinsic hydrogenated amorphous silicon layer is 3-9 nm; The total thickness of the P-type doped amorphous silicon layer is 8-15 nm, the thickness ratio of the hydrogen-doped P-type amorphous silicon layer to the deuterium-doped P-type amorphous silicon layer is 1:0.3-1; the thickness of the hydrogen-doped P-type amorphous silicon layer is 4-10.5 nm, and the hydrogen doping concentration is 3*10 20 -6*10 22 cm -3 , the boron doping concentration is 1*10 18 -7*10 19 cm -3 The thickness of the deuterium-doped P-type amorphous silicon layer is 2.4-7.5 nm, and the deuterium doping concentration of the deuterium-doped P-type amorphous silicon layer is 5*10 20 -9*10 22 cm -3 , the boron doping concentration is 1*10 18 -9*10 19 cm -3 .

2. The back contact cell with a specific contact layer according to claim 1, characterized in that: The ratio of phosphorus doping concentration to deuterium doping concentration in the deuterium-doped N-type polysilicon layer is 1:1-200, and the ratio of boron doping concentration to deuterium doping concentration in the deuterium-doped P-type amorphous silicon layer is 1:5-900.

3. The back contact cell with a specific contact layer according to claim 1, characterized in that: A second semiconductor opening region is provided between adjacent first semiconductor layers, and two ends of the second semiconductor layer located in the second semiconductor opening region respectively extend toward the surface of the adjacent first semiconductor layer by a preset distance and overlap with it to form an overlapping region.

4. The back contact cell with a specific contact layer according to claim 3, characterized in that: The back contact cell with a specific contact layer also includes: A conductive film layer, the conductive film layer is laid on the first semiconductor layer and the second semiconductor layer, the thickness of the conductive film layer is 40-80nm, the material of the conductive film layer is an indium oxide-based film doped with one or a combination of tin, tungsten, titanium and zinc, or a zinc oxide-based film doped with one or a combination of aluminum and boron, and the conductive film layer is provided with an insulating groove at the position of each overlapping area, and the width of the insulating groove is 20-100μm; and / or, The back contact cell with a specific contact layer also includes: A metal electrode is arranged in a first semiconductor opening region and a second semiconductor opening region; the first semiconductor opening region is arranged on a portion outside an overlapping region on the first semiconductor layer, the width of the first semiconductor opening region is 150-350 μm, and the width of the second semiconductor opening region is 400-600 μm.

5. The back contact cell with a specific contact layer according to claim 1, characterized in that: The back contact cell with a specific contact layer also includes: A third semiconductor layer, wherein the third semiconductor layer is laid on the light-receiving surface of the silicon wafer, and the third semiconductor layer comprises a passivation layer and an anti-reflection layer arranged in sequence, wherein the passivation layer is one or a combination of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, an oxide layer and a doped oxide layer; and the anti-reflection layer is one or a combination of a silicon nitride layer, a silicon oxynitride layer and an oxide layer.

6. A method for preparing a back contact battery with a specific contact layer, the method being used to prepare a back contact battery with a specific contact layer as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: S1, provide double-sided polished silicon wafers; S2. Depositing a first semiconductor layer and a mask layer on the backlight surface of the silicon wafer in sequence, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer arranged in sequence, and the N-type doped polysilicon layer comprises a hydrogen-doped N-type polysilicon layer and a deuterium-doped N-type polysilicon layer arranged in sequence; S3, performing a first etching opening on the backlight surface obtained in S2 to form second semiconductor opening regions arranged at intervals; S4, removing the first semiconductor layer remaining in the second semiconductor opening region by texturing, and forming a textured surface on the light-receiving surface of the silicon wafer and the second semiconductor opening region, and then removing the mask layer outside the second semiconductor opening region on the backlight side of the silicon wafer during the cleaning process of the textured surface; S5, forming a passivation layer and an anti-reflection layer on the light-receiving surface of the silicon wafer; S6, removing the wrap-around coating produced by the deposition on the backlight surface of the silicon wafer in S5 and cleaning the second semiconductor opening area again; S7. Depositing a second semiconductor layer on the backlight side of the silicon wafer, the second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous silicon layer arranged in sequence, and the P-type doped amorphous silicon layer comprises a hydrogen-doped P-type amorphous silicon layer and a deuterium-doped P-type amorphous silicon layer arranged in sequence.

7. The method for preparing a back contact battery with a specific contact layer according to claim 6, characterized in that: In S2, the first semiconductor layer and the mask layer are sequentially deposited by PECVD and annealed in an annealing furnace at 800-950°C for 30-90 minutes. The deposition temperature is 350-550°C. The specific deposition conditions are as follows: When depositing a hydrogen-doped N-type polysilicon layer, the gas flow rate of silane is 1000-3000sccm, the gas flow rate of phosphine is 1000-2500sccm, the gas flow rate of hydrogen is 3000-9000sccm, the pressure is 300-450 Pa, the power is 5-20KW, the time is 800-2500 seconds, and the composition of phosphine is 2-8% PH3 and 92-98% H2; When depositing a deuterium-doped N-type polysilicon layer, the gas flow rate of silane is 1000-3000sccm, the gas flow rate of phosphine is 1000-2500sccm, the gas flow rate of deuterium gas is 1000-9000sccm, the pressure is 300-450 Pa, the power is 5-20KW, the time is 300-1300 seconds, and the composition of phosphine is 2-8% PH3 and 92-98% H2; When depositing the tunneling silicon oxide layer, the gas flow rate of nitrous oxide is 8000-12000 sccm, the pressure is 100-300 Pa, the power is 3-20 KW, and the time is 20-100 seconds; When depositing the mask layer, the gas flow rate of silane is 1000-2000sccm, the gas flow rate of nitrogen is 2000-10000sccm, the pressure is 200-300 Pa, the power is 3-20KW, and the time is 300-800 seconds; wherein the mask layer is at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, and the thickness of the mask layer is 50-100nm.

8. The method for preparing a back contact battery with a specific contact layer according to claim 6, characterized in that: In S7, the second semiconductor layer is deposited by PECVD, and the specific deposition conditions are as follows: When depositing a hydrogen-doped P-type amorphous silicon layer, the gas flow rate of silane is 300-1000sccm, the gas flow rate of diborane or trimethylborane is 200-2000sccm, the gas flow rate of hydrogen is 1500-10000sccm, the temperature is 160-300°C, the gas pressure is 200-600pa, the power is 300-1500w, the time is 90-210 seconds, the composition of diborane is 2-8% B2H6 and 92-98% H2, and the composition of trimethylborane is 2-8% TMB and 92-98% H2; When depositing a deuterium-doped P-type amorphous silicon layer, the gas flow rate of silane is 300-1000sccm, the gas flow rate of diborane or trimethylborane is 200-2000sccm, the gas flow rate of deuterium gas is 1500-10000sccm, the temperature is 160-300°C, the gas pressure is 200-600Pa, the power is 300-1500W, the time is 27-105 seconds, the composition of diborane is 2-8% B2H6 and 92-98% H2, and the composition of trimethylborane is 2-8% TMB and 92-98% H2; When depositing the intrinsic hydrogenated amorphous silicon layer, the gas flow rate of silane is 300-2000sccm, the gas flow rate of hydrogen is 1500-10000sccm, the temperature is 160-300°C, the gas pressure is 200-600Pa, the power is 300-1500W, and the time is 20-120 seconds.

9. The method for preparing a back contact battery with a specific contact layer according to claim 6, characterized in that: In S4, the texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%-5%, the mass percentage of the texturing additive is 0.5%-1%, the texturing time is 8-30 minutes, and the texturing temperature is 75°C-85°C; and / or, In S4, the cleaning solution is HF solution, the mass percentage of HF acid is 0.5%-5%, the mass percentage of deionized water is 95%-99.5%, the processing temperature is 20°C-30°C, and the removal time is 60-500s.

10. The method for preparing a back contact battery with a specific contact layer according to claim 6, characterized in that: The method for preparing the back contact battery also includes: S8, performing a second etching opening on the second semiconductor layer to form first semiconductor opening regions that are alternately arranged with and spaced from the second semiconductor opening regions; S9, depositing a conductive film layer on the backlit surface obtained in S8; S10, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove; S11 , forming metal electrodes in the first semiconductor opening region and the second semiconductor opening region respectively.

11. The method for preparing a back contact battery with a specific contact layer according to claim 10, characterized in that: Also includes at least one of the following methods: In S3, the first etching opening is performed by mask etching or laser, the laser is ultraviolet or green laser, and the pulse width is less than 10 ns; In S6, the removal cleaning solution is an HF solution, the mass percentage of HF acid is 1%-10%, the mass percentage of deionized water is 90%-99%, the treatment temperature is 20°C-30°C, and the removal time is 30-500s; In S8, the second etching opening is performed by laser, the laser is ultraviolet or green laser, and the pulse width is less than 10 ns; In S9, a conductive film layer is deposited by PVD or RPD; In S10, the third etching opening is performed by mask etching or laser etching, and the resistance between the first semiconductor layer and the second semiconductor layer after etching is greater than 1KΩ; In S11, a metal electrode is formed by using a screen printing technique.

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