Display device and method for manufacturing display device

Abstract

A display device and a method for manufacturing the same are disclosed. The display device may include a semiconductor wafer substrate, a complementary metal oxide semiconductor (CMOS) circuit layer disposed on the semiconductor wafer substrate, and a light emitting element layer disposed on the CMOS circuit layer. The light emitting element layer may include a pixel defining film separating a plurality of pixels, pixel electrodes independently disposed in each of the plurality of pixels, an aged wiring disposed between the plurality of pixels, a light emitting layer commonly covering the pixel electrodes and the aged wiring of each of the plurality of pixels, and a common electrode covering the light emitting layer. A portion of the light emitting layer between the aging wiring and the common electrode may include an aging portion in which at least a portion of a conductive layer included in the light emitting layer is aged.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all rights arising from Korean Patent Application No. 10-2023-0100978 filed in the Korean Intellectual Property Office on August 2, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0004] Wearable devices that are developed in the form of glasses or helmets and are focused at a distance close to the user's eyes are being developed. For example, the wearable device may be a head-mounted display (HMD) device or AR glasses. Such a wearable device provides an augmented reality (hereinafter, referred to as "AR") screen or a virtual reality (hereinafter, referred to as "VR") screen to the user.

[0005] Wearable devices such as HMD devices or AR glasses require a display specification of at least 2000 pixels per inch (PPI) to allow users to use the device for a long time without feeling dizzy. To this end, organic light emitting diode on silicon (OLEDoS) technology, that is, a small organic light emitting display device with high resolution is emerging. OLEDoS is a technology that disposes an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed.

[0006] Because the distance between pixels is reduced in a display panel to which OLEDoS technology is applied, unexpected leakage current may be generated between adjacent pixels. The leakage current may be generated through some conductive layers of the light-emitting layer disposed between the pixel electrode (e.g., anode) and the common electrode (e.g., cathode). It is known that the leakage current is the cause of color crosstalk between adjacent pixels. Summary of the invention

[0007] Aspects of the present disclosure provide a display device capable of preventing color interference (color crosstalk) between adjacent pixels by preventing leakage current between adjacent pixels, and a method for manufacturing the display device.

[0008] According to an embodiment of the present disclosure, a display device may include: a semiconductor wafer substrate, a complementary metal oxide semiconductor (CMOS) circuit layer disposed on the semiconductor wafer substrate, and a light emitting element layer disposed on the CMOS circuit layer. The light emitting element layer may include: a pixel defining film separating a plurality of pixels, a pixel electrode independently disposed in each of the plurality of pixels, an aging wiring disposed between the plurality of pixels, a light emitting layer that commonly covers the pixel electrodes and the aging wiring of each of the plurality of pixels, and a common electrode covering the light emitting layer. A portion of the light emitting layer located between the aging wiring and the common electrode may include an aging portion in which at least some of the conductive layers included in the light emitting layer are aged.

[0009] The aged portion of the light emitting layer has a conductive layer with a higher resistance than other portions of the light emitting layer.

[0010] The pixel defining film may include a first opening in which the pixel electrode is disposed, and second and third openings in which the burn-in wiring is disposed.

[0011] The aging wiring may include a first aging wiring disposed in the second opening to pass between respective columns of the plurality of pixels and a second aging wiring disposed in the third opening to pass between respective rows of the plurality of pixels.

[0012] The burn-in wiring may have a mesh shape in which the first burn-in wiring and the second burn-in wiring are located in the same layer.

[0013] The first aging wiring and the second aging wiring may be provided at the same layer as the pixel electrode.

[0014] The first burn-in wiring and the second burn-in wiring may be provided in different layers.

[0015] The first aging wiring may be disposed at a different layer from the pixel electrode, and the second aging wiring may be disposed at the same layer as the pixel electrode.

[0016] Each of the first aging wiring and the second aging wiring may include a pair of wirings arranged between adjacent pixels with a gap between them.

[0017] At least some of the conductive layers included in the light emitting layer may include at least one layer among a charge generation layer, a hole injection layer, a hole transport layer, an electron transport layer, and a p-doped layer.

[0018] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: forming a complementary metal oxide semiconductor (CMOS) circuit layer on a semiconductor wafer substrate; forming a light emitting element layer including a pixel electrode, a light emitting layer, and a common electrode on the CMOS circuit layer; and aging at least some conductive layers included in the light emitting layer by supplying a specified voltage to an aging wiring disposed between a plurality of pixels during a specified time. At least some of the conductive layers have increased resistance between the plurality of pixels due to aging.

[0019] Forming the light emitting element layer may include forming a pixel defining film that separates a plurality of pixels. The pixel defining film may include a first opening in which the pixel electrode is disposed, and a second opening and a third opening in which the burn-in wiring is disposed.

[0020] The aging wiring may include a first aging wiring disposed in the second opening to pass between respective columns of the plurality of pixels and a second aging wiring disposed in the third opening to pass between respective rows of the plurality of pixels.

[0021] The burn-in wiring may have a mesh shape in which the first burn-in wiring and the second burn-in wiring are formed in the same layer.

[0022] A method of manufacturing a display device may include forming a first aging wiring and a second aging wiring at the same layer as a pixel electrode.

[0023] The first burn-in wiring and the second burn-in wiring may be provided in different layers.

[0024] The first aging wiring may be disposed at a different layer from the pixel electrode, and the second aging wiring may be disposed at the same layer as the pixel electrode.

[0025] Each of the first aging wiring and the second aging wiring may include a pair of wirings arranged between adjacent pixels with a gap between them.

[0026] At least some of the conductive layers included in the light emitting layer may include at least one layer among a charge generation layer, a hole injection layer, a hole transport layer, an electron transport layer, and a p-doped layer.

[0027] The specified voltage supplied to the burn-in wiring may be approximately 50V.

[0028] According to the display device and the method of manufacturing the display device according to the embodiment, leakage current and color crosstalk between adjacent pixels can be prevented by aging some conductive layers of the light emitting layer disposed between adjacent pixels.

[0029] However, aspects of the present disclosure are not limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings.

[0031] Figure 1 is a perspective view of a display device according to an embodiment.

[0032] Figure 2 is a plan view of a display panel according to an embodiment.

[0033] Figure 3 is a block diagram of a configuration of a display device according to an embodiment.

[0034] Figure 4 is a circuit diagram of a pixel of a display device according to an embodiment.

[0035] Figure 5 is a schematic cross-sectional view of a portion of a display panel of a display device according to an embodiment.

[0036] Figure 6 is a cross-sectional view schematically showing a structure of a light emitting element according to an embodiment.

[0037] Figure 7 , Figure 8 , Fig. 9 and Fig.10 is a cross-sectional view showing a structure of a light emitting element according to an embodiment.

[0038] Fig.11 It is shown Fig. 9 A cross-sectional view of an example of a light emitting element.

[0039] Fig.12 It is shown Fig.10 A cross-sectional view of an example of a light emitting element.

[0040] Fig.13 is a cross-sectional view showing a structure of a pixel of a display device according to an embodiment.

[0041] Fig.14 is a plan view schematically showing a portion of a pixel of a display panel according to an embodiment.

[0042] Fig.15 is shown along Fig.14 FIG. 1 is a diagram of a portion of a cross section of a display panel taken along line AA′.

[0043] Fig.16 is a plan view of a display panel showing an example in which a pair of aging wirings are provided between pixels.

[0044] Fig.17 is shown along Fig.16 FIG. 1 is a diagram of a portion of a cross section of a display panel taken along line BB′.

[0045] Fig.18 is a cross-sectional view of a display panel showing an example in which a burn-in wiring is provided on a pixel defining film.

[0046] Fig.19 is a plan view of a display panel showing an example in which a burn-in wiring is not formed in a mesh structure.

[0047] Fig. 20 is a flowchart illustrating a method for manufacturing a display device according to an embodiment.

[0048] Fig.21 is an exemplary view of a VR device including a display device according to an embodiment.

[0049] Fig. 22 and Fig.23 : is an exemplary view showing an HMD device to which the display device according to the embodiment is applied. DETAILED DESCRIPTION

[0050] The inventive concept will now be described more fully below with reference to the accompanying drawings, in which embodiments of the inventive concept are shown. However, the inventive concept may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

[0051] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0052] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0053] The features of each of the various embodiments of the present disclosure may be partially or entirely combined with each other and may technically interact with each other differently, and the respective embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0054] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0055] Figure 1 is a perspective view of a display device 10 according to an embodiment.

[0056] refer to Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs).

[0057] The display device 10 may have a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral having short sides in the first direction DR1 and long sides in the second direction DR2. Alternatively, the display device 10 may have a planar shape similar to a quadrilateral having long sides in the first direction DR1 and short sides in the second direction DR2. Figure 1 , the third direction DR3 represents a normal direction perpendicular to the plane defined by the first direction DR1 and the second direction DR2. Each corner where the short side intersects the long side may be rounded with a predetermined curvature or may be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0058] The display device 10 includes a display panel 110 , a circuit board 120 , and a power supply unit 130 .

[0059] The display panel 110 uses a semiconductor wafer substrate ( Figure 2 The display panel 110 may include a main area MA and a sub-area SBA.

[0060] The main area MA may include Figure 3The display panel 110 may include a display area DA of a pixel PX displaying an image and a non-display area NDA disposed around the display area DA. The non-display area NDA may refer to an area other than the display area DA. The display area DA may emit light from a plurality of light emitting areas or a plurality of opening areas. For example, the display panel 110 may include Figure 4 A pixel driving circuit PC including a switching element, Figure 5 A pixel definition film PDL defining a light emitting area or an opening area and Figure 5 The light-emitting element LEL is a self-luminous element.

[0061] The light emitting element LEL may include, but is not limited to, at least one of an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, and a micro light emitting diode.

[0062] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 110. The non-display area NDA may include fan-out lines (not shown) extending from lines (e.g., gate lines, data lines, and emission control lines) of the display area DA and a display panel unit (not shown).

[0063] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a main pad unit connected to the circuit board 120. Alternatively, the sub-area SBA may be omitted, and the main pad unit may be provided in the non-display area NDA.

[0064] Circuit board 120 may be attached to the main pad unit of display panel 110 using an anisotropic conductive film (ACF). Leads of circuit board 120 may be electrically connected to the main pad unit of display panel 110. Circuit board 120 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0065] The power supply unit 130 may be disposed on the circuit board 120, and may supply a power supply voltage to the display driving circuit 210 (see Figure 2 ) and the display panel 110. The power supply unit 130 may generate a driving voltage and supply the driving voltage to the driving voltage line. For example, the driving voltage may include a high potential voltage (see, for example Figure 4 The first driving voltage ELVDD in the embodiment of the present invention), the low potential voltage (see for example Figure 4 The second driving voltage ELVSS in Figure 4 The initialization voltage VINT used to drive the light emitting element LEL.

[0066] Figure 2 is a plan view of a display panel 110 according to an embodiment.

[0067] refer to Figure 2 , the display panel 110 may be an organic light emitting diode on silicon (OLEDoS) panel using the semiconductor wafer substrate 200 as a base substrate. For example, the display panel 110 may include the semiconductor wafer substrate 200, and Figure 4 The pixel driving circuit PC in the display area DA and the display driving circuit 210 for controlling the pixel driving circuit PC may be disposed on the front surface 201 of the semiconductor wafer substrate 200. The pixel driving circuit PC is disposed to be in contact with the display area DA. Figure 3 Each pixel PX in Figure 5 The display driving circuit 210 is disposed in the non-display area NDA and is used to drive the pixel driving circuit PC.

[0068] Figure 4 The pixel driving circuit PC and the display driving circuit 210 in the embodiment may be formed on a metal oxide semiconductor field effect transistor (MOSFET) layer 501 (see FIG. 2 ) disposed on the front surface 201 of the semiconductor wafer substrate 200. Figure 5 ) In the embodiment of the present invention, the MOSFET layer 501 may include, for example, an N-type MOSFET and / or a P-type MOSFET.

[0069] Figure 3 is a block diagram showing a configuration of a display device 10 according to an embodiment.

[0070] refer to Figure 3 The display device 10 includes a semiconductor wafer substrate 200 (see Figure 2 ) of the display panel 110. The display driving circuit 210 is embedded in the display panel 110. The display driving circuit 210 is formed on the MOSFET layer 501 (see Figure 5 ). The display driving circuit 210 may include a timing controller 310, a gate driver 320, an emission control driver 330, and a data driver 340, but the present disclosure is not limited thereto. Although not shown, the display driving circuit 210 may also include a memory (e.g., OTP), an interface circuit (e.g., I / F), an image processing circuit (e.g., logic), and / or a gamma processing circuit.

[0071] The display area DA of the display panel 110 includes a plurality of pixels PX arranged in a matrix form. Each of the plurality of pixels PX may be connected to a first driving voltage line VDL, a second driving voltage line VSL, a gate line GL, an emission control line EML, an initialization line VIL, and a data line DL.

[0072] The first driving voltage line VDL is input from the power supply unit 130 Figure 4The first driving voltage ELVDD in the second driving voltage line VSL is supplied to the plurality of pixels PX. Figure 4 The second driving voltage ELVSS in the gate driver 320 is supplied to the plurality of pixels PX. Figure 4 The gate signals GI and GW in the emission control driver 330 are supplied to the plurality of pixels PX. The emission control line EML is input from the emission control driver 330. Figure 4 The emission control signal EM in the initialization line VIL is supplied to the plurality of pixels PX. Figure 4 The data line DL supplies the initialization voltage VINT in the input voltage range to the plurality of pixels PX. The data line DL supplies the analog data voltage input from the data driver 340 to the pixels PX.

[0073] The first driving voltage ELVDD may be a high potential voltage, and the second driving voltage ELVSS may be a low potential voltage. For example, the first driving voltage ELVDD may have a higher potential than that of the second driving voltage ELVSS. Figure 4 The initialization voltage VINT in the pixel driving circuit ( Figure 4 The potential at which the PC in is initialized.

[0074] Figure 3 One gate line GL shown in FIG. 1 may include a first gate line GWL and a second gate line GIL, but the present disclosure is not limited thereto.

[0075] Each of the plurality of pixels PX includes Figure 4 The light emitting element LEL may include a plurality of transistors and one or more capacitors as Figure 4 A pixel driving circuit PC for driving the light emitting element LEL.

[0076] The timing controller 310 can be connected to the circuit board 120 (see Figure 1 ) receives the data signal DATA and the timing signal. The timing controller 310 can control the operation timing of the data driver 340 by generating the data control signal DCS based on the timing signal. The timing controller 310 can control the operation timing of the gate driver 320 by generating the gate control signal GCS based on the timing signal. The timing controller 310 can control the operation timing of the emission control driver 330 by generating the emission control driving signal ECS based on the timing signal.

[0077] The data driver 340 may convert the data signal DATA into an analog data voltage and supply the converted analog data voltage to the pixel PX through the data line DL. The gate signal of the gate driver 320 may select the pixel PX to which the data voltage is supplied, and the selected pixel PX may receive the data voltage through the data line DL.

[0078] The power supply unit 130 may be disposed on the circuit board 120 (see Figure 1 ) and may supply a power supply voltage to the display driving circuit 210 and the display panel 110. The power supply unit 130 may generate a driving voltage and supply the driving voltage to the first driving voltage line VDL, and may generate a common voltage and supply the common voltage to a common electrode (e.g., Figure 5 The common electrode CAE in the circuit).

[0079] The gate driver 320 can transmit Figure 4 The gate signals GI and GW in are supplied to the pixels PX.

[0080] The emission control driver 330 can transmit the Figure 4 The emission control signal EM in is supplied to the pixel PX.

[0081] Figure 4 is a circuit diagram of a pixel PX of a display device according to an embodiment.

[0082] refer to Figure 4 , the pixel PX may include a light emitting element LEL (e.g., an organic light emitting diode) as a display element and a pixel driving circuit PC connected to the light emitting element LEL. The pixel driving circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4 and a first capacitor C1, but the present disclosure is not limited thereto. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be implemented as an N-type metal oxide semiconductor field effect transistor (MOSFET) and / or a P-type MOSFET. Figure 4 It is shown in FIG. 1 that the first transistor T1 , the second transistor T2 , the third transistor T3 , and the fourth transistor T4 are P-type MOSFETs, but the present disclosure is not limited thereto.

[0083] The first transistor T1 may be a driving transistor whose source-drain current is determined according to a gate-source voltage, and each of the second to fourth transistors T2 to T4 may be a switching transistor turned on / off according to a gate-source voltage (substantially, a gate voltage).

[0084] The first transistor T1 includes a gate connected to the first node N1, a source connected to the second node N2, and a drain connected to the third node N3. The first transistor T1 is turned on or off based on the voltage level of the first node N1. The turned-on first transistor T1 connects the second node N2 and the third node N3. The second node N2 is a node connected to the drain of the third transistor T3, and is a node to which the first driving voltage ELVDD is supplied when the third transistor T3 is turned on in response to the emission control signal EM. The third node N3 is connected to the light emitting element LEL. Figure 5 The pixel electrode ANE in the fourth transistor T4 and the drain electrode of the fourth transistor T4 are connected. The third node N3 is a node to which the initialization voltage VINT is supplied when the fourth transistor T4 is turned on in response to the second gate signal GI.

[0085] The second transistor T2 includes a gate connected to the first gate line GWL, a source connected to the data line DL, and a drain connected to the first node N1. The second transistor T2 is turned on in response to the first gate signal GW supplied from the first gate line GWL. The turned-on second transistor T2 supplies the data signal Vdat supplied from the data line DL to the first node N1.

[0086] The third transistor T3 includes a gate connected to the emission control line EML, a source connected to the first driving voltage line VDL supplied with the first driving voltage ELVDD, and a drain connected to the second node N2. The third transistor T3 is turned on in response to the emission control signal EM supplied from the emission control line EML. The turned-on third transistor T3 supplies the first driving voltage ELVDD to the second node N2.

[0087] The fourth transistor T4 includes a gate connected to the second gate line GIL, a source connected to the initialization line VIL supplied with the initialization voltage VINT, and a drain connected to the third node N3. The fourth transistor T4 is turned on in response to the second gate signal GI supplied from the second gate line GIL. The turned-on fourth transistor T4 supplies the initialization voltage VINT to the third node N3.

[0088] The first capacitor C1 is disposed between the first node N1 and the second node N2. The first capacitor C1 is used to store the data signal Vdat input through the second transistor T2.

[0089] The light emitting element LEL may include a pixel electrode (eg, Figure 5 The pixel electrode ANE in the middle) and the common electrode facing the pixel electrode (eg, Figure 5The common electrode CAE in the plurality of pixels PX may be connected to a common electrode CAE in the plurality of pixels PX, and the common electrode may be applied with a second driving voltage ELVSS. The common electrode may be connected to a second driving voltage line VSL transmitting the second driving voltage ELVSS. The common electrode may be commonly disposed in a plurality of pixels PX.

[0090] Figure 5 is a schematic cross-sectional view of a portion of a display panel 110 of a display device according to an embodiment. For example, Figure 5 1 is a view schematically showing a stack structure of each of the non-display area NDA and the display area DA of the display panel 110 according to an embodiment.

[0091] In reference Figure 5 In the description of , the expression “located on” may mean that the front surface of the semiconductor wafer substrate 200 faces the third direction DR3. The front surface of the semiconductor wafer substrate 200 may refer to a direction in which the light emitting elements LEL disposed in the display area DA emit light for displaying an image.

[0092] refer to Figure 5 The display panel 110 uses a semiconductor wafer substrate 200 as a base substrate. It includes a display driving circuit 210 and a pixel driving circuit PC (see Figures 2 to 4 ), a MOSFET layer 501 including a light emitting element LEL, at least one wiring layer 502, a light emitting element layer 503 including a light emitting element LEL, an encapsulation layer 504 covering the light emitting element LEL, a color filter layer 505 including a color filter CF, a light control layer 506 including a refractive film MLA, and a protective layer 507 including a cover glass CV may be sequentially stacked on the front surface of the semiconductor wafer substrate 200. At least some of the light emitting element layer 503, the encapsulation layer 504, the color filter layer 505, the light control layer 506, and the protective layer 507 may not be disposed in the non-display area NDA.

[0093] The semiconductor wafer substrate 200 may be a silicon substrate, a germanium substrate or a silicon-germanium substrate. The semiconductor wafer substrate 200 may be a substrate doped with first type impurities.

[0094] The MOSFET layer 501 including N-type MOSFET and / or P-type MOSFET is disposed on the semiconductor wafer substrate 200. The first type impurity may be a P-type impurity, and the second type impurity may be an N-type impurity. Alternatively, the first type impurity may be an N-type impurity, and the second type impurity may be a P-type impurity.

[0095] Herein, an N-type MOSFET MOS included in the MOSFET layer 501 will be described as an example. The N-type MOSFET MOS may include a well region W1 doped with N-type impurities in a substrate doped with P-type impurities.

[0096] The well region W1 may include a first low-concentration impurity region LDD1 and a second low-concentration impurity region LDD2 having a relatively low impurity concentration compared to other portions. The first low-concentration impurity region LDD1 may define a source region S1, and the second low-concentration impurity region LDD2 may define a drain region D1. A source electrode SE of the MOSFET MOS may be connected to the source region S1, and a drain electrode DE of the MOSFET MOS may be connected to the drain region D1.

[0097] A channel CH disposed to overlap the gate G1 is defined between the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. An oxide film (not shown) as an insulating layer may be disposed between the gate G1 and the well region W1.

[0098] The MOSFET MOS constitutes the display driving circuit 210, and the display driving circuit 210 is disposed in the non-display area NDA of the display panel 110. Figure 4 The transistors T1, T2, T3 and T4 included in the pixel driving circuit PC are arranged in the display area DA of the display panel 110. That is, each pixel driving circuit PC is a circuit including a combination of MOSFET MOS arranged in the MOSFET layer 501 to correspond to the display area DA. In addition, the display driving circuit 210 is a circuit including a combination of MOSFET MOS arranged in the MOSFET layer 501 to correspond to the non-display area NDA. For the convenience of explanation, Figure 5 One MOSFET MOS of the pixel driving circuit PC provided in the display area DA of the display panel 110 is exemplarily shown.

[0099] At least one wiring layer 502 is disposed on the MOSFET layer 501. The at least one wiring layer 502 includes an insulating layer VIA sequentially stacked on the MOSFET layer 501 and electrodes CE and wirings (not shown) connected to the MOSFET MOS through contact holes CT1 penetrating at least a portion of the insulating layer VIA.

[0100] The electrodes CE provided in the wiring layer 502 include first vertical connection electrodes CE, which are used to connect some of the plurality of MOSFET MOS corresponding to the pixel driving circuit PC provided in the MOSFET layer 501 with the light emitting element LEL provided on the wiring layer 502 in a vertical direction. Here, the vertical direction refers to the normal direction of the display panel 110, that is, the third direction DR3.

[0101] Wiring (not shown) provided in the wiring layer 502 includes lines (eg, Figure 3 The wirings provided in the wiring layer 502 also include lines connected to the pixel driving circuit PC (eg, Figure 3 The wiring layer 502 may include a wiring layer for transmitting the aging signal to a later reference signal. Figures 14 to 19 Description Fig.14 On the other hand, the wiring layer 502 may not include an aging signal supply wiring (not shown), in which case the aging wiring 1410 extends from the same layer as the pixel electrode ANE to the non-display area NDA to connect to the aging signal supply wiring (not shown). Fig.14 An aging pad 1420 to which an aging signal is applied.

[0102] The term “aging wiring” included in this document may be referred to as “heating wiring” because it performs a function of applying heat to a common layer, or as “dummy wiring” because it is not used during a driving period when the display device 10 displays a picture.

[0103] The wiring layer 502 may include pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 disposed to correspond to the non-display area NDA. The pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 may include pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 connected to the first gate line GWL (see Figure 4 ) connected to the first gate pad PD1 and the second gate line GIL (see Figure 4 ) connected to the second gate pad PD2 and the initialization line VIL (see Figure 4 ) connected to the initialization pad PD3, and the emission control line EML (see Figure 4 ) connected to the light emitting pad PD4 and the data line DL (see Figure 4 ) connected to the data pad PD5, and the first driving voltage line VDL (see Figure 4 ) and the first driving voltage pad PD6 connected to the second driving voltage line VSL (see Figure 4 ) is connected to the second driving voltage pad PD7. However, Figure 5 The pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 shown in the figure are only examples, and the present disclosure is not limited thereto. For example, the wiring layer 502 may further include an aging pad 1420 connected to an aging signal supply wiring (not shown) or the aging wiring 1410 in the non-display area NDA. The aging pad 1420 may be electrically connected to the aging wiring 1410 through the aging signal supply wiring or may be directly connected to the aging wiring 1410.

[0104] The light emitting element layer 503 including the light emitting element LEL may be disposed on at least one wiring layer 502 including the planarization film FL. The light emitting element LEL includes a pixel electrode ANE connected to the first vertical connection electrode CE through a second contact hole CT2 in the planarization film FL and connected to a MOSFET MOS included in the pixel driving circuit PC through the first vertical connection electrode CE, a light emitting layer EL disposed on the pixel electrode ANE, and a common electrode CAE disposed on the light emitting layer EL. The light emitting element layer 503 may further include a pixel defining film PDL that separates each of the plurality of pixels PX.

[0105] An encapsulation layer 504 including at least one organic encapsulation layer and at least one inorganic encapsulation layer may be disposed on the light emitting element layer 503. For example, the encapsulation layer 504 may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3, but the present disclosure is not limited thereto.

[0106] A color filter layer 505 including a color filter CF may be disposed on the encapsulation layer 504. The color filter CF may include a red color filter that transmits red light, a green color filter that transmits green light, and a blue color filter that transmits blue light, but the present disclosure is not limited thereto. When the light emitting element LEL of the light emitting element layer 503 emits white light, the color filter layer 505 is provided. If the light emitting element LEL of the light emitting element layer 503 directly emits red light, green light, and blue light, the color filter layer 505 may be omitted.

[0107] The light control layer 506 including the refractive film MLA is disposed on the color filter layer 505. The refractive film MLA may refract incident light so that light emitted from the light emitting element layer 503 is directed toward the normal direction of the display panel 110, that is, the third direction DR3. Such a refractive film MLA may include a microlens array.

[0108] A protective layer 507 serving as a cover layer may be disposed on the light control layer 506. The protective layer 507 may include a cover glass CV made of glass, but the present disclosure is not limited thereto. The protective layer 507 may include, for example, a protective film.

[0109] Figure 6 is a cross-sectional view schematically showing the structure of a light emitting element LEL according to an embodiment, and Figures 7 to 10 is a cross-sectional view showing the structure of a light emitting element LEL according to an embodiment.

[0110] refer to Figure 6According to the embodiment, the light emitting element LEL (eg, organic light emitting diode) may include a pixel electrode 601, a common electrode 605, and an intermediate layer 603 located between the pixel electrode 601 and the common electrode 605. In the following description, the pixel electrode 601 may refer to the reference Figure 5 The common electrode 605 may refer to the pixel electrode ANE described above. Figure 5 Describe the common electrode CAE.

[0111] The pixel electrode 601 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The pixel electrode 601 may be a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. For example, the pixel electrode 601 may have a three-layer structure of ITO / Ag / ITO.

[0112] The common electrode 605 may be disposed on the intermediate layer 603. The common electrode 605 may include a metal, an alloy, a conductive compound, or any combination thereof having a low work function. For example, the common electrode 605 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The common electrode 605 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0113] The intermediate layer 603 may include a high molecular or low molecular organic material emitting light of a predetermined color. In addition to various organic materials, the intermediate layer 603 may also include a metal-containing compound such as an organic metal compound, an inorganic material such as a quantum dot, and the like.

[0114] In an embodiment, the intermediate layer 603 may include a light-emitting layer and a first functional layer and a second functional layer respectively disposed below and above the light-emitting layer. The first functional layer may include, for example, a hole transport layer (HTL), or a hole transport layer and a hole injection layer (HIL). The second functional layer is a component disposed on the light-emitting layer and is optional. For example, the intermediate layer 603 may include or may not include a second functional layer. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0115] In an embodiment, the intermediate layer 603 may include two or more light emitting units sequentially stacked between the pixel electrode 601 and the common electrode 605 and a charge generation layer CGL disposed between the two light emitting units. When the intermediate layer 603 includes the light emitting unit and the charge generation layer CGL, the light emitting element LEL (e.g., an organic light emitting diode) may be a light emitting element LEL connected in series. The light emitting element LEL (e.g., an organic light emitting diode) may improve color purity and light emitting efficiency by having a stacked structure of a plurality of light emitting units.

[0116] One light-emitting unit may include a light-emitting layer and a first functional layer and a second functional layer disposed below and above the light-emitting layer, respectively. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. The luminous efficiency of an organic light-emitting diode as a light-emitting element LEL having a plurality of light-emitting layers connected in series may be further increased by the negative charge generation layer and the positive charge generation layer.

[0117] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0118] In an embodiment, if Figure 7 As shown in , the light emitting element LEL (e.g., an organic light emitting diode) may include a first light emitting unit EU1 and a second light emitting unit EU2 stacked in sequence, the first light emitting unit EU1 including a first light emitting layer EL1, and the second light emitting unit EU2 including a second light emitting layer EL2. The charge generation layer CGL may be disposed between the first light emitting unit EU1 and the second light emitting unit EU2. For example, the light emitting element LEL (e.g., an organic light emitting diode) may include a pixel electrode 601, a first light emitting layer EL1, a charge generation layer CGL, a second light emitting layer EL2, and a common electrode 605 stacked in sequence. The first functional layer and the second functional layer may be disposed below and above the first light emitting layer EL1, respectively. The first functional layer and the second functional layer may be disposed below and above the second light emitting layer EL2, respectively. The first light emitting layer EL1 may be a blue light emitting layer, and the second light emitting layer EL2 may be a yellow light emitting layer.

[0119] In an embodiment, if Figure 8As shown in , the light emitting element LEL (e.g., an organic light emitting diode) may include a first light emitting unit EU1 including a first light emitting layer EL1, a third light emitting unit EU3 including the first light emitting layer EL1, and a second light emitting unit EU2 including a second light emitting layer EL2. The first charge generation layer CGL1 may be disposed between the first light emitting unit EU1 and the second light emitting unit EU2, and the second charge generation layer CGL2 may be disposed between the second light emitting unit EU2 and the third light emitting unit EU3. For example, the light emitting element LEL (e.g., an organic light emitting diode) may include a pixel electrode 601, a first light emitting layer EL1, a first charge generation layer CGL1, a second light emitting layer EL2, a second charge generation layer CGL2, a first light emitting layer EL1, and a common electrode 605 stacked in sequence. The first functional layer and the second functional layer may be disposed below and above the first light emitting layer EL1, respectively. The first functional layer and the second functional layer may be disposed below and above the second light emitting layer EL2, respectively. The first light emitting layer EL1 may be a blue light emitting layer, and the second light emitting layer EL2 may be a yellow light emitting layer.

[0120] In an embodiment, in the light emitting element LEL (e.g., an organic light emitting diode), in addition to the second light emitting layer EL2, the second light emitting unit EU2 may further include a third light emitting layer and / or a fourth light emitting layer directly contacting the second light emitting layer EL2 below and / or above the second light emitting layer EL2. Here, the phrase "directly contacting" may mean that no other layer is disposed between the second light emitting layer EL2 and the third light emitting layer and / or between the second light emitting layer EL2 and the fourth light emitting layer. The third light emitting layer may be a red light emitting layer, and the fourth light emitting layer may be a green light emitting layer.

[0121] refer to Fig. 9 The light emitting element LEL (eg, an organic light emitting diode) may include a pixel electrode 601, a first light emitting layer EL1, a first charge generation layer CGL1, a third light emitting layer EL3, a second light emitting layer EL2, a second charge generation layer CGL2, a first light emitting layer EL1, and a common electrode 605 stacked in sequence.

[0122] refer to Fig.10 The light-emitting element LEL (e.g., an organic light-emitting diode) may include a pixel electrode 601, a first light-emitting layer EL1, a first charge generation layer CGL1, a third light-emitting layer EL3, a second light-emitting layer EL2, a fourth light-emitting layer EL4, a second charge generation layer CGL2, a first light-emitting layer EL1, and a common electrode 605 stacked in sequence.

[0123] Fig.11 It is shown Fig. 9 A cross-sectional view of an example of a light emitting element LEL. Fig.12 It is shown Fig.10A cross-sectional view of an example of a light emitting element LEL.

[0124] refer to Fig.11 , the light emitting element LEL (e.g., an organic light emitting diode) may include a first light emitting unit EU1, a second light emitting unit EU2, and a third light emitting unit EU3 stacked in sequence. The first charge generation layer CGL1 may be disposed between the first light emitting unit EU1 and the second light emitting unit EU2, and the second charge generation layer CGL2 may be disposed between the second light emitting unit EU2 and the third light emitting unit EU3. Each of the first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0125] The first light emitting unit EU1 may include a blue light emitting layer BEML. The first light emitting unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL located between the pixel electrode 601 and the blue light emitting layer BEML. In an embodiment, a p-doped layer PHIL may be further included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer PHIL may be formed by doping the hole injection layer HIL with a p-type doping material. In an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue light emitting layer BEML and the hole transport layer HTL. The blue light auxiliary layer may improve the emission efficiency of the blue light emitting layer BEML. The blue light auxiliary layer may improve the emission efficiency of the blue light emitting layer BEML by adjusting the hole charge balance. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted from the light emitting layer.

[0126] The second light emitting unit EU2 may include a yellow light emitting layer YEML and a red light emitting layer REML directly contacting the yellow light emitting layer YEML below the yellow light emitting layer YEML. The second light emitting unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may further include an electron transport layer ETL between the yellow light emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0127] The third light-emitting unit EU3 may include a blue light-emitting layer BEML. The third light-emitting unit EU3 may also include a hole transport layer HTL located between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue light-emitting layer BEML. The third light-emitting unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL located between the blue light-emitting layer BEML and the common electrode 605. The electron transport layer ETL may be a single layer or a multilayer. In an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue light-emitting layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may also be included between the blue light-emitting layer BEML and the electron transport layer ETL. The hole blocking layer may prevent holes from being injected into the electron transport layer ETL.

[0128] Fig.12 The light emitting element LEL (eg, organic light emitting diode) shown in FIG. Fig.11 The light emitting element LEL (eg, organic light emitting diode) shown in FIG. 1 is different from the light emitting element LEL (eg, organic light emitting diode) in the stacked structure of the second light emitting unit EU2 and is similar to the light emitting element LEL (eg, organic light emitting diode) in other configurations. Fig.11 The light emitting elements LEL (eg, organic light emitting diodes) shown in FIG. Fig.12 , the second light emitting unit EU2 may include a yellow light emitting layer YEML, a red light emitting layer REML directly contacting the yellow light emitting layer YEML below the yellow light emitting layer YEML, and a green light emitting layer GEML directly contacting the yellow light emitting layer YEML above the yellow light emitting layer YEML. The second light emitting unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may further include an electron transport layer ETL between the green light emitting layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0129] Fig.13 is a cross-sectional view showing a structure of a pixel of a display device according to an embodiment.

[0130] refer to Fig.13 , the display panel 110 of the display device 10 (see Figure 1 ) may include a plurality of pixels (e.g., sub-pixels). The plurality of pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode 601, a common electrode 605, and an intermediate layer 603. In one embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel.

[0131] The pixel electrode 601 may be independently provided in each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0132] The intermediate layer 603 of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first light emitting unit EU1 and a second light emitting unit EU2 stacked in sequence and a charge generation layer CGL located between the first light emitting unit EU1 and the second light emitting unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and interconnected with each other. Such a charge generation layer CGL may be a common layer and may cause leakage current between adjacent pixels. Accordingly, as will be described later with reference to Figures 14 to 20 As described, the present invention conceives to arrange the aging wiring 1410 between adjacent pixels, and to age the portion of the charge generation layer CGL located between the adjacent pixels using the aging wiring 1410. The aged charge generation layer CGL changes its shape and its resistance increases. Accordingly, the charge generation layer CGL is commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and connected to each other, but by including Fig.15 The aging part AEL in the circuit can block the leakage current.

[0133] The first light emitting unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red light emitting layer REML, and an electron transport layer ETL sequentially stacked on the pixel electrode 601. The first light emitting unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 601. The first light emitting unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue light emitting layer BEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 601. The hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the plurality of first light emitting units EU1 may be stacked in common and may be common layers connected to each other. At least among some of these common layers (e.g., layers HIL, HTL, ETL), at least some of the common layers located between adjacent pixels may be aged using the aging wiring 1410 like the charge generation layer CGL. At least some of the aged common layers may be commonly stacked in the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 and connected to each other, but include the aged portion AEL, thereby blocking the leakage current.

[0134] The second light emitting unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red light emitting layer REML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second light emitting unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second light emitting unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue light emitting layer BEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. Each of the hole transport layers HTL and the electron transport layers ETL of the plurality of second light emitting units EU2 may be commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and may be a common layer connected to each other. In an embodiment, in the second light emitting unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3, at least one of a hole blocking layer and a buffer layer may be further included between the light emitting layer and the electron transport layer ETL. At least in some of the common layers (e.g., layers HTL, ETL), portions of at least some of the common layers located between adjacent pixels may be aged like the charge generation layer CGL using the aging wiring 1410. At least some of the aged common layers may be commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and connected to each other, but include an aging portion AEL, thereby blocking leakage current.

[0135] The thickness H1 of the red light emitting layer REML, the thickness H2 of the green light emitting layer GEML, and the thickness H3 of the blue light emitting layer BEML may be determined according to the resonance distance. The auxiliary layer AXL may be a layer added to adjust the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer AXL may include the same material as that of the hole transport layer HTL.

[0136] exist Fig.13 In the embodiment, the auxiliary layer AXL may be disposed only in the first pixel PX1, but the embodiments of the present disclosure are not limited thereto. For example, the auxiliary layer AXL may be disposed in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonance distance of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0137] According to an embodiment, the display panel 110 may further include a cover layer 607 disposed outside the common electrode 605. The cover layer 607 may be used to improve the luminous efficiency through the principle of constructive interference. Accordingly, the light extraction efficiency of the light emitting element LEL (e.g., an organic light emitting diode) may be increased, thereby improving the luminous efficiency of the light emitting element LEL (e.g., an organic light emitting diode).

[0138] Fig.14 is a plan view schematically showing a portion of a pixel of a display panel 110 according to an embodiment. Fig.15 is shown along Fig.14 FIG. 1 is a diagram of a portion of a cross section of a display panel taken along line AA'. For example, Fig.15 Shown is a reference Figure 5 A portion of the light emitting element layer 503 of the display panel 110 is described. Accordingly, it should be understood that Fig.15 The upper and lower parts of the components shown are further provided with reference Figure 5 Describes the layer. Fig.15 In the present invention, the light emitting layer EL may refer to Figures 6 to 13 The middle layer 603 is described.

[0139] refer to Fig.14 and Fig.15 According to the embodiment, the display panel 110 includes a pixel defining film PDL, and the pixel defining film PDL divides a plurality of pixels including a first pixel PX1, a second pixel PX2, and a third pixel PX3. In the pixel defining film PDL disposed between adjacent (i.e., mutually adjacent) pixels, a light emitting layer EL (e.g., anode) disposed between a pixel electrode ANE (e.g., anode) and a common electrode CAE (e.g., cathode) is provided. Figure 5 The aging wiring 1410 is a wiring for aging some conductive layers corresponding to the common layer among the light emitting layer EL in the aging wiring 1410. Here, the common layer aged by the aging wiring 1410 refers to the reference Figures 6 to 13 At least one layer among the charge generation layer CGL, the hole injection layer HIL, the hole transport layer HTL, the electron transport layer ETL and the p-doped layer PHIL is described.

[0140] According to an embodiment, the aging wiring 1410 may be disposed in a portion of the pixel defining film PDL located between adjacent (i.e., adjacent to each other) pixels, and may be disposed in a mesh shape. For example, the aging wiring 1410 includes a first aging wiring 1411 arranged to extend in a second direction DR2 and a second aging wiring 1412 arranged to extend in a first direction DR1 perpendicular to the second direction DR2. The first aging wiring 1411 and the second aging wiring 1412 may be formed in the same layer. The first aging wiring 1411 is arranged to pass between the columns of a plurality of pixels in the second direction DR2. The second aging wiring 1412 is arranged to pass between the rows of a plurality of pixels in the first direction DR1.

[0141] According to an embodiment, the aging wiring 1410 may be formed at the same layer as the pixel electrode ANE of each of the plurality of pixels. For example, the material of the aging wiring 1410 may be the same as that of the pixel electrode ANE.

[0142] According to an embodiment, the aging wiring 1410 is disposed to face the common electrode CAE when viewed in a cross section of the display panel 110. Accordingly, when power is applied to the aging wiring 1410, a vertical electric field is formed between the aging wiring 1410 and the common electrode CAE, and the electric field ages the common layer around the aging wiring 1410. Here, aging the common layer means damaging some of the conductive layers included in the common layer to change its shape and intentionally increase the resistance of the corresponding region.

[0143] According to an embodiment, the aging process of the common layer using the aging wiring 1410 is performed after the display panel 110 is manufactured. During the aging process, a specified voltage is applied to the aging wiring 1410. The specified voltage may be about 50V, but the inventive concept is not necessarily limited thereto. When the specified voltage is applied to the aging wiring 1410, a vertical electric field is formed between the aging wiring 1410 and the common electrode CAE, and some conductive layers corresponding to the common layer in the light emitting layer EL are aged by the vertical electric field. A portion of the aged conductive layer changes its shape and its resistance increases. Accordingly, the common layer may be commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and connected to each other, but leakage current may be blocked by including an aging portion AEL.

[0144] According to an embodiment, the aging wiring 1410 may be disposed in an opening of a pixel defining film PDL. For example, the display panel 110 includes a pixel defining film PDL for separating a plurality of pixels, and the pixel defining film PDL includes a first opening OP1 corresponding to each of the plurality of pixels. The pixel electrode ANE of each of the plurality of pixels may be disposed in each of the first openings OP1. In addition, the pixel defining film PDL includes a second opening OP2 arranged to pass between columns of a plurality of pixels in a second direction DR2 and a third opening OP3 arranged to pass between rows of a plurality of pixels in a first direction DR1. The mesh-shaped aging wiring 1410 may be disposed in each of the second opening OP2 and the third opening OP3. For example, the first aging wiring 1411 is disposed in the second opening OP2 to pass between columns of a plurality of pixels in a second direction DR2. The second aging wiring 1412 is disposed in the third opening OP3 to pass between rows of a plurality of pixels in a first direction DR1.

[0145] According to an embodiment, the aging wiring 1410 receives an aging signal of a specified voltage through a aging pad 1420 provided in the non-display area NDA. The aging pad 1420 may be electrically connected to the aging wiring 1410 through an aging signal supply wiring or may be directly connected to the aging wiring 1410.

[0146] In the case of an embodiment in which the aging wiring 1410 is directly connected to the aging pad 1420 , the aging wiring 1410 may have a mesh shape, but a portion thereof may extend to the non-display area NDA outside the display area DA and be connected to the aging pad 1420 .

[0147] In the case of an embodiment in which an aging signal supply wiring (not shown) connecting the aging wiring 1410 and the aging pad 1420 is provided, the aging signal supply wiring may be provided at a position located at the light emitting element layer 503 (see Figure 5 ) below the wiring layer 502 (see Figure 5 ), and the aging wiring 1410 and the aging signal supply wiring may be electrically connected to each other through a contact hole penetrating at least a portion of the wiring layer 502. The aging signal supply wiring may extend to the non-display area NDA outside the display area DA and be connected to the aging pad 1420.

[0148] exist Fig.14 , a single aging pad 1420 is shown, but considering the increase in resistance of the aging wiring 1410, the display panel 110 may include a plurality of aging pads 1420. The plurality of aging pads 1420 may be arranged at intervals in the non-display area NDA located on one side (e.g., left direction) of the display area DA to send an aging signal to a plurality of aging wiring 1410 groups including the aging wiring 1410. Alternatively, the plurality of aging pads 1420 may be provided in the non-display area NDA located on one side (e.g., left direction) and the other side (e.g., right direction) of the display area DA to supply an aging signal to the aging wiring 1410.

[0149] exist Fig.15 , the pixel defining film PDL is illustrated as not covering the burn-in wiring, but the inventive concept is not limited thereto, and portions of both ends of the burn-in wiring may be covered by the pixel defining film PDL.

[0150] Fig.16 16 is a plan view of the display panel 110 showing an example in which a pair of aging wirings 1610 are provided between pixels. Fig.17 is shown along Fig.16 FIG. 1 is a diagram of a portion of a cross section of a display panel taken along line BB′.

[0151] Fig.16 and Fig.17 The implementation method can be Fig.14 and Fig.15 The embodiments of the present invention are at least partially similar. Fig.14 and Fig.15 Different implementation methods Fig.16 and Fig.17Therefore, Fig.16 and Fig.17 Features not described in Fig.14 and Fig.15 The description of the implementation method is replaced.

[0152] Fig.16 and Fig.17 The implementation method and Fig.14 and Fig.15 The difference of the embodiment of is that the paired aging wiring 1610 is arranged at intervals between adjacent pixels. For example, the first aging wiring 1611 is arranged in the second opening OP2 to pass between the columns of the plurality of pixels in the second direction DR2, but the first aging wiring 1611 is a pair of wirings arranged at intervals from each other. In addition, the second aging wiring 1612 is arranged in the third opening OP3 to pass between the rows of the plurality of pixels in the first direction DR1, but the second aging wiring 1612 is a pair of wirings arranged at intervals from each other.

[0153] Different voltages may be applied to a pair of aging wirings 1610 to form a horizontal electric field between the pair of aging wirings 1610. The horizontal electric field ages at least a portion of the common layer located around the pair of aging wirings 1610. The voltage applied to each of the pairs of aging wirings 1610 may have a voltage difference of, for example, about 50 V, but the inventive concept is not necessarily limited thereto.

[0154] exist Fig.17 , the pixel defining film PDL is illustrated as not covering the burn-in wiring, but the inventive concept is not limited thereto, and portions of both ends of the burn-in wiring may be covered by the pixel defining film PDL.

[0155] Fig.18 18 is a cross-sectional view of a display panel showing an example in which a burn-in wiring 1811 is provided on a pixel defining film PDL.

[0156] refer to Fig.18 , the aging wiring 1811 according to the embodiment may be provided on the pixel definition film PDL. Fig.18 In the implementation mode, different from Figures 14 to 16 In an embodiment, the pixel definition film PDL does not include the second opening OP2 and the third opening OP3, and the aging wiring 1811 is disposed on the pixel definition film PDL. Fig.18 In the case of the embodiment of FIG. 5 , the aging wiring 1811 may be electrically connected to the aging signal supply wiring (not shown) through a contact hole (not shown) penetrating the pixel definition film PDL and at least a portion of the wiring layer 502 .

[0157] Fig.1914 is a plan view of the display panel 110 showing an example in which the burn-in wiring 1410 is not formed in a mesh structure.

[0158] Fig.19 The implementation method can be Fig.14 and Fig.15 The embodiments of the present invention are at least partially similar. Fig.14 and Fig.15 Different implementation methods Fig.19 Therefore, Fig.19 Features not described in Fig.14 and Fig.15 The description of the implementation method is replaced.

[0159] exist Fig.19 In the implementation mode, different from Fig.14 and Fig.15 In an embodiment of the present invention, the aging wiring 1410 may not be formed in a mesh shape, but may be arranged to cross each other between adjacent pixels. For example, the aging wiring 1410 includes a first aging wiring 1411 arranged to pass between columns of a plurality of pixels in a second direction DR2 and a second aging wiring 1412 arranged to pass between rows of a plurality of pixels in a first direction DR1. The first aging wiring 1411 and the second aging wiring 1412 may be disposed in different layers and cross each other between adjacent pixels, but may be electrically connected to each other through the contact hole 1911.

[0160] According to an embodiment, the first aging wiring 1411 may be disposed on a different layer from the pixel electrode ANE, and the second aging wiring 1412 may be disposed on the same layer as the pixel electrode ANE. For example, the first aging wiring 1411 may be disposed on at least a portion of the wiring layer 502. On the other hand, unlike the above example, the second aging wiring 1412 may be placed on the same layer as the pixel electrode ANE, and the first aging wiring 1411 may be placed on a different layer from the pixel electrode ANE.

[0161] Fig. 20 is a flowchart illustrating a method of manufacturing a display device according to an embodiment.

[0162] Can be omitted Fig. 20 At least some of the steps of the manufacturing process shown in FIG. Fig. 20 Before or after each of the steps of the manufacturing process shown in FIG. 1 , a manufacturing process of a display device described with reference to this document or known in the art may be additionally performed.

[0163] In the following, reference will be made to Fig. 20 A method of manufacturing a display device according to an embodiment is described.

[0164] In step 2010, a semiconductor wafer substrate 200 (see Figure 5 ), and a CMOS circuit layer (eg, Figure 5 The MOSFET layer 501 in the CMOS circuit layer includes an N-type MOSFET and / or a P-type MOSFET. The first type impurity may be a P-type impurity, and the second type impurity may be an N-type impurity. Alternatively, the first type impurity may be an N-type impurity and the second type impurity may be a P-type impurity. The MOSFET MOS in the CMOS circuit layer (see Figure 5 ) constitutes the display driving circuit 210 (see Figure 2 ) and pixel drive circuit PC (see Figure 4 ).

[0165] In step 2020, a wiring process may be performed to form at least one wiring layer 502 on the CMOS circuit layer (see Figure 5 ). At least one wiring layer 502 may include a plurality of insulating layers VIA sequentially stacked on the MOSFET layer 501 (see Figure 5 ) and a contact hole CT1 (see Figure 5 ) is connected to the wiring (not shown) of the MOSFET MOS and the electrode CE (see Figure 5 ).

[0166] The wiring layer 502 may include a wiring layer disposed in contact with the non-display area NDA (see Figure 5 ) corresponding to the pad electrodes PD1, PD2, PD3, PD4, PD5, PD6 and PD7 (see Figure 5 ). The pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 may include pad electrodes connected to the first gate line GWL (see Figure 4 ) connected to the first gate pad PD1 and the second gate line GIL (see Figure 4 ) connected to the second gate pad PD2 and the initialization line VIL (see Figure 4 ) connected to the initialization pad PD3, and the emission control line EML (see Figure 4 ) connected to the light emitting pad PD4 and the data line DL (see Figure 4 ) connected to the data pad PD5, and the first driving voltage line VDL (see Figure 4 ) and the first driving voltage pad PD6 connected to the second driving voltage line VSL (see Figure 4 ) is connected to the second driving voltage pad PD7. However, Figure 5The pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 shown in FIG. 1 are merely examples, and the present disclosure is not limited thereto. For example, the wiring layer 502 may further include a wiring layer connected to an aging signal supply wiring (not shown) or an aging wiring 1410 (see FIG. 14 ) in the non-display area NDA. Fig.14 ) of the aged pad 1420 (see Fig.14 ). The aging pad 1420 may be electrically connected to the aging wiring 1410 through an aging signal supply wiring or may be directly connected to the aging wiring 1410 .

[0167] In step 2030, a light emitting element layer 503 may be formed on the wiring layer 502 (see Figure 5 ). The light emitting element layer 503 may further include a plurality of pixels PX separated (see Figure 3 ) each of the pixel definition films PDL (see Figure 5 Each of the plurality of pixels PX includes a pixel electrode ANE (see Figure 5 ), a light-emitting layer EL (see Figure 5 ) and a common electrode CAE disposed on the light emitting layer EL (see Figure 5 ).

[0168] The light emitting layer EL is an intermediate layer 603 (see Figure 6 ) and may include a polymer or low-molecular organic material that emits light of a predetermined color. In addition to various organic materials, the intermediate layer 603 may also include a metal-containing compound such as an organic metal compound, an inorganic material such as a quantum dot, and the like.

[0169] The intermediate layer 603 includes a first pixel PX1, a second pixel PX2, and a third pixel PX3 (see FIG. Fig.13 ) and connected to each other. Common layer means reference Figures 6 to 13 At least one layer among the charge generation layer CGL, the hole injection layer HIL, the hole transport layer HTL, the electron transport layer ETL and the p-doped layer PHIL is described.

[0170] In step 2040, an aging process may be performed in which a specified voltage is supplied to an aging wiring 1410 disposed between adjacent pixels during a specified time. According to an embodiment, an aging process for a common layer using the aging wiring 1410 is performed after the display panel is manufactured. During the aging process, a specified voltage is applied to the aging wiring 1410. The specified voltage may be approximately 50V, but the inventive concept is not necessarily limited thereto. When a specified voltage is applied to the aging wiring 1410, a vertical electric field is formed between the aging wiring 1410 and the common electrode CAE, and some conductive layers corresponding to the common layer in the light emitting layer EL are aged by the vertical electric field. A portion of the aged conductive layer changes its shape and its resistance increases. Accordingly, the common layer may be commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and connected to each other, but leakage current may be blocked by including an aging portion AEL.

[0171] Fig.21 is an exemplary view of a VR device 2100 including a display device according to an embodiment.

[0172] The display device 10 according to the embodiment (see Figure 1 ) may be included in a mobile electronic device. The display device 10 according to an embodiment may be included in a wearable device developed in the form of glasses or a helmet and forming a focus at a short distance from the user's eyes. For example, the wearable device may be an HMD or augmented reality (AR) glasses. Such a wearable device provides an AR screen or a virtual reality (VR) screen to the user.

[0173] Fig.21 FIG. 2 shows a VR device 2100 to which a display device 2160 according to an embodiment is applied. Here, the display device 2160 may include the above-mentioned Figures 1 to 19 components.

[0174] refer to Fig.21 According to an embodiment, the VR device 2100 may be an AR glasses in the form of glasses. According to an embodiment, the VR device 2100 may include a display device 2160, a left lens 2111, a right lens 2112, a support frame 2120, glasses frame legs 2131 and 2132, a reflective member 2140, and a housing unit 2150.

[0175] Despite Fig.21 The VR device 2100 in the form of AR glasses is exemplified in the embodiment, but the VR device 2100 according to the embodiment can be applied to HMD. That is, the VR device 2100 according to the embodiment is not limited to Fig.21 The device shown in the figure can be applied to various other mobile electronic devices in various forms.

[0176] The housing unit 2150 may include a display device 2160 and a reflective member 2140. The image displayed on the display device 2160 may be reflected by the reflective member 2140 and provided to the right eye of the user through the right lens 2112. Accordingly, the user may view the VR image displayed on the display device 2160 through the right eye.

[0177] Although the accommodation unit 2150 is arranged in Fig.21 , but the present disclosure is not limited thereto. For example, the accommodating unit 2150 may also be disposed at the left end of the supporting frame 2120. In this case, the image displayed on the display device 2160 may be reflected by the reflective member 2140 and provided to the user's left eye through the left lens 2111. Accordingly, the user may view the VR image displayed on the display device 2160 through the left eye. Alternatively, the accommodating unit 2150 may be disposed at both the right end and the left end of the supporting frame 2120. In this case, the user may view the VR image displayed on the display device 2160 through both the left eye and the right eye.

[0178] Fig. 22 and Fig.23 : is an exemplary view showing an HMD device to which the display device according to the embodiment is applied.

[0179] refer to Fig. 22 and Fig.23 According to the display device 10 of the embodiment (see Figure 1 ) can be applied to an HMD device. The HMD device includes a first display device 2310 and a second display device 2320, each of which may be the display device 10 according to an embodiment. The first display device 2310 provides an image to the right eye of the user, and the second display device 2320 provides an image to the left eye of the user.

[0180] The first lens array 2330 may be disposed between the first display device 2310 and the receiving unit cover 2210. The first lens array 2330 may include a plurality of lenses 2331. The plurality of lenses 2331 may be formed as convex lenses that protrude in a direction of the receiving unit cover 2210.

[0181] The second lens array 2340 may be disposed between the second display device 2320 and the receiving unit cover 2210. The second lens array 2340 may include a plurality of lenses 2341. The plurality of lenses 2341 may be formed as convex lenses convex in a direction of the receiving unit cover 2210.

[0182] The accommodating unit 2230 is used to accommodate the first display device 2310, the second display device 2320, the first lens array 2330 and the second lens array 2340. In order to accommodate the first display device 2310, the second display device 2320, the first lens array 2330 and the second lens array 2340, one surface of the accommodating unit 2230 may be open.

[0183] The accommodating unit cover 2210 is provided to cover the opening surface of the accommodating unit 2230. The accommodating unit cover 2210 may include a first opening 2221 at which a right eye of a user is provided and a second opening 2222 at which a left eye of a user is provided. Fig. 22 and Fig.23 2 shows that the first opening 2221 and the second opening 2222 are formed in a quadrilateral shape, but the present disclosure is not limited thereto. The first opening 2221 and the second opening 2222 may be formed in a circular shape or an elliptical shape. Alternatively, the first opening 2221 and the second opening 2222 may be combined to form one opening.

[0184] The first opening 2221 may be aligned with the first display device 2310 and the first lens array 2330, and the second opening 2222 may be aligned with the second display device 2320 and the second lens array 2340. Therefore, the user may view the image of the first display device 2310 magnified as a virtual image by the first lens array 2330 through the first opening 2221, and may view the image of the second display device 2320 magnified as a virtual image by the second lens array 2340 through the second opening 2222.

[0185] The head mounting band 2240 is used to fix the accommodating unit 2230 to the user's head so that the first opening 2221 and the second opening 2222 of the accommodating unit cover 2210 are respectively disposed on the right eye and the left eye of the user. The head mounting band 2240 may be connected to the upper surface, the left side surface, and the right side surface of the accommodating unit 2230.

[0186] At the end of the detailed description, it will be appreciated by those skilled in the art that many variations and modifications can be made to the embodiments without departing substantially from the principles of the inventive concept. Therefore, the embodiments of the inventive concept disclosed are used only in a general and descriptive sense and not for a limiting purpose.

Claims

1. A display device, comprising: Semiconductor wafer substrate; A complementary metal oxide semiconductor circuit layer, wherein the complementary metal oxide semiconductor circuit layer is disposed on the semiconductor wafer substrate; as well as a light emitting element layer, wherein the light emitting element layer is disposed on the complementary metal oxide semiconductor circuit layer, Wherein, the light emitting element layer comprises: A pixel defining film, wherein the pixel defining film separates a plurality of pixels; a pixel electrode independently disposed in each of the plurality of pixels; An aging wiring, wherein the aging wiring is arranged between the plurality of pixels; a light emitting layer that commonly covers the pixel electrode and the burn-in wiring of each of the plurality of pixels; and a common electrode, the common electrode covering the light emitting layer, The portion of the light emitting layer located between the aging wiring and the common electrode includes an aged portion where at least some of the conductive layers included in the light emitting layer are aged.

2. The display device according to claim 1, in, The aged portion of the light emitting layer has the conductive layer having a higher resistance than other portions of the light emitting layer.

3. The display device according to claim 1, in, The pixel definition film comprises: a first opening, wherein the pixel electrode is disposed in the first opening; and A second opening and a third opening, wherein the burn-in wiring is arranged in the second opening and the third opening.

4. The display device according to claim 3, in, The aging wiring comprises: a first aging wiring disposed in the second opening to pass between respective columns of the plurality of pixels; and A second aging wiring is provided in the third opening to pass between the respective rows of the plurality of pixels.

5. The display device according to claim 4, in, The aging wiring has a mesh shape in which the first aging wiring and the second aging wiring are located in the same layer.

6. The display device according to claim 5, in, The first aging wiring and the second aging wiring are provided in the same layer as the pixel electrode.

7. The display device according to claim 4, in, The first aging wiring and the second aging wiring are provided in different layers.

8. The display device according to claim 7, in, The first aging wiring and the pixel electrode are arranged in different layers, and Wherein, the second aging wiring and the pixel electrode are arranged on the same layer.

9. The display device according to claim 4, in, Each of the first aging wiring and the second aging wiring includes a pair of wirings arranged between adjacent pixels with a gap between them.

10. The display device according to claim 1, in, The at least some conductive layers included in the light emitting layer include at least one layer among a charge generation layer, a hole injection layer, a hole transport layer, an electron transport layer, and a p-doped layer.

11. A method for manufacturing a display device, comprising: forming a complementary metal oxide semiconductor circuit layer on a semiconductor wafer substrate; forming a light-emitting element layer including a pixel electrode, a light-emitting layer and a common electrode on the complementary metal oxide semiconductor circuit layer; as well as aging at least some of the conductive layers included in the light emitting layer by supplying a specified voltage to an aging wiring provided between a plurality of pixels during a specified time, Wherein, at least some of the conductive layers have an increased resistance between the plurality of pixels due to aging.

12. The method according to claim 11, in, The forming of the light emitting element layer includes forming a pixel definition film separating the plurality of pixels. Wherein, the pixel defining film comprises: a first opening, wherein the pixel electrode is disposed in the first opening; and A second opening and a third opening, wherein the burn-in wiring is arranged in the second opening and the third opening.

13. The method according to claim 12, in, The aging wiring comprises: a first aging wiring disposed in the second opening to pass between respective columns of the plurality of pixels; and A second aging wiring is provided in the third opening to pass between the respective rows of the plurality of pixels.

14. The method according to claim 13, in, The aging wiring has a mesh shape in which the first aging wiring and the second aging wiring are formed in the same layer.

15. The method according to claim 14, further comprising: The first aging wiring and the second aging wiring are formed in the same layer as the pixel electrode.

16. The method according to claim 13, in, The first aging wiring and the second aging wiring are provided in different layers.

17. The method according to claim 16, in, The first aging wiring and the pixel electrode are arranged in different layers, and Wherein, the second aging wiring and the pixel electrode are arranged on the same layer.

18. The method according to claim 13, in, Each of the first aging wiring and the second aging wiring includes a pair of wirings arranged between adjacent pixels with a gap between them.

19. The method according to claim 11, in, The at least some conductive layers included in the light emitting layer include at least one layer among a charge generation layer, a hole injection layer, a hole transport layer, an electron transport layer, and a p-doped layer.

20. The method according to claim 11, in, The specified voltage supplied to the burn-in wiring is 50V.

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