Semiconductor device

Abstract

A semiconductor device includes: a landing pad on a substrate; a lower electrode extending in a vertical direction on the landing pad, the lower electrode being connected to the landing pad; a capacitor dielectric layer on the lower electrode; a doped layer between the lower electrode and the capacitor dielectric layer, the doped layer being in contact with each of the lower electrode and the capacitor dielectric layer, the doped layer being doped with a first material having three valence electrons, a second material having four valence electrons, and a third material having five valence electrons; and an upper electrode on the capacitor dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] A buried channel array transistor (BCAT) may include a gate electrode buried in a trench to overcome the short channel effect of a DRAM structure.

[0003] As semiconductor devices become more and more highly integrated, individual circuit patterns become increasingly finer in order to implement more semiconductor devices in the same area. That is, the design rules of the components of semiconductor devices are being reduced. As DRAM devices are also being integrated, the amount of charge that can be stored in a capacitor is constantly decreasing. Therefore, research is being conducted to increase the amount of charge stored in a capacitor and attenuate leakage characteristics. Summary of the invention

[0004] An example embodiment of the present inventive concept provides a semiconductor device in which a doped layer doped with all of a first material having three valence electrons, a second material having four valence electrons, and a third material having five valence electrons is formed on the surface of a lower electrode to increase its capacitance, reduce its bridge defects, and improve the distribution of the third material.

[0005] An example embodiment of the present invention provides a semiconductor device including: a landing pad on a substrate; a lower electrode extending in a vertical direction on the landing pad, the lower electrode being connected to the landing pad; a capacitor dielectric layer on the lower electrode; a doping layer between the lower electrode and the capacitor dielectric layer, the doping layer contacting each of the lower electrode and the capacitor dielectric layer, the doping layer being doped with a first material, a second material, and a third material, the first material having three valence electrons, the second material having four valence electrons, and the third material having five valence electrons; and an upper electrode on the capacitor dielectric layer.

[0006] An example embodiment of the inventive concept also provides a semiconductor device, the semiconductor device comprising: a landing pad located on a substrate; a lower electrode, the lower electrode extending in a vertical direction on the landing pad, the lower electrode connected to the landing pad; a first support pattern, the first support pattern located on at least one side of the lower electrode, the first support pattern in contact with a sidewall of the lower electrode; a second support pattern, the second support pattern located on at least one side of the lower electrode, the second support pattern in contact with the sidewall of the lower electrode, the second support pattern spaced apart from the first support pattern in a vertical direction; a capacitor dielectric layer, the capacitor dielectric layer located on the lower electrode and the second support pattern; and a doping layer, the doping layer located between the lower electrode and the capacitor dielectric layer, the doping layer in contact with each of the lower electrode and the capacitor dielectric layer, the doping layer being doped with a first material, a second material, and a third material, the first material having three valence electrons, the second material having four valence electrons, and the third material having five valence electrons. At least a portion of the doping layer is in contact with the sidewall of the second support pattern on an upper surface of the lower electrode.

[0007] An example embodiment of the inventive concept also provides a semiconductor device, the semiconductor device comprising: a landing pad located on a substrate; a lower electrode, the lower electrode extending in a vertical direction on the landing pad, the lower electrode connected to the landing pad; a first support pattern, the first support pattern located on at least one side of the lower electrode, the first support pattern in contact with a sidewall of the lower electrode; a second support pattern, the second support pattern located on at least one side of the lower electrode, the second support pattern in contact with the sidewall of the lower electrode, the second support pattern spaced apart from the first support pattern in a vertical direction; a capacitor dielectric layer, the capacitor dielectric layer located on the lower electrode and the second support pattern; a doping layer, the doping layer located between the lower electrode and the capacitor dielectric layer and between an upper surface of the second support pattern and the capacitor dielectric layer, the doping layer in contact with each of the lower electrode, the capacitor dielectric layer, and the upper surface of the second support pattern, the doping layer being doped with a first material, a second material, and a third material, the first material having three valence electrons, the second material having four valence electrons, and the third material having five valence electrons; and an upper electrode, the upper electrode being located on the capacitor dielectric layer. At least a portion of the doping layer is in contact with the sidewall of the second support pattern on the upper surface of the lower electrode. The atomic percentage of the first material doped in the doping layer is less than the atomic percentage of the third material doped in the doping layer. The doping layer on the upper surface of the lower electrode has a first thickness in the vertical direction, and the doping layer on the upper surface of the second support pattern has a second thickness in the vertical direction, and the first thickness is greater than the second thickness.

[0008] The objects of the inventive concept are not limited to those mentioned above, and those skilled in the art will clearly understand other objects of the inventive concept not mentioned herein from the following description of the inventive concept. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present inventive concept will become more apparent by describing in detail some example embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0010] Figure 1 are diagrams illustrating semiconductor devices according to some example embodiments of the inventive concept;

[0011] Figure 2 It is shown Figure 1 An enlarged view of region R1;

[0012] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 It shows the production Figure 1 diagrams showing intermediate steps of a method for illustrating a semiconductor device;

[0013] Fig.10 are diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept;

[0014] Fig.11 It is shown Fig.10 A magnified view of the R2 region is shown;

[0015] Fig.12 , Fig.13 and Fig.14 It shows the production Fig.10 diagrams showing intermediate steps of a method for illustrating a semiconductor device;

[0016] Fig.15 are diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept;

[0017] Fig.16 are diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept;

[0018] Fig.17 are diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept;

[0019] Fig.18 are layout diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept;

[0020] Fig.19 is a perspective view showing a semiconductor device according to some other example embodiments of the inventive concept;

[0021] Fig. 20 It is along Fig.18 A cross-sectional view taken along line FF and line GG;

[0022] Fig.21 are layout diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept; and

[0023] Fig. 22 is a perspective view illustrating a semiconductor device according to some other example embodiments of the inventive concept. DETAILED DESCRIPTION

[0024] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, the associated numerical value is intended to include a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it means that the precision of the geometric shape is not required, but the range of variation of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "approximately" or "substantially", it should be understood that these numerical values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0025] In addition, for example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as, for example, ABC, AB, BC, and AC.

[0026] In the following, reference will be made to Figure 1 and Figure 2 Semiconductor devices according to some example embodiments of the inventive concepts are described.

[0027] Figure 1 are diagrams illustrating semiconductor devices according to some example embodiments of the inventive concept. Figure 2 It is shown Figure 1 Magnified view of region R1.

[0028] refer to Figure 1 and Figure 2 , a semiconductor device according to some example embodiments of the present inventive concept includes a substrate 100, a first interlayer insulating layer 110, a storage contact 115, a landing pad 118, an etch stop layer 120, a lower electrode 130, a first support pattern 141, a second support pattern 142, a doping layer 150, a capacitor dielectric layer 160, an upper electrode 170, and a second interlayer insulating film 180.

[0029] The substrate 100 may be bulk silicon or silicon on insulator (SOI). Alternatively, the substrate 100 may include a silicon substrate, or may include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. The following description will be based on the substrate 100 being a silicon substrate.

[0030] Although not shown, a gate electrode used as a word line may be provided inside the substrate 100. A cell active region and a device isolation region may be formed in the substrate 100. For example, two transistors may be formed in one cell active region.

[0031] Hereinafter, each of the first horizontal direction DR1 and the second horizontal direction DR2 may be defined as a direction parallel to the upper surface of the substrate 100. The vertical direction DR3 may be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 may be defined as a direction perpendicular to the upper surface of the substrate 100.

[0032] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a low-k material, or a combination thereof. The storage contact 115 may be disposed inside the first interlayer insulating layer 110 on the substrate 100. The landing pad 118 may be disposed inside the first interlayer insulating layer 110 on the substrate 100. The landing pad 118 may be disposed on the storage contact 115. The landing pad 118 may be connected to the substrate 100 via the storage contact 115. The landing pad 118 may be electrically connected to a conductive region formed on or in the substrate 100. Each of the storage contact 115 and the landing pad 118 may include a conductive material.

[0033] The etch stop layer 120 may be disposed on the first interlayer insulating layer 110. The etch stop layer 120 may surround a portion of a sidewall of the lower electrode 130 formed adjacent to an upper surface of the first interlayer insulating layer 110. The etch stop layer 120 may include a layer containing an oxide relative to the first mold layer ( Figure 3 10) and the second molding layer ( Figure 3 The etch stop layer 120 may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxycarbide (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), or silicon oxycarbonitride (SiO). For example, silicon oxycarbide (SiCO) includes silicon (Si), carbon (C), and oxygen (O), but does not mean the ratio of silicon (Si), carbon (C), and oxygen (O).

[0034] A plurality of lower electrodes 130 may be disposed on the landing pad 118. Each of the plurality of lower electrodes 130 is connected to the landing pad 118. Each of the plurality of lower electrodes 130 may extend longitudinally in the vertical direction DR3. For example, the length of the lower electrode 130 extending in the vertical direction DR3 is greater than the length of the lower electrode 130 extending in the first horizontal direction DR1. Alternatively, the length of the lower electrode 130 extending in the vertical direction DR3 is greater than the width of the lower electrode 130 in the first horizontal direction DR1. For example, the lower electrode 130 may have a columnar shape. For example, a portion of the lower surface of the lower electrode 130 and a portion of the sidewall of the lower portion of the lower electrode 130 may contact the etch stop layer 120.

[0035] The lower electrode 130 may include, for example, a conductive metal nitride (eg, titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (eg, ruthenium, iridium, titanium, or tantalum), and a conductive metal oxide (eg, iridium oxide or niobium oxide), but the inventive concept is not limited thereto.

[0036] The first support pattern 141 may be disposed on the etch stop layer 120. The first support pattern 141 may be spaced apart from the etch stop layer 120 in the vertical direction DR3. The first support pattern 141 may be disposed on at least one side of the lower electrode 130. The first support pattern 141 may contact a portion of a sidewall of the lower electrode 130. For example, the first support pattern 141 may connect the lower electrodes 130 adjacent to each other in the first horizontal direction DR1. Figure 1 14 and 15 as being connected to each other through the first supporting pattern 141 , but this is for convenience of description and the inventive concept is not limited thereto.

[0037] The second support pattern 142 may be disposed on the first support pattern 141. The second support pattern 142 may be spaced apart from the first support pattern 141 in the vertical direction DR3. The second support pattern 142 may be disposed on at least one side of the lower electrode 130. The second support pattern 142 may contact a portion of a sidewall of the lower electrode 130. For example, the second support pattern 142 may connect the lower electrodes 130 adjacent to each other in the first horizontal direction DR1. Although the two lower electrodes 130 are Figure 1 140 and 141. The upper surface 142a of the second support pattern 142 is shown as being connected to each other by the second support pattern 142, but this is for ease of description and the inventive concept is not limited thereto. For example, the upper portion of the second support pattern 142 may protrude further than the upper surface 130a of the lower electrode 130 in the vertical direction DR3. That is, the upper surface 142a of the second support pattern 142 may be formed to be higher than the upper surface 130a of the lower electrode 130.

[0038] For example, the thickness of the first support pattern 141 in the vertical direction DR3 may be less than the thickness of the second support pattern 142 in the vertical direction DR3. In some other example embodiments, only one of the first support pattern 141 and the second support pattern 142 may be disposed on the sidewall of the lower electrode 130. Furthermore, in some other example embodiments, an additional support pattern may be disposed between the etch stop layer 120 and the first support pattern 141 or between the first support pattern 141 and the second support pattern 142. Each of the first support pattern 141 and the second support pattern 142 may include, for example, at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), silicon oxycarbide (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), or silicon oxycarbon nitride (SiOCN).

[0039] The doping layer 150 may be disposed on the sidewall and the upper surface 130a of the lower electrode 130. The doping layer 150 may be disposed on the lower surface and the upper surface of the first support pattern 141. The doping layer 150 may be disposed on the lower surface and the upper surface 142a of the second support pattern 142. The doping layer 150 may be disposed on the upper surface of the etch stop layer 120. For example, the doping layer 150 may contact each of the lower electrode 130, the first support pattern 141, the second support pattern 142, and the etch stop layer 120.

[0040] For example, on the upper surface 130a of the lower electrode 130, at least a portion of the doping layer 150 may contact the sidewall of the second supporting pattern 142. For example, between the etch stop layer 120 and the first supporting pattern 141, at least a portion of the doping layer 150 may overlap the lower electrode 130 in the vertical direction DR3. For example, between the first supporting pattern 141 and the second supporting pattern 142, at least a portion of the doping layer 150 may overlap the lower electrode 130 in the vertical direction DR3.

[0041] For example, a first thickness t1 of the doping layer 150 disposed on the upper surface 130a of the lower electrode 130 in the vertical direction DR3 may be greater than a second thickness t2 of the doping layer 150 disposed on the upper surface 142a of the second support pattern 142 in the vertical direction DR3. For example, a first thickness t1 of the doping layer 150 disposed on the upper surface 130a of the lower electrode 130 in the vertical direction DR3 may be greater than a thickness of the doping layer 150 disposed on the upper surface of the etch stop layer 120 in the vertical direction DR3.

[0042] The doping layer 150 may include a metal oxide as a base material. For example, the doping layer 150 may include titanium oxide, tantalum oxide, iridium oxide, niobium oxide, or ruthenium oxide as a base material. The doping layer 150 may include a first material, a second material, and a third material doped in the base material. The first material, the second material, and the third material may be different materials from each other.

[0043] For example, the first material may be a material having three valence electrons. The first material may include, for example, at least one of aluminum (Al), gallium (Ga), indium (In), yttrium (Y), scandium (Sc), or lanthanum (La). The second material may be a material having four valence electrons. The second material may include, for example, at least one of zirconium (Zr), hafnium (Hf), silicon (Si), germanium (Ge), or tin (Sn). The third material may be a material having five valence electrons. The third material may include, for example, at least one of niobium (Nb), tantalum (Ta), vanadium (V), nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb).

[0044] For example, the third material having five valence electrons can increase the capacitance of the doping layer 150. The second material having four valence electrons can improve the distribution of the third material having five valence electrons doped in the doping layer 150. The first material having three valence electrons can reduce bridge defects of the doping layer 150.

[0045] For example, the atomic percentage of the first material doped in the doping layer 150 may be about 0.1 at % to 10 at %. The atomic percentage of the second material doped in the doping layer 150 may be about 1 at % to 30 at %. The atomic percentage of the third material doped in the doping layer 150 may be about 0.1 at % to 10 at %. For example, the atomic percentage of the first material doped in the doping layer 150 may be less than the atomic percentage of the third material doped in the doping layer 150.

[0046] The capacitor dielectric layer 160 may be disposed on the doping layer 150. The capacitor dielectric layer 160 may be disposed along a surface of the doping layer 150. The capacitor dielectric layer 160 may contact the doping layer 150. For example, the doping layer 150 may be disposed between the lower electrode 130 and the capacitor dielectric layer 160. The doping layer 150 may be disposed between the first supporting pattern 141 and the capacitor dielectric layer 160. The doping layer 150 may be disposed between the second supporting pattern 142 and the capacitor dielectric layer 160. The doping layer 150 may be disposed between the etch stop layer 120 and the capacitor dielectric layer 160. For example, the capacitor dielectric layer 160 may be formed to be conformal.

[0047] For example, the capacitor dielectric layer 160 is not disposed between the lower electrode 130 and the first supporting pattern 141. The capacitor dielectric layer 160 is not disposed between the lower electrode 130 and the second supporting pattern 142. The capacitor dielectric layer 160 is not disposed between the lower electrode 130 and the etch stop layer 120.

[0048] The capacitor dielectric layer 160 may include, for example, one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, lead zinc niobate, and combinations thereof, but the inventive concept is not limited thereto. Although the capacitor dielectric layer 160 is Figure 1 and Figure 2 In some other example embodiments, the capacitor dielectric layer 160 may be formed of multiple layers.

[0049] The upper electrode 170 may be disposed on the capacitor dielectric layer 160. The upper electrode 170 may be disposed to cover the sidewall and the upper surface of the lower electrode 130. The upper electrode 170 may be disposed between the etch stop layer 120 and the first support pattern 141. The upper electrode 170 may be disposed between the first support pattern 141 and the second support pattern 142.

[0050] The upper electrode 170 may include, for example, a conductive metal nitride (eg, titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (eg, ruthenium, iridium, titanium, or tantalum), and a conductive metal oxide (eg, iridium oxide or niobium oxide), but the inventive concept is not limited thereto.

[0051] The second interlayer insulating layer 180 may be disposed on the upper electrode 170. The second interlayer insulating layer 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a low-k material, or a combination thereof.

[0052] In the semiconductor device according to some example embodiments of the inventive concept, the doping layer 150 may be doped with a first material having three valence electrons, a second material having four valence electrons, and a third material having five valence electrons. For example, the third material having five valence electrons may increase the capacitance of the doping layer 150. However, when the concentration of the third material having five valence electrons doped in the doping layer 150 increases to a critical concentration or higher, a problem arises in that the capacitance of the doping layer 150 is no longer increased, and the third material having five valence electrons located on the surface of the doping layer 150 is oxidized to act as a low dielectric.

[0053] In order to limit and / or prevent such a problem, in the semiconductor device according to some example embodiments of the present inventive concept, the doping layer 150 may be doped with a second material having four valence electrons. For example, the second material having four valence electrons doped in the doping layer 150 may improve the distribution of the third material having five valence electrons doped in the doping layer 150. In addition, in the semiconductor device according to some example embodiments of the present inventive concept, the doping layer 150 may be doped with a first material having three valence electrons. For example, the first material having three valence electrons may reduce bridge defects of the doping layer 150.

[0054] Therefore, in some example embodiments of the semiconductor devices conceived according to the present invention, the doping layer 150 can be doped with all of the first material having three valence electrons, the second material having four valence electrons, and the third material having five valence electrons, thereby increasing the capacitance of the doping layer 150, improving the distribution of the third material having five valence electrons doped in the doping layer 150, and reducing bridge defects of the doping layer 150.

[0055] In the following, reference will be made to Figure 1 and Figures 3 to 9 Methods of fabricating a semiconductor device according to some other example embodiments of the inventive concepts are described.

[0056] Figures 3 to 9 It is shown that the description is made Figure 1 A diagram showing intermediate steps of a method for producing a semiconductor device.

[0057] refer to Figure 3 , a storage contact 115 and a landing pad 118 may be formed in the first interlayer insulating layer 110 on the substrate 100. Then, an etch stop layer 120, a first mold layer 10, a first supporting material layer 141M, a second mold layer 20, and a second supporting material layer 142M may be sequentially formed on the first interlayer insulating layer 110.

[0058] Each of the first support material layer 141M and the second support material layer 142M may include at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), silicon oxycarbide (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), or silicon oxycarbon nitride (SiOCN). Each of the first mold layer 10 and the second mold layer 20 may include, for example, silicon oxide (SiO 2). Each of the first mold layer 10 and the second mold layer 20 may include, for example, flowable oxide (FOX), tonine silicon nitride (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borate silicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), fluorosilicate glass (FSG), or a combination thereof.

[0059] Subsequently, a plurality of lower electrodes 130 may be formed on the landing pad 118 through each of the etch stop layer 120, the first mold layer 10, the first supporting material layer 141M, the second mold layer 20, and the second supporting material layer 142M in the vertical direction DR3. Each of the plurality of lower electrodes 130 may be connected to the landing pad 118.

[0060] refer to Figure 4 , first and second supporting patterns 141 and 142 connecting adjacent lower electrodes 130 may be formed. Each of the first and second supporting patterns 141 and 142 may contact a portion of a sidewall of the lower electrode 130.

[0061] For example, by removing the second support material layer ( Figure 3 The second support pattern 142 is formed by removing the first support material layer ( Figure 3 Then, the first mold layer ( 141M) may be etched through a region where each of the second support pattern 142 and the first support pattern 141 is not formed. Figure 3 10) and the second molding layer ( Figure 3 20). The first molding layer ( Figure 3 10) and the second molding layer ( Figure 3 20) to expose the sidewall of the lower electrode 130. A space may be formed between the etch stop layer 120 and the first supporting pattern 141 and between the first supporting pattern 141 and the second supporting pattern 142.

[0062] refer to Figure 5 , the exposed portion of the lower electrode 130 may be oxidized to form a metal oxide layer 30. For example, the metal oxide layer 30 may be formed on the sidewall and the upper surface of the lower electrode 130. For example, the metal oxide layer 30 may be formed on the exposed sidewall of the lower electrode 130 between the etch stop layer 120 and the first support pattern 141. The metal oxide layer 30 may be formed on the exposed sidewall of the lower electrode 130 between the first support pattern 141 and the second support pattern 142. For example, the metal oxide layer 30 may include titanium oxide, tantalum oxide, iridium oxide, niobium oxide, or ruthenium oxide.

[0063] The first layer 40 may be formed on the upper surface of the etch stop layer 120, the exposed surface of the metal oxide layer 30, the exposed surface of the first support pattern 141, and the exposed surface of the second support pattern 142. For example, the first layer 40 may be formed to be conformal. The first layer 40 may be, for example, an oxide layer including a first material having three valence electrons and a second material having four valence electrons. The second layer 50 may be formed on the first layer 40. For example, the second layer 50 may be formed to be conformal. The second layer 50 may be, for example, an oxide layer including a third material having five valence electrons.

[0064] Figure 6 is different from Figure 5 Another production process of the production process shown. Figure 6 , after forming the metal oxide layer 30, a second layer 50 may be formed on the upper surface of the etch stop layer 120, the exposed surface of the metal oxide layer 30, the exposed surface of the first support pattern 141, and the exposed surface of the second support pattern 142. For example, the second layer 50 may be formed to be conformal. The second layer 50 may be, for example, an oxide layer including a third material having five valence electrons. Then, the first layer 40 may be formed on the second layer 50. For example, the first layer 40 may be formed to be conformal. The first layer 40 may be, for example, an oxide layer including a first material having three valence electrons and a second material having four valence electrons.

[0065] refer to Figure 7 , the metal oxide layer ( Figure 5 and Figure 6 30), the first layer ( Figure 5 and Figure 6 40) and the second layer ( Figure 5 and Figure 6 The metal oxide layer ( Figure 5 and Figure 6 30), the first layer ( Figure 5 and Figure 6 40) and the second layer ( Figure 5 and Figure 6 50) is converted into a doping layer 150. The doping layer 150 may include a metal oxide as a base material. The doping layer 150 may include each of a first material having three valence electrons doped, a second material having four valence electrons doped, and a third material having five valence electrons doped.

[0066] refer to Figure 8 , the capacitor dielectric layer 160 may be formed on the doping layer 150. For example, the capacitor dielectric layer 160 may be formed along an exposed surface of the doping layer 150. For example, the capacitor dielectric layer 160 may be formed to be conformal.

[0067] refer to Fig. 9 , an upper electrode 170 may be formed on the capacitor dielectric layer 160 . The upper electrode 170 may be formed to cover a sidewall and an upper surface of the lower electrode 130 .

[0068] refer to Figure 1 , a second interlayer insulating layer 180 may be formed on the upper electrode 170. For example, a plurality of wiring layers may be formed inside the second interlayer insulating layer 180. By this manufacturing process, Figure 1 and Figure 2 The semiconductor device shown.

[0069] In the following, reference will be made to Fig.10 and Fig.11 The following description will be based on the semiconductor devices of some other exemplary embodiments of the present invention. Figure 1 and Figure 2 The differences between the semiconductor devices shown.

[0070] Fig.10 are diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept. Fig.11 It is shown Fig.10 An enlarged view of region R2 is shown.

[0071] refer to Fig.10 and Fig.11 In the semiconductor device according to some other example embodiments of the inventive concepts, the capacitor dielectric layer 260 may contact a surface of the etch stop layer 120 , a surface of the first support pattern 141 , and a surface of the second support pattern 142 .

[0072] For example, the doping layer 250 is not disposed on each of the upper surface of the etch stop layer 120, the lower and upper surfaces of the first support pattern 141, and the lower and upper surfaces 142a of the second support pattern 142. The capacitor dielectric layer 260 may contact each of the upper surface of the etch stop layer 120, the lower and upper surfaces of the first support pattern 141, and the lower and upper surfaces 142a of the second support pattern 142. For example, the uppermost surface 250a of the doping layer 250 may be formed on the same plane as the upper surface 142a of the second support pattern 142.

[0073] In the following, reference will be made to Fig.10 and Figure 12 to Figure 14 Methods for making semiconductor devices according to some other exemplary embodiments of the present invention are described. Figures 3 to 9 The differences in the method of manufacturing a semiconductor device are shown.

[0074] Figure 12 to Figure 14It is shown that the description is made Fig.10 A diagram showing intermediate steps of a method for producing a semiconductor device.

[0075] refer to Fig.12 , in execution Figures 3 to 7 After the fabrication process shown, the exposed doped layer can be etched ( Figure 7 150) of the surface. In performing the doping layer ( Figure 7 After the etching process of 150), the remaining doped layer ( Figure 7 150) can be defined as Fig.12 The doping layer 250 is shown. Figure 7 After the etching process of the first support pattern 141 and the second support pattern 142, the upper surface of the etch stop layer 120, the lower surface and the upper surface of the first support pattern 141, and the lower surface and the upper surface of the second support pattern 142 may be exposed. For example, the uppermost surface of the doping layer 250 may be formed on the same plane as the upper surface of the second support pattern 142, but the inventive concept is not limited thereto.

[0076] refer to Fig.13 , a capacitor dielectric layer 260 may be formed on an upper surface of the etch stop layer 120, a surface of the doping layer 250, lower and upper surfaces of the first support pattern 141, and lower and upper surfaces of the second support pattern 142. The capacitor dielectric layer 260 may contact each of the upper surface of the etch stop layer 120, the surface of the doping layer 250, the lower and upper surfaces of the first support pattern 141, and the lower and upper surfaces of the second support pattern 142. For example, the capacitor dielectric layer 260 may be formed to be conformal.

[0077] refer to Fig.14 , an upper electrode 170 may be formed on the capacitor dielectric layer 260 . The upper electrode 170 may be formed to cover a sidewall and an upper surface of the lower electrode 130 .

[0078] refer to Fig.10 , a second interlayer insulating layer 180 may be formed on the upper electrode 170. For example, a plurality of wiring layers may be formed inside the second interlayer insulating layer 180. By this manufacturing process, Fig.10 and Fig.11 The semiconductor device shown.

[0079] In the following, reference will be made to Fig.15 The following description will be based on the semiconductor devices of some other exemplary embodiments of the present invention. Figure 1 and Figure 2 The differences between the semiconductor devices shown.

[0080] Fig.15are diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept.

[0081] refer to Fig.15 In the semiconductor device according to some other example embodiments of the present inventive concept, the lower electrode 330 may have a cylindrical shape. For example, the lower electrode 330 may have a sidewall and a bottom surface and may have a hollow cylindrical shape. The sidewall of the lower electrode 330 may extend in the vertical direction DR3.

[0082] For example, the doping layer 350 may be disposed on the lower electrode 330. The doping layer 350 is not disposed between the lower electrode 330 and the etch stop layer 120, between the lower electrode 330 and the first support pattern 141, and between the lower electrode 330 and the second support pattern 142. The capacitor dielectric layer 360 may be disposed on the doping layer 350. The capacitor dielectric layer 360 may be disposed along the upper surface of the etch stop layer 120, the lower and upper surfaces of the first support pattern 141, and the lower and upper surfaces of the second support pattern 142.

[0083] The upper electrode 170 may be disposed on the capacitor dielectric layer 360 . A portion of the upper electrode 170 may fill a space between sidewalls of the lower electrode 330 having a cylindrical shape. That is, at least a portion of the upper electrode 170 may be surrounded by the lower electrode 330 .

[0084] In the following, reference will be made to Fig.16 The following description will be based on the semiconductor devices of some other exemplary embodiments of the present invention. Figure 1 and Figure 2 The differences between the semiconductor devices shown.

[0085] Fig.16 are diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept.

[0086] refer to Fig.16 , the semiconductor device according to some other example embodiments of the inventive concepts may include an insulating pattern 490 disposed between the two lower electrodes 430. The insulating pattern 490 may extend in the second horizontal direction DR2.

[0087] The landing pad 118 may be disposed on the etch stop layer 420. The lower electrode 430 may be disposed on the landing pad 118. The lower electrode 430 may have an L-shape. For example, the lower electrode 430 may include a first portion extending along a first horizontal direction DR1 and a second portion extending along a vertical direction DR3. The first portion of the lower electrode 430 may contact the landing pad 118. The second portion of the lower electrode 430 may be connected to one end of the first portion of the lower electrode 430.

[0088] The insulating pattern 490 may be disposed on the sidewall of the lower electrode 430. The insulating pattern 490 may be disposed on the sidewall of the second portion of the lower electrode 430. For example, the insulating pattern 490 may be disposed between the sidewalls of the second portions of the two lower electrodes 430. The insulating pattern 490 may contact the sidewall of the second portion of the lower electrode 430. The insulating pattern 490 may extend between the two lower electrodes 430 in the vertical direction DR3.

[0089] The doping layer 450 may be disposed on the upper surface of the etch stop layer 420, the surface of the lower electrode 430, and the upper surface of the insulating pattern 490. For example, at least a portion of the doping layer 450 may be in contact with the sidewall of the insulating pattern 490 on the uppermost surface of the lower electrode 430. For example, the uppermost surface of the lower electrode 430 may be formed to be lower than the upper surface of the insulating pattern 490.

[0090] The capacitor dielectric layer 460 may be disposed on the doping layer 450. The capacitor dielectric layer 460 may be disposed along a surface of the doping layer 450. The capacitor dielectric layer 460 may contact the doping layer 450. For example, the doping layer 450 may be disposed between the lower electrode 430 and the capacitor dielectric layer 460. The doping layer 450 may be disposed between the insulating pattern 490 and the capacitor dielectric layer 460. The doping layer 450 may be disposed between the etch stop layer 420 and the capacitor dielectric layer 460. For example, the capacitor dielectric layer 460 may be formed to be conformal. For example, the capacitor dielectric layer 460 is not disposed between the lower electrode 430 and the insulating pattern 490. The upper electrode 470 may be disposed on the capacitor dielectric layer 460.

[0091] In the following, reference will be made to Fig.17 The following description will be based on the semiconductor devices of some other exemplary embodiments of the present invention. Fig.16 The semiconductor devices shown are different.

[0092] Fig.17 are diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept.

[0093] refer to Fig.17 In the semiconductor device according to some other example embodiments of the inventive concepts, the capacitor dielectric layer 560 may contact the surface of the etch stop layer 420 and the upper surface of the insulating pattern 490 .

[0094] For example, the doping layer 550 is not disposed on the upper surface of the insulating pattern 490. The capacitor dielectric layer 560 may be in contact with each of the upper surface of the etch stop layer 420 and the upper surface of the insulating pattern 490. For example, the uppermost surface of the doping layer 550 may be formed on the same plane as the upper surface of the insulating pattern 490.

[0095] In the following, reference will be made to Figures 18 to 20 Semiconductor devices according to some other example embodiments of the inventive concepts are described.

[0096] Fig.18 are layout diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept. Fig.19 is a perspective view illustrating a semiconductor device according to some other example embodiments of the inventive concept. Fig. 20 It is along Fig.18 A cross-sectional view taken along line FF and line GG in FIG.

[0097] refer to Figures 18 to 20 , a semiconductor device according to some other example embodiments of the inventive concept may include a substrate 100, a plurality of first conductive lines 920, a channel layer 930, a gate electrode 940, a gate insulating layer 950, and a capacitor 980. A semiconductor device according to some other example embodiments of the inventive concept may include a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which a channel length of the channel layer 930 extends from the substrate 100 along a vertical direction DR3.

[0098] The lower insulating layer 912 may be disposed on the substrate 100. The plurality of first conductive lines 920 may be spaced apart from each other along the first horizontal direction DR1 on the lower insulating layer 912, and may extend along the second horizontal direction DR2. A plurality of first insulating patterns 922 may be disposed on the lower insulating layer 912 to fill the spaces between the plurality of first conductive lines 920. The plurality of first insulating patterns 922 may extend in the second horizontal direction DR2. The upper surfaces of the plurality of first insulating patterns 922 may be disposed at the same height as the upper surfaces of the plurality of first conductive lines 920. The plurality of first conductive lines 920 may serve as bit lines.

[0099] The plurality of first conductive lines 920 may include doped semiconductor materials, metals, conductive metal nitrides, conductive metal silicides, conductive metal oxides, or combinations thereof. For example, the plurality of first conductive lines 920 may include, but are not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x The plurality of first conductive lines 920 may include a single layer or multiple layers of the above materials. In some example embodiments, the plurality of first conductive lines 920 may include graphene, carbon nanotubes, or a combination thereof.

[0100] The channel layer 930 may be arranged on the plurality of first conductive lines 920 in the form of a matrix along the first horizontal direction DR1 and the second horizontal direction DR2, spaced apart from another channel layer. The channel layer 930 may have a first width according to the first horizontal direction DR1 and a first height according to the vertical direction DR3, wherein the first height may be greater than the first width. In some example embodiments, the vertical direction DR3 intersects the first horizontal direction DR1 and the second horizontal direction DR2, and may be, for example, a direction perpendicular to the upper surface of the substrate 100. For example, the first height may be approximately 2 to 10 times the first width, but the inventive concept is not limited thereto. The bottom of the channel layer 930 may be used as a first source / drain region (not shown), the upper portion of the channel layer 930 may be used as a second source / drain region (not shown), and the portion of the channel layer 930 between the first source / drain region and the second source / drain region may be used as a channel region (not shown).

[0101] In some example embodiments, the channel layer 930 may include an oxide semiconductor, and the oxide semiconductor may include, for example, In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga yO or a combination thereof. The channel layer 930 may include a single layer or multiple layers of an oxide semiconductor. In some example embodiments, the band gap energy of the channel layer 930 may be greater than the band gap energy of silicon. For example, the band gap energy of the channel layer 930 may be approximately 1.5 eV to 5.6 eV. For example, when the band gap energy of the channel layer 930 is approximately 2.0 eV to 4.0 eV, the channel layer 930 may have optimal channel performance. For example, the channel layer 930 may be polycrystalline or amorphous, but is not limited thereto. In some example embodiments, the channel layer 930 may include graphene, carbon nanotubes, or a combination thereof.

[0102] The gate electrode 940 may extend along the first horizontal direction DR1 on both sidewalls of the channel layer 930. The gate electrode 940 may include a first sub-gate electrode 940P1 facing the first sidewall of the channel layer 930 and a second sub-gate electrode 940P2 facing the second sidewall opposite to the first sidewall of the channel layer 930. Since one channel layer 930 is disposed between the first sub-gate electrode 940P1 and the second sub-gate electrode 940P2, the semiconductor device may have a dual-gate transistor structure, but the inventive concept is not limited to this structure. The second sub-gate electrode 940P2 may be omitted, and only the first sub-gate electrode 940P1 facing the first sidewall of the channel layer 930 may be formed, so that a single-gate transistor structure may be realized. The gate electrode 940 may include a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal oxide, a conductive metal oxynitride, or a metal.

[0103] The gate insulating layer 950 may be interposed between the channel layer 930 and the gate electrode 940 while surrounding the sidewalls of the channel layer 930. Fig.18 As shown, the entire sidewall of the channel layer 930 may be surrounded by the gate insulating layer 950, and a portion of the sidewall of the gate electrode 940 may be in contact with the gate insulating layer 950. In some other example embodiments, the gate insulating layer 950 may extend in an extension direction (e.g., the first horizontal direction DR1) of the gate electrode 940, and only two sidewalls facing the gate electrode 940 among the sidewalls of the channel layer 930 may be in contact with the gate insulating layer 950. In some example embodiments, the gate insulating layer 950 may be made of a silicon oxide layer, a silicon oxynitride layer, a high-k layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof.

[0104] A plurality of second insulating patterns 932 may extend along the second horizontal direction DR2 on the plurality of first insulating patterns 922, and the channel layer 930 may be disposed between two adjacent second insulating patterns 932 among the plurality of second insulating patterns 932. In addition, a first buried layer 934 and a second buried layer 936 may be disposed in a space between two adjacent channel layers 930 and between two adjacent second insulating patterns 932. The first buried layer 934 may be disposed on the bottom of the space between the two adjacent channel layers 930, and the second buried layer 936 may be formed to fill up the remaining portion of the space between the two adjacent channel layers 930 on the first buried layer 934. The upper surface of the second buried layer 936 may be disposed at the same height as the upper surface of the channel layer 930, and the second buried layer 936 may cover the upper surface of the gate electrode 940. Alternatively, the plurality of second insulating patterns 932 may be formed of a material layer continuous with the plurality of first insulating patterns 922 , or the second buried layer 936 may be formed of a material layer continuous with the first buried layer 934 .

[0105] The capacitor contact 960 may be disposed on the channel layer 930. The capacitor contact 960 may be disposed to overlap the channel layer 930 in the vertical direction DR3, and may be arranged in a matrix to be spaced apart from each other in the first horizontal direction DR1 and the second horizontal direction DR2. The capacitor contact 960 may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x The upper insulating layer 962 may surround sidewalls of the capacitor contacts 960 on the plurality of second insulating patterns 932 and the second buried layer 936 .

[0106] The etch stop layer 970 may be disposed on the upper insulating layer 962, and the capacitor 980 may be disposed on the etch stop layer 970. The capacitor 980 may include a lower electrode 982, a doping layer 990, a capacitor dielectric layer 984, and an upper electrode 986. The lower electrode 982 may be electrically connected to the upper surface of the capacitor contact 960 through the etch stop layer 970. The lower electrode 982 may be formed of a column extending in the vertical direction DR3, but the inventive concept is not limited thereto. In some example embodiments, the lower electrode 982 may be disposed to overlap the capacitor contact 960 in the vertical direction DR3, and may be arranged in a matrix form spaced apart from another lower electrode in the first horizontal direction DR1 and the second horizontal direction DR2. Alternatively, a landing pad (not shown) may be further disposed between the capacitor contact 960 and the lower electrode 982, and the lower electrode 982 may be arranged in a hexagon.

[0107] The doping layer 990 may be disposed between the lower electrode 982 and the capacitor dielectric layer 984. The doping layer 990 may include a metal oxide as a base material. For example, the doping layer 990 may include titanium oxide, tantalum oxide, iridium oxide, niobium oxide, or ruthenium oxide as a base material. The doping layer 990 may include a first material, a second material, and a third material doped in the base material. The first material, the second material, and the third material may be different materials from each other.

[0108] For example, the first material may be a material having three valence electrons. The first material may include, for example, at least one of aluminum (Al), gallium (Ga), indium (In), yttrium (Y), scandium (Sc), or lanthanum (La). The second material may be a material having four valence electrons. The second material may include at least one of zirconium (Zr), hafnium (Hf), silicon (Si), germanium (Ge), or tin (Sn). The third material may be a material having five valence electrons. The third material may include, for example, at least one of niobium (Nb), tantalum (Ta), vanadium (V), nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb).

[0109] For example, the atomic percentage of the first material doped in the doping layer 990 may be approximately 0.1 at % to 10 at %. The atomic percentage of the second material doped in the doping layer 990 may be approximately 1 at % to 30 at %. The atomic percentage of the third material doped in the doping layer 990 may be approximately 0.1 at % to 10 at %. For example, the atomic percentage of the first material doped in the doping layer 990 may be less than the atomic percentage of the third material doped in the doping layer 990.

[0110] In the following, reference will be made to Fig.21 and Fig. 22 Semiconductor devices according to some other example embodiments of the inventive concepts are described.

[0111] Fig.21 are layout diagrams illustrating semiconductor devices according to some other example embodiments of the inventive concept. Fig. 22 is a perspective view illustrating a semiconductor device according to some other example embodiments of the inventive concept.

[0112] refer to Figure 21 to Figure 22 , a semiconductor device according to some other example embodiments of the inventive concept may include a substrate 100, a plurality of first conductive lines 920A, a channel structure 930A, a contact gate electrode 940A, a plurality of second conductive lines 942A, and a capacitor 980. A semiconductor device according to some other example embodiments of the inventive concept may include a vertical channel transistor (VCT).

[0113] A plurality of active regions AC may be defined by a first device isolation pattern 912A and a second device isolation pattern 914A in the substrate 100. A channel structure 930A may be disposed inside each of the plurality of active regions AC. The channel structure 930A may include a first active pillar 930A1 and a second active pillar 930A2 extending in a vertical direction DR3, respectively, and a connection portion 930L connected to the bottom of the first active pillar 930A1 and the bottom of the second active pillar 930A2. The first source / drain region SD1 may be disposed in the connection portion 930L. The second source / drain region SD2 may be disposed above the first active pillar 930A1 and the second active pillar 930A2. Each of the first active pillar 930A1 and the second active pillar 930A2 may form an independent unit memory cell.

[0114] A plurality of first conductive lines 920A may extend in a direction intersecting each of the plurality of active regions AC, and may extend, for example, in the second horizontal direction DR2. One of the plurality of first conductive lines 920A may be disposed on a connection portion 930L between a first active column 930A1 and a second active column 930A2. One first conductive line 920A may be disposed on a first source / drain region SD1. Another first conductive line 920A adjacent to the above-mentioned first conductive line 920A may be disposed between two channel structures 930A. One of the plurality of first conductive lines 920A may be used as a common bit line, which is included in two unit memory cells consisting of a first active column 930A1 and a second active column 930A2 disposed on both sides thereof.

[0115] One contact gate electrode 940A may be disposed between two channel structures 930A adjacent to each other along the second horizontal direction DR2. For example, the contact gate electrode 940A may be disposed between a first active pillar 930A1 included in a channel structure 930A and a second active pillar 930A2 adjacent to the first active pillar 930A1 of the channel structure 930A. One contact gate electrode 940A may be shared by the first active pillar 930A1 and the second active pillar 930A2 disposed on both side walls thereof. A gate insulating layer 950A may be disposed between the contact gate electrode 940A and the first active pillar 930A1 and between the contact gate electrode 940A and the second active pillar 930A2. A plurality of second conductive wires 942A may extend along the first horizontal direction DR1 on the upper surface of the contact gate electrode 940A. A plurality of second conductive wires 942A may be used as word lines of a semiconductor device.

[0116] The capacitor contact 960A may be disposed on the channel structure 930A. The capacitor contact 960A may be disposed on the second source / drain region SD2, and the capacitor 980 may be disposed on the capacitor contact 960A. The capacitor 980 may include a lower electrode 982, a doping layer 990, a capacitor dielectric layer 984, and an upper electrode 986, as shown in FIG. Fig. 20 shown.

[0117] Although the exemplary embodiments of the inventive concept have been described with reference to the accompanying drawings, it is clear to those skilled in the art that the inventive concept can be made in various forms without being limited to the exemplary embodiments described above, and can be implemented in other specific forms without departing from the technical spirit and basic characteristics of the inventive concept. Therefore, the exemplary embodiments described above should be considered in all aspects to be illustrative rather than restrictive.

Claims

1. A semiconductor device, comprising: a landing pad located on the substrate; a lower electrode extending in a vertical direction on the landing pad, the lower electrode being connected to the landing pad; a capacitor dielectric layer, the capacitor dielectric layer being located on the lower electrode; a doping layer located between the lower electrode and the capacitor dielectric layer, the doping layer contacting each of the lower electrode and the capacitor dielectric layer, the doping layer being doped with a first material, a second material, and a third material, The first material has three valence electrons, the second material has four valence electrons, and the third material has five valence electrons; and An upper electrode is located on the capacitor dielectric layer.

2. The semiconductor device according to claim 1, wherein The atomic percentage of the first material doped in the doping layer is less than the atomic percentage of the third material doped in the doping layer.

3. The semiconductor device according to claim 1, wherein The atomic percentage of the first material doped in the doping layer is 0.1 at % to 10 at %, the atomic percentage of the second material doped in the doping layer is 1 at % to 30 at %, and the atomic percentage of the third material doped in the doping layer is 0.1 at % to 10 at %.

4. The semiconductor device according to claim 1, further comprising a support pattern located on at least one side of the lower electrode, the support pattern being in contact with a sidewall of the lower electrode, in, At least a portion of the doping layer contacts a sidewall of the support pattern on an upper surface of the lower electrode.

5. The semiconductor device according to claim 4, wherein: At least another portion of the doping layer is located on the upper surface of the support pattern.

6. The semiconductor device according to claim 5, wherein: At least a portion of the doping layer on the upper surface of the lower electrode has a first thickness in the vertical direction, another portion of the doping layer on the upper surface of the support pattern has a second thickness in the vertical direction, and the first thickness is greater than the second thickness.

7. The semiconductor device according to claim 4, wherein: The capacitor dielectric layer contacts an upper surface of the support pattern.

8. The semiconductor device according to claim 4, wherein: The uppermost surface of the doping layer is coplanar with an upper surface of the support pattern.

9. The semiconductor device according to claim 1, wherein: At least a portion of the upper electrode is surrounded by the lower electrode.

10. The semiconductor device according to claim 1, further comprising an insulating pattern located on a sidewall of the lower electrode, the insulating pattern being in contact with the sidewall of the lower electrode, the insulating pattern extending in the vertical direction, in, The lower electrode has an L-shape, and At least a portion of the doping layer contacts the sidewall of the insulating pattern on the uppermost surface of the lower electrode.

11. The semiconductor device according to claim 10, wherein: At least a portion of the doping layer is located on an upper surface of the insulating pattern.

12. The semiconductor device according to claim 10, wherein: The capacitor dielectric layer contacts an upper surface of the insulating pattern.

13. A semiconductor device, comprising: a landing pad located on the substrate; a lower electrode extending in a vertical direction on the landing pad, the lower electrode being connected to the landing pad; A first supporting pattern, wherein the first supporting pattern is located on at least one side of the lower electrode, and the first supporting pattern is in contact with a sidewall of the lower electrode; a second supporting pattern, the second supporting pattern being located at at least one side of the lower electrode, the second supporting pattern being in contact with the sidewall of the lower electrode, and the second supporting pattern being spaced apart from the first supporting pattern in the vertical direction; a capacitor dielectric layer, the capacitor dielectric layer being located on the lower electrode and the second supporting pattern; as well as a doping layer located between the lower electrode and the capacitor dielectric layer, the doping layer contacting each of the lower electrode and the capacitor dielectric layer, the doping layer being doped with a first material, a second material, and a third material, The first material has three valence electrons, the second material has four valence electrons, and the third material has five valence electrons; At least a portion of the doping layer contacts the sidewall of the second supporting pattern on the upper surface of the lower electrode.

14. The semiconductor device according to claim 13, wherein: The atomic percentage of the first material doped in the doping layer is less than the atomic percentage of the third material doped in the doping layer.

15. The semiconductor device according to claim 13, wherein: At least a portion of the doping layer overlaps the lower electrode in the vertical direction between the first supporting pattern and the second supporting pattern.

16. The semiconductor device according to claim 13, wherein: At least a portion of the doping layer is located on an upper surface of the second supporting pattern.

17. The semiconductor device according to claim 16, wherein: At least a portion of the doping layer on the upper surface of the lower electrode has a first thickness in the vertical direction, and at least a portion of the doping layer on the upper surface of the second support pattern has a second thickness in the vertical direction, and the first thickness is greater than the second thickness.

18. The semiconductor device according to claim 13, wherein: The capacitor dielectric layer contacts an upper surface of the second supporting pattern.

19. The semiconductor device according to claim 13, wherein: The uppermost surface of the doping layer is coplanar with an upper surface of the second supporting pattern.

20. A semiconductor device, comprising: a landing pad located on the substrate; a lower electrode extending in a vertical direction on the landing pad, the lower electrode being connected to the landing pad; A first supporting pattern, wherein the first supporting pattern is located on at least one side of the lower electrode, and the first supporting pattern is in contact with a sidewall of the lower electrode; a second supporting pattern, the second supporting pattern being located at at least one side of the lower electrode, the second supporting pattern being in contact with the sidewall of the lower electrode, and the second supporting pattern being spaced apart from the first supporting pattern in the vertical direction; a capacitor dielectric layer, the capacitor dielectric layer being located on the lower electrode and the second supporting pattern; a doping layer, the doping layer being located between the lower electrode and the capacitor dielectric layer and between the upper surface of the second supporting pattern and the capacitor dielectric layer, the doping layer being in contact with each of the lower electrode, the capacitor dielectric layer and the upper surface of the second supporting pattern, the doping layer being doped with a first material, a second material and a third material, The first material has three valence electrons, the second material has four valence electrons, and the third material has five valence electrons; as well as an upper electrode, the upper electrode being located on the capacitor dielectric layer, wherein at least a portion of the doping layer contacts the sidewall of the second supporting pattern on the upper surface of the lower electrode, The atomic percentage of the first material doped in the doping layer is less than the atomic percentage of the third material doped in the doping layer, and Wherein, at least a portion of the doping layer on the upper surface of the lower electrode has a first thickness in the vertical direction, at least a portion of the doping layer on the upper surface of the second support pattern has a second thickness in the vertical direction, and the first thickness is greater than the second thickness.

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