Selective atomic layer deposition of metal oxide or dielectric layer regions on patterned substrates

Abstract

Described herein are methods of selectively depositing a metal oxide or dielectric layer on a non-metal substrate without accompanying growth on a metal substrate using cycloazosilanes, epithio silanes or cyclotellurium silanes to inhibit growth on a metal surface. Film having a thickness greater than 7 nanometers may be grown on a dielectric substrate (e.g., hot silica and silicon) without any growth on a metal region (e.g., copper). This dielectric-to-dielectric (DoD) growth is a key element of many proposed schemes in future semiconductor device fabrication, such as fully self-aligned vias.

Description

[0001] Related cross-applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 333,286, filed on April 21, 2022, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] As pattern sizes shrink during semiconductor manufacturing, alignment of the mask with existing features on the substrate has become a critical barrier to further reducing feature size. Misalignment of the substrate and mask can lead to edge placement errors, which are differences between the desired and actual locations of features on the device. These differences can cause immediate or time-dependent dielectric breakdown, which can affect device reliability. In addition, in cases where vias contact metal lines, edge placement errors can lead to increased capacitance between the via and adjacent metal lines and reduce the contact area between the via and the target line, thereby increasing resistance. The resulting RC delay slows down the switching speed of the transistor, significantly reducing device performance.

[0004] One approach to avoiding edge placement error issues is to create fully self-aligned vias (FSAVs), in which dielectric films are selectively grown over existing dielectric layers and not over metal lines. This area selective deposition (ASD) can alleviate these manufacturing challenges by enabling bottom-up material placement without the use of masks. In the case of FSAVs, the topography produced by the ASD dielectric-on-dielectric (DoD) process provides greater vertical distance between subsequent metal layers, allowing for greater horizontal misalignment latitudes or larger critical dimension (CD) vias. Many of the previously described schemes involve deposition of ASD DoD layers, but few have been able to achieve the required film thicknesses of 5 to 10 nm while meeting other film performance and manufacturability targets.

[0005] Brief description of the invention

[0006] In one embodiment, the present invention relates to a method for selectively depositing a metal oxide or dielectric layer on a patterned substrate, the method comprising:

[0007] (a) introducing a patterned substrate having metal and non-metal regions into a reaction zone of a deposition chamber, and heating the reaction zone to a temperature of about 175° C. to about 350° C.;

[0008] (b) exposing the patterned substrate to a pulse of a heteroatom silicon ring compound and purging the deposition chamber; and

[0009] (c) performing atomic layer deposition or chemical vapor deposition on the patterned substrate to form a metal oxide or dielectric layer on the substrate;

[0010] Wherein, the metal oxide or dielectric layer is selectively formed on the non-metallic area of ​​the patterned substrate.

[0011] In summary, within the scope of the present invention, the following embodiments are particularly preferred:

[0012] Embodiment 1: A method for selectively depositing a metal oxide or a dielectric layer on a patterned substrate, the method comprising:

[0013] (a) introducing a patterned substrate having metal and non-metal regions into a reaction zone of a deposition chamber, and heating the reaction zone to a temperature of about 175° C. to about 350° C.;

[0014] (b) exposing the patterned substrate to a pulse of a heteroatom silicon ring compound and purging the deposition chamber; and

[0015] (c) performing atomic layer deposition or chemical vapor deposition on the patterned substrate to form a metal oxide or dielectric layer on the patterned substrate;

[0016] Embodiment 2: The method of embodiment 1, wherein step (c) comprises:

[0017] (d) exposing the patterned substrate to a pulse of a metal alkyl compound;

[0018] (e) purging the deposition chamber;

[0019] (f) exposing the patterned substrate to a pulse of water;

[0020] (g) purging the deposition chamber; and

[0021] (h) Repeating steps (d) to (g) until the desired metal oxide or dielectric layer thickness is achieved.

[0022] Wherein, a metal oxide or a dielectric layer is selectively formed on the non-metallic region of the pattern substrate.

[0023] Embodiment 3: The method as described in Embodiment 1 or 2 further comprises performing a plasma treatment step before step (a).

[0024] Embodiment 4: The method as described in any of the above embodiments further comprises performing at least one plasma treatment step before or after steps (a) to (g).

[0025] Embodiment 5: The method as described in any one of Embodiments 2-4, wherein the metal alkyl compound is a Group 12 or Group 13 metal alkyl compound.

[0026] Embodiment 6: A method as described in Embodiment 5, wherein the metal alkyl compound is selected from the group consisting of diethylzinc, trimethylaluminum, dimethylaluminum isopropoxide, dimethylzinc, trimethylgallium, triethylgallium, triethylaluminum, triethylindium, dimethylcadmium and dimethylmercury.

[0027] Embodiment 7: The method according to any of the above embodiments, wherein the heteroatom silicon ring compound is a cyclonitrogen silane according to formula (1), a cyclosulfur silane according to formula (2), or a cyclotellurium silane according to formula (3):

[0028]

[0029] Where R 1 is hydrogen or a linear, branched or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl or alkylamino group containing 1 to about 12 carbon atoms, R 2 is a linear, branched or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl, or alkylamino group containing 1 to about 12 carbon atoms, n is an integer from 1 to about 4, and X and Y are each independently a linear, branched or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl, or alkylamino group.

[0030] Embodiment 8: A method as described in Embodiment 7, wherein the heteroatom silicon ring compound is (N-methyl-aza-2,2,4-trimethylsilanol, N-(2-aminoethyl)-2,2,4-trimethyl-1-aza-silanol, N-n-butyl-aza-2,2-dimethoxysilanol, N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silanol, (N,N-dimethylamino (1-(3-triethoxysilyl)propyl)-2,2-diethoxy-1-aza-silacyclopentane, N-allyl-aza-2,2-dimethoxysilacyclopentane, N-tert-butyl-aza-2,2-dimethyloxysilacyclopentane, 2,2,4-trimethyl-1-thio-2-silacyclopentane, or 2,2,4-trimethyl-1-tellur-2-silacyclopentane

[0031] Embodiment 9: A method as described in any of the above embodiments, wherein the metal region of the substrate includes at least one of copper, cobalt, tungsten, ruthenium and molybdenum.

[0032] Embodiment 10: A method as described in Embodiment 1, wherein the non-metallic region of the substrate includes at least one of silicon, germanium, silicon-germanium alloy, silicon dioxide, silicon nitride, titanium nitride, tantalum nitride, silicon oxycarbide, silicon oxynitride, silicon carboxynitride, aluminum oxide, hafnium dioxide, titanium dioxide and zinc oxide.

[0033] Embodiment 11: The method as described in any of the above embodiments, wherein the substrate is silicon dioxide or copper on silicon.

[0034] Embodiment 12: The method as described in any of the above embodiments, wherein the pulse duration of the heteroatom silicon ring compound in step (b) is at least about 0.1 seconds.

[0035] Embodiment 13: The method as described in any of the above embodiments, wherein the pulse duration of the heteroatom silicon ring compound in step (b) is about 0.1 seconds to about 10 seconds.

[0036] Embodiment 14: A method as described in Embodiment 13, wherein the pulse length of the heteroatom silicon ring compound in step (b) is about 5 seconds.

[0037] Embodiment 15: A method as described in any of the above embodiments, wherein the reaction zone in step (a) is heated to about 225°C to about 275°C.

[0038] Embodiment 16: The method of any of the above embodiments, wherein the mixed oxide dielectric film has a thickness of about 5 nm to about 50 nm.

[0039] Embodiment 17: The method as described in Embodiment 16 above, wherein the mixed oxide dielectric film has a thickness of about 5 nm to about 10 nm.

[0040] Embodiment 18: The method as described in any of the above embodiments, wherein step (b) forms a blocking layer on the patterned substrate.

[0041] Embodiment 19: A method as described in Embodiment 1, wherein step (c) comprises:

[0042] (d) exposing the patterned substrate to a pulse of a metal alkyl compound;

[0043] (e) purging the deposition chamber;

[0044] (f) exposing the patterned substrate to a pulse of water;

[0045] (g) purging the deposition chamber;

[0046] (h) repeating steps (d) to (g) at least once;

[0047] (i) performing a plasma treatment step; and

[0048] (j) Repeating steps (d) to (i) until the desired metal oxide or dielectric layer thickness is achieved.

[0049] Embodiment 20: The method of Embodiment 1, wherein the metal oxide or dielectric layer is formed from a metal alkyl compound.

[0050] Embodiment 21: The method of Embodiment 19, wherein the metal alkyl compound is a Group 12 or Group 13 metal alkyl compound.

[0051] Embodiment 22: A method as described in Embodiment 21, wherein the metal alkyl compound is selected from the group consisting of diethylzinc, trimethylaluminum, dimethylaluminum isopropoxide, dimethylzinc, trimethylgallium, triethylgallium, triethylaluminum, triethylindium, dimethylcadmium and dimethylmercury.

[0052] Brief description of several views of the accompanying drawings

[0053] Combined with Figure 1 The following detailed description of the preferred embodiments of the present invention will be better understood when read together with the accompanying drawings. For the purpose of illustrating the invention, there are shown in the accompanying drawings presently preferred embodiments. However, it should be understood that the invention is not limited to the precise arrangements and apparatus shown. In the drawings:

[0054] Figure 1 is a graph of the thickness of the films of Examples 1 and 2 and Comparative Examples 1 and 2 versus time. DETAILED DESCRIPTION OF THE INVENTION

[0056] Various aspects of the present invention relate to a method of forming an area selectively deposited dielectric-on-dielectric (ASD DoD) layer by first reacting a patterned substrate with a heteroatom silicon ring compound and then growing a metal oxide atomic layer deposition (ALD) using sequential pulses of a metal alkyl and water, or growing a metal oxide by chemical vapor deposition (CVD) using simultaneous addition of a metal alkyl and water to selectively grow the resulting metal oxide or dielectric layer or film on non-metallic portions of the patterned substrate.

[0057] It has been found that exposure of a metal surface to a heteroatom silicon ring compound at a sufficiently high temperature, such as from about 175°C to about 350°C, preferably from about 225°C to about 275°C, significantly inhibits the growth of a thin film during subsequent exposure to a metal oxide to form a deposition process. Specifically, heteroatom silicon ring compounds act as blocking groups to control the growth of metal oxides (such as zinc oxide) on various patterned substrates. Although the inhibitory effect on non-metallic substrates was also observed after exposure to heteroatom silicon ring compounds, this inhibitory effect has a greater impact on the metal portion of the substrate, resulting in the selective growth of metal oxide films on the non-metallic regions of the substrate. Under the same conditions, a zinc oxide film with a thickness of more than 7nm was grown on a thermal oxide substrate, but not on a copper substrate. Taking PVD copper on a silicon patterned substrate as a specific example, it has been found that at a sufficiently high temperature (e.g., from about 175°C to about 350°C, particularly from about 225°C to 275°C), the heteroatom silicon ring compound blocking layer delays the growth of zinc oxide films on the copper portion of the substrate, thereby achieving selective growth on the silicon portion.

[0058] The method of the present invention involves introducing a patterned substrate having metal and non-metal regions into a reaction zone of a deposition chamber, heating the reaction zone to about 175°C to about 350°C, exposing the patterned substrate to a pulse of a heteroatom silicon ring compound and cleaning the deposition chamber, and then performing ALD or CVD on the patterned substrate to form a metal oxide or dielectric layer or film. For the purposes of the present invention, the terms "layer" and "film" may be understood as synonymous. In one embodiment, ALD involves exposing the substrate (now including a blocking layer) to a sequence of the following steps, which are repeated as many times as necessary to achieve a film of the desired thickness: exposing the substrate to a pulse of a metal alkyl compound, cleaning the deposition chamber, exposing the substrate to a pulse of deionized water, and cleaning the deposition chamber. The resulting metal oxide or dielectric layer is selectively formed on the non-metallic regions of the patterned substrate.

[0059] In some embodiments, it is within the scope of the present invention to pretreat the substrate prior to exposing it to the metal alkyl compound. Pretreatment can be accomplished by chemical, structural, or plasma pretreatment methods well known in the art. For example, the substrate can be pretreated by washing in ethanol, isopropanol, citric acid, or acetic acid-based formulations, or by exposing the substrate to 5% H at 2500 W, 225° C. to 250° C. 2 / 95% N 2 The pretreatment is performed in a remote inductively coupled plasma for 60 seconds. Other similar substrate pretreatment processes known in the art are also applicable. The treatment can improve the performance of the resulting film, but the appropriate pretreatment method and conditions can be determined one by one according to the specific substrate, equipment, reactants and reaction conditions.

[0060] In some embodiments, after completing several metal alkyl exposure / purge / water exposure / purge sequences (e.g., about 1 to about 50 steps), the substrate is subjected to a plasma pulse treatment, e.g., for about 10 seconds. For example, a series of five exposure / pulse sequences may be performed before the plasma treatment. Such a sequence consisting of 5 (for example) exposure / pulse sequences followed by a plasma pulse may be referred to as a "super cycle." Such a super cycle may be repeated as many times as desired to form a metal oxide film or dielectric film having a desired thickness. In some embodiments, it is also within the scope of the present invention to perform a plasma treatment step before or after any exposure or purge step.

[0061] It is within the scope of the present invention to prepare mixed oxide dielectric films having a thickness of 5 to 10 nm, particularly mixed oxide dielectric films having a thickness of 7 nm to 10 nm as currently required in the microelectronics industry, and further to prepare mixed oxide dielectric films having a thickness of up to about 50 nm. The desired film or layer thickness can be obtained by repeatedly repeating the method steps described herein.

[0062] A variety of metal alkyl compounds can be used in the methods described herein, including, but not limited to, Group 12 and Group 13 metal alkyl compounds. Exemplary metal alkyl compounds that can be employed include the presently preferred diethylzinc, trimethylaluminum, dimethylaluminum isopropoxide, dimethylzinc, trimethylgallium, triethylgallium, triethylaluminum, triethylindium, dimethylcadmium, and dimethylmercury.

[0063] The blocking layer can be formed on the patterned substrate by exposing the substrate to a pulse of a heteroatom silicon ring compound (such as cycloazasilane, cyclotellurylsilane or cyclosulfidesilane compound).

[0064] Suitable cyclonitrosilane is shown in formula (1):

[0065]

[0066] In formula (1), R 1 is hydrogen or a linear, branched or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl or alkylamino group containing 1 to about 12 carbon atoms (preferably 1 to about 4 carbon atoms), R 2 is a linear, branched or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl or alkylamino group containing 1 to about 12 carbon atoms (preferably 1 to about 4 carbon atoms), n is an integer from 1 to about 4, and X and Y are each independently a linear, branched or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl or alkylamino group (preferably 1 to about 4 carbon atoms). In the present invention, R 1 , R 2, X and Y are unsubstituted or substituted, such as but not limited to alkyl (e.g. methyl, ethyl or propyl), alkoxy (e.g. trimethoxy or triethylmethoxy), alkoxy (e.g. methoxy or alkoxy) and / or halogen (e.g. chlorine, bromine, fluorine or iodine).

[0067] Exemplary R 1 , R 2 Substituents on X and Y include, but are not limited to, hydrogen, methyl, ethyl, n-propyl, isopropyl, n-butyl, sec-butyl, tert-butyl, pentyl, hexyl, phenyl, cyclohexyl, heptyl, n-octyl, 2-ethylhexyl, nonyl, decyl, dodecyl, octadecyl, methoxy, ethoxy, n-propoxy, isopropoxy, n-butoxy, sec-butoxy, tert-butoxy, vinyl, allyl, norbornenyl, methyl norbornenyl, ethyl norbornenyl, propyl norbornenyl, trimethylsilyl, trimethoxysilyl, methyl(trimethoxysilyl), ethyl(trimethoxysilyl), propyl(trimethoxysilyl), triethoxysilyl, methyl(triethoxysilyl), ethyl(triethoxysilyl), propyl(triethoxysilyl), amino, methylamino, ethylamino, propylamino, methyl(dimethylamino), ethyl(dimethylamino), propyl(dimethylamino), and chloromethyl.

[0068] Preferably, R 1 is hydrogen or an alkyl group, such as methyl or ethyl, R 2 is an optionally substituted alkyl, alkenyl or alkylamino group containing 1 to about 4 carbon atoms, such as 1, 2, 3 or 4 carbon atoms, and X and Y are preferably alkyl or alkoxy groups containing 1 to about 4 carbon atoms, such as 1, 2, 3 or 4 carbon atoms.

[0069] Exemplary cyclonitrosilane compounds that can effectively form a blocking layer on a patterned substrate include, but are not limited to: (N-methyl-aza-2,2,4-trimethylsilanol, N-(2-aminoethyl)-2,2,4-trimethyl-1-aza-silanol, N-n-butyl-aza-2,2-dimethoxysilanol, N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silanol, (N,N-dimethylaminopropyl)-aza-2-methyl-2-methoxysilanol, (1-(3-triethoxysilyl)propyl)-2,2-diethoxy-1-aza-silanol, N-allyl-aza-2,2-dimethoxysilanol, N-tert-butyl-aza-2,2,-dimethyloxysilanol, having the following structure:

[0070]

[0071] Suitable episulfide silanes are shown in formula (2):

[0072]

[0073] In formula (2), R 1 , n, X and Y are as described above. Preferably, R 1 is hydrogen or an alkyl group, such as methyl or ethyl, and X and Y are preferably alkyl or alkoxy groups containing from 1 to about 4 carbon atoms, such as 1, 2, 3 or 4 carbon atoms.

[0074] An exemplary episulfide silane compound that is effective in forming mixed oxide dielectric layers on patterned substrates is 2,2,4-trimethyl-1-thio-2-silacyclopentane and has the following structure:

[0075]

[0076] Suitable cyclotellurylsilane is shown in formula (3):

[0077]

[0078] In formula (3), R 1 , n, X and Y are as described above. Preferably, R 1 is hydrogen or an alkyl group, such as methyl or ethyl, and X and Y are preferably alkyl or alkoxy groups containing from 1 to about 4 carbon atoms, such as 1, 2, 3 or 4 carbon atoms.

[0079] An exemplary cyclotellurylsilane compound that is effective in forming mixed oxide dielectric layers on patterned substrates is 2,2,4-trimethyl-1-telluryl-2-silacyclopentane and has the following structure:

[0080]

[0081] Currently preferred compounds for use in the methods described herein are cyclonitrosilanes, particularly N-methyl-aza-2,2,4-trimethylsilacyclopentane is a preferred compound:

[0082]

[0083] The parameters of the purge cycle are not particularly limited and can be optimized based on the specific reaction conditions, equipment and reactants. In general, any inert gas, such as argon or nitrogen, can be used; a typical purge period is at least 2 seconds. In a preferred embodiment, the purge is about 5 seconds (after the metal alkyl pulse and the water pulse) and about 30 seconds after the heteroatom silicon ring compound pulse.

[0084] The temperature of the substrate and the reaction zone of the deposition chamber is critical to the preparation of an effective blocking layer of heteroatom silicon ring compounds. Specifically, at least during the deposition of the metal oxide or dielectric layer, the temperature of the substrate and the reaction zone is preferably about 175°C to about 350°C, more preferably about 225°C to about 275°C. It should be understood that the range of substrate temperature includes all temperatures within the range, so that the temperature of about 175°C to about 350°C includes temperatures such as about 200°C, about 225°C, about 250°C, about 275°C, about 300°C, about 325°C, about 300°C, about 325°C, and all temperatures between the two.

[0085] If the deposition of the blocking layer is performed in the same deposition chamber and under the same reaction conditions as the metal oxide or dielectric layer, the deposition temperature of the substrate and the reaction zone may also be within this temperature range. Alternatively, the blocking layer may be deposited in the same or different reaction chamber at a different temperature, such as from about 20°C to about 325°C, including all temperatures within this range.

[0086] The pulse duration of each reactant can also be optimized according to specific reaction conditions and equipment, and is generally kept as short as possible. In some embodiments, the pulse duration of the metal alkyl compound and water can be shorter than 0.05 seconds or about 1 second. The pulse duration of the heteroatom silicon ring compound is relatively short, for example at least about 0.1 seconds, preferably about 0.1 to about 10 seconds, more preferably about 2 to about 6 seconds, even more preferably about 3 to about 5 seconds, even more preferably about 5 seconds.

[0087] It is within the scope of the present invention to move reactants such as heteroatom silicon ring compounds and metal alkyl compounds in a carrier gas. Any inert gas, such as argon, or inert gas, such as nitrogen, is suitable without limitation. However, it is also within the scope of the present invention not to use a carrier gas.

[0088] The methods described herein are applicable to a variety of different types of patterned substrates, as long as they contain metal and non-metal regions. Suitable substrates include, but are not limited to, the currently preferred silicon dioxide and copper on silicon. Other potentially suitable substrates include, but are not limited to, substrates containing non-metal regions, including silicon, germanium, silicon germanium alloys, silicon dioxide, silicon nitride, titanium nitride, tantalum nitride, silicon oxycarbide, silicon oxynitride, silicon carboxynitride, aluminum oxide, hafnium dioxide, titanium dioxide and / or zinc oxide, and substrates containing metal regions composed of copper, cobalt, tungsten, ruthenium and / or molybdenum.

[0089] The present invention will now be described with reference to the following non-limiting examples.

[0090] Comparative Example 1

[0091] At 225°C, 60 seconds of N 2 Zinc oxide was grown on thermally grown silicon dioxide using a remote inductively coupled plasma (2500 W) cleaning method using an alternating pulse sequence of 0.1 sec diethyl zinc, 5 sec purge, 0.1 sec water, and 5 sec purge, repeated 50 times. The film grew rapidly at a rate of 2.8 angstroms per cycle. After 24 cycles, the film thickness was 5.0 nm.

[0092] Comparative Example 2

[0093] The PVD copper on silicon was cleaned by ultrasonic cleaning in ethanol for 5 min. The 2 Zinc oxide was grown on the cleaned copper using a remote inductively coupled plasma (2500 W) using an alternating pulse sequence of 0.1 sec diethylzinc, 5 sec purge, 0.1 sec water, and 5 sec purge, repeated 50 times. The film grew rapidly at a rate of 2.8 angstroms per cycle. After 24 cycles, the film thickness was 5.0 nm.

[0094] Example 1

[0095] At 225°C, N 2 The thermally grown silicon dioxide was cleaned by remote inductively coupled plasma (2500W) and then exposed to N-methyl-aza-2,2,4-trimethylsilylcyclopentane for 5 seconds, followed by a purge for 30 seconds. Next, the substrate was exposed to an alternating pulse sequence of 0.1 second diethylzinc, 5 second purge, 0.1 second water, and 5 second purge, repeated 50 times. The film began to grow at the 11th cycle and reached 3.0 angstroms per cycle by the last cycle. After the 44th cycle, the film thickness was 7.3nm.

[0096] Example 2

[0097] PVD copper on silicon was ultrasonically cleaned in ethanol for 5 min. The copper was exposed to N at 225 °C for 60 s. 2 The substrate was exposed to a remote inductively coupled plasma (2500 W) and then to N-methyl-aza-2,2,4-trimethylsilylcyclopentane for 5 seconds, followed by a 30-second purge. Subsequently, the substrate was exposed to an alternating pulse sequence of 0.1 second diethylzinc, 5 second purge, 0.1 second water, and 5 second purge, repeated 50 times. The film began to grow at the 44th cycle and remained below 1 angstrom per cycle until the last cycle.

[0098] Table 1 below summarizes the operating steps in Examples 1 and 2; Step 2 is omitted in Comparative Examples 1 and 2. The thickness variation of the films prepared in Examples 1 and 2 and Comparative Examples 1 and 2 over time is shown in Table 1. Figure 1 shown.

[0099] It can be observed that in the absence of the heteroatom silicon ring compound, growth on the non-metallic oxide surface starts immediately, while growth on the metallic copper surface is slow, and after about 30 cycles, ALD-like metal oxide deposition begins. The thickness gap between the growth on the non-metallic and metallic surfaces is not sufficient to meet the requirements of most ASD DoD schemes, and the slow growth on the copper surface observed in the first 30 cycles requires further process steps to clean or mitigate. In contrast, applying the heteroatom silicon ring compound before the start of the metal oxide deposition process results in a larger thickness gap between the two surfaces, and no signs of metal oxide growth on copper for more than 40 cycles. This provides a >7nm thick ASD DoD layer on the non-metallic surface while retaining the metallic surface without deposited metal oxide or dielectric film. This thickness is sufficient for the FSAV scheme.

[0100] Table 1 Pulse sequences of Example 1 and Example 2

[0101] 1: 60s 5% N 2 Medium plasma pre-cleaning (2500W)

[0102] 2: 5.0s N-methyl-aza-2,2,4-trimethylsilylcyclopentane, 30s purge

[0103] 3: 0.1s diethyl zinc, 5s purge

[0104] 4: 0.1s water, 5s purge

[0105] 5: Repeat steps 3-4 49 times

[0106] Those skilled in the art will appreciate that modifications may be made to the above embodiments without departing from the broad inventive concept thereof. It should be understood that the present invention is not limited to the specific embodiments disclosed, but is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A method for selectively depositing a metal oxide or a dielectric layer on a patterned substrate, the method comprising: (a) introducing a patterned substrate having metal and non-metal regions into a reaction zone of a deposition chamber, and heating the reaction zone to a temperature of about 175° C. to about 350° C.; (b) exposing the patterned substrate to a pulse of a heteroatom silicon ring compound and purging the deposition chamber; and (c) performing atomic layer deposition or chemical vapor deposition on the patterned substrate to form a metal oxide or dielectric layer on the patterned substrate; Wherein, the metal oxide or dielectric layer is selectively formed on the non-metallic area of ​​the patterned substrate.

2. The method of claim 1, wherein step (c) comprises: (d) exposing the patterned substrate to a pulse of a metal alkyl compound; (e) purging the deposition chamber; (f) exposing the patterned substrate to a pulse of water; (g) purging the deposition chamber; and (h) Repeating steps (d) to (g) until the desired metal oxide or dielectric layer thickness is achieved.

3. The method of claim 1 or 2, further comprising performing a plasma treatment step before step (a).

4. A method as claimed in any preceding claim, further comprising performing at least one plasma treatment step before or after steps (a) to (g).

5. A process as claimed in any one of claims 2 to 4 wherein the metal alkyl compound is a Group 12 or Group 13 metal alkyl compound.

6. The method of claim 5, wherein the metal alkyl compound is selected from the group consisting of diethylzinc, trimethylaluminum, dimethylaluminum isopropoxide, dimethylzinc, trimethylgallium, triethylgallium, triethylaluminum, triethylindium, dimethylcadmium and dimethylmercury.

7. The method according to any one of the preceding claims, wherein the heteroatom silicon ring compound is a cyclonitrogen silane as described in formula (1), a cyclosulfur silane as described in formula (2), or a cyclotellurium silane as described in formula (3): wherein R1 is hydrogen or a linear, branched or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl or alkylamino group having 1 to about 12 carbon atoms, R2 is a linear, branched or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl or alkylamino group having 1 to about 12 carbon atoms, n is an integer from 1 to about 4, and X and Y are each independently a linear, branched or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl or alkylamino group.

8. The method according to claim 7, wherein the heteroatom silicon ring compound is N-methyl-aza-2,2,4-trimethylsilanol, N-(2-aminoethyl)-2,2,4-trimethyl-1-aza-silanol, N-n-butyl-aza-2,2-dimethoxysilanol, N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silanol, (N,N-dimethylaminopropyl) -Aza-2-methyl-2-methoxysilacyclopentane, (1-(3-triethoxysilyl)propyl)-2,2-diethoxy-1-aza-silacyclopentane, N-allyl-aza-2,2-dimethoxysilacyclopentane, N-tert-butyl-aza-2,2,-dimethyloxysilacyclopentane, 2,2,4-trimethyl-1-thio-2-silacyclopentane, or 2,2,4-trimethyl-1-tellurium-2-silacyclopentane.

9. The method of any preceding claim, wherein the metal region of the substrate comprises at least one of copper, cobalt, tungsten, ruthenium and molybdenum.

10. A method as claimed in any of the preceding claims, wherein the non-metallic region of the substrate comprises at least one of silicon, germanium, silicon germanium alloy, silicon dioxide, silicon nitride, titanium nitride, tantalum nitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, hafnium dioxide, titanium dioxide and zinc oxide.

11. A method as claimed in any preceding claim, wherein the substrate is silicon dioxide or copper on silicon.

12. A method as claimed in any preceding claim, wherein the pulse duration of the heteroatom silicon ring compound in step (b) is at least about 0.1 seconds.

13. The method of any preceding claim, wherein the pulse duration of the heteroatom silicon ring compound in step (b) is from about 0.1 seconds to about 10 seconds.

14. The method of claim 13, wherein the pulse duration of the heteroatom silicon ring compound in step (b) is about 5 seconds.

15. A process as claimed in any preceding claim wherein the reaction zone in step (a) is heated to a temperature of about 225°C to about 275°C.

16. The method of any preceding claim, wherein the mixed oxide dielectric film has a thickness of about 5 nm to about 50 nm.

17. The method of claim 16, wherein the mixed oxide dielectric film has a thickness of about 5 nm to about 10 nm.

18. A method as claimed in any preceding claim, wherein step (b) forms a blocking layer on the patterned substrate.

19. The method of claim 1, wherein step (c) comprises: (d) exposing the patterned substrate to a pulse of a metal alkyl compound; (e) purging the deposition chamber; (f) exposing the patterned substrate to a pulse of water; (g) purging the deposition chamber; (h) repeating steps (d) to (g) at least once; (i) performing a plasma treatment step; and (j) Repeating steps (d) to (i) until the desired metal oxide or dielectric layer thickness is achieved.

20. The method of claim 1, wherein the metal oxide or dielectric layer is formed of a metal alkyl compound.

21. The method of claim 19, wherein the metal alkyl compound is a Group 12 or Group 13 metal alkyl compound.

22. The method of claim 21, wherein the metal alkyl compound is selected from the group consisting of diethylzinc, trimethylaluminum, dimethylaluminum isopropoxide, dimethylzinc, trimethylgallium, triethylgallium, triethylaluminum, triethylindium, dimethylcadmium and dimethylmercury.

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