Platform efficiency tracker

Abstract

Systems, apparatus, and methods for dynamically estimating power loss in a computing system. A system management circuit tracks a state of a computing system and dynamically estimates power loss in the computing system based in part on the state. Based on the estimated power loss, power consumption of the computing system is estimated. In response to detecting a reduced power loss in at least a portion of the computing system, the system management circuitry is configured to improve a power performance state of one or more circuits of the computing system while remaining within a power allocation limit of the computing system.

Description

Background Art

[0001] Related technical description

[0002] When designing a computer or other processor-based system, many design factors must be considered. A successful design may require various trade-offs between power consumption, performance, heat output, etc. For example, the design of a computer system that emphasizes high performance may allow for greater power consumption and heat output. Conversely, the design of a portable computer system that is sometimes powered by a battery may emphasize reducing power consumption at the expense of some performance. Regardless of the specific design goals, a computing system generally has a given amount of power available during operation. This power must be allocated among the various components within the system - some power to the central processing circuitry, some power to the memory subsystem, some power to the graphics processing circuitry, and so on. How power is allocated among the system components may also change during operation.

[0003] Computers and other complex electronic systems are often designed with thermal and power budgets. Power consumption and heat output must be kept within certain limits. However, power consumption and heat output maximums are parameters that must be considered in the context of system performance requirements. In the case where too much emphasis is placed on power and thermal requirements in the design of a system, performance goals may not be achieved. Conversely, too much emphasis on performance may result in power and thermal goals being exceeded. Because changes in the required processing load can result in large changes in power consumption and heat output, many processors have the ability to adjust the operating voltage and operating clock frequency. This allows power consumption and thermal output to be controlled and can allow these parameters to meet design requirements.

[0004] When designing a computing system, the total amount of power required and available is determined. For example, it may be determined that the central processing circuit has a certain range of power requirements, that the memory subsystem has a certain power requirement, and so on. The computing system power requirements are then determined based on the requirements of all components of the system. Generally speaking, components within a computing system are inefficient, which results in power loss. For example, voltage regulators, board traces, fans, and other components within the system are not completely efficient in terms of power consumption. To address this inefficiency, assumptions are made at design time about how much power loss there is and how much power is actually available. For example, at design time, it may be determined that the voltage regulator in the system is between 80% and 95% efficient when operating under different conditions. Since the system designer must consider all conditions, a conservative assumption is made that the voltage regulator is 80% efficient, and the total available board power is determined based on this assumption. Making conservative assumptions ensures that there is always enough power available. However, during actual system operation, the efficiency is not always 80%. Sometimes the efficiency is higher, and the actual available power can be more than assumed. Therefore, power that could have been used to improve system performance is not used, and performance is unnecessarily limited. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:

[0006] Figure 1 is a block diagram of a specific implementation of a computing system.

[0007] Figure 2 is a block diagram of another specific implementation of a computing system.

[0008] Figure 3 is a graph illustrating the power loss in the system.

[0009] Figure 4 is a block diagram of a specific implementation of the system management circuit.

[0010] Figure 5 is a generalized flow chart illustrating one specific implementation of a method for tracking power loss and changing power performance states in a system.

[0011] Figure 6 is a generalized flow chart illustrating one specific implementation of a method for transferring a portion of a power budget between system components. DETAILED DESCRIPTION

[0012] In the following description, many specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, it will be appreciated by those of ordinary skill in the art that each specific implementation may be practiced without these specific details. In some cases, well-known structures, components, signals, computer program instructions, and techniques are not shown in detail to avoid blurring the methods described herein. It should be understood that, for simplicity and clear illustration, the elements shown in the accompanying drawings are not necessarily drawn to scale. For example, the size of some of these elements may be enlarged relative to other elements.

[0013] Disclosed are systems, devices, and methods for tracking power efficiency in a computing system and changing a power performance state. In this context, power efficiency refers to the percentage of total power actually available to the SoC that is drawn from a power source. The computing system includes a system management circuit that estimates the power efficiency of one or more components of the system based on various system conditions. In one embodiment, the system management circuit allocates power to components in the system based on determined system requirements. In one embodiment, a given component is allocated a maximum available power budget within which the given component needs to operate. During operation of the computing system, various conditions are monitored. In response to detecting a first condition, it is determined that the given component operates with increased power efficiency, and the power performance state of the given component is improved. In various embodiments, the power performance of the given component is improved without increasing the estimated power consumption. In this way, improved performance is obtained while maintaining a given estimated power consumption level.

[0014] In one implementation, the estimated power consumption of a given component is determined in part based on previously determined characterizations and current operating conditions. Such characterizations can be performed pre-silicon or post-silicon. Such operating conditions can include one or more of operating temperature, operating frequency, current drawn, etc. In one implementation, the power efficiency tracking circuit is configured to generate an estimate of power consumption based on dynamic calculations using the above operating conditions and / or other parameters. In some implementations, the dynamic calculations are performed based on formulas implemented in hardware (i.e., circuits). In other implementations, the calculations are performed using a combination of hardware and software.

[0015] Reference now Figure 1, a block diagram of one implementation of a computing system 100 is shown. In this example, a power source 104 is shown coupled to a board 102 including system components. In this implementation, the power source 104 represents the total amount of power available to the components of the board 102 and the system components. In this implementation, the illustrated computing system 100 includes a system on a chip (SoC) 105 coupled to a memory 160. However, it is possible and conceivable that one or more of the illustrated components of the SoC 105 are not integrated onto a single chip. In some implementations, the SoC 105 includes a plurality of processor cores 110A to 110N and a GPU 140. In the illustrated implementation, the SoC 105, the memory 160, and other components (not shown) are part of a system board 102 (e.g., a motherboard), and one or more of the peripherals 150A to 150N and the GPU 140 are discrete entities (e.g., daughter boards, etc.) coupled to the system board 102. In other specific implementations, GPU 140 and / or one or more of peripherals 150 may be permanently mounted on board 102 or otherwise integrated into SoC 105. It should be noted that processor cores 110A to 110N may also be referred to as processing circuits or processors. Processor cores 110A to 110N and GPU 140 are configured to execute instructions of one or more instruction set architectures (ISAs), which may include operating system instructions and user application instructions. These instructions include memory access instructions, which may be translated and / or decoded into memory access requests or memory access operations for memory 160.

[0016] In another specific implementation, the SoC 105 includes a single processor core 110. In a multi-core specific implementation, the processor cores 110 may be identical to each other (i.e., symmetric multi-core), or one or more cores may be different from other cores (i.e., asymmetric multi-core). Each processor core 110 includes one or more execution circuits, cache memories, schedulers, branch prediction circuits, etc. In addition, each processor core 110 is configured to assert access requests to a memory 160, which is used as the main memory of the computing system 100. Such requests include read requests and / or write requests and are initially received by the bridge 120 from the corresponding processor core 110. Each processor core 110 may also include a queue or buffer for storing flight instructions that have not yet completed execution. The queue may be referred to as an "instruction queue" in this article. Some of the instructions in the processor core 110 may still wait for their operands to become available, while other instructions may wait for an available arithmetic logic circuit (ALU). Instructions waiting for an available ALU may be referred to as pending ready instructions. In one specific implementation, each processor core 110 is configured to track the number of pending ready instructions.

[0017] In the illustrated implementation, an input / output memory management circuit (IOMMU) 135 is coupled to the bridge 120. In one implementation, in the computing system 100, the bridge 120 is used as a north bridge device and the IOMMU 135 is used as a south bridge device. In other implementations, the bridge 120 can be a structure, a switch, a bridge, any combination of these components, or another component. A variety of different types of peripheral buses (e.g., a peripheral component interconnect (PCI) bus, a PCI expansion (PCI-X), a PCIE (PCI Express) bus, a Gigabit Ethernet (GBE) bus, a universal serial bus (USB)) can be coupled to the IOMMU 135. Various types of peripheral devices 150A to 150N can be coupled to some or all of the peripheral buses. Such peripheral devices 150A to 150N include (but are not limited to) keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc. At least some of the peripheral devices 150A-150N coupled to the IOMMU 135 via corresponding peripheral buses may assert memory access requests using direct memory access (DMA). These requests, which may include read requests and write requests, are transmitted to the network bridge 120 via the IOMMU 135 .

[0018] In some implementations, SoC 105 includes a graphics processing circuit (GPU) 140 that is configured to be coupled to a display 145 (not shown) of computing system 100. In some implementations, GPU 140 is an integrated circuit that is separate and distinct from SoC 105. GPU 140 performs various video processing functions and provides processed information to display 145 for output as visual information. GPU 140 may also be configured to perform other types of tasks scheduled to GPU 140 by an application scheduler. GPU 140 includes "N" computing circuits for performing tasks of various applications or processes, where "N" is a positive integer. The "N" computing circuits of GPU 140 may also be referred to as "processing circuits". Each computing circuit of GPU 140 is configured to assert an access request to memory 160.

[0019] In one implementation, the memory controller 130 is integrated into the bridge 120. In other implementations, the memory controller 130 is separate from the bridge 120. The memory controller 130 receives memory requests transmitted from the bridge 120. Data accessed from the memory 160 in response to a read request is transmitted by the memory controller 130 to the request agent via the bridge 120. In response to a write request, the memory controller 130 receives the request and the data to be written from the request agent via the bridge 120. In the event that there are multiple memory access requests pending at a given time, the memory controller 130 arbitrates between these requests. For example, when the power budget allocated to the memory controller 130 limits the total number of requests that can be executed on the memory 160, the memory controller 130 can prioritize critical requests while delaying non-critical requests.

[0020] In some implementations, the memory 160 includes a plurality of memory modules. Each of the memory modules includes one or more memory devices (e.g., memory chips) mounted thereon. In some implementations, the memory 160 includes one or more memory devices mounted on a motherboard or other carrier on which the SoC 105 is also mounted. In some implementations, at least a portion of the memory 160 is implemented on a bare die of the SoC 105 itself. Implementations with a combination of the above implementations are also possible and expected. In one implementation, the memory 160 is used to implement a random access memory (RAM) for use with the SoC 105 during operation. The RAM implemented may be a static RAM (SRAM) or a dynamic RAM (DRAM). The DRAM types used to implement the memory 160 include, but are not limited to, double data rate (DDR) DRAM, DDR2 DRAM, DDR3 DRAM, and the like.

[0021] although Figure 1 105. Although not explicitly shown, the SoC 105 may also include one or more cache memories inside the processor cores 110. For example, each processor core 110 may include an L1 data cache and an L1 instruction cache. In some implementations, the SoC 105 includes a shared cache 115 shared by the processor cores 110. In some implementations, the shared cache 115 is a second level (L2) cache. In some implementations, each processor core in the processor cores 110 has an L2 cache implemented therein, and thus the shared cache 115 is a third level (L3) cache. The cache 115 may be part of a cache subsystem that includes a cache controller.

[0022] In one implementation, the system management circuit 125 is integrated into the bridge 120. In other implementations, the system management circuit 125 can be separate from the bridge 120, and / or the system management circuit 125 can be implemented as multiple separate components in multiple locations of the SoC 105. The system management circuit 125 is configured to manage the power states of the various processing circuits of the SoC 105. The system management circuit 125 may also be referred to as a power management circuit. In one implementation, the system management circuit 125 uses dynamic voltage and frequency scaling (DVFS) to change the frequency and / or voltage of the processing circuits to limit the power consumption of the processing circuits to a selected power allocation.

[0023] SoC 105 includes a plurality of temperature sensors 170A to 170N, which represent any number of temperature sensors. It should be understood that although sensors 170A to 170N are shown on the left side of the block diagram of SoC 105, sensors 170A to 170N may be distributed throughout SoC 105, and / or may be located near major components of SoC 105 in an actual implementation of SoC 105. In one implementation, there are sensors 170A to 170N for each core 110A to 110N, the computing circuits of GPU 140, and other major components. In this implementation, each sensor 170A to 170N tracks the temperature of the corresponding component. In another implementation, there are sensors 170A to 170N for different geographic regions of SoC 105. In this implementation, sensors 170A to 170N are distributed throughout SoC 105 and are positioned to track the temperature of different regions of SoC 105 to monitor whether there are any hot spots in SoC 105. In other implementations, other schemes for positioning sensors 170A- 170N within SoC 105 are possible and contemplated.

[0024] SoC 105 also includes a plurality of performance counters 175A to 175N, which represent any number and type of performance counters. It should be understood that, although performance counters 175A to 175N are shown on the left side of the block diagram of SoC 105, performance counters 175A to 175N may be distributed throughout SoC 105 and / or may be located within major components of SoC 105 in an actual implementation of SoC 105. For example, in one implementation, each core 110A to 110N includes one or more performance counters 175A to 175N, memory controller 130 includes one or more performance counters 175A to 175N, GPU 140 includes one or more performance counters 175A to 175N, and other performance counters 175A to 175N are utilized to monitor the performance of other components. Performance counters 175A-175N may track a variety of different performance metrics, including instruction execution rates of cores 110A-110N and GPU 140, memory bandwidth consumed, line buffer hit rates, cache hit rates of various caches (e.g., instruction cache, data cache), and / or other metrics.

[0025] In one implementation, the SoC 105 includes a phase-locked loop (PLL) circuit 155 coupled to receive a system clock signal. The PLL circuit 155 includes a plurality of PLLs configured to generate and distribute corresponding clock signals to each of the processor cores in the processor cores 110 and other components of the SoC 105. In one implementation, the clock signals received by each of the processor cores in the processor cores 110 are independent of each other. In addition, in this implementation, the PLL circuit 155 is configured to individually control and change the frequency of each of the clock signals provided to the corresponding processor cores in the processor cores 110 independently of each other. The frequency of the clock signal received by any given processor core in the processor cores 110 can be increased or decreased according to the power state assigned by the system management circuit 125. The various frequencies of the clock signal output from the PLL circuit 155 correspond to different operating points of each of the processor cores in the processor cores 110. Therefore, by changing the frequency of its corresponding received clock signal, a change in the operating point of a specific one of the processor cores 110 is achieved.

[0026] For purposes of this disclosure, an operating point may be defined as a clock frequency, and may also include an operating voltage (e.g., a supply voltage supplied to a functional circuit). Increasing the operating point of a given functional circuit may be defined as increasing the frequency of a clock signal supplied to that circuit, and may also include increasing its operating voltage. Similarly, reducing the operating point of a given functional circuit may be defined as reducing the clock frequency, and may also include reducing the operating voltage. Limiting an operating point may be defined as limiting the clock frequency and / or operating voltage to a specified maximum value under a particular set of conditions (but not necessarily a maximum limit across all conditions). Thus, when the operating point is limited for a particular processing circuit, it may operate at a clock frequency and operating voltage up to a specified value under the current set of conditions, but may also operate at a clock frequency and operating voltage value less than the specified value.

[0027] In the case where changing the respective operating point of one or more processor cores 110 includes changing one or more respective clock frequencies, the system management circuit 125 changes the state of the digital signals provided to the PLL circuit 155. In response to the changes in these signals, the PLL circuit 155 changes the clock frequency of the affected processor cores 110. In addition, the system management circuit 125 may also cause the PLL circuit 155 to disable providing the respective clock signal to the corresponding one of the processor cores 110.

[0028] In the illustrated implementation, the SoC 105 also includes a plurality of voltage regulators (VRs) 165A to 165M, which are included on the board 102. Each of these voltage regulators is coupled to one or more components within the system to provide a given voltage. In other implementations, the voltage regulator 165 may be implemented separately from the SoC 105. In various implementations, the power source 104 represents a power source that establishes the maximum amount of power available to the board / platform 102. A portion of the power provided by the power source 104 is actually available as available power for the SoC 105, while another portion of the power is lost. Power loss in the system occurs in a variety of ways. For example, power is lost when power is transmitted from the power source 104 to the voltage regulator 165. For example, when power is transmitted from one location to another, losses occur in the signal traces of the board 102. Similarly, power loss occurs in the voltage regulator 165. As known to those skilled in the art, the voltage regulator 165 is not completely efficient and cannot convert power completely efficiently. Each of the components of the SoC 105 is also not completely efficient in its power usage, and some power losses occur during operation. More generally, a portion of the maximum amount of power provided by the power source 104 is consumed by the SoC and other components of the system 100, while the remaining power is consumed in the form of platform / power delivery losses. Therefore, some portions of the power provided by the power source 104 are lost. The voltage regulator 165 provides a supply voltage to each of the processor cores 110 and other components of the SoC 105. In some specific implementations, the voltage regulator 165 provides a supply voltage that is variable according to a specific operating point. In some specific implementations, each of the processor cores in the processor core 110 shares a voltage plane. Therefore, in this specific implementation, each of the processor cores in the processor core 110 operates at the same voltage as the other processor cores in the processor core 110. In another specific implementation, the voltage plane is not shared, and therefore the supply voltage received by each processor core 110 is set and adjusted independently of the corresponding supply voltage received by the other processor cores 110. Thus, in a specific implementation with a non-shared voltage plane, operating point adjustments including adjustments of the supply voltage can be selectively applied to each processor core 110 independently of other operating point adjustments. In the event that changing the operating point includes changing the operating voltage of one or more processor cores 110, the system management circuitry 125 changes the state of a digital signal provided to the voltage regulator 165. In response to the change in the signal, the voltage regulator 165 adjusts the supply voltage provided to the affected processor core 110. In the event that power is to be removed from one of the processor cores 110 (i.e., gated), the system management circuitry 125 sets the state of the corresponding signal of the signal so that the voltage regulator 165 does not provide power to the affected processing core 110.

[0029] In various implementations, computing system 100 may be any of a computer, a laptop, a mobile device, a server, a network server, a cloud computing server, a storage system, or various other types of computing systems or devices. It should be noted that the number of components of computing system 100 and / or SoC 105 may vary depending on the implementation. The number of each component / subcomponent may be comparable. Figure 1 The number shown may be greater or less. Note also that computing system 100 and / or SoC 105 may include Figure 1 In addition, in other specific implementations, the computing system 100 and the SoC 105 are different from Figure 1 Constructed as shown in .

[0030] Now go to Figure 2 , showing the coupling to Figure 1 The power source 104 Figure 1 1 is a block diagram of a portion of a board 102 of FIG. 1. In the example shown, one specific implementation of a system management circuit 210 is shown. The system management circuit 210 is coupled to computing circuits 205A to 205N, a memory controller 225, a phase-locked loop (PLL) circuit 230, and a voltage regulator 235A. As illustrated, a power source 104 is coupled to supply power to a plurality of voltage regulators 335A to 235C and other components 240 on the board (not shown). In this example, the power source 104 is shown as supplying power to a voltage regulator 235A coupled to the computing circuit 205, a voltage regulator 235B coupled to the system management circuit 210, and a voltage regulator 224 coupled to the memory controller 225. As can be appreciated, other voltage regulators and system components can be coupled to receive power supplied by the power source 104, and Figure 2 The illustration is for exemplary purposes only. The system management circuit 210 may also be coupled to Figure 2 One or more other components not shown in the figure. Computing circuits 205A to 205N represent any number and type of computing circuits, and computing circuits 205A to 205N may also be referred to as processors or processing circuits. For example, in one specific implementation, at least one computing circuit is a CPU and another computing circuit is a GPU.

[0031] The system management circuit 210 includes an efficiency tracking circuit 202, a power allocation circuit 215, and a power management circuit 220. The efficiency tracking circuit 202 is configured to dynamically track and estimate the power efficiency of various components within the system. By dynamically tracking the power efficiency (or power loss), the tracking circuit 202 is able to dynamically estimate the power consumption. It should be noted that the total power consumed is composed of the power consumed by all components of the platform, including the SoC, other components, and other elements of the platform (e.g., power distribution network, etc.). In this case, the power efficiency or power loss tracked corresponds to the entire platform, which is not usually tracked as part of the power estimation / tracking of the SoC component. Based on the estimate of the power consumed by the SOC and the power loss estimate in the board / platform, the total power drawn from the power source can be estimated. The power allocation circuit 215 is configured to allocate a power budget to each computing circuit in the computing circuits 205A to 205N, the memory subsystem including the memory controller 225, and / or one or more other components. For the host system or device, the total amount of power that the power allocation circuit 215 can be used to disperse to the components can be limited. The power allocation circuit 215 receives various inputs from the computing circuits 205A to 205N, including the status of the missing status holding register (MSHR) of the computing circuits 205A to 205N, the instruction execution rate of the computing circuits 205A to 205N, the number of instructions to be processed and ready to be executed in the computing circuits 205A to 205N, the instruction and data cache hit rate of the computing circuits 205A to 205N, the consumed memory bandwidth, and / or one or more other input signals. The power allocation circuit 215 can use these inputs to determine whether the computing circuits 205A to 205N have tasks to execute, and then the power allocation circuit 215 can adjust the power budget allocated to the computing circuits 205A to 205N based on these determinations. The power allocation circuit 215 can also receive inputs from the memory controller 225, including the consumed memory bandwidth, the total number of requests in the pending request queue, the number of critical requests in the pending request queue, the number of non-critical requests in the pending request queue, and / or one or more other input signals. The power allocation circuit 215 may utilize the states of these inputs to determine the power budget allocated to the memory subsystem.

[0032] The PLL circuit 230 receives the system clock signal and includes any number of PLLs configured to generate corresponding clock signals and distribute the clock signals to each of the computing circuits 205A to 205N and other components. The power management circuit 220 is configured to transmit control signals to the PLL circuit 230 to control the clock frequency supplied to the computing circuits 205A to 205N and other components. The voltage regulator 235 provides a supply voltage to each of the computing circuits 205A to 205N and other components. The power management circuit 220 is configured to transmit control signals to the voltage regulator 235 to control the voltage supplied to the computing circuits 205A to 205N and other components.

[0033] The memory controller 225 is configured to control the memory (not shown) of the host computing system or device. For example, the memory controller 225 issues read, write, erase, refresh, and various other commands to the memory. In one specific implementation, the memory controller 225 includes ( Figure 2 The memory controller 225 is a component of the memory controller 225 of the system management circuit 210. When the memory controller 225 receives the power budget from the system management circuit 210, the memory controller 225 converts the power budget into the number of memory requests per second that the memory controller 225 is allowed to perform on the memory. The number of memory requests per second is executed by the memory controller 225 to ensure that the memory controller 225 remains within the power budget allocated to the memory subsystem by the system management circuit 210. The number of memory requests per second can also take into account the state of the DRAM to allow the memory controller 225 to issue pending critical and non-critical requests to the currently open DRAM rows as long as the given memory power constraints are met. The memory controller 225 prioritizes critical requests without exceeding the number of requests per second that the memory controller 225 is allowed to perform. When all critical requests have been processed and the memory controller 225 has not reached the specified request limit per second, the memory controller 225 processes non-critical requests.

[0034] Reference now Figure 3 , presents an example graph illustrating how the power efficiency of a platform may vary according to various operating conditions. In the example shown, the y-axis enumerates the estimated power range loss Loss (W) (e.g., 0 watts to 400 watts), and the x-axis illustrates the current range I drawn by the platform. out (e.g., 0 amps to 800 amps). As shown, during operation, power loss increases as the maximum current increases. In various implementations, the loss may vary based on various conditions, including, for example, temperature. For example, when I out = 100A, the power loss is about 10W. On the other hand, when I out=300W, the power loss is about 70W. Furthermore, it can be seen that the relationship is non-linear. In the example shown, the relationship between current and power loss is quadratic. Therefore, the power loss rate in the platform increases as the current increases.

[0035] As described above, when designing a computing system, the designer must consider the inefficiencies that cause power losses when determining how much power to allocate to various components within the system. Designers and suppliers of various components used in such computing systems (e.g., processors, storage controllers, memory, I / O circuits, etc.) must determine the power requirements of the components in the design. For example, when determining the power requirements of the GPU, the GPU designer makes assumptions about how much power is lost in the power delivery network during operation. As an example, the GPU designer may determine that the sum of all components of the GPU requires a maximum of 400 watts of power to operate. In addition, it may be determined that 7% to 15% of the power is lost in the power delivery network of the GPU during operation. Taking into account this estimated power loss, the GPU designer determines the actual power budget required to deliver 400 watts of power to the components of the GPU, and reports to the platform / board designer that the GPU needs to allocate more than 400 watts of power to account for these losses. For example, a GPU supplier may report that the GPU requires approximately 400 / 0.85=471 watts, assuming an efficiency of only 85%.

[0036] In the above example, the GPU vendor uses the upper limit of the power loss range (15% loss) to ensure normal operation of the GPU under all operating conditions. In other words, the GPU vendor assumes a worst-case power loss and statically assumes that power loss at all times during operation. However, actual power losses vary during operation, and the platform may actually operate more efficiently (with respect to power) at different times and under different conditions than the 15% power loss assumption. Therefore, in the case where the GPU is consuming the maximum amount of power based on an estimate assuming 85% efficiency, the GPU will be limited from further performance improvements - even if the GPU is not actually consuming the maximum amount of power.

[0037] In order to enable a component (the GPU used in this example) to better track power efficiency, in one implementation, at least one power efficiency tracking circuit is integrated into the system. Figure 4System management circuitry 410 is illustrated, which includes efficiency tracking circuitry 402, power allocation circuitry 415, and power / performance management circuitry 440. System management circuitry 410 is also shown as being configured to receive any number of various system parameters corresponding to the condition, operation, or state of the system, as shown at 420A to 420Z. In the example shown, the parameters are shown to include an operating temperature 420A for a given circuit, a maximum current 420B for a given circuit, and an operating frequency for a given circuit. Other parameters are also possible and contemplated. In various implementations, one or more of parameters 420 are reported from other circuits or portions of the system (e.g., based on sensors, performance counters, other event / activity detection, or other means). In some implementations, one or more parameters are tracked within system management circuitry 410. For example, system management circuitry 410 may track the current power performance state of components within the system, the duration of a power performance state, previously reported parameters, and the like.

[0038] exist Figure 4 In the example of , the efficiency tracking circuit 402 includes a model 430. The model 430 is used to estimate the power efficiency of the circuit based on the parameters 420. In one embodiment, the model 430 includes a circuit configured to perform a calculation representing the relationship between power loss and current based on the parameters 420. In other embodiments, the model 430 may include a combination of hardware and software (e.g., firmware) to calculate the estimate. In various embodiments, the model 430 is developed at least in part based on the operational characterization of the circuit being tracked. For example, taking a GPU as an example, a designer may perform a large number of tests to characterize the power loss of the GPU during operation under various conditions. These conditions include characterizing the power loss based on operating frequency, voltage, current, workload type (e.g., compute-intensive vs. memory-intensive), circuits in operation, temperature, etc. Based on these characteristics, a model representing the power loss based on these different conditions is developed. In one embodiment, a formula / function representing such a model (as described above) is created to represent the power efficiency of the circuit, and a circuit that implements the function is designed. For example, in some embodiments, a function represented by the formula P is used. 损耗 =c2*I out 2 +c1*I out +c0 to represent the power loss. In this example, c is a fixed coefficient that can be determined experimentally, by simulation or other means, and I out is the current. In other embodiments, a more advanced model may be used, which is given by the formula P 损耗 =f2(v,temp)*I out 2 +f1(v,temp)*I out+f0(v,temp). In this model, the coefficients are replaced with functions that depend on voltage and temperature. In other specific implementations, a lookup table or other structure can be used to estimate the current power efficiency. During system operation, the system management circuit 410 monitors the estimated power loss based on the estimate of the efficiency tracking circuit 402. Based on the estimated power loss, the system management circuit 410 can change the power performance state of one or more circuits of the system. For example, in one specific implementation, a circuit (e.g., a computing circuit) is configured to operate in multiple power performance states. Under sufficient power budget, the computing circuit can operate at a higher power performance state and complete work at a faster rate. However, under a reduced power budget, the computing circuit may be restricted to a lower power performance state, which causes the work to be completed at a slower rate.

[0039] Reference now Figure 5 , a specific implementation of how dynamically determined power losses can be used to improve system performance. Figure 5 500 and 520. In one implementation, processes 500 and 520 correspond to functions performed by system management circuitry (e.g., system management circuitry 410) to track power efficiency and modify power performance states based on dynamically determined power consumption estimates. For example, in one implementation, system management circuitry 410 includes circuitry configured to perform the functions illustrated by processes 500 and 520. In some implementations, processes 500 and 520 operate simultaneously, although this is not necessarily the case.

[0040] Figure 5 Process 500 corresponds to the functionality of the efficiency tracking circuit to monitor system conditions (e.g., Figure 4 420, etc.) and dynamically calculate power consumption estimates. As described above, the model can be integrated into a circuit for estimating power loss under various conditions. As previously described, static assumptions (e.g., 15%) are traditionally made about power loss, which are assumed in all cases. In the illustrated embodiment, process 500 is shown as including an initial power consumption estimate (PCE) 502. However, other specific implementations can calculate the initial estimate based on box 512 discussed below. Process 500 is configured to monitor and detect various conditions (e.g., condition 504 and condition 506), and calculate new power consumption estimates based on dynamic detection and estimation of power loss (or power efficiency). It should be noted that in order to simplify the drawings, only two conditions are illustrated. In fact, a specific implementation can monitor any number of conditions.

[0041] In the example shown, a determination is made as to whether a first condition is detected (504). The condition takes into account a system state represented by a parameter received or otherwise available by a system management circuit (e.g., circuit 410). Based on the state of the system, a determination is made as to whether a change in the estimated power consumption is detected (decision block 504). In the event that a decrease in the estimated power consumption (i.e., an increase in the estimated efficiency) is detected, the current estimated power consumption is reduced (508), and a new power consumption estimate (PCE) is generated or otherwise calculated. Alternatively, in the event that a decrease in the estimate is not detected (decision block 504), a determination is made as to whether an increase in the estimated power consumption is detected (decision block 506). In such an event, the estimated power consumption is increased (510), and a new estimated power consumption is generated or otherwise calculated based on the increase (512). In the event that neither condition is detected (504 or 506), monitoring continues until such a condition is detected or some event occurs (e.g., a restart, a power failure, a reduced power state of the system management circuit, an overwrite signal that prevents monitoring, etc.).

[0042] As described above, process 500 and process 520 operate simultaneously in various implementations. Regardless of whether both operate simultaneously at all times or at different times, process 520 is configured to modify the power performance state (PPS) of components within the system based on the estimated power consumption generated by process 500. In various implementations, the estimated power consumption is generated by efficiency tracking circuit 402 and is available to power performance management circuit 440, which is configured to perform the functions exemplified by process 520.

[0043] In one implementation, process 520 is configured to compare the current estimated power consumption with the maximum power allocated to a given circuit. For example, in one implementation, the given circuit is a GPU. However, in other implementations, the circuit is only considered to be part of a GPU (or other system component). As can be appreciated, the methods and mechanisms described herein are applicable to computing circuits at any of a variety of granularities. For example, the power consumption of the GPU as a whole can be estimated and acted upon. Alternatively, specific computing circuits of the GPU can be tracked for power efficiency. All such embodiments are possible and conceivable.

[0044] like Figure 5As shown, the current power consumption estimate (PCE) is compared with the maximum power allocated to the circuit. Using the entire GPU as an example, the platform of which the GPU is a part may have allocated 471 watts of power to the GPU, as described above. Depending on the operating conditions, due to the estimated reduction in power loss, the process 500 may have generated a current estimated power consumption of less than 471 watts. In the case where the estimate is lower than the maximum value (conditional box 522), the PPS of the GPU or some parts of the GPU can be increased while remaining within the total power limit of the power source. As shown, it is determined whether a change in the power performance state (PPS) is indicated (conditional box 524). For example, in the case where the current task benefits from a higher operating frequency of the computing circuit (e.g., a video game that expects a higher frame rate), the power management circuit will increase the PPS of the computing circuit. This may require or otherwise result in applying a higher frequency and voltage to the computing circuit, which consumes additional power. Changing the power performance state may also include allocating more or less power budget to the circuit. After increasing the PPS of the computing circuit, the process 500 will generate a new estimate.

[0045] Conversely, in the event that a PCE is determined to be exceeding the maximum power allocated (decision block 528), the PPS of the circuit may be changed if such a change is indicated (conditional block 530). In some scenarios, the PCE may be allowed to exceed the maximum value for a limited time. Otherwise, a PPS change may be indicated and the PPS reduced (block 532). It should be noted that the circuit whose PPS is changed by process 520 need not be a circuit that is directly tracked for efficiency. For example, in the event that reduced power losses are dynamically detected in the system due to one or more first circuits (e.g., circuit A) operating at a higher power efficiency, the power saved by circuit A may be allocated for use by one or more different circuits (e.g., circuit B). The system management circuitry 410 may be configured to detect scenarios in which such an allocation may be made. For example, models developed during characterization may identify this possibility as well as various other combinations of system operations that may improve performance in one area while efficiency is improved in other areas. Now referring to Figure 6 , shows an example of a method 600 for changing a power performance state (PPS) of a circuit based on an estimated power consumption in a computing system. The example illustrates how the reallocation of power can be modified based on dynamically tracking power efficiency in a computing system. Generally speaking, the reallocation of power budget in a system can remove a portion X of the allocated power budget from one circuit and allocate the portion X to another circuit. However, the example illustrates how the above-described dynamic power consumption estimation can change such a reallocation.

[0046] In this example, it is determined that the computing circuitry is operating with reduced power consumption, and an increase in the PPS of the memory subsystem is initiated (condition 605). The memory subsystem includes a memory controller and one or more memory devices. In one specific implementation, the decision to increase the PPS of the memory subsystem is based in part on detecting the execution of tasks that require increased memory bandwidth (e.g., due to the type of workload), pending critical memory access requests, or other. Depending on the specific implementation, the system management circuitry may utilize one or more of the following: a number of tasks that one or more processors must perform, a current operating point of one or more processors, consumed memory bandwidth, the number of critical and non-critical pending requests in the memory controller, the temperature of one or more components and / or the temperature of the entire system, and / or one or more other metrics for determining how much power to allocate to the memory subsystem.

[0047] After the condition is detected (condition 605), the power budget allocated to the computing circuit is reduced by an amount X (box 615). The amount X can represent an amount of reduced power consumption without considering the computing circuit. In other words, an algorithm can be established for reallocating the power budget within the system without considering the above-mentioned efficiency tracking. For example, power budget reallocation can occur in the system regardless of whether the power consumption is reduced (for example, due to changes in workload, etc.). Based on the algorithm, it is determined that X will be reallocated to the memory subsystem. Assuming that the system management circuit 410 is configured to dynamically track power consumption and corresponding improved efficiency, the system management circuit 410 calculates how much power budget to transfer to the memory subsystem when considering the current power consumption. In the example shown, due to the reduced power consumption, the power budget removed from the computing circuit in excess of the amount X can be allocated to the memory subsystem. Therefore, a certain amount of power X+Y is allocated to the memory subsystem, and the PPS of the memory subsystem is improved and the power consumption is increased to utilize the newly allocated power (box 620). It should be noted that the opposite situation may also occur. In the event that a relatively high (higher) power loss is detected, when a power budget reallocation condition is detected, the amount of reallocated power budget may be reduced to account for the reduced efficiency. A number of such scenarios are possible and contemplated.

[0048] In various specific implementations, program instructions of the software application are used to implement the methods and / or mechanisms previously described. The program instructions describe the behavior of the hardware in a high-level programming language (such as C). Alternatively, a hardware design language (HDL) such as Verilog is used. The program instructions are stored on a non-transitory computer-readable storage medium. Various types of storage media are available. The storage medium can be accessed by a computing system during use to provide the computing system with program instructions and accompanying data for program execution. The computing system includes at least one or more memories and one or more processors configured to execute the program instructions.

[0049] It should be emphasized that the above specific implementation is only a non-limiting example of a specific implementation. Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. It is intended that the following claims be interpreted as covering all such variations and modifications.

Claims

1. A system, comprising: A system management circuit, the system management circuit being configured to: Dynamically estimating power consumption of a computing system; as well as In response to dynamic detection of one of an increase or a decrease in power loss in the computing system, a power performance state of a first circuit among a plurality of circuits of the computing system is changed. 2 . The system of claim 1 , wherein the system management circuit is configured to dynamically estimate power consumption of each of a plurality of circuits of the computing system. 3 . The system of claim 2 , wherein in response to detecting a reduced power loss in a first circuit of the plurality of circuits, the system management circuit is configured to increase a power performance state of a second circuit of the plurality of circuits.

4. The system of claim 2, wherein the computing system is a graphics processing circuit and the system management circuit is configured to increase a power performance state of the computing circuit in response to detecting reduced power consumption in the memory subsystem.

5. The system of claim 2, wherein the system management circuit is configured to dynamically estimate the power consumption of the computing system based on a state of the computing system, wherein the state is based in part on a plurality of parameters including one or more of an amount of current drawn, an operating frequency, and an operating temperature.

6. The system of claim 1, wherein the system management circuit is configured to dynamically estimate power consumption of the plurality of circuits based in part on a calculation representing a relationship between power loss, current, and one or more of voltage and temperature.

7. The system of claim 1 , wherein the system management circuit is configured to: determining that the computing system is estimated to be consuming a maximum amount of power allocated for use by the computing system; and Power consumption for use by at least a portion of the system is increased in response to detecting a condition without decreasing power consumed elsewhere in the system and without increasing estimated power consumption.

8. The system of claim 7, wherein the condition is dynamically estimating reduced power consumption in at least a portion of the computing system.

9. A method comprising: Dynamically estimating power consumption of a computing system; as well as In response to dynamically detecting one of an increase or a decrease in power loss in the computing system, a power performance state of a first circuit among a plurality of circuits of the computing system is changed.

10. The method of claim 9, further comprising dynamically estimating power consumption of each of a plurality of circuits of the computing system.

11. The method of claim 9, wherein in response to detecting reduced power loss in a first circuit of the plurality of circuits, the method includes increasing a power performance state of a second circuit of the plurality of circuits.

12. The method of claim 10, wherein the computing system is a graphics processing circuit and the method includes increasing a power performance state of the computing circuit in response to detecting reduced power consumption in a memory subsystem.

13. The method of claim 10, further comprising dynamically estimating the power consumption of the computing system based on a state of the computing system, wherein the state is based in part on a plurality of parameters including one or more of an amount of current drawn, an operating frequency, and an operating temperature.

14. The method of claim 9, further comprising dynamically estimating power consumption of the plurality of circuits based in part on calculations representing a relationship between power loss, current, and one or more of voltage and temperature.

15. The method according to claim 9, further comprising: determining that the computing system is estimated to be consuming a maximum amount of power allocated for use by the computing system; as well as Power consumption used by at least a portion of the computing system is increased in response to detecting a condition without decreasing power consumed elsewhere in the computing system and without increasing estimated power consumption.

16. The method of claim 15, wherein the condition is dynamically estimating reduced power consumption in at least a portion of the computing system.

17. A system, comprising: a plurality of circuits, the plurality of circuits comprising central processing circuitry, graphics processing circuitry, memory subsystems, and system management circuitry; Wherein the system management circuit is configured to: dynamically estimating power consumption of the plurality of circuits; and In response to dynamic detection of one of an increase or a decrease in power loss in the system, a power performance state of a first circuit of the plurality of circuits is changed.

18. The system of claim 17, wherein in response to detecting a reduced power loss in a first circuit of the plurality of circuits, the system management circuit is configured to increase a power performance state of a second circuit of the plurality of circuits.

19. The system of claim 17, wherein the system management circuit is configured to dynamically estimate power consumption of the plurality of circuits based in part on a calculation representing a relationship between power loss and current.

20. The system of claim 1, wherein the system management circuit is configured to: determining that the computing system is estimated to be consuming a maximum amount of power allocated for use by the computing system; and Power consumption for use by at least a portion of the system is increased in response to detecting a condition without decreasing power consumed elsewhere in the system and without increasing estimated power consumption.

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