Real-time configuration file-driven cache aging policy

Abstract

A technique for operating a cache is disclosed. The technique includes recording access data for a first set of memory accesses for a first frame; identifying parameters of a second set of memory accesses for a second frame following the first frame based on the access data; and applying the parameter to the second set of memory accesses.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 17 / 850,905, filed on June 27, 2022, the entire contents of which are hereby incorporated by reference. Background Art

[0003] Caching improves performance by storing copies of data that is considered likely to be accessed again in the future in low-latency cache memory. Improvements in cache technology are continually being made. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] A more detailed understanding may be obtained from the following description, given by way of example in conjunction with the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of an example computing device that may implement one or more features of the present disclosure;

[0006] Figure 2 is a block diagram of a device illustrating additional details related to performing processing tasks on an APD according to one example;

[0007] Figure 3 A dynamic cache policy system for caching according to one example is illustrated;

[0008] Figure 4 illustrates additional details of a dynamic cache policy controller according to an example;

[0009] Figure 5 An operation for recording access patterns according to one example is illustrated;

[0010] Figure 6 is a block diagram illustrating utilizing an access data item to modify an access in a second frame according to one example; and

[0011] Figure 7 is a flow chart of a method for managing memory access according to one example. DETAILED DESCRIPTION

[0012] A technique for operating a cache is disclosed. The technique includes recording access data of a first set of memory accesses of a first frame; based on the access data, identifying parameters of a second set of memory accesses of a second frame after the first frame; and applying the parameters to the second set of memory accesses.

[0013] Figure 11 is a block diagram of an example computing device 100 that may implement one or more features of the present disclosure. In various examples, computing device 100 is, for example, but not limited to, one of a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, a tablet computer, or other computing device. Device 100 includes, but is not limited to, one or more processors 102, a memory 104, one or more auxiliary devices 106, a storage device 108, and a last level cache (“LLC”) 110. An interconnect 112, which may be a bus, a combination of busses, and / or any other communication component, communicatively links one or more processors 102, memory 104, one or more auxiliary devices 106, a storage device 108, and last level cache 110.

[0014] In various alternatives, the one or more processors 102 include a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU on the same die, or one or more processor cores, where each processor core may be a CPU, a GPU, or a neural processor. In various alternatives, at least a portion of the memory 104 is located on the same die as one or more of the one or more processors 102, such as on the same chip or in an interposer arrangement, and / or at least a portion of the memory 104 is located separately from the one or more processors 102. The memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache.

[0015] The storage device 108 includes a fixed or removable storage device, such as but not limited to a hard disk drive, a solid state drive, an optical disk, or a flash drive. One or more auxiliary devices 106 include, but are not limited to, one or more auxiliary processors 114 and / or one or more input / output ("IO") devices. The auxiliary processor 114 includes, but is not limited to, a processing unit capable of executing instructions, such as a central processing unit, a graphics processing unit, a parallel processing unit capable of performing compute shader operations in a single instruction multiple data form, a multimedia accelerator such as a video encoding or decoding accelerator, or any other processor. Any auxiliary processor 114 may be implemented as a programmable processor that executes instructions, a fixed function processor that processes data according to fixed hardware circuits, a combination thereof, or any other type of processor. The auxiliary processor 114 includes an accelerated processing device ("APD") 116.

[0016] The one or more IO devices 118 include one or more input devices, such as a keyboard, a keypad, a touch screen, a touchpad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless LAN card for sending and / or receiving wireless IEEE 802 signals), and / or one or more output devices, such as a display, a speaker, a printer, a tactile feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless LAN card for sending and / or receiving wireless IEEE 802 signals).

[0017] The last level cache 110 acts as a shared cache for various components of the device 100, such as the processor 102, the APD 116, and various auxiliary devices 106. In some implementations, other caches are present within the device 100. For example, in some examples, the processor 102 includes a cache hierarchy that includes different levels, such as level 1 and level 2. In some examples, each such cache level is specific to a particular logical partition of the processor 102, such as a processor core, or a processor chip, die, or package. In some examples, the hierarchy also includes other types of caches. In various examples, one or more of the auxiliary devices 106 include one or more caches.

[0018] In some examples, the last level cache 110 is "last level" in the sense that such cache is the last cache that the device 100 attempts to service a memory access request before servicing the request from the memory 104 itself. For example, if the processor 102 accesses data that is not stored in any of the cache levels of the processor 102, the processor exports a memory access request to be satisfied by the last level cache 110. The last level cache 110 determines whether the requested data is stored in the last level cache 110. If the data is within the last level cache 110, the last level cache 110 services the request by providing the requested data from the last level cache 110. If the data is not within the last level cache 110, the device 100 services the request from the memory 104. It can be seen that in some specific implementations, the last level cache 110 acts as the final cache level before the memory 104, which helps to reduce the total amount of memory access latency for accesses to the memory 104. Although the techniques described herein are used for operations involving last level cache 110, it should be appreciated that these techniques may alternatively be used with other types of caches or memories.

[0019] Figure 21 is a block diagram of device 100 illustrating additional details related to performing processing tasks on APD 116 according to one example. Processor 102 maintains one or more control logic modules in system memory 104 for execution by processor 102. The control logic modules include operating system 120, driver 122, and application 126, and may optionally include other modules not shown. These control logic modules control various aspects of the operation of processor 102 and APD 116. For example, operating system 120 communicates directly with hardware and provides an interface to the hardware for other software executing on processor 102. Driver 122 controls the operation of APD 116 by, for example, providing an application programming interface ("API") to software executing on processor 102 (e.g., application 126) to access various functions of APD 116. Driver 122 also includes a just-in-time compiler that compiles shader code into shader programs for execution by processing components of APD 116 (such as SIMD unit 138 described in further detail below).

[0020] APD 116 executes commands and programs for selected functions, such as graphics operations and non-graphics operations that may be suitable for parallel processing. APD 116 may be used to perform graphics pipeline operations, such as pixel operations, geometry calculations, and rendering of images to display device 118 based on commands received from processor 102. APD 116 also performs computational processing operations not directly related to graphics operations, such as operations related to video, physics simulations, computational fluid dynamics, or other tasks, or computational processing operations that are not part of the "normal" information flow of the graphics processing pipeline, or are completely unrelated to graphics operations (sometimes referred to as "GPGPU" or "general purpose graphics processing unit") based on commands received from processor 102.

[0021] The APD 116 includes a computing unit 132 (collectively referred to herein as a "programmable processing unit"), which includes one or more SIMD units 138 configured to perform operations in a parallel manner according to the SIMD paradigm. The SIMD paradigm is a paradigm in which multiple processing elements share a single program control flow unit and program counter and thereby execute the same program, but are capable of executing the program with different data. In one example, each SIMD unit 138 includes sixteen channels, each of which executes the same instruction simultaneously with other channels in the SIMD unit 138, but can execute the instruction with different data. If not all channels need to execute a given instruction, the channel can be closed by prediction. Prediction can also be used to execute programs with divergent control flow. More specifically, for programs with conditional branches or other instructions in which the control flow is based on calculations performed by a single channel, predicting the channels corresponding to the control flow paths that are not currently executed and the serial execution of different control flow paths allows arbitrary control of subsequent flows.

[0022] The basic execution unit in the computing unit 132 is a work item. Each work item represents a single instantiation of a shader program to be executed in parallel in a specific channel of a wavefront. Work items can be executed simultaneously as a "wavefront" on a single SIMD unit 138. Multiple wavefronts can be included in a "workgroup", which includes a set of work items designated to execute the same program. The workgroup can be executed by executing each of the wavefronts that constitute the workgroup. The wavefront can be executed sequentially on a single SIMD unit 138, or partially or completely in parallel on different SIMD units 138. The wavefront can be considered as a parallel execution instance of the shader program, wherein each wavefront includes multiple work items (e.g., an instruction control unit that executes the same instruction stream with multiple data) that are executed simultaneously on a single SIMD unit 138 according to the SIMD paradigm. The command processor 137 is present in the computing unit 132 and starts the wavefront based on the work that is waiting to be completed (e.g., executing a task). The scheduler 136 is configured to perform operations involving scheduling various wavefronts on different computing units 132 and SIMD units 138.

[0023] The parallelism provided by the computing units 132 is suitable for graphics-related operations such as pixel value calculations, vertex transformations, surface tessellation, geometry shading operations, and other graphics operations. Therefore, the graphics processing pipeline 134 that accepts graphics processing commands from the processor 102 provides computing tasks to the computing units 132 for parallel execution.

[0024] Compute units 132 are also used to perform computational tasks that do not involve graphics or are not performed as part of the "normal" operation of graphics processing pipeline 134 (e.g., custom operations performed to supplement the processing performed for the operation of graphics processing pipeline 134). Applications 126 or other software executing on processor 102 send programs that define such computational tasks (commonly referred to as "compute shader programs," which may be compiled by driver 122) to APD 116 for execution. Although APD 116 is illustrated as having graphics processing pipeline 134, the teachings of the present disclosure are also applicable to APD 116 without graphics processing pipeline 134. Various entities of APD 116, such as compute units 132, may access last level cache 110.

[0025] Figure 3 A dynamic cache policy system 300 for a cache 302 is illustrated according to one example. The system 300 includes an APD 116, a cache 302, and a dynamic cache policy controller 304. In some examples, the cache 302 is Figure 1 110. In other examples, cache 302 is any other cache that services memory access requests of APD 116. In some examples, dynamic cache policy controller 304 is a hardware circuit, software executed on a processor, or a combination thereof. In some examples, dynamic cache policy controller 304 is included in cache 302 or is separate from the cache.

[0026] APD 116 processes data for a series of frames 306. Each frame 306 is a complete image rendered by APD 116. To generate graphics data over time, APD 116 renders a series of frames, each frame including a graphics object at a particular moment in time.

[0027] To generate each frame 306, various components of the APD 116 access data stored in memory. These accesses are served by the cache 302, which stores a copy of the accessed data. The accessed data includes various data types used to render graphics, such as geometric data (e.g., vertex coordinates and attributes), texture data, pixel data, or various other types of data. Aspects of cache performance such as hit rate (the ratio of hits in the cache to the total number of accesses) depend in part on the way the cache 302 retains data in eviction events. The cache replacement policy indicates which cache lines are to be evicted when a new cache line is to be introduced into the cache. A variety of replacement policies and other techniques are known. However, many of these techniques have inaccuracies because overly general rules may not apply to specific data items. For example, the least recently used replacement policy does not apply to all data access patterns.

[0028] For at least these reasons, the dynamic cache policy controller 304 dynamically applies cache management policies to access requests from the APD 116 based on observed access history. The dynamic cache policy controller 304 maintains cache usage data that records memory access information over the course of a frame. The memory access information is related to aspects of memory accesses, such as the re-reference interval and re-reference intensity of memory pages. The re-reference interval is the "time" (e.g., number of clock cycles, number of instructions, or other "time" measurement) between accesses to a particular memory page. The re-reference intensity is the frequency with which a particular memory page is accessed within a given amount of "time" (e.g., number of clock cycles, number of instructions, or other time measurement).

[0029] Based on the memory access information from the previous frame, the dynamic cache policy controller 304 applies the memory access policy to the memory access request from the APD 116 in the current frame. More specifically, the memory access patterns between frames are usually very similar. Therefore, the memory accesses can be observed in one frame and these observations can be used to control the memory access policy of these accesses in subsequent frames. In other words, based on the observation of specific memory accesses in a particular frame, the dynamic cache policy controller 304 controls the memory access policy of the same memory access in one or more subsequent frames. If the memory accesses occur in approximately the same position in the memory access order of a frame, the memory accesses are considered to be "the same" from frame to frame. More specifically, typically, temporally adjacent frames present very similar graphics information and therefore have very similar memory access patterns. The term "approximately" takes into account the possibility that some memory accesses that occur in one frame may not occur in another frame because the frames may be somewhat different, which means that the order of memory accesses between frames will not be the same.

[0030] The memory access policy is a policy that controls how the cache 302 manages information about cache lines targeted by memory access requests. In an example, the memory access policy controls three aspects: the age at which new cache lines are introduced into the cache (e.g., as a result of a miss), the way in which the age of a cache line is updated when a miss occurs (e.g., how cache lines other than the cache line being accessed are aged), and the age to which a cache line is updated when a cache line hit occurs (e.g., what age a cache line is set to when it is accessed). These features will be discussed in more detail elsewhere herein.

[0031] It should be noted that the age referred to is the age in the cache replacement strategy of the least recently used. More specifically, cache 302 is a set associative cache including multiple sets, each set having multiple paths. Any given cache line is mapped to at least one set and can be placed in any path in the set, but cannot be placed in any set to which the cache line is not mapped. A cache line is defined as a portion of a memory address space. In the example, each cache line has a cache line address including a specific number of most significant bits of the address, so that the remaining least significant bits specify the offset in the cache line. Typically, although not necessarily, a cache line is the smallest unit of data read into or written back to a cache. When a cache line is to be introduced into a set of cache 302 and there is no free path for the cache line, cache 302 evicts one of the cache lines in the set. The replacement algorithm selects the oldest cache line as the cache line to be evicted based on the age of the cache lines in the set. Cache 302 also places new cache lines into cache 302 with a "starting age." In the event of a hit, cache 302 updates the age of the cache line where the hit occurred based on the memory access policy. Additional details are provided elsewhere herein.

[0032] Figure 4 Additional details of a dynamic cache policy controller 304 according to one example are illustrated. The dynamic cache policy controller 304 stores and maintains cache usage data 402. The cache usage data 402 includes memory access information for a "set" of memory accesses in a frame. Each access data item 406 includes information characterizing a particular set of one or more memory accesses. In some examples, each memory access set is one or more memory accesses that occur within a particular "time" amount and within a particular memory address range (such as a page). In some examples, time is represented by real time, cycle count, instruction count, or any other time metric. Therefore, each data item 406 includes information about memory accesses that occur within a particular time period within a frame and occur within the same memory address range. In other words, in different examples, accesses that occur within a threshold number of instructions, a threshold number of computer clock cycles, or a threshold amount of time are grouped together into a set corresponding to the access data item 406.

[0033] In some examples, the dynamic policy controller 304 records the access data item 406 when the corresponding access occurs. In some examples, the dynamic policy controller 304 calculates additional information for each access data item 406 in response to the end of the frame or at some other point in time (e.g., when the "time" of the access data item 406 ends). In one example, the dynamic policy controller 304 determines the re-reference interval and re-reference strength for the access corresponding to the access data item 406. The dynamic policy controller 304 then determines the policy corresponding to the access data item 406 based on the re-reference interval and re-reference strength of the access corresponding to the access data item 406. In some examples, the dynamic policy controller 304 determines the policy based on the re-reference interval and re-reference strength from multiple frames. In some examples, the dynamic policy controller 304 records the policy in the access data item 406 for use in subsequent frames. Therefore, the access data item 406 indicates what policy to use for a particular page and a particular "time" in a frame.

[0034] This policy information allows the dynamic cache policy controller 304 to "regulate" accesses made in frames subsequent to the frame in which the access data item 406 is recorded. "Regulating" memory accesses means setting parameters for the memory accesses, where these parameters correspond to a determined re-reference interval value and a determined re-reference intensity value. For example, in a first frame, the dynamic cache policy controller 304 records a first access data item 406 of a set of memory accesses that access the same page. The first access data item 406 indicates a specific policy for the set of memory accesses. In subsequent frames, the dynamic cache policy controller 304 identifies the same accesses (i.e., accesses of the first access data item 406) and "regulates" these accesses according to the policy stored in the first access data item 406. More specifically, the dynamic cache policy controller 304 configures these accesses to use the policy corresponding to the first access data item 406. Such a policy indicates that these accesses in subsequent frames should be made according to a specific set of settings. In some examples, the policy dictates the following: how to age cache lines other than the cache line being accessed and in the same set as the cache line in the event of a miss; the age of the cache line to insert new cache lines into; and what age to set the cache line to when a hit occurs.

[0035] Aging cache lines in the case of a miss is now described. When a miss occurs in cache 302, cache 302 identifies the cache line to be introduced into the cache. Cache 302 also determines which set the identified cache line will be introduced into. If the age of any cache line in the set is equal to or greater than a threshold (e.g., 3 if the age counter is two bits), cache 302 selects the cache line for eviction. If no cache line has an age above the threshold, cache 302 will age the cache lines of the set. The setting of how to age cache lines in the case of a miss indicates which cache lines in the set are aged when a miss occurs in the set and no cache line has an age equal to or greater than the threshold. In some examples, the setting indicates which cache lines will be aged in the case of a miss by age. In other words, the setting indicates the age of the cache lines that will be aged in the case of a miss. In the example of this setting, the setting indicates that all cache lines with ages below the above threshold ("eviction threshold") are aged. In another example, the setting indicates that cache lines with an age above an age trigger threshold are aged, which age trigger threshold may be lower than the eviction threshold. In this case, cache lines with an age below or equal to the lower threshold are not aged in the event of a miss. In summary, in some examples, the re-reference interval and re-reference intensity of a memory access set of one frame indicate how to age a cache line (specifically, the age of the cache line to be aged) in the event of a memory access set miss in a subsequent frame.

[0036] The setting of the age at which new cache lines are inserted into the cache is now described. When a cache line is introduced into the cache due to a miss, the cache line is initially assigned a particular age. In some examples, this "starting" age is the minimum age possible, some intermediate age above the minimum age possible, or a maximum age. Again, this setting depends on the memory access reflected in the access data item 406. Thus, the access data item 406 corresponding to the memory page indicates the starting age of the cache line in the event that a miss occurs and the cache line is copied into the cache.

[0037] Now describe what age the new cache line is set to when a hit occurs. When a cache line is hit, the cache 302 updates the age of the cache line (e.g., indicating that the cache line is "newer"). In some examples, the setting indicates that when a hit occurs for the cache line, the cache line will have a specific age (such as 0). In other examples, the setting indicates that in the case of a hit, the cache line will have a different age, such as 1, 2, or 3 (for a two-bit age counter). In other examples, the setting indicates that the age of the cache line will be modified in a particular manner, such as by decrementing the age by a number, such as 1. In summary, the access data item 406 corresponding to the memory page indicates how the age of the cache line is modified when a hit occurs for the cache line.

[0038] It should be understood that regulating a particular cache access according to a policy means causing the cache access to occur in accordance with the policy. For an insertion age policy, if the access results in a miss, the policy is applied to the access regulated according to the policy. The cache line to be introduced is introduced according to the age specified by the policy. For an aging policy, this occurs for an access regulated according to the policy in the event that the access results in a miss. In this case, the aging policy causes other cache lines of the same set to be aged as specified by the policy. For a policy that defines what age a cache line will be set to in the event of a hit, when an access regulated according to the policy occurs and the access results in a hit, the policy causes the age of the cache line targeted by the access to be set in accordance with the policy.

[0039] Figure 5 An operation for recording access patterns according to one example is illustrated. Figure 5 A single frame, frame 1 508(1), is illustrated in which multiple accesses 512 occur. The first set of accesses, accesses 512(1) to 512(4), are accesses to a first page P1 and occur within a certain time period. The dynamic cache policy controller 304 identifies three access sets 502 and generates access data items 506 corresponding to each of the access sets 502. These data items indicate the access time and the target address (including or represented as a page) of the access. For the first set 502(1), the dynamic cache policy controller 304 notes that the set has a high reference intensity and a low re-reference interval. There is a high re-reference intensity because there are a large number of accesses to the same page, and there is a low reference interval because the accesses occur relatively close in "time". Therefore, the dynamic cache policy controller 304 records the access data item 506(1) indicating the policy associated with the re-reference interval and the re-reference intensity in the access data item 506(1).

[0040] For the second set of accesses 502(2), which includes access 512(5) and accesses to page P2, there is a low re-reference intensity and a low re-reference interval. Therefore, the dynamic cache policy controller 304 records the policy associated with this combination in access data item 506(2). For the third set of accesses 502(3), which includes accesses with low re-reference intensity and high re-reference interval, reflected in accesses 502(6)-502(7) and accesses to page P3, the dynamic cache policy controller 304 records access data item 506(3), which records the policy reflecting the re-reference intensity and re-reference interval of set 502(3).

[0041] Figure 6 6 is a block diagram illustrating the use of access data items to regulate access in the second frame 508 (2) according to one example. Three sets 602 of data accesses 612 are shown. The dynamic cache policy controller 304 controls the accesses according to the Figure 5 508(1) of the first frame 602 to regulate these accesses. For the data access 612 of the first set 602, the dynamic cache policy controller 304 identifies the first access data item 506(1). The access data item 506 indicates a specific manner in which the access 612 of the set 602(1) is regulated. As described elsewhere herein, the access data item 506 indicates a policy that indicates one or more of how to age the cache line when a miss occurs, to what age the new cache line is set, and to what age the cache line is set in the event of a hit. In addition, the policy depends on data recorded in frame 1 508(1) about the same access from that frame. The dynamic cache policy controller 304 causes the policy applied to the access of a given set 602 to be applied based on the recorded access data item 506 for the same access in the previous frame. Similar activities apply to the set 602(2) and the set 602(3).

[0042] The dynamic cache policy controller 304 determines which accesses in a particular frame are "the same" as the accesses in the previous frame in the following manner. In each frame, memory accesses occur in a specific sequence. This sequence is mostly repeated frame by frame. Therefore, the dynamic cache policy controller 304 tracks the sequence of memory accesses to identify which accesses are "the same" from frame to frame. Indeed, some accesses may be different from frame to frame, so the dynamic cache policy controller 304 takes such differences into account. For example, the dynamic cache policy controller 304 can notice omitted accesses, added accesses, or other modifications, and take these into account. In some examples, memory accesses that occur to the same page at the same "time" in different frames are considered to be "the same" memory accesses. In the example, "time" is defined based on the order of accesses. For example, the first access to the one hundredth access is in the first "time", and the one hundred and first access to the two hundredth access is in the second "time", and so on. Any other technically feasible means for determining time is possible.

[0043] It should be understood that the manner in which accesses are "regulated" is based on the access data items 506 recorded in the previous frame. Thus, for one particular access data item 506 indicating a particular combination of re-reference interval and re-reference strength, a corresponding access is performed using a first set of parameters, including a manner in which cache lines are aged, an age at which new cache lines are inserted, and an age at which hit cache lines are updated. For another particular access data item 506 indicating a different combination of re-reference interval and re-reference strength, a corresponding access is performed using a second set of parameters, including a manner in which cache lines are aged, an age at which new cache lines are inserted, and an age at which hit cache lines are updated. At least one of the parameters of the second set is different from at least one of the parameters of the first set.

[0044] Figure 7 is a flow chart of a method 700 for managing memory access according to one example. Figures 1 to 6 Although the system is described as a system of the present invention, those skilled in the art will understand that any system configured to perform the steps of method 700 in any technically feasible order falls within the scope of the present disclosure.

[0045] At step 702, the dynamic cache policy controller 304 records access data items 406 for memory accesses of a first frame. Each access data item 406 corresponds to a set of one or more memory accesses. In some examples, the memory accesses of each set share a different subset of memory or a shared memory. Each access data item 406 includes information characterizing the memory accesses of the set corresponding to the access data item 406. In some examples, the information is associated with one or both of a re-reference interval (e.g., the "time" between references to the same address or page) or a re-reference intensity (e.g., the number of times a re-access is made within a particular "time" window - meaning the number of instructions, clock time, clock cycles, or other time measurements). In some examples, the dynamic cache policy controller 304 records access data items 406 for multiple access sets within a frame.

[0046] At step 704, for a second frame following the first frame, the dynamic cache policy controller 304 identifies parameters for memory accesses corresponding to accesses for which access data was recorded in the first frame. The parameters include information indicating how such memory accesses are regulated when provided to the cache 302 to be satisfied. In some examples, the memory accesses for which the parameters are identified are the same as the memory accesses for which the corresponding access data was stored in the first frame. In other words, in some examples, at step 704, the dynamic cache policy controller 304 identifies how to regulate accesses for the second frame based on the access data recorded for those accesses in the first frame.

[0047] At step 706, the dynamic cache policy controller 304 applies the identified parameters to the memory access in the second frame. In some examples, as described elsewhere herein, the parameters indicate how to age the cache line in the case of a miss. In some examples, the parameters indicate the age at which a new cache line is inserted into the cache 302 in the case of a miss. In some examples, the parameters indicate what age the cache line is set to in the case of a hit. Applying these parameters to memory access is described elsewhere herein.

[0048] Elements in the figures are embodied as software executing on a processor, a fixed function processor, a programmable processor, or a combination thereof, where appropriate. Processor 102, last level cache 110, interconnect 112, memory 104, storage 108, various auxiliary devices 106, APD 116 and elements thereof, and dynamic cache policy controller 304 include at least some hardware circuitry and, in some implementations, include software executing on a processor within that component or another component.

[0049] It should be understood that many variations are possible based on the disclosure herein. Although the above features and elements are described in particular combinations, each feature or element may be used alone without the other features and elements, or in various combinations with or without the other features or elements.

[0050] The provided methods may be implemented in a general purpose computer, a processor, or a processor core. Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data including a netlist (such instructions capable of being stored on a computer readable medium). The results of such processing may be masks, which are then used in a semiconductor manufacturing process to manufacture processors that implement the features of the present disclosure.

[0051] The methods or flow charts provided herein may be implemented in a computer program, software, or firmware incorporated into a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media (such as CD-ROM disks), and digital versatile disks (DVDs).

Claims

1. A method for operating a cache, the method comprising: Recording access data of a first set of memory accesses of a first frame; identifying, based on the access data, parameters of a second set of memory accesses for a second frame following the first frame; as well as The parameters are applied to the second set of memory accesses.

2. The method according to claim 1, wherein: The access data includes memory accesses characterized by one or both of a re-reference interval and a re-reference intensity.

3. The method according to claim 2, wherein: The re-reference interval indicates the time between accesses, and the re-reference intensity indicates the number of accesses to the same address in a time window.

4. The method according to claim 1, wherein: The parameters include one or more of: an indication of how to age the cache line in the case of a miss, an indication of inserting the age of the cache line in the case of a miss; and an indication of how to modify the age of the cache line in the case of a hit.

5. The method according to claim 1, wherein: The second set of memory accesses is considered to be the same as the first set of memory accesses based on an order of the first memory accesses within the first frame and an order of second memory accesses within the second frame.

6. The method according to claim 1, wherein: Applying the parameters to the second set of memory accesses includes causing the second set of memory accesses to proceed as specified by the parameters.

7. The method according to claim 1, wherein: The first set of memory accesses and the second set of memory accesses include accesses to a cache.

8. The method according to claim 1, wherein: The first frame and the second frame are graphics rendering frames.

9. The method according to claim 1, wherein: Each memory access in said first set of memory accesses is an access to the same memory page.

10. A system, comprising: Cache; and A dynamic cache policy controller, the dynamic cache policy controller being configured to: Recording access data of a first set of memory accesses of a first frame; identifying, based on the access data, parameters of a second set of memory accesses for a second frame following the first frame; as well as The parameters are applied to the second set of memory accesses.

11. The system according to claim 10, wherein: The access data includes memory accesses characterized by one or both of a re-reference interval and a re-reference intensity.

12. The system according to claim 10, wherein: The re-reference interval indicates the time between accesses, and the re-reference intensity indicates the number of accesses to the same address in a time window.

13. The system according to claim 10, wherein: The parameters include one or more of: an indication of how to age the cache line in the case of a miss, an indication of inserting the age of the cache line in the case of a miss; and an indication of how to modify the age of the cache line in the case of a hit.

14. The system according to claim 10, wherein: Based on an order of the first memory accesses within the first frame and an order of the second memory accesses within the second frame, the second set of memory accesses is considered to be the same as the first set of memory accesses.

15. The system according to claim 10, wherein: Applying the parameters to the second set of memory accesses includes causing the second set of memory accesses to proceed as specified by the parameters.

16. The system of claim 10, wherein: The first set of memory accesses and the second set of memory accesses include accesses to a cache.

17. The system according to claim 10, wherein: The first frame and the second frame are graphics rendering frames.

18. The system of claim 10, wherein: Each memory access in said first set of memory accesses is an access to the same memory page.

19. The system according to claim 10, further comprising: A graphics processing pipeline is configured to render the first frame and the second frame.

20. A non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to perform operations comprising: Recording access data of a first set of memory accesses of a first frame; identifying, based on the access data, parameters of a second set of memory accesses for a second frame following the first frame; as well as The parameters are applied to the second set of memory accesses.

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