Tunable hybrid broadband LNA architecture

Abstract

A circuit and method for an LNA enable selection of a first mode providing high gain and wide output impedance matching and a second mode providing broadband output impedance matching with improved NF and linearity at medium gain. Some embodiments allow multiple intermediate modes to enable selection of gain and linearity and NF. One embodiment includes a matching network having an input configured to be coupled to an amplified signal terminal of an amplification core and an output, the matching network including: a first inductor coupled between the input and a first node; a second inductor coupled to the first node; a reinforced amplification branch coupled between the input end and the output end; and a non-amplification branch coupled between the first node and the output terminal; wherein the enhanced amplification branch is enabled in a first mode, and the non-amplification branch is enabled in a second mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 855,418, filed on June 30, 2022, the entire contents of which are incorporated herein by reference. background (1) Technical field

[0004] The present invention relates to electronic circuits and, more particularly, to radio frequency amplifier circuits. (2) Background technology

[0005] Many modern electronic systems include radio frequency (RF) receivers; examples include cellular phones, personal computers, tablet computers, wireless network components, televisions, cable system "set-top boxes", and radar systems. Many RF receivers are paired with an RF transmitter in the form of a transceiver, which is typically a fairly complex two-way radio. In some cases, an RF transceiver is capable of transmitting and receiving across multiple frequencies in multiple frequency bands.

[0006] Amplifiers are common components in RF transmitters, receivers, and transceivers, and are often used for power amplification of transmitted RF signals and low-noise amplification of received RF signals. For many RF systems, especially those that require low power and / or portability (e.g., cell phones, WiFi-connected computers, cameras, and other devices), it has become common to use complementary metal oxide semiconductor (CMOS) manufacturing technology to create low-cost, low-power integrated circuits (ICs). CMOS devices include bulk CMOS, silicon-on-insulator (SOI) CMOS, and silicon-on-sapphire (SOS) CMOS (SOS is a SOI manufacturing technology).

[0007] Receiving RF signals in many environments requires a high-quality low noise amplifier (LNA) as part of the RF "front end" (RFFE) receiver or transceiver circuit chain. Important desired characteristics of an LNA are high gain with low noise, wide bandwidth, good linearity, and good input and output impedance matching. However, typically, all of these factors cannot be optimized simultaneously, and therefore, there is a trade-off between these characteristics when designing an LNA.

[0008] The five important design parameters for LNAs are gain, noise figure (NF), input referred third intercept point (IIP3), output reflection coefficient, and input reflection coefficient. NF is a measure of the degradation of the signal-to-noise ratio (SNR) caused by components in the signal chain, where lower numbers indicate better performance. IIP3 is a figure of merit that indicates the linearity of the amplifier, where higher numbers indicate better performance. Typically, NF has tighter specifications in high gain mode than in low gain mode, and IIP3 has tighter specifications in low gain mode than in high gain mode. The output reflection coefficient is S 22 The input reflection coefficient is S. 11 The S parameter indicates how much power is reflected back to the antenna, where lower values ​​(more negative when evaluated logarithmically) indicate better performance (lower input loss).

[0009] The increase in the frequency of RF communication bands and channels and the continued increase in the number of bands and channels in use have pushed current LNA architectures to their limits. For example, for some new 5G mobile network bands, particularly in the 3 GHz to 6 GHz NR band, the upcoming 7 GHz to 24 GHz band, and the millimeter wave range (e.g., 24.25 GHz to 52.6 GHZ), achieving the stringent requirements for gain, percentage bandwidth, linearity, and output impedance matching using conventional LNA architectures is difficult and sometimes impossible.

[0010] Therefore, there is a need for an LNA architecture that overcomes the limitations of conventional LNA architectures. Summary of the invention

[0011] The present invention includes circuits and methods for an LNA that enable selection of a first operating mode that provides high gain with a wide output impedance match, where a trade-off is made in terms of current, NF, and linearity, and a second operating mode that provides a wideband output impedance match with improved NF and linearity at lower current and moderate gain. Some embodiments allow for multiple intermediate operating modes to allow selection of gain versus linearity and NF characteristics. The circuits and methods of the present invention may also be applied to other types of amplifiers, such as power amplifiers.

[0012] One embodiment of the present invention includes a tunable hybrid broadband output impedance matching network, the tunable hybrid broadband output impedance matching network has an input end configured to be coupled to an amplified signal end of an amplification core and an output end configured to be coupled to a radio frequency (RF) output end, the tunable hybrid broadband output impedance matching network includes: a first inductor, the first inductor is coupled between the input end and a first node; a second inductor, the second inductor is coupled to the first node and is configured to be coupled to a power supply; an enhanced amplification branch, the enhanced amplification branch is coupled between the input end and the output end; and a non-amplification branch, the non-amplification branch is coupled between the first node and the output end; wherein the enhanced amplification branch is enabled in a first operating mode, and the non-amplification branch is enabled in a second operating mode.

[0013] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A is a simplified schematic diagram of a first embodiment of a low noise amplifier circuit with a tunable hybrid broadband output impedance matching network.

[0015] Figure 1B is a schematic diagram of one embodiment of an enhanced IIM circuit.

[0016] Figure 1C is a schematic diagram of one embodiment of an input matching feedback circuit.

[0017] Figure 1D is a simplified schematic diagram of one implementation of an output matching deQing circuit.

[0018] Figure 1E is a schematic diagram of one embodiment of an alternative degradation circuit.

[0019] Figure 2A It is a comparison Figure 1A A graph of gain versus frequency for a modeled implementation of an LNA circuit is shown in FIG.

[0020] Figure 2B It is a comparison Figure 1A A graph of NF versus frequency for the modeled implementation of the LNA circuit is shown in FIG.

[0021] Figure 2C It is a comparison Figure 1A A graph of input return loss versus frequency for the modeled implementation of the LNA circuit is shown in FIG.

[0022] Figure 2D It is a comparison Figure 1AA graph of the output return loss versus frequency for a modeled implementation of an LNA circuit is shown in FIG.

[0023] Figure 3 is a simplified schematic diagram of a second embodiment of a low noise amplifier circuit with a tunable hybrid broadband output impedance matching network.

[0024] Figure 4 is a simplified schematic diagram of a third embodiment of a low noise amplifier circuit with a tunable hybrid broadband output impedance matching network.

[0025] Figure 5 is a top view of a substrate which may be, for example, a printed circuit board or a chip module substrate (eg, a thin film tile).

[0026] 6 illustrates an exemplary prior art wireless communication environment that includes different wireless communication systems and may include one or more mobile wireless devices.

[0027] Figure 7 is a block diagram of a transceiver that may be used in a wireless device such as a cellular telephone and that may beneficially incorporate embodiments of the present invention to improve performance.

[0028] Figure 8 is a process flow diagram illustrating one method of implementing different gain modes for a radio frequency amplifier having an amplifier core with an amplified signal terminal.

[0029] Unless context requires otherwise, like reference numbers and names in the various drawings indicate like elements. DETAILED DESCRIPTION

[0030] The present invention comprises circuits and methods for an LNA that enable selection of a first operating mode providing high gain with a wide output impedance match, where a trade-off is made in terms of current, NF and linearity, and a second operating mode providing a wideband output impedance match with improved NF and linearity at lower current and moderate gain. Some embodiments allow multiple intermediate operating modes to allow selection of gain versus linearity and NF characteristics. The circuits and methods of the present invention may also be applied to other types of amplifiers, such as power amplifiers.

[0031] Bandwidth Terminology

[0032] For the purposes of this disclosure, “narrowband”, “wideband” and “ultra-wideband” may be characterized as being equal to (stop frequency f STOP Subtract the starting frequency f START ) divided by the center frequency f of the band CENTER or (f STOP -f START ) / f CENTER(expressed as a percentage) of the bandwidth, where f CENTER =(f STOP +f START ) / 2. Table 1 below shows typical guidelines (not a strict definition) for characterizing typical percentage bandwidths.

[0033] Nominal frequency band name %Bandwidth Range Narrowband <7.5％ Extended Narrowband 7.5％～15％ broadband 15％～25％ Ultra-Wideband >25％

[0034] Table 1

[0035] Table 2 below provides examples of common cellular telephone frequency bands and characterizes them as either wideband or ultra-wideband using the guidelines in Table 1.

[0036] Typical Applications <![CDATA[f START (GHz)]]> <![CDATA[f STOP (GHz)]]> <![CDATA[f CENTER (GHz)]]> %bandwidth Broadband (N77) 3.3 4.2 3.75 24.00％ Ultra-wideband (NR-U) 5.125 7.125 6.125 32.65％ Ultra-Wideband (UWB) 6.2 9 7.6 36.84％

[0037] Table 2

[0038] First embodiment

[0039] Figure 1A 1 is a simplified schematic diagram of a first embodiment of a low noise amplifier circuit 100 having a tunable hybrid broadband output impedance matching network 102. In the example shown, the LNA circuit 100 includes an amplifier core 104 including two series-connected FETs M in a cascode arrangement. CS 、M CG stack. Apply to the RF input RF IN The RF input signal can pass through the input impedance matching (IIM) circuit 106 and couple to the common source FET M CS The control gate can be regarded as the input terminal INT of the amplification core 104.

[0040] Common source FET M CS The source of the common source FET M is usually connected to a reference potential, such as circuit ground, through the degeneration circuit 108. CS The source of can be regarded as the degenerate terminal DT of the amplifying core 104 .

[0041] Common-gate FET M CG The source of the common source FET M CS The drain of the common-gate FET M CG The drain of provides an amplified RF output signal at the amplified signal terminal AST which can be regarded as the amplification core 104.

[0042] The bias circuit 110 is configured to bias the common-gate FET M in a known manner. CG Provide a suitable bias voltage CG_V BIAS , and to the common source FET M CS Provide a suitable bias voltage CS_V BIASNote that in some applications, the bias voltage CG_V BIAS or CS_V BIAS One or both of CG_V and CG_V may be zero volts (ie, no added voltage), and in some applications, CG_V BIAS This may be a reference voltage, such as AC ground. Additional well-known circuit elements that may be included in certain applications, such as DC blocking capacitors, have been omitted for clarity.

[0043] The tunable hybrid broadband output impedance matching network ("THWOIM network") 102 has an IN terminal configured to be coupled to the amplified signal terminal AST of the amplification core 104, and a RF output terminal RF configured to be coupled to the RF output terminal RF OUT The amplified output of the amplifier core 104 is coupled to the RF output terminal RF through the THWOIM network 102. OUT , RF output terminal RF OUT is shown coupled to a resistor represented as R L For many modern RF circuits, R L The value is usually 50 ohms.

[0044] The THWOIM network 102 includes a first inductor L1 coupled in series with a second inductor L2 at a node X, wherein the inductor pair L1, L2 is coupled to an IN terminal and is configured to be coupled to a power source V DD The THWOIM network 102 in the illustrated example includes two branches.

[0045] The first branch includes a first DC blocking capacitor C coupled between the amplified signal terminal AST of the amplification core 104 and the first terminal of the switch S1. BLK1 The second end of the switch S1 is coupled to the second stage FET M SF The control gate of the second stage FET M SF A source follower circuit as a voltage buffer provides a second stage of amplification. In the example shown, the second stage FET M SF With coupling at V DD The conductive channel (drain to source) between the second stage FET M and the third inductor L3 is coupled to a reference potential, such as circuit ground. SF The source of the second DC blocking capacitor C BLK2 is coupled to node Y. Switch S2 is coupled between node Y and the OUT terminal. Shunt switch S3 is coupled between a reference potential such as circuit ground and node Y. Switches S1 to S3 may be implemented (by way of example only) as FETs, in particular MOSFETs.

[0046] The second branch includes a third capacitor C coupled between the node X and the switch S4.SER The third capacitor C SER Can be used as part of an output matching network. Switch S5 is coupled between switch S4 and the OUT terminal. Shunt switch S6 is coupled between a reference potential such as circuit ground and a node Z between switches S4 and S5. Switches S4 to S6 can be implemented (by way of example only) as FETs, in particular MOSFETs.

[0047] To enable the first operating mode, which may be referred to as a high gain or gain enhancement mode, the first branch is set to an active state, wherein switches S1, S2, and S6 are set to a closed state, and switches S3, S4, and S5 are set to an open state. The combination of inductors L1 and L2 acts as a load for the first stage of inductive degeneration (i.e., amplification core 104) of the entire LNA 100. Closing shunt switch S6 provides a path to ground to avoid loading the RF due to the first stage tap load (i.e., L1+L2 tapped at node X). OUT The AC component of the amplified signal from the amplified signal terminal AST is output by the second stage FET M SF Further amplification, where the AC component of the amplified signal is provided at the RF OUT Therefore, the first branch can be selectively enabled as the enhanced amplification branch.

[0048] The first operating mode provides high gain due to two-stage amplification with wide output impedance matching. The tradeoff for such high gain is higher DC current, NF, and linearity compared to the second operating mode.

[0049] To enable the second operating mode, which may be referred to as a high performance medium gain mode, the second branch is set to an active state, wherein switches S3, S4, and S5 are set to a closed state, and switches S1, S2, and S6 are set to an open state. Closing shunt switch S3 provides a path to ground to avoid the source follower second stage FET M of the first (high gain) branch from being disconnected. SF Loading RF OUT In this mode, the inductor L1 is located between the common-gate FET M CG The drain of the cascode device and the capacitor C SER and the AC component of the amplified signal from the amplified signal terminal AST is coupled to the RF OUT Therefore, the second branch can be selectively enabled as a non-amplified branch.

[0050] Since the common-gate FET M CG The increased impedance at the drain of the cascode device, and the inductive load L2, extend the output bandwidth of the LNA 100 and also provide higher gain compared to a conventional unipolar cascode LNA.

[0051] Inductors L1 and L2 are typically tuned so that they provide a wide output impedance match in both operating modes while ensuring that their sum still provides a flat gain response for the high-gain operating mode. For the high-performance mode, capacitor C SER Implement additional tuning.

[0052] Optional circuit components

[0053] A. Stacking of FETs. In some embodiments, to overcome the relatively low breakdown voltage of each CMOS FET, multiple common-gate FETs can be coupled in series with the bottom common-gate FET M. CG In the FET stack 120 between the drain and the amplified signal terminal AST, the Figure 1A As shown, that is, the amplifying core 104 may have a plurality of common-gate FETs coupled in series in a common-source common-gate configuration. Then, the amplified signal terminal AST is located at the drain of the uppermost common-gate FET in the amplifying core 104 .

[0054] B. Enhanced input impedance matching circuit. Figure 1A In the embodiment of the present invention, a variety of circuits can be used for the IIM circuit 106, but it may be useful to use an enhanced input impedance matching circuit. For example, Figure 1B FIG. 1 is a schematic diagram of one embodiment of an enhanced IIM circuit 106. The enhanced IIM circuit 106 includes a IN The series inductor L between the terminal and the input terminal INT of the amplifier core 104 SER , and coupled to L SER A shunt inductor L between the reference potential (e.g., circuit ground) SH In an alternative embodiment, L SH Can be found in L SER The INT terminal side instead of the RF IN Connect the end side to L SER (Note that if the order of the connections is changed, there may be different input impedance matching bandwidth and noise figure tradeoffs.) As shown, L SER and L SH Either or both of may be adjustable components, or have fixed values. In an embodiment including the degeneration circuit 108, the series shunt inductor L of the enhanced IIM circuit 106 is SER , L SH The common source FET M coupled to the degeneration circuit 108 CS Together they form a double-ended bandpass filter that increases the input bandwidth of the LNA circuit 100 .

[0055] C. Input Match Feedback Circuit. Some embodiments may include an input match (IM) feedback circuit 122. The IM feedback circuit 122 is Figure 1A 104 is shown as coupled between the input terminal INT and the amplified signal terminal AST. More generally, the IM feedback circuit 122 can be coupled to a feedback node in the output signal path of the amplifying core 104, and the feedback node can be the drain of any FET in the amplifying core 104. For example, the feedback node for connecting to the IM feedback circuit 122 can be selected based on different desired feedback strengths and different desired input impedances.

[0056] Figure 1C FIG. 1 is a schematic diagram of one embodiment of the input matching feedback circuit 122. The IM feedback circuit 122 in the illustrated example includes a switch S F1 Series coupled DC blocking capacitor C F1 , switch S F1 It is coupled in series to the resistor R F1 In some embodiments, as shown, C F1 and / or R F1 may be adjustable, or have a fixed value. In an alternative embodiment, the IM feedback circuit 122 may include one or more parallel switches S F11 ……S F1n (collectively referred to as S F1x ), the one or more parallel switches S F11 ……S F1n is coupled in series to the corresponding parallel resistor R F11 ……R F1n (collectively referred to as R F1x ). In the case of n parallel switch / resistor branches, the resistor R F1x The tunability is equal to 2 n (Total number of switch combinations). Note that resistor R F1x The values ​​of do not have to be the same. This can be achieved by disconnecting all feedback switches S F1x to disable the IM feedback circuit 122.

[0057] In an alternative embodiment, capacitor C F1 , one or more switches S F1x A collection of one or more resistors R F1x The set of can be connected in any series order. In other embodiments, the switch S can be omitted. F1x , thereby permanently coupling one or more resistors R between the input terminal INT and the feedback node in the output signal path of the amplifier core 104 F1x A collection of .

[0058] In various gain modes, there are one or more resistors R in the circuit. F1x This allows the Q factor of the input impedance match to be lowered, which increases the bandwidth of the enhanced LNA circuit 100 at the expense of gain and NF.

[0059] An advantage of using a variable or multi-state IM feedback circuit 122 is that multiple resistor values ​​enable multiple gain modes. For example, an LNA in a mobile RF receiver device may require multiple gain modes depending on the range of input signal strengths at the receiver. In addition, by using a variable or multi-state feedback resistor R F1x Enabling multiple gain modes can eliminate the need for output attenuators (common in conventional receiver LNAs).

[0060] More information about the IM feedback circuit 122 can be found in U.S. patent application Ser. No. 17 / 337,227, filed on June 2, 2021, and entitled “Wideband Multi Gain LNA Architecture,” which is assigned to the assignee of the present invention and is incorporated herein by reference.

[0061] D. Output matching deQing circuit. Some embodiments may include an output matching (OM) deQing circuit 124. The OM deQing circuit 124 is Figure 1A is shown as coupling the amplified signal terminal AST with the common gate FET M CG Between the control gates of the common-gate FET M CG The control gate of is in turn connected to AC ground 112 through a blocking capacitor C. OM deQ circuit 124 is used to reduce the transformed Q of THWOIM network 102. Reducing the transformed Q extends the output impedance matching bandwidth of LNA circuit 100. Compared with other known circuits, this architecture exhibits better gain and bandwidth tradeoffs in various applications.

[0062] Figure 1D FIG. 1 is a simplified schematic diagram of one embodiment of the output matching de-quenching circuit 124. The OM de-quenching circuit 124 in the example shown includes a switch S F2 Series coupled DC blocking capacitor C F2 , switch S F2 It is also coupled in series to the resistor R F2 In some embodiments, as shown, C F2 and / or R F2 It may be adjustable or have a fixed value. In an alternative embodiment, the OM deQing circuit 124 may include one or more parallel switches S F21 ……SF2n (collectively referred to as S F2x ), one or more parallel switches S F21 ……S F2n is coupled in series to the corresponding parallel resistor R F21 ……R F2n (collectively referred to as R F2x ). In the case of n parallel switch / resistor branches, the resistor R F2x The tunability is equal to 2 n (Total number of switch combinations). Note that resistor R F2x The values ​​of do not have to be the same. This can be achieved by disconnecting all feedback switches S F2x to disable the OM deQing circuit 124.

[0063] In an alternative embodiment, capacitor C F2 , one or more switches S F2x A collection of one or more resistors R F2x The set of can be connected in any series order. In other embodiments, the switch S can be omitted. F2x , thereby placing one or more resistors R F2x The set is permanently coupled at the amplified signal end AST with the common gate FET M CG between the control gates.

[0064] In various gain modes, there are one or more resistors R in the circuit. F2x This allows the Q factor of the output impedance matching to be reduced, which increases the bandwidth of the enhanced LNA circuit 100 at the expense of gain and NF. For example, switching a single resistor R F2 Two operation modes are provided, the first mode has a wider output impedance matching bandwidth, and the second mode has a narrower output impedance matching bandwidth but has a higher gain than the first mode. As described above, R F2 Changing or enabling more than one resistor value enables additional operating modes.

[0065] More specifically, when the switch S F2 When closed, R F2 The amplified signal terminal AST is coupled to the common gate FET M CG The control gate effectively places R F2 The equivalent resistance R of the amplifier core 104 circuit D In parallel, there is R F2 The impedance Z of the amplifier core 104 as seen at the AST terminal is reduced. DRAIN , and reduces the transformed Q of the THWOIM network 102, where Q is approximately equal to Z DRAIN The real part of the load resistance RL , or Re(Z DRAIN ) / R L Therefore, the conversion Q is reduced, thereby extending the output impedance matching bandwidth of the LNA circuit 100. Compared with other known circuits, this architecture exhibits a better gain and bandwidth trade-off in various applications.

[0066] On the contrary, when the switch S F2 When disconnected, R F2 Relative to R in the equivalent circuit D is open circuited, and the transformation Q of the THWOIM network 102 is not reduced.

[0067] An advantage of using a variable or multi-state OM deQing circuit 124 is that multiple resistor values ​​enable multiple gain modes. For example, an LNA in a mobile RF receiver device may require multiple gain modes depending on the range of input signal strengths at the receiver. In addition, by using a variable or multi-state deQing resistor R F2x Enabling multiple gain modes can eliminate the need for output attenuators (common in conventional receiver LNAs).

[0068] E. Degenerate circuit. Figure 1A The degradation circuit 108 shown in FIG. 1 may simply include a fixed inductor. However, to obtain greater flexibility, additional components may be included in the degradation circuit 108. For example, Figure 1E is a schematic diagram of one embodiment of an optional degradation circuit 108. The degradation circuit 108 may include an adjustable degradation inductor L DEG , such as a multi-port integrated circuit inductor coil. Adjustable degeneration inductor L DEG Can be used to improve linearity in low gain modes. For example, a smaller degeneration inductor L can be used in higher gain modes. DEG value, and a larger degeneration inductor L can be used in lower gain modes DEG Some embodiments of the degradation circuit 108 may include a degradation inductor L DEG Parallel coupled bypass switch Sw BP .therefore, Figure 1E The degradation circuit 108 allows for an operating mode selected by suitable control circuitry (not shown) in which no inductor is present or in which a fixed or variable amount of inductance is present.

[0069] Performance Examples

[0070] Figure 2A It is a comparison Figure 1AGraph 202a shows the response for a first or high gain mode in which the first branch of the THWOIM network 102 is active. Graph line 204a shows the response for a second or high performance medium gain mode in which the second branch of the THWOIM network 102 is active. In this example, the high gain mode achieves a gain of greater than 21 dB over a bandwidth of approximately 900 MHz, while the high performance medium gain mode achieves a gain of approximately 18.5 dB over nearly the same bandwidth.

[0071] Figure 2B It is a comparison Figure 1A Graph 202b shows the response for the high gain mode, and graph 204b shows the response for the high performance medium gain mode. In this example, graph 204b shows better NF performance for the high performance medium gain mode, but the NF of the high gain mode (about 0.9 dB to about 1 dB over the entire frequency range) is quite sufficient for many applications.

[0072] Figure 2C It is a comparison Figure 1A Graph 202c shows the response for the high gain mode, and graph 204c shows the response for the high performance medium gain mode. In this example, graph line 204c shows better input return loss performance for the high performance medium gain mode, but the input return loss performance of the high gain mode is quite adequate for many applications.

[0073] Figure 2D It is a comparison Figure 1A Graph 202d shows the response for the high gain mode, and graph 204d shows the response for the high performance medium gain mode. In this example, graph line 202d shows better output return loss performance for the high gain mode, but the output return loss performance of the high performance medium gain mode is quite adequate for many applications.

[0074] Note that for FIG. 2A to FIG. 2D All graphs in Figure 1 are for high performance medium gain mode, with input current I applied to the modeled LNA100 DD is set to 7.5 mA. In comparison, for high gain mode, the input current I applied to the modeled LNA100 DD is set to 10 mA. In other embodiments, I DD Can be optimized for performance tradeoffs.

[0075] Second embodiment

[0076] Figure 3 is a simplified schematic diagram of a second embodiment of a low noise amplifier circuit 300 having a tunable hybrid broadband output impedance matching network 102. Figure 1A , LNA circuit 300 implements inductors L1 and L2 as asymmetric T-coils, indicated by the points near L1 and L2 connected by dashed arrow k. The asymmetric T-coil is an inductor peaking circuit that can extend the bandwidth of the amplifier and accelerate the output signal rise time. As is known, the asymmetric T-coil includes series coupled inductors (equivalent to discrete inductors L1 and L2) and inherent bridging capacitance (not shown) across the inductors. Since the T-coil inherently includes bridging capacitance, Figure 1A The LNA circuit 100 has a C SER The value of capacitor C may need to be adjusted compared to SER The value of .

[0077] An integrated circuit implementation of an asymmetric T-coil can be in the form of a three-tap spiral inductor structure, where the first portion of the spiral (e.g., from the input tap to the middle tap) corresponds to L1, and the second portion of the spiral (e.g., from the middle tap to the output tap) corresponds to L2.

[0078] An advantage of using an asymmetric T-coil instead of discrete inductors L1 and L2 is that the implementation of the IC (e.g., as a three-tap spiral inductor structure) typically saves die area compared to discrete inductors. In addition, in high gain mode, the mutual inductance of the asymmetric T-coil inductors L1 and L2 also contributes to the total inductance of the amplifier core 104 load, so the asymmetric T-coil does not detract from the load inductor Q and the gain in high gain mode.

[0079] Third embodiment

[0080] Figure 1A and Figure 3 Embodiments of may benefit from providing adjustable circuit elements for operation in multiple different modes that allow tradeoffs between gain, bandwidth, and linearity. For example, Figure 4 is a simplified schematic diagram of a third embodiment of a low noise amplifier circuit 400 having a tunable hybrid broadband output impedance matching network 102. Figure 1A Similar to the embodiment shown in FIG. 1 , the LNA circuit 400 may implement any one or all of the inductors L1, L2, and / or L3 as adjustable inductors, and may use the capacitor C BLK1 , C BLK2 and / or C SERAny or all of the inductors, resistors and / or capacitors in the IIM circuit 106, the degradation circuit 108, the IM feedback circuit 122 and / or the OM deQing circuit 124 may be tunable, as described above. Figure 3 The asymmetric T-coil implementation of can be similarly enhanced with adjustable circuit elements.

[0081] In addition to making some or all of the inductors, resistors, and / or capacitors within LNA circuit 400 adjustable to achieve different operating modes, multiple operating modes can be achieved by selectively opening and closing various switches (including within degeneration circuit 108, IM feedback circuit 122, and / or OM deQing circuit 124) as needed to further achieve a tradeoff between gain, bandwidth, and linearity. In addition, the gain, bandwidth, and linearity can be further improved by adding a switch (e.g., a bypass switch S coupled in parallel with inductor L1). BP ) to include or exclude circuit elements in one or more modes to achieve multiple operating modes. Such additional modes can be based on the two basic operating modes (high performance, medium gain mode and high gain mode) for overall better performance in all such modes.

[0082] As should now be appreciated, embodiments of the present invention provide broadband input and output impedance matching for wide bandwidths in all modes without the need for band switching. Furthermore, the benefits of the present invention can be realized in a single LNA fabricated as an integrated circuit with very little added die area compared to conventional LNA designs.

[0083] Circuit Implementation

[0084] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be enclosed in IC packages and / or modules for ease of processing, manufacturing and / or improved performance. Specifically, IC embodiments of the present invention are typically used in modules, wherein one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possible additional ICs) into a package. Then, the IC and / or module are typically combined with other components on a printed circuit board to form a part of a terminal product such as a cellular phone, a laptop computer, or an electronic tablet, or to form a more advanced module that can be used for various products such as vehicles, test equipment, medical equipment, etc. Through various configurations of modules and components, such an IC is typically able to implement a communication mode, typically wireless communication.

[0085] As an example of further integration of embodiments of the present invention with other components, Figure 5 5 is a top view of a substrate 500, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin film block). In the example shown, the substrate 500 includes a plurality of ICs 502a to 502d having terminal pads 504 that are interconnected by conductive vias and / or traces on and / or within the substrate 500 or on an opposing (rear) surface of the substrate 500 (to avoid clutter, surface conductive traces are not shown and not all terminal pads are labeled). The ICs 502a to 502d may be embodied as, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuit systems. For example, IC 502b may incorporate one or more instances of an LNA circuit similar to that described in Figure 1A , Figure 3 and Figure 4 The circuit shown in .

[0086] The substrate 500 may also include one or more passive devices 506 embedded in, formed on, and / or secured to the substrate 500. Although shown as generally rectangular, the passive devices 506 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., which are interconnected with other passive devices 506 and / or individual ICs 502a to 502d via conductive traces on or in the substrate 500.

[0087] The front or back surface of substrate 500 can be used as a location for forming other structures. For example, one or more antennas can be formed on or affixed to the front or back surface of substrate 500; one example is shown of front surface antenna 508 coupled to IC die 502b, which can include RF front end circuitry. Thus, by including one or more antennas on substrate 500, a complete radio can be created.

[0088] System

[0089] Embodiments of the present invention may be used in a variety of larger radio frequency (RF) circuits and systems, such as radio systems (particularly including cellular radio systems), personal computers, tablet computers, wireless network components, televisions, cable system "set-top" boxes, radar systems (including phased array and automotive radar systems), and test equipment.

[0090] Radio system uses include wireless RF systems (including base stations, relay stations, and handheld transceivers) using various technologies and protocols, including various types of Orthogonal Frequency Division Multiplexing (“OFDM”), Quadrature Amplitude Modulation (“QAM”), Code Division Multiple Access (“CDMA”), Time Division Multiple Access (“TDMA”), Wideband Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G and WiFi (e.g., 802.11a, 802.11b, 802.11g, 802.11ac, 802.11ax), and other radio communication standards and protocols.

[0091] As an example of wireless RF system usage, FIG. 6 illustrates an exemplary prior art wireless communication environment 600 that includes different wireless communication systems 602 and 604 and may include one or more mobile wireless devices 606 .

[0092] The wireless device 606 may be able to communicate with multiple wireless communication systems 602, 604 using one or more of the above-mentioned telecommunication protocols. The wireless device 606 may also be able to communicate with one or more satellites 608 such as navigation satellites (e.g., GPS) and / or telecommunication satellites. The wireless device 606 may be equipped with multiple antennas externally and / or internally for operation at different frequencies and / or to provide diversity to resist harmful path effects such as fading and multipath interference. The wireless device 606 may be a cellular phone, a personal digital assistant (PDA), a wireless-enabled computer or tablet computer, or some other wireless communication unit or device. The wireless device 606 may also be referred to as a mobile station, user equipment, access terminal, or some other terminology.

[0093] The wireless system 602 may be, for example, a CDMA-based system that includes one or more base transceiver stations (BSTs) 610 and at least one switching center (SC) 612. Each BST 610 provides over-the-air RF communications for wireless devices 606 within its coverage area. The SC 612 couples to one or more BSTs in the wireless system 602 and provides coordination and control for the BSTs.

[0094] The wireless system 604 may be, for example, a TDMA-based system including one or more transceiver nodes 614 and a network center (NC) 616. Each transceiver node 614 provides over-the-air RF communications for wireless devices 606 within its coverage area. The NC 616 is coupled to one or more transceiver nodes 614 in the wireless system 604 and provides coordination and control for these transceiver nodes 614.

[0095] Typically, each BST 610 and transceiver node 614 is a fixed station that provides communication coverage for wireless devices 606 and may also be referred to as a base station or some other terminology. SC 612 and NC 616 are network entities that provide coordination and control for the base stations and may also be referred to by other terminology.

[0096] An important aspect of any wireless system lies in the details of how the constituent elements of the system perform. Figure 7 is a block diagram of a transceiver 700 that may be used in a wireless device such as a cellular telephone and that may beneficially incorporate embodiments of the present invention to improve performance. As shown, the transceiver 700 includes a mix of RF analog circuitry for directly transmitting and / or transforming signals on an RF signal path, non-RF analog circuitry for operating requirements outside the RF signal path (e.g., for bias voltages and switching signals), and digital circuitry for control and user interface requirements. In this example, the receiver path Rx includes an RF front end portion, an intermediate frequency (IF) block portion, a back end portion, and a baseband portion (note that in some implementations, the distinction between the portions may be different). The various illustrated portions and circuit elements may be embodied in one die or in multiple IC dies. For example, the RF front end in the example shown may include an RFFE module and a hybrid block, which may be embodied in (or as part of) different IC dies or modules. The different dies and / or modules may be connected to each other via transmission lines T IN and T OUT (e.g., microstrip, coplanar waveguide, or equivalent structure or circuit) coupling, transmission line T IN and T OUT Either or both may have an impedance of, for example, 50Ω.

[0097] The receiver path Rx receives the air RF signal via at least one antenna 702 and a switch unit 704, which may be implemented using active switching devices (e.g., field effect transistors or FETs) and / or using passive devices such as diplexers or duplexers that implement frequency domain multiplexing. The RF filter 706 passes the desired received RF signal to at least one low noise amplifier (LNA) 708a, the output of which is coupled from the RFFE module to at least one LNA 708b in the hybrid block (in this example via a transmission line T). IN). The LNA 708b may provide buffering, input matching, and reverse isolation. The output of the LNA 708b is combined with the output of the first local oscillator 712 in a corresponding mixer 710 to produce an IF signal. The IF signal may be applied to a demodulator 718 after being amplified by an IF amplifier 714 and passed through an IF filter 716, and the demodulator 718 may be coupled to a second local oscillator 720. The demodulated output of the demodulator 718 is converted to a digital signal by an analog-to-digital converter 722 and provided to one or more system components 724 (e.g., video graphics circuits, sound circuits, memory devices, etc.). The converted digital signal may represent, for example, a video or still image, a sound, or a symbol, such as text or other characters.

[0098] In the example shown, the transmitter path Tx includes a baseband section, a backend section, an IF block section, and an RF front end section (again, in some implementations, the distinction between the sections may be different). Digital data from one or more system components 724 is converted to an analog signal by a digital-to-analog converter 726, and the output of the digital-to-analog converter 726 is applied to a modulator 728, which may also be coupled to a second local oscillator 720. The modulated output of the modulator 728 may be amplified by an IF amplifier 732 after passing through an IF filter 730. The output of the IF amplifier 732 is then combined with the output of the first local oscillator 712 in a mixer 734 to produce an RF signal. The RF signal may be amplified by a driver 736, and the output of the driver 736 is coupled to a power amplifier (PA) 738 (in this example via a transmission line T OUT ). The amplified RF signal may be coupled to the RF filter 740 , and the output of the RF filter 740 is coupled to the at least one antenna 702 via the switch unit 704 .

[0099] The operation of transceiver 700 is controlled in a known manner by a microprocessor 742, which interacts with system control components 744 (e.g., user interface, memory / storage, application programs, operating system software, power control, etc.) In addition, transceiver 700 will typically include other circuitry, such as bias circuitry 746 (which may be distributed throughout transceiver 700 near transistor devices), electrostatic discharge (ESD) protection circuitry, test circuitry (not shown), a factory programming interface (not shown), etc.

[0100] In modern transceivers, there is typically more than one receiver path Rx and transmitter path Tx, for example to accommodate multiple frequencies and / or signaling modalities. In addition, as should be apparent to one of ordinary skill in the art, some components of transceiver 700 may be positioned in a different order (e.g., filters) or omitted. Other components may (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.

[0101] As will be appreciated by those of ordinary skill in the art, RF system architecture is beneficially impacted by the present invention in key ways, including the ability to select a first operating mode that provides high gain with a wide output impedance match, where tradeoffs are made in current, NF, and linearity, and a second operating mode that provides a wideband output impedance match with improved NF and linearity at lower current and moderate gain. These system-level improvements are specifically enabled by the present invention, and enable embodiments of the present invention to meet the stringent performance specifications of customers and many RF standards. Thus, the present invention is of great benefit to Figure 7 The embodiment of the overall system shown is critical.

[0102] method

[0103] Figure 8 800 is a process flow diagram illustrating a method of implementing different gain modes for a radio frequency amplifier having an amplifier core with an amplified signal terminal. The method includes: coupling a first inductor coupled to the amplified signal terminal to a first node (block 802); coupling a second inductor to the first node, and configuring the second inductor to be coupled to a power supply (block 804); coupling an enhanced amplification branch between the amplified signal terminal and an output terminal (block 806); coupling a non-amplified branch between the first node and the output terminal (block 808); selectively enabling the enhanced amplification branch in a first operating mode (block 810); and selectively enabling the non-amplified branch in a second operating mode (block 812).

[0104] Additional aspects of the above method may include modifying the implementation as described above and in Figure 1A , Figure 3 and Figure 4 Circuit components of the method shown.

[0105] Manufacturing Techniques and Options

[0106] Although Figure 1A , Figure 3 and Figure 4 The example implementation shown in FIG. 5 is an LNA, but the circuits and methods of the present invention may also be applied to other types of amplifiers, such as power amplifiers.

[0107] For clarity, additional known circuit elements that may be included in some applications, such as DC blocking capacitors, additional impedance matching circuitry, and additional filters, are omitted. It should also be noted that a circuit component characterized as "adjustable" may have its value selected from a plurality of possible component value settings and fixed during manufacture, when assembled in a circuit module, during factory testing, or in the field (e.g., by burning or "blowing" a fusible link), or may have its value dynamically changed, tuned, or programmatically set, for example, in response to other circuitry (e.g., temperature compensation and / or power control circuitry) or in response to a generated or received command signal.

[0108] The operating mode of the LNA circuit of the present invention can be set by a control circuit (not shown) in a known manner. The control circuit can also be connected to the adjustable components to select different component values ​​(e.g., capacitance, resistance, inductance) for different gain states, for example to help input and / or output impedance matching, or to change gain and linearity and / or NF in some operating modes.

[0109] The switches shown in the embodiments of the present invention can be implemented as FETs, in particular MOSFETs. As used in the present disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and includes an insulated gate having a metal or metalloid, insulator and / or semiconductor structure. The term "metal" or "metalloid" includes at least one conductive material (e.g., aluminum, copper or other metal or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material); and "semiconductor" includes at least one semiconductor material.

[0110] As used in this disclosure, the term "radio frequency" (RF) refers to oscillation rates in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or the frequency of an alternating voltage or current in an electrical circuit.

[0111] With respect to the drawings cited in this disclosure, the sizes of the various elements are not to scale; some dimensions are greatly exaggerated in the vertical and / or horizontal directions for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "lower," "upper," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0112] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise specified above, selecting appropriate component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure) or hybrid or discrete circuit form. Any suitable substrate and process can be used to manufacture integrated circuit embodiments, including but not limited to standard bulk silicon, silicon on insulator (SOI) and silicon on sapphire (SOS). Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when using SOI or SOS-based process manufacturing or when using processes with similar characteristics. The manufacture of SOI or SOS processes in CMOS enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., up to and exceeding 300GHz radio frequency). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can usually be kept low (or at least consistent across all units, allowing them to be compensated for).

[0113] Voltage levels may be adjusted, and / or voltage and / or logic signal polarity may be reversed, depending on the particular specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS transistor devices, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, such as by adjusting device size, "stacking" components (particularly FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0114] in conclusion

[0115] A number of embodiments of the present invention have been described. It should be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be order-independent and thus may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0116] It should be understood that the above description is intended to illustrate but not to limit the scope of the invention, which is limited by the scope of the appended claims, and other embodiments are also within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or components of matter set forth in the appended claims. (Note that parenthetical markings of claim elements are for convenience of reference to such elements and do not, by themselves, indicate a specific required order or enumeration of the elements; furthermore, such markings may be repeated in dependent claims as references to additional elements without being considered as starting a conflicting marking order).

Claims

1. A tunable hybrid broadband output impedance matching network, the tunable hybrid broadband output impedance matching network having an input end configured to be coupled to an amplified signal end of an amplifier core and an output end configured to be coupled to a radio frequency (RF) output end, the tunable hybrid broadband output impedance matching network comprising: (a) a first inductor coupled between the input terminal and a first node; (b) a second inductor coupled to the first node and configured to be coupled to a power source; (c) a reinforcing amplifying branch, the reinforcing amplifying branch being coupled between the input end and the output end; as well as (d) a non-amplifying branch coupled between the first node and the output terminal; The enhanced amplification branch is enabled in a first operation mode, and the non-amplification branch is enabled in a second operation mode.

2. The invention according to claim 1, wherein: The enhanced amplification branch comprises: (a) a first blocking capacitor coupled to the input terminal; (b) a third inductor configured to be coupled to a reference voltage; (c) a FET having a control gate, a source coupled to the third inductor, and a drain configured to be coupled to the power source; (d) a first switch coupled between the first blocking capacitor and a control gate of the FET; (e) a second blocking capacitor coupled between the source of the FET and a second node; (f) a second switch coupled between the second node and the output terminal; and (g) A third switch coupled to the second node and configured to be coupled to the reference voltage.

3. The invention according to claim 1, wherein: The non-amplified branch comprises: (a) a first blocking capacitor coupled to the first node; (b) a first switch coupled between the first blocking capacitor and a second node; (c) a second switch coupled between the second node and the output terminal; and (d) A third switch coupled to the second node and configured to be coupled to the reference voltage.

4. The invention according to claim 1, wherein: The first inductor and the second inductor are implemented as asymmetric T-shaped coils.

5. The invention according to claim 1, wherein: At least one of the first inductor and the second inductor is adjustable.

6. The invention according to claim 1, wherein: At least one of the first inductor and the second inductor is dynamically variable.

7. A tunable hybrid broadband output impedance matching network, the tunable hybrid broadband output impedance matching network having an input end configured to be coupled to an amplified signal end of an amplifier core and an output end configured to be coupled to a radio frequency (RF) output end, the tunable hybrid broadband output impedance matching network comprising: (a) a first inductor coupled between the input terminal and a first node; (b) a second inductor coupled to the first node and configured to be coupled to a power source; (c) a first branch, the first branch being coupled between the input end and the output end, the first branch comprising: (1) a first blocking capacitor, the first blocking capacitor being coupled to the input terminal; (2) a third inductor configured to be coupled to a reference voltage; (3) a FET having a control gate, a source coupled to the third inductor, and a drain configured to be coupled to the power source; (4) a first switch coupled between the first blocking capacitor and a control gate of the FET; (5) a second blocking capacitor coupled between the source of the FET and a second node; (6) a second switch coupled between the second node and the output terminal; and (7) a third switch coupled to the second node and configured to be coupled to the reference voltage; and (d) a second branch, the second branch being coupled between the first node and the output terminal, the second branch comprising: (1) a third blocking capacitor, the third blocking capacitor being coupled to the first node; (2) a fourth switch, the fourth switch being coupled between the third blocking capacitor and a third node; (3) a fifth switch coupled between the third node and the output terminal; and (4) a sixth switch coupled to the third node and configured to be coupled to the reference voltage; The first branch is enabled in a first operation mode, and the second branch is enabled in a second operation mode.

8. The invention according to claim 7, wherein: The first inductor and the second inductor are implemented as asymmetric T-shaped coils.

9. The invention according to claim 7, wherein: At least one of the first inductor and / or the second inductor is adjustable.

10. The invention according to claim 7, wherein: At least one of the first inductor and / or the second inductor is dynamically variable.

11. The invention according to claim 7, wherein: At least one of the third inductor, the first blocking capacitor, the second blocking capacitor, and / or the third blocking capacitor is adjustable.

12. The invention according to claim 7, wherein: At least one of the third inductor, the first blocking capacitor, the second blocking capacitor, and / or the third blocking capacitor is dynamically variable.

13. An amplifier, comprising: (a) an amplifier core, the amplifier core comprising: (1) an amplifier input terminal, the amplifier input terminal being configured to receive a radio frequency (RF) signal; and (2) Amplifying the signal end; (b) a tunable hybrid broadband output impedance matching network, the tunable hybrid broadband output impedance matching network having a network input terminal coupled to the amplified signal terminal of the amplifying core and a network output terminal, the tunable hybrid broadband output impedance matching network comprising: (1) a first inductor, wherein the first inductor is coupled between the network input terminal and a first node; (2) a second inductor coupled to the first node and configured to be coupled to a power source; (3) a strengthening amplification branch, wherein the strengthening amplification branch is coupled between the network input end and the network output end; (4) a non-amplifying branch, the non-amplifying branch being coupled between the first node and the network output end; The enhanced amplification branch is enabled in a first operation mode, and the non-amplification branch is enabled in a second operation mode.

14. The invention according to claim 13, wherein: The enhanced amplification branch comprises: (a) a first blocking capacitor coupled to the input terminal; (b) a third inductor configured to be coupled to a reference voltage; (c) a FET having a control gate, a source coupled to the third inductor, and a drain configured to be coupled to the power source; (d) a first switch coupled between the first blocking capacitor and a control gate of the FET; (e) a second blocking capacitor coupled between the source of the FET and a second node; (f) a second switch coupled between the second node and the output terminal; and (g) A third switch coupled to the second node and configured to be coupled to the reference voltage.

15. The invention according to claim 13, wherein: The non-amplified branch comprises: (a) a first blocking capacitor coupled to the first node; (b) a first switch coupled between the first blocking capacitor and a second node; (c) a second switch coupled between the second node and the output terminal; and (d) A third switch coupled to the second node and configured to be coupled to the reference voltage.

16. The invention according to claim 13, wherein: The first inductor and the second inductor are implemented as asymmetric T-shaped coils.

17. The invention according to claim 13, wherein: At least one of the first inductor and / or the second inductor is adjustable.

18. The invention according to claim 13, wherein: At least one of the first inductor and / or the second inductor is dynamically variable.

19. The invention according to claim 13, wherein: The amplifier is a low noise amplifier.

20. The invention according to claim 13, wherein: The amplifier is implemented as an integrated circuit fabricated in silicon-on-insulator technology and includes MOS devices.

21. The invention according to claim 13, wherein: The amplifier is implemented as an integrated circuit assembled in a circuit module.

22. The invention according to claim 13, wherein: The amplifier is implemented as an integrated circuit comprising a part of a communication device.

23. The invention according to claim 13, wherein: The amplifier core also includes a feedback node in an output signal path of the amplifier core, and the invention further includes an input feedback circuit coupled between the amplifier input and the feedback node.

24. The invention according to claim 23, wherein: The input feedback circuit is selectively switchable between an enabled state and a disabled state.

25. The invention according to claim 13, wherein: The amplifier core also includes a feedback node in an output signal path of the amplifier core, and the invention further includes an output feedback circuit coupled between the feedback node and a gate of a common-gate FET within the amplifier core.

26. The invention according to claim 25, wherein: The output feedback circuit is selectively switchable between an enabled state and a disabled state.

27. The invention according to claim 13, wherein: The amplifier core also includes: (a) a common-source FET having a gate, a source, and a drain coupled to the amplifier input; (b) a stack comprising at least one common-gate FET, each common-gate FET having a gate, a source, and a drain that outputs an amplified version of the received RF signal, wherein the source of one of the at least one common-gate FET is coupled to the drain of the common-source FET, and wherein the drain of one of the at least one common-gate FET is coupled to an amplified signal end of the stack.

28. The invention according to claim 13, wherein: The amplifier core includes a degeneration terminal, and the invention further includes a degeneration circuit coupled to the degeneration terminal and configured to be coupled to a reference potential, the degeneration circuit including a degeneration inductor.

29. The invention of claim 28 further comprising a bypass switch coupled in parallel with the degeneration inductor.

30. The invention of claim 13 further comprising an input impedance matching circuit coupled to the amplifier input and configured to receive the RF signal.

31. The invention according to claim 30, wherein: The input impedance matching circuit includes a series inductor coupled to the input terminal and configured to receive the RF signal, and a shunt inductor coupled between the series inductor and a reference potential.

32. A method for implementing different gain modes for a radio frequency amplifier having an amplifier core with a signal amplification terminal, the method comprising: (a) coupling a first inductor coupled to the amplified signal terminal to a first node; (b) coupling a second inductor to the first node, and configuring the second inductor to be coupled to a power source; (c) coupling an enhanced amplification branch between the amplified signal terminal and the output terminal; (d) coupling a non-amplifying branch between the first node and the output terminal; (e) selectively enabling the enhanced amplification branch in a first operating mode; as well as (f) selectively enabling the non-amplifying branch in a second operating mode.

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