Method for manufacturing laminate and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. Sequentially forming an oxide semiconductor, a first conductor, a first insulator, a second insulator, an inorganic film, a first coating film and a second coating film on the substrate; processing the second coating film by a dry etching method to form an island-shaped second coating film; processing the first coating film by a dry etching method using the island-shaped second coating film as a mask to form the island-shaped first coating film and remove the resist mask; sequentially processing the inorganic film, the second insulator, the first insulator, and the first conductor by a dry etching method using the island-shaped first coating film as a mask to form an island-shaped inorganic film, an island-shaped second insulator, an island-shaped first insulator, and an island-shaped first conductor, and removing the island-shaped second coating film; forming an island-shaped oxide semiconductor by processing the oxide semiconductor by a dry etching method using the island-shaped inorganic film as a mask, and removing the island-shaped first coating film; and removing the island-like inorganic film by a dry etching method, in which the first insulator is a nitride and the second insulator is an oxide.

Description

Technical Field

[0001] One embodiment of the present invention relates to a method for processing a laminate including an oxide semiconductor layer and a conductor layer. In addition, one embodiment of the present invention relates to a semiconductor device, a storage device, and an electronic device using the laminate. In addition, one embodiment of the present invention relates to a method for manufacturing a semiconductor device using the laminate.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), and a driving method or a manufacturing method of the above-mentioned device can be cited.

[0003] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, or storage devices are also a form of semiconductor devices. Sometimes it can be said that display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, electronic devices, etc. include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI, CPU, memory, etc. are mainly used for semiconductor devices. CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memory) formed by processing a semiconductor wafer into a chip and having electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards (eg, printed wiring boards) and are used as one of the components of various electronic devices.

[0006] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply recorded as display devices). As a semiconductor thin film that can be applied to transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that a transistor using an oxide semiconductor has extremely low leakage current in a non-conducting state. For example, Patent Document 1 has disclosed a low-power CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0008] In addition, Patent Document 3 discloses a transistor having a microstructure in which a source electrode layer and a drain electrode layer are provided in contact with the top surface of an oxide semiconductor layer. [Prior technical literature] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2016-125052 Summary of the invention Technical problem to be solved by the invention

[0010] One of the purposes of one embodiment of the present invention is to provide a method for processing a laminated body having a microstructure including an oxide semiconductor layer and a conductor layer. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device having the above-mentioned laminated body. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device that can achieve miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with a fast operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with small unevenness in the electrical characteristics of transistors. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. In addition, one of the purposes of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device.

[0011] In addition, one of the purposes of one embodiment of the present invention is to provide a storage device with a large storage capacity. In addition, one of the purposes of one embodiment of the present invention is to provide a storage device with a fast operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a storage device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a novel storage device.

[0012] Note that the description of these purposes does not prevent the existence of other purposes. One embodiment of the present invention does not necessarily achieve all of the above purposes. In addition, purposes other than the above can be extracted from the description of the specification, drawings, and claims. Solutions to technical problems

[0013] One embodiment of the present invention is a method for manufacturing a stacked body, comprising: depositing an oxide semiconductor, a first conductor, a first insulator comprising a nitride, a second insulator comprising an oxide, an inorganic film, a first coating film and a second coating film in sequence on a substrate; forming a resist mask on the second coating film; using the resist mask as a mask to process the second coating film by a dry etching method to form an island-shaped second coating film; using the island-shaped second coating film as a mask to process the first coating film by a dry etching method to form an island-shaped first coating film and remove the resist mask; using the island-shaped first coating film as a mask to process the inorganic film, the second insulator, the first insulator and the first conductor in sequence by a dry etching method to form an island-shaped inorganic film, an island-shaped second insulator, an island-shaped first insulator and an island-shaped first conductor and remove the island-shaped second coating film; using the island-shaped inorganic film as a mask to process the oxide semiconductor by a dry etching method to form an island-shaped oxide semiconductor and remove the island-shaped first coating film; and removing the island-shaped inorganic film by dry etching.

[0014] Among the above, the oxide semiconductor preferably contains indium, gallium, and zinc.

[0015] In the above, the first conductor preferably includes tantalum nitride.

[0016] In the above, the first electric conductor may have a stacked-layer structure of a layer including tantalum nitride and a layer including tungsten on the layer including tantalum nitride.

[0017] In addition, in the above, the first insulator preferably includes silicon nitride.

[0018] In the above, the second insulator preferably includes silicon oxide.

[0019] In the above, the inorganic film preferably contains tungsten.

[0020] In addition, in the above, the first coating film preferably contains carbon.

[0021] In the above, the second coating film preferably contains silicon and oxygen.

[0022] In the above, it is preferred that a third insulator and a fourth insulator are sequentially deposited between the substrate and the oxide semiconductor, and after forming an island-shaped oxide semiconductor, the fourth insulator is processed by dry etching using the island-shaped inorganic film as a mask to form an island-shaped fourth insulator.

[0023] In addition, in the above, it is preferred that the third insulator contains hafnium oxide, and the fourth insulator contains silicon oxide.

[0024] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: processing a stack using the above-mentioned method for manufacturing a stack; then dividing a first conductor into a second conductor and a third conductor; and forming a fifth insulator and a fourth conductor on the fifth insulator in a manner that overlaps with a region between the second conductor and the third conductor. Effects of the Invention

[0025] According to one embodiment of the present invention, a method for processing a laminated body having a microstructure including an oxide semiconductor layer and a conductor layer can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device having the above-mentioned laminated body can be provided. In addition, according to one embodiment of the present invention, a semiconductor device that can achieve miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a high operating speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with small unevenness in the electrical characteristics of transistors can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. In addition, according to one embodiment of the present invention, a novel method for manufacturing a semiconductor device can be provided.

[0026] According to one embodiment of the present invention, a storage device with large storage capacity can be provided. In addition, according to one embodiment of the present invention, a storage device with high operating speed can be provided. In addition, according to one embodiment of the present invention, a storage device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a novel storage device can be provided.

[0027] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. In addition, effects other than the above can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1A to 1F This is a cross-sectional view showing an example of a method for producing a laminate. Figure 2A is a plan view showing an example of a semiconductor device. FIG. 2B to FIG. 2D is a cross-sectional view showing an example of a semiconductor device. Figure 3A and Figure 3B is a cross-sectional view showing an example of a semiconductor device. Figure 4A and Figure 4B is a cross-sectional view showing an example of a semiconductor device. Figure 5A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 5B to FIG. 5D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Fig. 6A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 6B to FIG. 6D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Fig. 7A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 7B to FIG. 7D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Fig. 8A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 8B to FIG. 8D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Fig.9A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 9B to FIG. 9D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Fig. 10A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 10B to FIG. 10D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Fig.11A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 11B to FIG. 11D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Fig.12 is a block diagram showing an example of a storage device. Fig.13A and Fig. 13B 1 is a schematic diagram and a circuit diagram showing an example of a storage device. Fig.14A and Fig. 14B is a schematic diagram showing an example of a storage device. Fig.15 is a circuit diagram showing an example of a storage device. Fig.16 is a cross-sectional view showing an example of a storage device. Fig.17 is a cross-sectional view showing an example of a storage device. 18A to 18C is a circuit diagram showing an example of a storage device. Fig.19A and Fig.19B is a diagram showing an example of a semiconductor device. Fig. 20A and Fig. 20B It is a diagram showing an example of an electronic component. FIG. 21A to FIG. 21J is a diagram showing an example of an electronic device. FIG. 22A to FIG. 22E is a diagram showing an example of an electronic device. FIG. 23A to FIG. 23C is a diagram showing an example of an electronic device. Fig.24 is a diagram showing an example of space equipment. Fig.25A and Fig.25B is a diagram according to this embodiment. Fig.26A and Fig.26B is a cross-sectional SEM image according to this example. Fig.27A and Fig.27B is a cross-sectional SEM image according to this example. Fig.28A and Fig.28B is a diagram according to this embodiment. Fig.29A and Fig.29B is a cross-sectional SEM image according to this example. Fig. 30A and Fig. 30B is a cross-sectional SEM image according to this example. Modes for Carrying Out the Invention

[0029] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0030] Note that in the invention structure described below, the same reference numerals are used in common in different drawings to represent the same parts or parts with the same function, and repeated description is omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding a reference numeral.

[0031] In addition, for ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.

[0032] Note that in this specification, etc., ordinal numbers such as "first" and "second" are added for convenience, but they do not limit the number of components or the order of components (for example, the order of processes or the order of stacking). In addition, the ordinal numbers added to components in one part of this specification may not be consistent with the ordinal numbers added to the components in other parts of this specification or claims.

[0033] In addition, depending on the situation or condition, "film" and "layer" may be interchanged. For example, "conductive layer" may be interchanged with "conductive film". In addition, "insulating film" may be interchanged with "insulating layer". In addition, depending on the situation or condition, "conductive body" may be interchanged with "conductive layer" or "conductive film". In addition, depending on the situation or condition, "insulator" may be interchanged with "insulating layer" or "insulating film".

[0034] The opening includes, for example, a groove, a slit, etc. In addition, a region where the opening is formed may be referred to as an opening portion.

[0035] Furthermore, the drawings used in this embodiment mode illustrate the case where the side walls of the opening of the insulator are substantially perpendicular to the substrate surface or the formed surface, but the side walls of the opening of the insulator may also be tapered.

[0036] Note that in this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to a substrate surface or a formed surface. For example, it is preferable to have a region in which the angle formed by the inclined side surface and the substrate surface or the formed surface (hereinafter, sometimes referred to as a taper angle) is less than 90°. Note that the side surface and the substrate surface of a constituent element do not necessarily have to be completely flat, and may be a substantially planar shape with a slight curvature or a substantially planar shape with fine concave-convex shapes.

[0037] (Implementation Method 1) In this embodiment, a method for processing a stacked body including an oxide semiconductor layer and a conductor layer according to one embodiment of the present invention is described. In addition, a semiconductor device including the stacked body is described.

[0038] <Example of Processing Method of Laminated Body> use Figures 1A to 1F An example of a method for processing a stacked body including an oxide semiconductor layer and a conductor layer according to one embodiment of the present invention will be described.

[0039] In this section, we explain the formation Figure 1F The method of forming a stacked body including an oxide 230 (oxide 230a and oxide 230b) and a conductor 242 on the oxide 230 is shown. That is, the oxide 230 is provided as an oxide semiconductor layer constituting the stacked body, and the conductor 242 is provided as a conductor layer. Figure 1F In the illustrated stacked body, an island-shaped insulator 224, an island-shaped oxide 230 (oxide 230a and oxide 230b), an island-shaped conductor 242, and an island-shaped insulator 271 (insulator 271_1, insulator 271_2) are provided on the insulator 216 and the insulator 222 used as the base insulating film.

[0040] The oxide 230 is a metal oxide used as an oxide semiconductor, and can be used as an active layer of a transistor, for example. In this case, the conductor 242 in contact with the top surface of the oxide 230 can be used as a source electrode or a drain electrode of the transistor.

[0041] Below, use Figures 1A to 1F A specific example of processing of a stacked body including the insulator 224, the oxide 230, the conductor 242, and the insulator 271 will be described.

[0042] First, an insulator 216, an insulator 222, an insulating film 224f, an oxide film 230af, an oxide film 230bf, a conductive film 242f, an insulating film 271_1f, and an insulating film 271_2f are sequentially deposited on a substrate (not shown). Figure 1A). Here, the insulating film 224f is an insulating film that will become the insulator 224 in a later process. In addition, the oxide film 230af is a metal oxide film that will become the oxide 230a in a later process. In addition, the oxide film 230bf is a metal oxide film that will become the oxide 230b in a later process. In addition, the conductive film 242f is a conductive film that will become the conductor 242 in a later process. In addition, the insulating film 271_1f is an insulating film that will become the insulator 271_1 in a later process. In addition, the insulating film 271_2f is an insulating film that will become the insulator 271_2 in a later process.

[0043] Here, the insulating film 271_1f and the insulating film 271_2f are films for protecting the conductor 242 and will be used as an etching stopper film in the following process. In addition, since the insulating film 271_1f is in contact with the conductive film 242f, it is preferable to use an inorganic insulating film that does not easily oxidize the conductive film 242f. The insulating film 271_1f preferably uses a nitride insulator, for example, silicon nitride. In addition, the insulating film 271_2f preferably uses an oxide insulator, for example, silicon oxide. In addition, the insulating film 271_1f and the insulating film 271_2f may be continuously deposited without being exposed to the atmosphere.

[0044] For example, silicon oxide may be used for the insulator 216 and the insulating film 224f. For example, hafnium oxide may be used for the insulator 222. For example, oxides containing In, Ga, and Zn may be used for the oxide films 230af and 230bf. For example, tantalum nitride may be used for the conductive film 242f. For example, the conductive film 242f may have a stacked structure, or may have a stacked structure of a layer containing tantalum nitride and a layer containing tungsten on the layer containing tantalum nitride.

[0045] The detailed structures of insulator 216, insulator 222, insulating film 224f (insulator 224), oxide film 230af (oxide 230a), oxide film 230bf (oxide 230b), conductive film 242f (conductor 242), insulating film 271_1f (insulator 271_1) and insulating film 271_2f (insulator 271_2) will be described in <Structural example of semiconductor device>.

[0046] Next, an inorganic film 276f is deposited on the insulating film 271_2f (see Figure 1A). The deposition of the inorganic film 276f can be performed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The inorganic film 276f is a film that will be used as a hard mask for forming the oxide 230a, the oxide 230b, and the insulator 224 in a subsequent process. The inorganic film 276f can use a metal material or an inorganic insulating material, or the like. For example, tungsten deposited by a sputtering method can be used as the inorganic film 276f. In addition, the inorganic film 276f can be continuously deposited without being exposed to the atmosphere after the insulating film 271_1f and the insulating film 271_2f are deposited.

[0047] Next, a coating film 277f is deposited on the inorganic film 276f, and then a coating film 278f is deposited (see Figure 1A The coating film 277f and the coating film 278f may also have the function of improving the adhesion between the resist mask described later and the inorganic film 276. The coating film 277f and the coating film 278f may be deposited by, for example, spin coating. The coating film 277f and the coating film 278f may be made of a non-photosensitive organic resin.

[0048] Here, the coating film 278f is used as a mask in the etching process of processing the coating film 277f. Therefore, in the etching conditions of the coating film 277f, the etching rate of the coating film 278f is preferably lower than the etching rate of the coating film 277f. For example, a film containing carbon can be used as the coating film 277f and a film containing silicon and carbon can be used as the coating film 278f. In this embodiment, a SOC (Spin On Carbon) film is deposited as the coating film 277f and a SOG (Spin On Glass) film is deposited as the coating film 278f.

[0049] In addition, the coating film 277f and the coating film 278f contain organic solvents such as alcohol when applied, but the organic matter contained is sometimes reduced or removed in the subsequent process or when the semiconductor device is completed. In addition, the coating film can be provided as needed, a single-layer coating film can be provided, or a coating film may not be provided when only the resist mask described later is sufficient.

[0050] Next, a resist mask 279 is formed on the coating film 278f by photolithography (see Figure 1A ). As the resist mask 279, a photosensitive organic resin also called a photoresist can be used. For example, a positive photoresist or a negative photoresist can be used. For example, the photoresist to be the resist mask 279 can be deposited to a uniform thickness by using a spin coating method or the like.

[0051] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into a desired shape. For example, a KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. can be used to expose the resist to form a resist mask. In addition, a liquid immersion technique in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or an ion beam can also be used instead of the above-mentioned light. In addition, when an electron beam or an ion beam is used, a mask may sometimes not be used.

[0052] Below, according to Figures 1B to 1F In the process of dry etching, Figure 1A Etching process of the stacked film shown. The dry etching method can perform anisotropic etching and is therefore suitable for forming a stacked body having a microstructure with a high aspect ratio including the insulator 224, the oxide 230, the conductor 242, and the insulator 271.

[0053] Here, as the etching gas used for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. As the etching gas, for example, C 4 F 6 Gas, C 5 F 6 Gas, C 4 F 8 Gas, CF 4 Gas, SF 6 Gas, CHF 3 Gas, CH 2 F 2 Gas, Cl 2 Gas, BCl 3 Gas, SiCl 4 and BBr 3 In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas or hydrocarbon gas may be appropriately added to the above-mentioned etching gas. In addition, depending on the object to be processed by dry etching, a gas containing hydrocarbon gas or hydrogen gas instead of halogen gas may be used as the etching gas. Methane (CH 4 ), ethane (C 2 H 6 ), propane (C 3 H 8 ), butane (C 4 H10 ), ethylene (C 2 H 4 ), propylene (C 3 H 6 ), acetylene (C 2 H 2 ) and propyne (C 3 H 4 The etching conditions can be appropriately set according to the etching object.

[0054] As a dry etching device, for example, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which a plurality of different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with different frequencies is applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device can be used. The etching device can be appropriately set according to the etching object.

[0055] according to Figures 1B to 1F The process is preferably carried out continuously without being exposed to the outside air. For example, a multi-chamber etching device can be used to carry out the process without being exposed to the outside air. Here, a CCP etching device is preferably used, which is arranged according to Figures 1B to 1F In the process of applying high-frequency voltages of different frequencies to the parallel plate-type electrodes in the processing chamber, respectively, in this case, a high-frequency voltage of high frequency can be applied to the upper electrode and a low-frequency voltage of high frequency can be applied to the lower electrode where the substrate is set.

[0056] First, the coating film 278f is processed using the resist mask 279 to form an island-shaped coating film 278. For example, when an SOG film is used as the coating film 278f, CHF 3 and O 2 As etching gas.

[0057] Next, the coating film 277f is processed using the coating film 278 as a mask to form an island-shaped coating film 277 (see Figure 1B For example, when a SOC film is used as the coating film 277f, H 2 and N 2Here, an SOG film is used as the coating film 278, thereby preventing the coating film 278 from disappearing during the etching process of the coating film 277f.

[0058] In addition, it is preferable to remove the resist mask 279 simultaneously with processing the coating film 277f. Since the SOC film is used as the coating film 277f, the resist mask 279 can be easily removed. In addition, when the resist mask 279 remains after forming the coating film 277, it is preferable to remove the resist mask 279.

[0059] Next, the inorganic film 276f, the insulating film 271_2f, the insulating film 271_1f, and the conductive film 242f are processed in sequence using the coating film 277 as a mask to form an island-shaped inorganic film 276, an island-shaped insulator 271_1, an island-shaped insulator 271_2, and an island-shaped conductor 242 (see Figure 1C For example, when a tungsten film is used as the inorganic film 276f, CF 4 and Cl 2 For example, when silicon nitride is used as the insulating film 271_1f and silicon oxide is used as the insulating film 271_2f, CHF may be used for etching the insulating film 271_1f and the insulating film 271_2f. 3 and O 2 As an etching gas. For example, when a tantalum nitride film is used as the conductive film 242f, CHF 3 , Cl 2 Similarly, when a stacked film of a tantalum nitride layer and a tungsten layer is used as the conductive film 242f, HF may be used. 3 , Cl 2 and Ar as etching gas.

[0060] Here, the same metal material (e.g., tungsten, etc.) may be used as the inorganic film 276 and the conductive film 242f. When the coating film 277 used as a mask disappears during the etching of the conductive film 242f, the inorganic film 276 is exposed to the etching. As a result, the conductive film 242f and the like are over-etched, which may cause the width of the conductor 242 to be narrower than designed.

[0061] Therefore, in the etching process of the conductive film 242f, it is preferable to perform etching under the condition that the etching rate of the conductive film 242f is higher than the etching rate of the coating film 277. For example, in the etching process of the conductive film 242f, it is preferable to reduce the power consumption of the lower electrode provided with the substrate. For example, the power consumption of the lower electrode provided with the substrate can be lower than the power consumption of the lower electrode when etching the inorganic film 276f, preferably lower than 25W, and more preferably lower than 10W. By performing etching under the above conditions, processing can be performed as designed even in a microstructured laminate.

[0062] It is preferable that the coating film 278 be removed simultaneously with the processing of the insulating film 271_1f and the insulating film 271_2f. Since a silicon-based insulating film is used as the insulating film 271_1f and the insulating film 271_2f, the coating film 278 can be easily removed.

[0063] Next, the oxide film 230bf and the oxide film 230af are processed using the inorganic film 276 as a mask to form an island-shaped oxide 230b and an island-shaped oxide 230a (see Figure 1D For example, when an oxide containing any one or more selected from In, Ga, and Zn is used as the oxide film 230bf and the oxide film 230af, CH 4 and Ar as etching gas. Oxides containing In, Ga, Zn and CH 3 The free radicals react to form highly volatile metal complexes. 4 The gas can easily process oxides containing In, Ga, and Zn, which are difficult-to-etch materials, even at a low substrate temperature.

[0064] When the inorganic film 276 includes tungsten and the insulating film 224f includes silicon oxide, methane (CH 4 ) gas is used to etch the oxide film 230bf and the oxide film 230af. By etching in this way, the etching rate of the oxide film 230bf and the oxide film 230af can be significantly greater than that of the inorganic film 276 and the insulating film 224f. Therefore, in this process, the oxide film 230bf and the oxide film 230af can be formed into an island shape while the insulating film 224f is flat. Therefore, in the process of forming the insulating film 224f into an island shape described later, the area of ​​the insulating film 224f that does not overlap with the oxide 230a can be completely removed, and the insulator 222 can be prevented from being over-etched.

[0065] In addition, it is preferable to remove the coating film 277 while processing the oxide film 230bf and the oxide film 230af. Figure 1D When the coating film 277 remains after the steps shown, the coating film 277 can be removed by performing dry etching such as ashing, performing wet etching, performing wet etching followed by dry etching, or performing dry etching followed by wet etching.

[0066] Alternatively, the coating film 277 may be removed after the formation of the conductor 242 is completed and before the oxide film 230bf and the oxide film 230af are processed.

[0067] Next, the insulating film 224f is processed using the inorganic film 276 to form an island-shaped insulator 224 (see Figure 1E For example, when a silicon oxide film is used as the insulating film 224f, CHF 3 and Ar as etching gas.

[0068] Here, in the processing of the insulating film 224f, the insulator 222 is preferably not overetched. Therefore, it is preferable to perform etching under a condition where the etching selectivity ratio with respect to the insulator 222 is large. For example, when the insulating film 224f contains silicon oxide and etching is performed using a gas containing fluorine, the insulator 222 preferably contains hafnium oxide.

[0069] Finally, the inorganic film 276 is removed (see Figure 1F Here, the insulator 271_1 and the insulator 271_2 are used as an etching stopper film to protect the conductor 242. Here, a silicon-based oxide insulating film is used as the insulator 271_2, thereby preventing the insulator 271_1 and the insulator 271_2 from disappearing during the etching process of the organic film 276.

[0070] For example, when a tungsten film is used as the inorganic film 276, CF 4 , Cl 2 and O 2 As an etching gas. In addition, when the material of the inorganic film 276 does not affect the subsequent process or can be used in the subsequent process, the inorganic film 276 does not necessarily need to be removed.

[0071] In addition, in the process of removing the inorganic film 276, the insulator 271_1 and the insulator 271_2 are used as a mask to protect the conductor 242, so the conductor 242 does not have a curved surface between the side and the top surface. Therefore, the end portion where the side and the top surface of the conductor 242 intersect becomes an angle. When the end portion where the side and the top surface of the conductor 242 intersect becomes an angle, the cross-sectional area of ​​the conductor 242 increases compared to the case where the end portion has a curved surface. Furthermore, by using a nitride insulator that is not easy to oxidize metal as the insulator 271_1, the conductor 242 can be prevented from being excessively oxidized. Therefore, when the above-mentioned laminate is used for a transistor, the resistance of the conductor 242 that becomes the source electrode and the drain electrode later is reduced, thereby increasing the on-state current of the transistor.

[0072] Through the above process, a Figure 1F In the island-shaped stacked body shown, the side surface of the conductor 242 does not excessively recede from the side surface of the oxide 230. In other words, the side end of the conductor 242 is roughly aligned with the side end of the oxide 230. By manufacturing a transistor using such a stacked body having a microstructure, miniaturization and high integration of semiconductor devices can be achieved.

[0073] In addition, the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, the insulator 271_1, and the insulator 271_2 can be processed into an island shape at one time. Therefore, the number of steps can be reduced compared to the case where the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, the insulator 271_1, and the insulator 271_2 are processed into island shapes separately. Therefore, the productivity of the semiconductor device can be improved.

[0074] <Structural Example of Semiconductor Device> A structural example of a semiconductor device using the above-mentioned stacked body will be described with reference to FIGS. 2 to 4 . FIG. 2A to FIG. 2D 1 and 2 are a plan view and a cross-sectional view of a semiconductor device (transistor 200 ). Figure 2A is a plan view of the semiconductor device. FIG. 2B to FIG. 2D is a cross-sectional view of the semiconductor device. Figure 2B It is along Figure 2A The cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. 1 is also a cross-sectional view along the channel length direction of the transistor 200. Figure 2C It is along Figure 2A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. 1 is also a cross-sectional view along the channel width direction of the transistor 200. Figure 2D It is along Figure 2A The cross-sectional view of the portion along the dashed line A5-A6 in FIG. 1 is also a cross-sectional view in the channel width direction of the transistor 200. Note that Figure 2A In the plan view, some components are omitted for clarity. Figure 3A and Figure 3B An enlarged cross-sectional view of the transistor 200 in the channel length direction is shown. Figure 4A and Figure 4B An enlarged cross-sectional view of the transistor 200 in the channel width direction is shown.

[0075] Transistor 200 includes: an insulator 216 on an insulator 215; a conductor 205 (conductor 205a and conductor 205b) arranged in a manner of embedding insulator 216; an insulator 222 on insulator 216 and conductor 205; an insulator 224 on insulator 222; an oxide 230 (oxide 230a and oxide 230b) on insulator 224; a conductor 242a and conductor 242b on oxide 230; an insulator 271a (insulator 271a1 and insulator 271a2) on conductor 242a; an insulator 271b (insulator 271b1 and insulator 271b2) on conductor 242b; an insulator 250 on oxide 230; and a conductor 260 (conductor 260a and conductor 260b) on insulator 250.

[0076] An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. The insulator 250 and the conductor 260 are embedded in the openings provided in the insulator 280 and the insulator 275. An insulator 282 is provided on the insulator 280 and the conductor 260. In addition, an insulator 283 is provided on the insulator 282.

[0077] The oxide 230 has a region used as a channel formation region of the transistor 200. In addition, the conductor 260 has a region used as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region used as a first gate insulator of the transistor 200. In addition, the conductor 205 has a region used as a second gate electrode (lower gate electrode) of the transistor 200. The insulator 224 and the insulator 222 both have a region used as a second gate insulator of the transistor 200.

[0078] The conductor 242a has a region that functions as one of a source electrode and a drain electrode of the transistor 200. The conductor 242b has a region that functions as the other of a source electrode and a drain electrode of the transistor 200.

[0079] like FIG. 2B to FIG. 2D As shown, when viewed from the cross section of the transistor 200, it is preferred that one side end of the conductor 242a is roughly aligned with one side end of the oxide 230, and one side end of the conductor 242b is roughly aligned with the other side end of the oxide 230. Furthermore, the side end of the insulator 224 is preferably roughly aligned with the side end of the oxide 230. As described above, one embodiment of the present invention can process the insulator 224, the oxide 230, and the conductor 242 to be the conductor 242a and the conductor 242b into an island shape at one time. Thus, a semiconductor device according to one embodiment of the present invention can be manufactured with good productivity. When processed as described above, the side ends of the insulator 224, the oxide 230, the conductor 242a, and the conductor 242b are all roughly aligned as described above.

[0080] In addition, the insulator 271a and the insulator 271b are used as an etching stop layer to protect the conductor 242a and the conductor 242b in the above-mentioned island processing. Figure 2B and Figure 2D As shown, when viewed from the cross section of the transistor 200, it is preferred that the side end of the insulator 271a is roughly aligned with the side end of the conductor 242a, and the side end of the insulator 271b is roughly aligned with the side end of the conductor 242b.

[0081] When the side ends are aligned or roughly aligned when viewed from a cross section, and when the top surface shapes are consistent or roughly consistent, it can be said that at least a portion of their contours overlap each other between the stacked layers when viewed from above. For example, this includes a situation where the lower portion of the side end of the upper layer contacts the upper portion of the side end of the lower layer. In addition, for example, this includes a situation where the upper layer and the lower layer are processed by the same or a part of the same mask pattern. However, in reality, there are situations where the contours do not overlap, and sometimes the upper layer is located on the inner side of the lower layer or the upper layer is located on the outer side of the lower layer. In this case, it can also be said that "the side ends are roughly aligned" or "the top surface shapes are roughly consistent."

[0082] The oxide 230 preferably includes an oxide 230a on the insulator 224 and an oxide 230b on the oxide 230a. By providing the oxide 230a below the oxide 230b, it is possible to suppress diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b.

[0083] Note that although this embodiment shows an example in which the oxide 230 has a two-layer structure of the oxide 230 a and the oxide 230 b , the present invention is not limited thereto. The oxide 230 may have a single-layer structure of the oxide 230 b or a stacked-layer structure of three or more layers.

[0084] like Figure 3A As shown, the oxide 230b has a region 230bc and a region 230ba and a region 230bb provided in a manner sandwiching the region 230bc in the transistor 200. Here, the region 230bc is used as a channel formation region. In addition, the region 230ba is used as one of the source region and the drain region, and the region 230bb is used as the other of the source region and the drain region. At least a portion of the region 230bc overlaps with the conductor 260. The region 230ba overlaps with the conductor 242a, and the region 230bb overlaps with the conductor 242b.

[0085] Since the region 230bc has fewer oxygen vacancies and a lower impurity concentration than the region 230ba and the region 230bb, the region 230bc is a high resistance region with a low carrier concentration. Therefore, the region 230bc can be regarded as an i-type (intrinsic) or substantially i-type region.

[0086] In addition, regions 230ba and 230bb have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, and are therefore low-resistance regions with high carrier concentrations. That is, regions 230ba and 230bb are n-type regions (low-resistance regions) with higher carrier concentrations than region 230bc.

[0087] The carrier concentration of region 230bc is preferably 1×10 18 cm -3 Below, less than 1×1017 cm -3 , less than 1×10 16 cm -3 , less than 1×10 15 cm -3 , less than 1×10 14 cm -3 , less than 1×10 13 cm -3 , less than 1×10 12 cm -3 , less than 1×10 11 cm -3 or less than 1×10 10 cm -3 Note that there is no particular restriction on the lower limit of the carrier concentration in the region 230bc, and it may be, for example, 1×10 -9 cm -3 .

[0088] In the case where the purpose is to reduce the carrier concentration of the oxide 230b, the impurity concentration in the oxide 230b can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0089] Therefore, in order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. In order to reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that the impurities in the oxide 230b refer to, for example, elements other than the main component constituting the oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0090] In addition, the region 230bc, the region 230ba, and the region 230bb may be formed not only in the oxide 230b but also in the oxide 230a.

[0091] In the oxide 230, it is sometimes difficult to clearly observe the boundaries between the regions. The concentrations of the metal element and the impurity elements such as hydrogen and nitrogen detected in each region do not need to change in stages for each region, but may change continuously in each region. That is, the closer to the region 230bc, the lower the concentration of the metal element and the impurity elements such as hydrogen and nitrogen may be.

[0092] Note that a metal oxide serving as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230 a and the oxide 230 b ).

[0093] The band gap of the metal oxide used as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced. Therefore, a transistor containing a metal oxide in the channel formation region is called an OS transistor. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be fully reduced. In addition, the frequency characteristics of the OS transistor are high, so the semiconductor device can be operated at high speed.

[0094] The oxide 230 preferably includes a metal oxide (oxide semiconductor). As metal oxides that can be used for the oxide 230, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three selected from indium, element M and zinc. In addition, the element M is a metal element or a metalloid element with a high bond energy with oxygen, for example, a metal element or a metalloid element with a bond energy with oxygen higher than that of indium. Specifically, as the element M, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In addition, in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification and the like may include metalloid elements.

[0095] The oxide 230 may be, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide, indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. Alternatively, indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. containing silicon may be used.

[0096] At this time, by increasing the atomic number ratio of indium contained in the metal oxide relative to the total atomic number of all metal elements, the field effect mobility of the transistor can be increased.

[0097] In addition, the metal oxide may also replace indium or contain one or more metal elements with a large period number in addition to indium. The greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As a metal element with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. In addition, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0098] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0099] In addition, by increasing the ratio of the number of zinc atoms contained in the metal oxide to the total number of atoms of all metal elements, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor is suppressed, thereby improving the reliability.

[0100] In addition, by increasing the atomic number ratio of the element M contained in the metal oxide relative to the sum of the atomic numbers of all metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the change of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0101] As described above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the oxide 230. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0102] The oxide 230 preferably has a stacked structure of a plurality of oxide layers having different chemical compositions. For example, the atomic number ratio of the element M in the metal oxide used for the oxide 230a to the metal element of the main component is preferably greater than the atomic number ratio of the element M in the metal oxide used for the oxide 230b to the metal element of the main component. In addition, the atomic number ratio of the element M in the metal oxide used for the oxide 230a to In is preferably greater than the atomic number ratio of the element M in the metal oxide used for the oxide 230b to In. By adopting this structure, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 230a to the oxide 230b.

[0103] In addition, it is preferable that the atomic number ratio of In in the metal oxide used for oxide 230b to element M is greater than the atomic number ratio of In in the metal oxide used for oxide 230a to element M. By adopting this structure, transistor 200 can obtain large on-state current and high frequency characteristics.

[0104] In addition, since oxide 230a and oxide 230b contain a common element as a main component in addition to oxygen, the defect state density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-state current and high frequency characteristics.

[0105] Specifically, as the oxide 230a, a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto can be used. In addition, as the oxide 230b, a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto can be used. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M. In addition, when a single layer of the oxide 230b is provided as the oxide 230, the metal oxide that can be used for the oxide 230a can also be used as the oxide 230b. In addition, the composition of the metal oxide that can be used for the oxide 230a and the oxide 230b is not limited thereto. For example, the composition of the metal oxide that can be used for the oxide 230a can also be applied to the oxide 230b. Similarly, the composition of the metal oxide that can be used for the oxide 230b can also be applied to the oxide 230a.

[0106] Furthermore, when the metal oxide is deposited by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0107] The oxide 230 b preferably has crystallinity. In particular, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used as the oxide 230 b.

[0108] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies). In particular, by heat treating the metal oxide at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0109] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide with CAAC-OS has heat resistance and high reliability.

[0110] In addition, by using a crystalline oxide such as CAAC-OS as the oxide 230 b, the source electrode or the drain electrode can suppress the extraction of oxygen from the oxide 230 b. Therefore, even if heat treatment is performed, the extraction of oxygen from the oxide 230 b can be reduced, so that the transistor 200 is also stable to the high temperature (so-called thermal budget) in the manufacturing process.

[0111] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the region where the oxide semiconductor forms a channel, the electrical characteristics are easily changed, and reliability is sometimes reduced. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the region 230bc of the oxide semiconductor that forms the channel, the transistor will have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the region 230bc of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H. In other words, it is preferable that the carrier concentration of the region 230 bc in the oxide semiconductor is reduced and the region 230 bc is converted to i-type (intrinsic) or substantially converted to i-type.

[0112] In contrast, by providing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V O H. Note that when too much oxygen is supplied to region 230ba or region 230bb, the on-state current of transistor 200 may decrease or the field effect mobility may decrease. Furthermore, when the amount of oxygen supplied to region 230ba or region 230bb is uneven within the substrate surface, the characteristics of the semiconductor device including the transistor become uneven. In addition, when the oxygen supplied from the insulator to the oxide semiconductor diffuses to the conductor such as the gate electrode, source electrode and drain electrode, the conductor is sometimes oxidized, which leads to a loss of conductivity, thereby having a negative impact on the electrical characteristics and reliability of the transistor.

[0113] Therefore, in the oxide semiconductor, it is preferred that the carrier concentration of the region 230bc is reduced and the region 230bc is i-type or substantially i-type, while it is preferred that the carrier concentration of the regions 230ba and 230bb is high and the region 230bb is n-type. In other words, it is preferred to reduce the oxygen vacancies and V O H. In addition, it is preferable that the region 230ba and the region 230bb are not supplied with excessive oxygen and the V of the region 230ba and the region 230bb are not excessively reduced.O H content. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor may form V O H, so in order to reduce V O H amount, it is necessary to reduce the hydrogen concentration.

[0114] Therefore, the semiconductor device in this embodiment has the following structure: the hydrogen concentration in the region 230bc is reduced; the oxidation of the conductors 242a, 242b, and 260 is suppressed; and the reduction of the hydrogen concentration in the regions 230ba and 230bb is suppressed.

[0115] The insulator 250 in contact with the region 230bc of the oxide 230b preferably has a function of capturing and fixing hydrogen. Thus, the hydrogen concentration in the region 230bc of the oxide 230b can be reduced. Therefore, the V O H makes the region 230bci-type or substantially i-type.

[0116] Here, if Figure 3A and Figure 4A As shown, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In this case, the insulator 250a preferably has a function of capturing and fixing hydrogen.

[0117] As an insulator having the function of capturing and fixing hydrogen, a metal oxide having an amorphous structure can be cited. As the insulator 250a, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium is preferably used. The above-mentioned metal oxide having an amorphous structure sometimes has the following property: the oxygen atom has a dangling bond and hydrogen is captured or fixed by the dangling bond. That is, it can be said that the metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.

[0118] In addition, the insulator 250a preferably uses a high dielectric constant (high-k) material. As an example of a high-k material, there is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as the insulator 250a, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0119] Therefore, as the insulator 250a, it is preferred to use an oxide containing one or both of aluminum and hafnium, more preferably to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and further preferably to use aluminum oxide having an amorphous structure. In this embodiment, aluminum oxide is used as the insulator 250a. In this case, the insulator 250a is an insulator containing at least oxygen and aluminum. In addition, the aluminum oxide has an amorphous structure. In this case, the insulator 250a has an amorphous structure.

[0120] Next, as the insulator 250b, an insulator having a thermally stable structure such as silicon oxide or silicon oxynitride is preferably used. Note that in this specification, etc., "oxynitride" refers to a material whose composition contains more oxygen than nitrogen, and "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen. For example, when "silicon oxynitride" is described, it refers to a material whose composition contains more oxygen than nitrogen, and when "silicon nitride oxide" is described, it refers to a material whose composition contains more nitrogen than oxygen.

[0121] In addition, if Figure 3B and Figure 4B As shown in FIG. 1 , a structure in which an insulator 250d is provided on the insulator 250b may also be adopted. In this case, an insulator that can be used as the insulator 250a may be provided as the insulator 250d. For example, hafnium oxide may be used as the insulator 250d. Here, by providing the insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b and the like may be more effectively captured and fixed.

[0122] Furthermore, in order to suppress oxidation of the conductors 242a, 242b, and 260, an oxygen blocking insulator is preferably provided near each of the conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulators 250a, 250c, 250d, and 275.

[0123] In addition, in this specification, etc., a blocking insulator refers to an insulator having a barrier property. In this specification, etc., the barrier property refers to a function of suppressing the diffusion of the corresponding substance (it can also be said that the permeability is low). Alternatively, it refers to a function of capturing and fixing the corresponding substance (also called doping).

[0124] Examples of oxygen blocking insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride. In addition, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, and 275 preferably use a single layer or a stack of the above-mentioned oxygen blocking insulators.

[0125] The insulator 250a preferably has an oxygen barrier property. The insulator 250a is preferably at least less likely to allow oxygen to penetrate than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. When the insulator 250a has an oxygen barrier property, it is possible to suppress the side surfaces of the conductor 242a and the conductor 242b from being oxidized and forming an oxide film on the side surfaces. Therefore, it is possible to suppress a decrease in the on-state current of the transistor 200 or a decrease in the field effect mobility.

[0126] The insulator 250a is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. When the insulator 250a has oxygen barrier properties, it is possible to suppress the release of oxygen from the region 230bc of the oxide 230b during heat treatment, etc. Therefore, the formation of oxygen vacancies in the oxides 230a and 230b can be reduced.

[0127] In addition, by providing the insulator 250a, even if the insulator 280 contains too much oxygen, it is possible to suppress the excessive supply of oxygen to the oxide 230a and the oxide 230b, and to supply an appropriate amount of oxygen to the oxide 230a and the oxide 230b. Therefore, it is possible to suppress a decrease in the on-state current of the transistor 200 or a decrease in the field effect mobility due to excessive oxidation of the regions 230ba and 230bb.

[0128] Since an oxide containing one or both of aluminum and hafnium has an oxygen barrier property, it can be suitably used as the insulator 250 a .

[0129] The insulator 250c preferably has oxygen barrier properties. The insulator 250c is provided between the region 230bc of the oxide 230 and the conductor 260 and between the insulator 280 and the conductor 260. By adopting this structure, it is possible to suppress the diffusion of oxygen in the region 230bc of the oxide 230 into the conductor 260 and the formation of oxygen vacancies in the region 230bc of the oxide 230. In addition, it is possible to suppress the diffusion of oxygen in the oxide 230 and oxygen in the insulator 280 into the conductor 260 and the oxidation of the conductor 260. The insulator 250c is preferably at least less likely to allow oxygen to penetrate than the insulator 280. For example, silicon nitride is preferably used as the insulator 250c. In this case, the insulator 250c is an insulator containing at least nitrogen and silicon.

[0130] In addition, the insulator 250c preferably has a hydrogen barrier property, so that impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide 230b.

[0131] Insulator 275 preferably has oxygen barrier properties. Insulator 275 is provided between insulator 280 and conductor 242a and between insulator 280 and conductor 242b. By adopting this structure, it is possible to suppress the diffusion of oxygen contained in insulator 280 into conductor 242a and conductor 242b. Therefore, it is possible to suppress the oxidation of conductor 242a and conductor 242b caused by oxygen contained in insulator 280, thereby increasing resistivity and reducing on-state current. Insulator 275 is preferably at least less likely to allow oxygen to penetrate than insulator 280. For example, silicon nitride is preferably used as insulator 275. At this time, insulator 275 is an insulator containing at least nitrogen and silicon.

[0132] In order to suppress a decrease in the hydrogen concentration in the region 230ba and the region 230bb in the oxide 230, a hydrogen barrier insulator is preferably provided near the region 230ba and the region 230bb. In the semiconductor device described in this embodiment, the hydrogen barrier insulator is, for example, the insulator 275.

[0133] Examples of the hydrogen barrier insulator include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 preferably has a single-layer structure or a stacked-layer structure of the above hydrogen barrier insulators.

[0134] The insulator 275 preferably has a hydrogen barrier property. When the insulator 275 has a hydrogen barrier property, the insulator 250 can be prevented from capturing and fixing hydrogen in the regions 230ba and 230bb. Therefore, the regions 230ba and 230bb can be converted to n-type.

[0135] By adopting the above structure, region 230bc can be i-type or substantially i-type and region 230ba and region 230bb can be n-type, and a semiconductor device with good electrical characteristics can be provided. By adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. In addition, by miniaturizing transistor 200, high-frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0136] Insulators 250a to 250d are used as part of the first gate insulator. Insulators 250a to 250d are provided together with conductor 260 in an opening formed in insulator 280 or the like. In order to achieve miniaturization of transistor 200, the thickness of insulators 250a to 250d is preferably thin. The thickness of insulators 250a to 250d is preferably 0.1nm or more and 10nm or less, more preferably 0.1nm or more and 5.0nm or less, further preferably 0.5nm or more and 5.0nm or less, further preferably 1.0nm or more and less than 5.0nm, and further preferably 1.0nm or more and 3.0nm or less. In addition, at least a portion of insulators 250a to 250d may include an area of ​​the above-mentioned thickness.

[0137] In order to reduce the thickness of the insulator 250a to the insulator 250d as described above, it is preferable to use the atomic layer deposition (ALD) method for deposition. The ALD method includes the thermal ALD method that uses only thermal energy to react the precursor and the reactant, and the PEALD (Plasma Enhanced ALD) method that uses the reactant excited by plasma. In the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred.

[0138] The ALD method can deposit atoms in layers, and thus has the advantages of being able to deposit extremely thin films, being able to deposit structures with high aspect ratios, being able to deposit with fewer defects such as pinholes, being able to deposit with excellent coverage, and being able to deposit at low temperatures. Therefore, the insulator 250 can be deposited with a small thickness and high coverage on the side surfaces of the openings formed in the insulator 280 and the like and on the side ends of the conductors 242a and 242b and the like.

[0139] The precursor used in the ALD method sometimes contains carbon, etc. Therefore, the film formed by the ALD method sometimes contains more impurities such as carbon than the film formed by other deposition methods. In addition, the quantitative analysis of impurities can be performed by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or Auger electron spectroscopy (AES: Auger Electron Spectroscopy).

[0140] Note that in the above description, the insulator 250 has a three-layer structure of the insulators 250a to 250c or a four-layer structure of the insulators 250a to 250d, but the present invention is not limited thereto. The insulator 250 may have a structure including at least one of the insulators 250a to 250d. By forming the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified, thereby improving productivity.

[0141] In this embodiment, it is preferred that the semiconductor device has a structure for suppressing the mixing of hydrogen into the transistor 200, etc. in addition to the above-mentioned structure. For example, it is preferred that an insulator having a function of suppressing the diffusion of hydrogen is provided in a manner covering one or both of the upper and lower parts of the transistor 200, etc. In the semiconductor device described in this embodiment, the insulator is, for example, an insulator 282 and an insulator 283. In addition, the insulator 215 under the transistor 200 may have the same structure as either or both of the insulator 282 and the insulator 283. In this case, the insulator 215 may have a stacked structure of the insulator 282 and the insulator 283, and may have a structure in which the insulator 282 is located at the bottom and the insulator 283 is located at the top, or may have a structure in which the insulator 282 is located at the top and the insulator 283 is located at the bottom.

[0142] One or more of the insulator 282 and the insulator 283 are preferably used as a blocking insulator for inhibiting impurities such as water and hydrogen from diffusing from the substrate side or above the transistor 200 to the transistor 200. Therefore, one or more of the insulator 282 and the insulator 283 preferably contains a material having a property of inhibiting hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 Insulating materials having the function of inhibiting the diffusion of impurities such as copper atoms, etc. (not allowing the impurities to pass through easily). In addition, it is preferred to include insulating materials having the function of inhibiting the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the oxygen to pass through easily).

[0143] Insulator 282 and insulator 283 preferably include an insulator having a function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen, respectively, and for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride or silicon oxynitride can be used. For example, as insulator 283, silicon nitride or the like with higher hydrogen barrier properties is preferably used. In addition, for example, insulator 282 preferably includes aluminum oxide or magnesium oxide or the like with high performance of capturing and fixing hydrogen. Thus, it is possible to inhibit impurities such as water and hydrogen from diffusing from an interlayer insulating film or the like disposed outside insulator 283 to transistor 200 or the like. Alternatively, it is possible to inhibit oxygen contained in insulator 280 or the like from diffusing through insulator 282 or the like to the top of transistor 200 or the like. In addition, by using the same structure as one or both of insulator 282 and insulator 283 as insulator 215, it is possible to inhibit impurities such as water and hydrogen from diffusing from the substrate side through insulator 215 to transistor 200 or the like. In addition, it is possible to inhibit oxygen contained in insulator 224 or the like from diffusing to the substrate side. As described above, it is preferable to adopt a structure in which an insulator having a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen, surrounds the upper and lower sides of the transistor 200 and the like.

[0144] In the transistor 200, the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be embedded in the opening formed in the insulator 216. Figure 2A and Figure 2C As shown in FIG. 1 , the conductor 205 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 205 can be used as wiring when a plurality of transistors are arranged.

[0145] The conductor 205 may have a single-layer structure or a stacked-layer structure. In FIG. 2 and the like, the conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in a manner of contacting the bottom surface and the side wall of the above-mentioned opening. The conductor 205b is provided in a manner of being embedded in the concave portion of the conductor 205a formed along the above-mentioned opening. Here, the height of the top surface of the conductor 205 is substantially the same as the height of the top surface of the insulator 216.

[0146] Here, the conductor 205a preferably contains a material having a structure that suppresses hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N 2 O, NO, NO 2 Alternatively, it is preferred that the conductive material contain a conductive material having a function of inhibiting the diffusion of impurities such as copper atoms and the like. Alternatively, it is preferred that the conductive material contain a conductive material having a function of inhibiting the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0147] By using a conductive material having a function of reducing the diffusion of hydrogen as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing to the oxide 230 through the insulator 216 and the like. In addition, by using a conductive material having a function of inhibiting the diffusion of oxygen as the conductor 205a, it is possible to inhibit the conductor 205b from being oxidized and the conductivity from being reduced. As the conductive material having the function of inhibiting the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be cited. The conductor 205a can have a single-layer structure or a laminated structure of the above-mentioned conductive material. For example, the conductor 205a preferably contains titanium nitride.

[0148] In addition, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0149] The conductor 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without linking it with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Thus, compared with the case where the negative potential is not applied to the conductor 205, when the negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced.

[0150] In addition, the resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the thickness of the conductor 205 is set according to the resistivity. In addition, the thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, it is preferred to reduce the thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so the diffusion of the impurities into the oxide 230 can be suppressed.

[0151] Insulator 222 and insulator 224 are used as a second gate insulator.

[0152] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). In addition, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, compared with the insulator 224, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen.

[0153] The insulator 222 preferably uses an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. Alternatively, an oxide containing hafnium and zirconium is preferably used, for example, hafnium zirconium oxide is used. When the insulator 222 is formed using such a material, the insulator 222 is used as a layer to suppress the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the surrounding part of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen to the inside of the transistor 200, etc., and to suppress the generation of oxygen vacancies in the oxide 230. In addition, the conductor 205 can be suppressed from reacting with the oxygen contained in the insulator 224 and the oxide 230.

[0154] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, the above-mentioned insulator may be nitrided. In addition, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above-mentioned insulator for use as the insulator 222.

[0155] In addition, as the insulator 222, for example, a single-layer structure or a stacked-layer structure of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide may be used. When miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material as an insulator used as a gate insulator, the gate potential during operation of the transistor can be reduced while maintaining the physical thickness. In addition, as the insulator 222, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 )、(Ba, Sr)TiO 3 (BST) and other materials with high dielectric constants.

[0156] The insulator 224 in contact with the oxide 230 preferably includes, for example, silicon oxide or silicon oxynitride. Thus, oxygen can be supplied from the insulator 224 to the oxide 230 to reduce oxygen vacancies.

[0157] In addition, the insulator 224 is preferably processed into an island shape in the same manner as the oxide 230. Thus, when a plurality of transistors 200 are provided, an insulator 224 of substantially the same size is provided in each transistor 200. Therefore, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 is substantially equal. Thus, the non-uniformity of the electrical characteristics of the transistor 200 within the substrate surface can be suppressed. Note that this is not limiting, and a structure in which the pattern of the insulator 224 is not formed in the same manner as the insulator 222 may be adopted.

[0158] In addition, the insulator 222 and the insulator 224 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials.

[0159] As the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion. As the conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thus, the conductivity of the conductor 242a, the conductor 242b, and the conductor 260 can be suppressed from decreasing. When a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors containing at least metal and nitrogen.

[0160] The conductors 242a and 242b may have a single-layer structure or a multi-layer structure. In addition, the conductor 260 may have a single-layer structure or a multi-layer structure.

[0161] As the conductors 242a and 242b, metal nitrides are preferably used, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if oxygen is absorbed, so they are preferred.

[0162] Note that hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used as the conductor 242a or the conductor 242b, hydrogen contained in the oxide 230b or the like may easily diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a or the conductor 242b.

[0163] In addition, if Figure 3BAs shown, the conductors 242a and 242b may also adopt a two-layer structure. In this case, the conductor 242a is a laminated film of the conductor 242a1 and the conductor 242a2 on the conductor 242a1, and the conductor 242b is a laminated film of the conductor 242b1 and the conductor 242b2 on the conductor 242b1. At this time, as the layer in contact with the oxide 230b (conductor 242a1 and conductor 242b1), it is preferable to use the above-mentioned conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion. This can suppress the decrease in the conductivity of the conductors 242a and 242b.

[0164] The electrical conductivity of the conductor 242a2 and the conductor 242b2 is preferably higher than that of the conductor 242a1 and the conductor 242b1. For example, the thickness of the conductor 242a2 and the conductor 242b2 is preferably greater than that of the conductor 242a1 and the conductor 242b1. As the conductor 242a2 and the conductor 242b2, a conductor that can be used for the conductor 205b described above can be used. By adopting the above structure, the resistance of the conductors 242a2 and 242b2 can be reduced. As a result, the operating speed of the transistor 200 can be increased.

[0165] For example, tantalum nitride or titanium nitride can be used as the conductor 242 a 1 and the conductor 242 b 1 , and tungsten can be used as the conductor 242 a 2 and the conductor 242 b 2 .

[0166] In addition, in order to suppress the decrease in the conductivity of the conductors 242a and 242b, a crystalline oxide such as CAAC-OS is preferably used as the oxide 230b. In particular, it is preferred to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. When CAAC-OS is used, it is possible to suppress the conductor 242a or the conductor 242b from extracting oxygen from the oxide 230b. In addition, it is possible to suppress the decrease in the conductivity of the conductors 242a and 242b.

[0167] As described above, the insulator 271a and the insulator 271b are inorganic insulators that protect the conductor 242a and the conductor 242b and serve as an etching stop layer when removing the inorganic film 276. In addition, since the insulator 271a and the insulator 271b are in contact with the conductor 242a and the conductor 242b, it is preferable that an inorganic insulator that does not easily oxidize the conductors 242a and 242b is used. Therefore, it is preferable that the insulator 271a has a stacked structure of the insulator 271a1 and the insulator 271a2 on the insulator 271a1, and the insulator 271b has a stacked structure of the insulator 271b1 and the insulator 271b2 on the insulator 271b1. Here, the insulators 271a1 and 271b1 preferably use a nitride insulator that can be used for the insulator 250c so as not to oxidize the conductors 242a and 242b. In addition, in order to function as an etching stopper when removing the inorganic film 276 as described above, the insulators 271a2 and 271b2 preferably use an oxide insulator that can be used for the insulator 250b.

[0168] Here, the insulator 271a1 is in contact with the top surface of the conductor 242a and a part of the insulator 275, and the insulator 271b1 is in contact with the top surface of the conductor 242b and a part of the insulator 275. In addition, the insulator 271a2 is in contact with the top surface of the insulator 271a1 and the bottom surface of the insulator 275, and the insulator 271b2 is in contact with the top surface of the insulator 271b1 and the bottom surface of the insulator 275. For example, silicon nitride can be used as the insulator 271a1 and the insulator 271b1, and silicon oxide can be used as the insulator 271a2 and the insulator 271b2.

[0169] As described above, the insulator 271, which will later become the insulator 271a and the insulator 271b, is used as a mask for the conductor 242, so the conductor 242 does not have a curved surface between the side surface and the top surface. Therefore, the ends where the side surfaces of the conductor 242a and the conductor 242b intersect with the top surface become angular. When the ends where the side surfaces of the conductor 242 intersect with the top surface become angular, the cross-sectional area of ​​the conductor 242 increases compared to the case where the ends have a curved surface. Furthermore, by using a nitride insulator that is not easy to oxidize metal as the insulators 271a1 and 271b1, it is possible to prevent the conductor 242 from being excessively oxidized. As a result, when the above-mentioned laminate is used in a transistor, the resistance of the conductor 242 is reduced, so the on-state current of the transistor can be increased.

[0170] like Figure 3A and Figure 4AAs shown, the conductor 260 is arranged in the opening formed in the insulator 280 and the insulator 275. In the opening, the conductor 260 is provided so as to cover the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, and the top surface of the oxide 230b via the insulator 250. In addition, the top surface of the conductor 260 is arranged so as to be substantially equal to the height of the uppermost portion of the insulator 250 and the top surface of the insulator 280.

[0171] In the opening portion provided in the insulator 280 etc. where the conductor 260 and the insulator 250 are arranged, the side wall of the opening portion may be substantially perpendicular to the top surface of the insulator 222, or may have a tapered shape. When the side wall has a tapered shape, the coverage of the insulator 250 etc. provided in the opening portion of the insulator 280 can be improved, thereby reducing defects such as voids.

[0172] The conductor 260 is used as a first gate electrode of the transistor 200. Figure 2B , Figure 4A and Figure 4B As shown in FIG. 1 , the conductor 260 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 260 can be used as wiring when a plurality of transistors are arranged.

[0173] In the case of adopting the above structure, if Figure 4A and Figure 4B As shown, when viewed from a cross section in the channel width direction of the transistor 200, a curved surface may be provided between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0174] The curvature radius of the curved surface is preferably greater than 0 nm and less than the thickness of the oxide 230 b in the region overlapping with the conductor 242 or less than half the length of the region without the curved surface. Specifically, the curvature radius of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By adopting the above shape, the coverage of the insulator 250 and the conductor 260 to the oxide 230 b can be improved.

[0175] In this specification, etc., a transistor structure in which a channel forming region is surrounded by an electric field of at least a first gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. is different from a Fin-type structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can be regarded as a type of Fin-type structure. In addition, in this specification, etc., a Fin-type structure refers to a structure in which a gate electrode is configured in a manner that surrounds at least two or more surfaces of a channel (specifically, two surfaces, three surfaces, or four surfaces, etc.). By adopting a Fin-type structure and an S-channel structure, resistance to short channel effects can be improved, in other words, a transistor that is not prone to short channel effects can be realized.

[0176] By adopting the above-mentioned S-channel structure as transistor 200, the channel formation region can be electrically surrounded. The S-channel structure is a structure that electrically surrounds the channel formation region, so it can also be said that the structure is substantially the same as the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate All Around: lateral full surround gate) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be set in the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor or the field effect mobility of the transistor can be improved.

[0177] As described above, this embodiment adopts a structure in which the insulator 224 is provided in an island shape. Figure 4A and Figure 4B As shown, at least a portion of the bottom surface of the conductor 260 can be disposed below the bottom surface of the oxide 230b. Thus, the conductor 260 can be disposed in a manner opposite to the top surface and the side surface of the oxide 230b, so that the electric field of the conductor 260 can act on the top surface and the side surface of the oxide 230b. In this way, by adopting a structure in which the insulator 224 is disposed in an island shape, the transistor 200 can have an S-channel structure.

[0178] Note that as Figure 4A and Figure 4B The transistor 200 shown is an S-channel structure transistor, but the semiconductor device of one embodiment of the present invention is not limited thereto. For example, as a structure of a transistor that can be used in one embodiment of the present invention, any one or more selected from a planar structure, a Fin structure, and a GAA structure can also be used.

[0179] exist Figure 2B In the embodiment, the conductor 260 has a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surface of the conductor 260b. At this time, as the conductor 260a, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion.

[0180] As the conductor 260a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0181] In addition, when the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 280. As a conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. can be used.

[0182] In addition, the conductor 260b preferably uses a conductor with high conductivity. For example, the conductor 260b can use a conductive material with tungsten, copper or aluminum as a main component. In addition, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials.

[0183] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably arranged in a region between the conductor 242a and the conductor 242b without alignment.

[0184] The dielectric constant of each of the insulator 216 and the insulator 280 is preferably lower than that of the insulator 214. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0185] For example, the insulator 216 and the insulator 280 preferably include one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores.

[0186] In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, silicon oxide, silicon oxynitride, silicon oxide having pores and the like are preferred because they easily form a region containing oxygen released by heating.

[0187] In addition, the top surfaces of the insulator 216 and the insulator 280 may also be planarized.

[0188] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, an oxide containing silicon, such as silicon oxide or silicon oxynitride, is preferably used as the insulator 280 .

[0189] <Materials Constituting Semiconductor Devices> The constituent materials that can be used for the semiconductor device are described below. Note that each layer constituting the semiconductor device may have a single-layer structure or a stacked-layer structure.

[0190] <<Substrate>> As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.) and a resin substrate can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate can also be cited, such as an SOI (Silicon On Insulator: Silicon on Insulator) substrate. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate can be cited. In addition, as a substrate, for example, a substrate containing a metal nitride, a substrate containing a metal oxide, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator can be cited. Alternatively, a substrate having one or more elements provided on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0191] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0192] For example, when miniaturization and high integration of transistors are being carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0193] Examples of insulators having a relatively high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0194] Examples of insulators having a relatively low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and resins.

[0195] In addition, by surrounding a transistor using a metal oxide with an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, a single layer or stack of an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium and tantalum can be used. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be cited.

[0196] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with oxide 230, oxygen vacancies contained in oxide 230 can be filled.

[0197] <<Conductor>> As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Alternatively, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

[0198] In the case of using a conductor with a stacked structure, for example, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen, or a stacked structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0199] In addition, when an oxide is used in the channel formation region of the transistor, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen is preferably used as a conductor used as a gate electrode. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0200] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide in which a channel is formed can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0201] <<Metal Oxides>> A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Next, a metal oxide that can be used for the oxide 230 according to one embodiment of the present invention will be described.

[0202] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it preferably contains aluminum, gallium, yttrium, tin, antimony, etc. In addition, it may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0203] Here, the case where the metal oxide is an In-M-Zn oxide containing indium, element M and zinc is considered. Note that element M is aluminum, gallium, yttrium, tin or antimony. Other elements that can be applied to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. Note that as element M, multiple of the above elements can sometimes be combined. In particular, element M is preferably selected from one or more of gallium, aluminum, yttrium and tin.

[0204] In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0205] Hereinafter, In—Ga—Zn oxide will be described as an example of the metal oxide.

[0206] Examples of the crystalline structure of an oxide semiconductor include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal.

[0207] In addition, when focusing on the structure of oxide semiconductors, the classification of oxide semiconductors is sometimes different from the above. For example, oxide semiconductors can be classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors other than single-crystal oxide semiconductors. As non-single-crystal oxide semiconductors, for example, the above-mentioned CAAC-OS and nc-OS can be cited. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

[0208] Here, the details of the above-mentioned CAAC-OS, nc-OS and a-like OS are explained.

[0209] [CAAC-OS] CAAC-OS is an oxide semiconductor including a plurality of crystalline regions, wherein the c-axis of the plurality of crystalline regions is oriented in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. In addition, the crystalline region is a region having a periodic atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region having a consistent lattice arrangement. Furthermore, CAAC-OS has a region where a plurality of crystalline regions are connected in the ab plane direction, and sometimes the region has distortion. In addition, distortion refers to a portion where the direction of the lattice arrangement changes between a region having a consistent lattice arrangement and other regions having a consistent lattice arrangement in a region where a plurality of crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor having a c-axis orientation and having no obvious orientation in the ab plane direction.

[0210] In addition, each of the above-mentioned multiple crystallization regions is composed of one or more tiny crystals (crystallizations with a maximum diameter less than 10 nm). In the case where a crystallization region is composed of one tiny crystal, the maximum diameter of the crystallization region is less than 10 nm. In addition, in the case where a crystallization region is composed of multiple tiny crystals, the maximum diameter of the crystallization region is sometimes about tens of nm.

[0211] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that in CAAC-OS, the reduction in electron mobility caused by grain boundaries is not easy to occur. In addition, the crystallinity of the oxide semiconductor is sometimes reduced due to the mixing of impurities or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, the oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called heat accumulation) in the manufacturing process. Therefore, by using CAAC-OS in the OS transistor, the degree of freedom of the manufacturing process can be expanded.

[0212] [nc-OS] In nc-OS, the atomic arrangement in a tiny region (e.g., a region of more than 1 nm and less than 10 nm, especially a region of more than 1 nm and less than 3 nm) is periodic. In other words, nc-OS has tiny crystals. In addition, for example, the size of the tiny crystal is more than 1 nm and less than 10 nm, especially more than 1 nm and less than 3 nm, and the tiny crystal is called a nanocrystal. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductor in certain analysis methods.

[0213] [a-like OS] A-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductor. A-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. In addition, the hydrogen concentration in the film of a-like OS is higher than that in the film of nc-OS and CAAC-OS.

[0214] Next, the details of the above-mentioned CAC-OS will be described. In addition, CAC-OS is related to the material composition.

[0215] [CAC-OS] CAC-OS refers to, for example, a structure in which elements contained in a metal oxide are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size. Note that in the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed is also referred to as a mosaic or patch shape, and the size of the region is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size.

[0216] Furthermore, CAC-OS refers to a composite metal oxide having a structure in which the material is divided into a first region and a second region to form a mosaic shape and the first region is distributed in the film (hereinafter also referred to as a cloud shape). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

[0217] In addition, CAC-OS in In-Ga-Zn oxide refers to a structure in which a region (first region) in which a part of the main component is In and a region (second region) in which a part of the main component is Ga exist irregularly in a mosaic shape in a material composition containing In, Ga, Zn, and O. Therefore, it can be inferred that CAC-OS has a structure in which metal elements are unevenly distributed.

[0218] CAC-OS can be formed, for example, by sputtering without heating the substrate. When CAC-OS is formed by sputtering, as the deposition gas, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition is made greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0219] Here, the first region is a region having higher conductivity than the second region. That is, when carriers flow through the first region, the conductivity as a metal oxide is exhibited. Therefore, when the first region is distributed in the metal oxide in a cloud-like manner, a high field effect mobility (μ) can be achieved.

[0220] On the other hand, the second region is a region having higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

[0221] Thus, when CAC-OS is used for a transistor, the complementary effect of the conductivity of the first region and the insulation of the second region can give CAC-OS a switch function (a function of controlling on / off). In other words, a portion of the CAC-OS material has a conductive function and another portion has an insulating function, and the entire material has a semiconductor function. By separating the conductive function and the insulating function, each function can be maximized. Therefore, by using CAC-OS for a transistor, a large on-state current (I on ), high field effect mobility (μ) and good switching performance.

[0222] In addition, transistors using CAC-OS have high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices such as display devices.

[0223] Oxide semiconductors have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0224] <<Other semiconductor materials>> As the semiconductor layer of the transistor, a semiconductor material having a band gap (a semiconductor material that is not a zero-band gap semiconductor) may be used. For example, a semiconductor of a single element such as silicon or a compound semiconductor such as gallium arsenide may be used.

[0225] In addition, as the semiconductor layer of the transistor, for example, a transition metal chalcogenide that is used as a semiconductor is preferably used. As the transition metal chalcogenide that can be used as the semiconductor layer of the transistor, molybdenum sulfide (typically MoS 2 ), Molybdenum selenide (typically MoSe 2 ), molybdenum telluride (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten telluride (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (typically ZrSe 2 ) etc. By using the above transition metal chalcogenide in a semiconductor layer of a transistor, a semiconductor device having a large on-state current can be provided.

[0226] <Example of Method for Manufacturing Semiconductor Device> use FIG. 5A to FIG. 11D An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention is described. FIG. 2A to FIG. 2D The case of the semiconductor device shown in FIG. 1 is described as an example.

[0227] A in each figure is a plan view. In addition, B in each figure is a cross-sectional view of a portion along the dot-dash line A1-A2 in A, which is equivalent to a cross-sectional view in the channel length direction of the transistor 200. C in each figure is a cross-sectional view of a portion along the dot-dash line A3-A4 in A, which is equivalent to a cross-sectional view in the channel width direction of the transistor 200. In addition, D in each figure is a cross-sectional view of a portion along the dot-dash line A5-A6 in A, which is equivalent to a cross-sectional view in the channel width direction of the transistor 200. For the sake of clarity, some components are omitted in the plan view of A in each figure.

[0228] Hereinafter, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors may be appropriately deposited using sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, or the like.

[0229] As the sputtering method, there can be cited an RF sputtering method using a high frequency power supply as a sputtering power supply, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing insulating films, and the DC sputtering method is mainly used when depositing metal conductive films. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0230] Note that the CVD method can be divided into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, and a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0231] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used, the thermal CVD method is a deposition method that can reduce plasma damage to the object being processed. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation due to receiving charges from plasma. At this time, the wiring, electrodes, components, etc. included in the semiconductor device are sometimes damaged due to the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur in the case of the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during deposition is not generated, so a film with fewer defects can be obtained.

[0232] As the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD method using a reactant excited by plasma, or the like is used.

[0233] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material or the like are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to use it in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0234] In addition, when the CVD method is used, a film of any composition can be deposited by adjusting the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while depositing. When depositing while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0235] When the ALD method is used, a film of any composition can be deposited by introducing different precursors at the same time. Alternatively, when introducing different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0236] First, a substrate (not shown) is prepared, and an insulator 215 is deposited on the substrate (see FIG. 5A to FIG. 5D). As described above, the insulator 215 may use the same insulator as the laminated film of any one or more of the insulators 224, the insulator 282, and the insulator 283. For example, the insulator 215 may be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 215 can be reduced, so it is preferred.

[0237] Next, an insulator 216 is deposited on the insulator 215. The insulator 216 is preferably deposited by sputtering. By using a sputtering method that does not require the use of molecules containing hydrogen for the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. Note that the deposition method of the insulator 216 is not limited to the sputtering method, and for example, a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.

[0238] In this embodiment, silicon oxide is deposited by pulse DC sputtering using a silicon target in an atmosphere containing oxygen as the insulator 216. By using the pulse DC sputtering method, the thickness distribution can be made more uniform, thereby improving the sputtering rate and film quality.

[0239] The insulator 215 and the insulator 216 are preferably deposited continuously without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. Thus, the insulator 215 and the insulator 216 can be deposited while reducing hydrogen in the film, and the mixing of hydrogen into the film between each deposition step can be reduced.

[0240] Next, an opening reaching the insulator 215 is formed in the insulator 216. When forming the opening, wet etching can be used, but dry etching is preferred for micro-machining. As the insulator 215, it is preferable to select an insulator that is used as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxide or silicon oxynitride is used as the insulator 216 for forming the groove, silicon nitride, aluminum oxide, or hafnium oxide is preferably used as the insulator 215.

[0241] After the opening is formed, a conductive film to be the conductor 205a is deposited. The conductive film to be the conductor 205a preferably includes a conductor having a function of inhibiting the transmission of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used as the conductive film. In addition, the conductive film can use a laminated film of a conductor having a function of inhibiting the transmission of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film to be the conductor 205a can be deposited, for example, by sputtering, CVD, MBE, PLD, ALD, or the like.

[0242] In this embodiment, titanium nitride is formed as a conductive film used as the conductor 205a. By using the above-mentioned metal nitride as the lower layer of the conductor 205b, it is possible to suppress the conductor 205b from being oxidized by the insulator 216. In addition, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing outward from the conductor 205a.

[0243] Next, a conductive film to be the conductor 205b is deposited. As the conductive film to be the conductor 205b, for example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film can be deposited by, for example, a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, tungsten is deposited as the conductive film to be the conductor 205b.

[0244] Next, a CMP treatment is performed to remove a portion of the conductive film to be the conductor 205a and the conductive film to be the conductor 205b, thereby exposing the insulator 216 (see FIG. 214 ). FIG. 5A to FIG. 5D ). As a result, the conductor 205a and the conductor 205b remain only in the opening. Note that part of the insulator 216 may be removed by the CMP process.

[0245] Next, an insulator 222 is deposited on the insulator 216 and the conductor 205 (see FIG. 6A to FIG. 6D ).

[0246] As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. As the insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. Alternatively, hafnium zirconium oxide is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. When the insulator 222 has a barrier property to hydrogen and water, the hydrogen and water contained in the structure surrounding the transistor can be suppressed from diffusing into the inside of the transistor through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0247] Alternatively, the insulator 222 may be a stacked film of an insulator including an oxide of one or both of aluminum and hafnium, and silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide.

[0248] The insulator 222 can be deposited by, for example, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, hafnium oxide is deposited by ALD as the insulator 222. Alternatively, a stack of silicon nitride deposited by PEALD and hafnium oxide deposited by ALD can be used as the insulator 222.

[0249] Next, an insulating film 224f is deposited on the insulator 222 (see FIG. 6A to FIG. 6D ). As the insulating film 224f, an insulator corresponding to the above-mentioned insulator 224 can be used.

[0250] The insulating film 224f can be deposited by, for example, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is deposited by sputtering as the insulating film 224f. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. The insulating film 224f is in contact with the oxide 230a in a subsequent process, so it is preferable that the hydrogen concentration is reduced as described above.

[0251] In addition, heat treatment may be performed before depositing the insulating film 224f. The heat treatment may be performed under reduced pressure, and the insulating film 224f may be continuously deposited without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen attached to the surface of the insulator 222 may be removed, and the moisture concentration and hydrogen concentration in the insulator 222 may be reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is set to 250° C.

[0252] Next, an oxide film 230af is deposited on the insulating film 224f, and an oxide film 230bf is deposited on the oxide film 230af (see FIG. 6A to FIG. 6D ). As the oxide film 230af, a metal oxide corresponding to the above-mentioned oxide 230a can be used, and as the oxide film 230bf, a metal oxide corresponding to the above-mentioned oxide 230b can be used. It is preferable to continuously deposit the oxide film 230af and the oxide film 230bf without exposing them to the atmospheric environment. By depositing the oxide film without exposing them to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230af and the oxide film 230bf, so that the vicinity of the interface between the oxide film 230af and the oxide film 230bf can be kept clean.

[0253] The oxide film 230af and the oxide film 230bf can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. In the present embodiment, sputtering is used as a method for depositing the oxide film 230af and the oxide film 230bf.

[0254] For example, when the oxide film 230af and the oxide film 230bf are deposited by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. In addition, when the above-mentioned oxide film is deposited by sputtering, an In-M-Zn oxide target or the like can be used.

[0255] In particular, when the oxide film 230af is deposited, part of the oxygen contained in the sputtering gas may be supplied to the insulating film 224f. Therefore, the ratio of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and further preferably 100%.

[0256] In the case of forming the oxide film 230bf by sputtering, an oxygen-excess oxide semiconductor can be formed by depositing under the condition that the ratio of oxygen contained in the sputtering gas is greater than 30% and less than 100%, preferably greater than 70% and less than 100%. A transistor using an oxygen-excess oxide semiconductor in a channel formation region can obtain relatively high reliability. Note that one embodiment of the present invention is not limited to this. In the case of forming the oxide film 230bf by sputtering, an oxygen-deficient oxide semiconductor is formed when deposition is performed under the condition that the ratio of oxygen contained in the sputtering gas is set to greater than 1% and less than 30%, preferably greater than 5% and less than 20%. A transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have a higher field effect mobility. In addition, by depositing while heating the substrate, the crystallinity of the oxide film can be improved.

[0257] In this embodiment, the oxide film 230af is deposited by sputtering using an oxide target of In:Ga:Zn=1:3:2 [atomic ratio] or an oxide target of In:Ga:Zn=1:3:4 [atomic ratio]. In addition, the oxide film 230bf is deposited by sputtering using an oxide target of In:Ga:Zn=1:1:1 [atomic ratio], an oxide target of In:Ga:Zn=1:1:1.2 [atomic ratio], an oxide target of In:Ga:Zn=4:2:4.1 [atomic ratio] or an oxide target of In:Ga:Zn=1:1:2 [atomic ratio]. Each oxide film is preferably formed by appropriately selecting deposition conditions and atomic ratios according to the characteristics required for the oxide 230a and the oxide 230b.

[0258] Note that the insulating film 224f, the oxide film 230af, and the oxide film 230bf are preferably deposited by sputtering without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. Thus, mixing of hydrogen into the insulating film 224f, the oxide film 230af, and the oxide film 230bf between each deposition step can be reduced.

[0259] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range where polycrystallization does not occur in the oxide film 230af and the oxide film 230bf. The heat treatment temperature is preferably 100°C or higher, 250°C or higher, or 350°C or higher and 650°C or lower, 600°C or lower, or 550°C or lower.

[0260] The heat treatment is carried out in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10%. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of the oxygen gas is preferably set to about 20%. The heat treatment can also be carried out under reduced pressure. Alternatively, the heat treatment can also be carried out in a nitrogen gas or inert gas atmosphere, and then the heat treatment is carried out in an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10% to fill the oxygen that has been separated.

[0261] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By using highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the oxide film 230af and the oxide film 230bf as much as possible.

[0262] In this embodiment, as a heat treatment, a treatment is performed for 1 hour under the conditions of a flow ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 450°C. Such a heat treatment containing oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf. By reducing the impurities in the film in this way, the crystallinity of the oxide film 230bf is improved, and a denser structure with a higher density can be achieved. Therefore, the crystallized area in the oxide film 230af and the oxide film 230bf can be increased, and the in-plane unevenness of the crystallized area in the oxide film 230af and the oxide film 230bf can be reduced. Therefore, the in-plane unevenness of the electrical characteristics of the transistor can be reduced.

[0263] In addition, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf is transferred to the insulator 222 and absorbed by the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf is diffused into the insulator 222. Therefore, although the hydrogen concentration in the insulator 222 increases, the hydrogen concentration in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf decreases.

[0264] In particular, the insulating film 224f (later insulator 224) is used as a second gate insulator of the transistor 200, and the oxide film 230af and the oxide film 230bf (later oxide 230a and oxide 230b) are used as a channel formation region of the transistor 200. The transistor 200 including the insulating film 224f, the oxide film 230af, and the oxide film 230bf in which the hydrogen concentration is reduced has excellent reliability and is therefore preferred.

[0265] Next, a conductive film 242f is deposited on the oxide film 230bf (see FIG. 6A to FIG. 6D As the conductive film 242f, a conductive material corresponding to the conductive material 242 described above can be used. After the oxide film 230bf is deposited, the conductive film 242f is deposited on and in contact with the oxide film 230bf without an etching step or the like, so that the top surface of the oxide film 230bf can be protected by the conductive film 242f. Thus, since the diffusion of impurities into the oxide 230 constituting the transistor can be reduced, the electrical characteristics and reliability of the semiconductor device can be improved.

[0266] The conductive film 242f can be deposited by sputtering, CVD, MBE, PLD, electroplating, or ALD.

[0267] In this embodiment, tantalum nitride is deposited as the conductive film 242f by sputtering. In addition, heat treatment may be performed before depositing the conductive film 242f. The heat treatment may also be performed under reduced pressure, and the conductive film 242f is continuously deposited without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably above 100°C and below 400°C. In this embodiment, the temperature of the heat treatment is set to 250°C.

[0268] The conductive film 242f may also be a laminated film. Figure 3B As shown in FIG. 1 , when a stacked structure of conductors 242a1 and 242b1 and conductors 242a2 and 242b2 is adopted, tantalum nitride may be deposited as the conductive film 242f by sputtering, and tungsten may be deposited thereon by sputtering.

[0269] Next, an insulating film 271_1f is deposited on the conductive film 242f, and an insulating film 271_2f is deposited thereon (see FIG. 6A to FIG. 6D ). As the insulating film 271_1f, an insulator corresponding to the insulator 271_1 can be used, and as the insulating film 271_2f, an insulator corresponding to the insulator 271_2 can be used. Here, by using an insulating film having a function of inhibiting oxygen permeation as the insulating film 271_1f as described above, oxidation of the conductive film 242f can be inhibited in the subsequent process.

[0270] The insulating film 271_1f and the insulating film 271_2f may be deposited by sputtering, CVD, MBE, PLD, ALD, etc. For example, a silicon nitride film may be deposited by sputtering as the insulating film 271_1f and a silicon oxide film may be deposited by sputtering as the insulating film 271_2f.

[0271] Here, the insulating film 271_1f and the insulating film 271_2f are continuously deposited without being exposed to the atmosphere. By performing the deposition without being exposed to the atmosphere, impurities or moisture from the atmosphere can be prevented from being attached to the insulating film 271_1f and the insulating film 271_2f, thereby keeping the vicinity of the interface between the insulating film 271_1f and the insulating film 271_2f clean. In addition, it is more preferable to continuously deposit the conductive film 242f to the insulating film 271_2f without being exposed to the atmosphere.

[0272] In addition, heat treatment may be performed before the insulating film 271_1f and the insulating film 271_2f are deposited. The heat treatment may also be performed under reduced pressure, wherein the insulating film 271_1f and the insulating film 271_2f are continuously deposited without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen attached to the surface of the conductive film 242f can be removed, and the moisture concentration and hydrogen concentration in the conductive film 242f can be reduced. The temperature of the heat treatment is preferably not less than 100° C. and not more than 400° C. In this embodiment, the temperature of the heat treatment is set to 250° C.

[0273] Next, the insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242f, the insulating film 271_1f, and the insulating film 271_2f are processed into island shapes by photolithography to form the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, the insulator 271_1, and the insulator 271_2 (see FIG. 7A to FIG. 7D The insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242f, the insulating film 271_1f, and the insulating film 271_2f may be processed according to the above Figures 1B to 1F The method described was carried out.

[0274] By processing by the method described in <Example of Processing Method of Laminated Body>, an island-shaped laminated body can be formed in which the side surface of the conductor 242 does not excessively recede from the side surface of the oxide 230, in other words, the side end of the conductor 242 is roughly aligned with the side end of the oxide 230. By manufacturing the transistor 200 using such a laminated body having a microstructure, miniaturization and high integration of semiconductor devices can be achieved.

[0275] In addition, it is preferred that the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, the insulator 271_1, and the insulator 271_2 are processed into an island shape at one time. At this time, the side end of the conductor 242 is preferably roughly aligned with the side end of the oxide 230a and the side end of the oxide 230b. Furthermore, the side end of the insulator 224 is preferably roughly aligned with the side end of the oxide 230. In addition, the side end of the insulator 271 is preferably roughly aligned with the side end of the conductor 242. By adopting the above structure, the number of steps of a semiconductor device according to one embodiment of the present invention can be reduced. Thus, a method for manufacturing a semiconductor device with good productivity can be provided.

[0276] At least a portion of the insulator 224, oxide 230a, oxide 230b, conductor 242, and insulator 271_1 are formed to overlap with the conductor 205. In addition, the insulator 222 is exposed in a region that does not overlap with the insulator 224, oxide 230a, oxide 230b, conductor 242, insulator 271_1, and insulator 271_2.

[0277] In addition, in the process of removing the inorganic film 276, the insulator 271 is used as a mask for the conductor 242, so the conductor 242 does not have a curved surface between the side and the top surface. As a result, the ends of the conductors 242a and 242b formed later, where the side and the top surface intersect, become angled. When the ends where the side and the top surface of the conductor 242 intersect become angled, the cross-sectional area of ​​the conductor 242 increases compared to the case where the ends have a curved surface. Furthermore, by using a nitride insulator that is not easy to oxidize metal as the insulator 271_1, the conductor 242 can be prevented from being over-oxidized. As a result, the resistance of the conductor 242 is reduced, so the on-state current of the transistor can be increased.

[0278] In addition, by processing the insulator 224 into an island shape, the insulator 275 can be provided in contact with the side surface of the insulator 224 and the top surface of the insulator 222. That is, the insulator 224 and the insulator 280 can be separated by the insulator 275. With such a structure, it is possible to prevent an excessive amount of impurities such as oxygen and hydrogen from being mixed into the oxide 230 through the insulator 224 from the insulator 280.

[0279] In addition, by processing the insulator 224 into an island shape, when a plurality of transistors 200 are provided, the insulator 224 of substantially the same size is provided in each transistor 200. Therefore, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 is substantially equal. Thus, the electrical characteristics of the transistor 200 in the substrate surface can be suppressed from being uneven. Note that the present invention is not limited to this, and a structure in which the pattern of the insulator 224 is not formed similarly to the insulator 222 may be adopted.

[0280] In addition, if FIG. 7B to FIG. 7D As shown, the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, the insulator 271_1, and the insulator 271_2 may also have a tapered shape. The taper angle of the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, the insulator 271_1, and the insulator 271_2 may also be, for example, 60° or more and less than 90°. In this way, by having the side surfaces have a tapered shape, the coverage of the insulator 275 and the like is improved in the subsequent process, and defects such as voids can be reduced.

[0281] The present invention is not limited to this, and the side surfaces of the insulator 224, oxide 230a, oxide 230b, conductor 242, insulator 271_1, and insulator 271_2 may be substantially perpendicular to the top surface of the insulator 222. With such a structure, a small area and high density can be achieved when a plurality of transistors are provided.

[0282] Next, an insulator 275 is deposited to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, the insulator 271_1, and the insulator 271_2, and then an insulator 280 is deposited over the insulator 275. As the insulator 275 and the insulator 280, the above-described insulators can be used.

[0283] Here, the insulator 275 is preferably in contact with the top surface of the insulator 222 .

[0284] As insulator 280, it is preferable to form an insulator with a flat top surface by forming an insulating film to be insulator 280 and then subjecting the insulating film to CMP. Alternatively, silicon nitride may be deposited on insulator 280 by, for example, sputtering and then subjected to CMP until the silicon nitride reaches insulator 280.

[0285] The insulator 275 and the insulator 280 can each be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0286] The insulator 275 preferably uses an insulator that has a function of inhibiting oxygen transmission. For example, silicon nitride is preferably deposited by the PEALD method as the insulator 275. In addition, aluminum oxide is preferably deposited by the sputtering method as the insulator 275, and silicon nitride is deposited thereon by the PEALD method. When the insulator 275 has the above structure, the function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen can be improved.

[0287] Thus, the oxide 230a, the oxide 230b, and the conductor 242 can be covered by the insulator 275 having the function of suppressing oxygen diffusion. Thus, direct diffusion of oxygen from the insulator 280 and the like into the insulator 224, the oxide 230a, the oxide 230b, and the conductor 242 in a subsequent step can be reduced.

[0288] In addition, silicon oxide is preferably deposited by sputtering as the insulator 280. By depositing the insulating film to be the insulator 280 by sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In addition, heat treatment can also be performed before depositing the insulating film. The heat treatment can also be performed under reduced pressure, and the insulating film is continuously deposited without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the insulator 275 can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b and the insulator 224 can be reduced. The heat treatment can adopt the conditions of the above-mentioned heat treatment.

[0289] Next, the conductor 242, the insulator 271_1, the insulator 271_2, the insulator 275, and the insulator 280 are processed by photolithography to form an opening reaching the oxide 230b (see FIG. 8A to FIG. 8D ). The opening reaching the oxide 230 b is provided in a region where the oxide 230 b and the conductor 205 overlap.

[0290] The above processing can be performed by dry etching or wet etching. Processing by dry etching is suitable for micro-processing. In addition, the processing of the conductor 242, the insulator 271_1, the insulator 271_2, the insulator 275 and the insulator 280 can also be performed under different conditions. In particular, when the conductor 242 is processed by dry etching, it is preferred to use an ICP etching device. In this case, it is preferred to apply a bias power to increase the etching rate of the conductor 242 for etching.

[0291] Through this processing, the conductor 242 is divided into island-shaped conductors 242a and 242b. Similarly, the insulator 271_1 is divided into island-shaped insulators 271a1 and 271b1. Similarly, the insulator 271_2 is divided into island-shaped insulators 271a2 and 271b2.

[0292] The width of the opening is preferably small because it is reflected in the channel length of the transistor 200. For example, the width of the opening is preferably less than 60 nm, less than 50 nm, less than 40 nm, less than 30 nm, less than 20 nm, or less than 10 nm and more than 1 nm or more than 5 nm. In this way, in order to process the opening into a micronized size, it is preferred to use a photolithography method using short-wavelength light such as EUV light or an electron beam.

[0293] Through the above-mentioned etching process, the following may occur: impurities are attached to the side surface of oxide 230a, the top surface and side surface of oxide 230b, the side surface of conductors 242a and 242b, the side surface of insulators 271a and 271b, the side surface of insulator 275, and the side surface of insulator 280; or the impurities diffuse into them. A process of removing these impurities may be performed. In addition, a damaged area may be formed on the surface of oxide 230b due to the above-mentioned dry etching. In addition, such a damaged area may also be removed. As examples of such impurities, there may be mentioned impurities caused by the following components: components contained in insulator 280, insulator 275, insulators 271a and 271b, and conductors 242a and 242b; components contained in the components of the device used when forming the above-mentioned opening; and components contained in the gas or liquid used for etching. As examples of such impurities, there may be mentioned hafnium, aluminum, silicon, tantalum, fluorine, chlorine, and the like.

[0294] In particular, impurities such as aluminum and silicon sometimes reduce the crystallinity of oxide 230b. Therefore, impurities such as aluminum and silicon are preferably removed from the surface of oxide 230b and its vicinity. In addition, it is preferred to reduce the impurity concentration. For example, the concentration of aluminum atoms on the surface of oxide 230b and its vicinity is preferably 5.0 atomic % or less, more preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, further preferably 1.0 atomic % or less, and particularly preferably less than 0.3 atomic %.

[0295] Due to impurities such as aluminum and silicon, the density of the crystal structure is reduced in the low crystallinity region of the oxide 230b, so a large amount of V O H makes the transistor easily normally-on. Therefore, it is preferable to reduce or remove the region with low crystallinity in the oxide 230b.

[0296] In contrast, the oxide 230b preferably has a layered CAAC structure. In particular, it is preferred that the lower end of the drain of the oxide 230b also has a CAAC structure. Here, in the transistor, the conductor 242a or the conductor 242b is preferably used as a drain. In other words, the oxide 230b near the lower end of the conductor 242a or the conductor 242b preferably has a CAAC structure. In this way, by removing the low-crystallinity region of the oxide 230b at the drain end that has a significant impact on the drain withstand voltage and making it have a CAAC structure, the variation of the electrical characteristics of the transistor can be further suppressed. In addition, the reliability of the transistor can be further improved.

[0297] In order to remove impurities and the like attached to the surface of the oxide 230b in the above-mentioned etching process, a cleaning process is performed. As a cleaning method, there are wet cleaning using a cleaning solution or the like (which may also be referred to as a wet etching process), plasma treatment using plasma, cleaning using a heat treatment, etc., and the above-mentioned cleanings may be appropriately combined. Note that the above-mentioned groove may become deeper by performing this cleaning process.

[0298] As wet cleaning, an aqueous solution, pure water or carbonated water etc. formed by diluting one or more of ammonia, oxalic acid, phosphoric acid or hydrofluoric acid with carbonated water or pure water can be used. Alternatively, ultrasonic cleaning can be performed using the above aqueous solution, pure water or carbonated water. In addition, the above cleaning can also be appropriately combined.

[0299] Note that in this specification, etc., an aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of ammonia water diluted with pure water is sometimes referred to as dilute ammonia water. In addition, the concentration, temperature, etc. of the aqueous solution can be appropriately adjusted according to the impurities to be removed, the structure of the semiconductor device to be washed, etc. The ammonia concentration of the dilute ammonia water is preferably set to 0.01% or more and 5% or less, and more preferably set to 0.1% or more and 0.5% or less. In addition, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01ppm or more and 100ppm or less, and more preferably set to 0.1ppm or more and 10ppm or less.

[0300] In addition, it is preferable to use a frequency of 200 kHz or higher, and more preferably a frequency of 900 kHz or higher for ultrasonic cleaning. By using such a frequency, damage to the oxide 230 b and the like can be reduced.

[0301] In addition, the above-mentioned washing treatment may be performed multiple times, and the washing liquid may be changed for each washing treatment. For example, the first washing treatment may be a treatment using dilute hydrofluoric acid or dilute ammonia water, and the second washing treatment may be a treatment using pure water or carbonated water.

[0302] In this embodiment, the cleaning process is performed by wet cleaning using dilute ammonia water. This cleaning process can remove impurities attached to the surface of the oxide 230a, the oxide 230b, etc. or diffused into the inside thereof. In addition, the crystallinity of the oxide 230b can be improved.

[0303] In addition, heat treatment may be performed after the above-mentioned etching or the above-mentioned washing. The temperature of the heat treatment is preferably above 100°C, above 250°C, or above 350°C and below 650°C, below 600°C, below 550°C, or below 400°C. The heat treatment is performed in an atmosphere of nitrogen gas, inert gas, or an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more. For example, it is preferred to perform the treatment at a flow ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 350°C for 1 hour. Thus, oxygen is supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. In addition, by performing the above-mentioned heat treatment, the crystallinity of the oxide 230b can be improved. Furthermore, the hydrogen remaining in the oxide 230a and the oxide 230b reacts with the supplied oxygen and the hydrogen can be converted into H 2 O is removed (dehydrated). This can prevent the hydrogen remaining in the oxide 230a and the oxide 230b from recombining with oxygen vacancies to form V O H. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an oxygen atmosphere and then continuously in a nitrogen atmosphere without being exposed to the air.

[0304] When heat treatment is performed in a state where the conductor 242a and the conductor 242b are in contact with the oxide 230b, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242a and the oxide 230b in the region overlapping with the conductor 242b may be reduced. In addition, the carrier concentration may be increased. Therefore, the resistance of the oxide 230b in the region overlapping with the conductor 242a and the oxide 230b in the region overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0305] In addition, the above heat treatment may not be performed. Figure 3B As shown in FIG. 1 , when the conductors 242a and 242b have a stacked structure and a tungsten film that is easily oxidized is used as the conductors 242a2 and 242b2, the above heat treatment may not be performed. Thus, the conductors 242a2 and 242b2 can be prevented from being excessively oxidized by the above heat treatment.

[0306] Next, an insulating film 250A (see FIG. 25A ) serving as the insulator 250 is deposited to fill the above-mentioned opening. 9A to 9D). The insulating film 250A can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. The insulator 250 is preferably deposited by the ALD method. The insulating film 250A is preferably formed thin, and the thickness non-uniformity needs to be suppressed to a small value. In this regard, the ALD method is a deposition method that alternately introduces precursors and reactants (for example, oxidants, etc.). Since the thickness of the film can be adjusted according to the number of times the cycle is repeated, the thickness can be precisely adjusted. In addition, the insulator 250 needs to be formed on the bottom and side surfaces of the opening with high coverage. By using the ALD method, since each atomic layer can be deposited on the bottom and side surfaces of the above-mentioned opening, the insulator 250 can be formed in the opening with high coverage.

[0307] When the insulating film 250A is deposited by the ALD method, ozone (O 3 ), oxygen (O 2 ), water (H 2 O), etc. By using ozone (O 3 ), oxygen (O 2 ) etc. as an oxidant, which can reduce the hydrogen diffused into the oxide 230b.

[0308] like Figure 3A and Figure 4A as well as Figure 3B and Figure 4B As shown, the insulator 250 may have a laminated structure. Figure 3A and Figure 4A In the structure shown in FIG. 1 , aluminum oxide can be deposited as an insulating film to be insulator 250a by thermal ALD, silicon oxide can be deposited as an insulating film to be insulator 250b by PEALD, and silicon nitride can be deposited as an insulating film to be insulator 250c by PEALD. Figure 3B and Figure 4B In the structure shown, hafnium oxide is deposited thereon by a thermal ALD method as an insulating film to be the insulator 250d.

[0309] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere. Here, microwave treatment refers to, for example, treatment using a device including a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Note that when the insulator 250 has a laminated structure, the above-mentioned microwave treatment is not necessarily performed after all the insulating films 250A are deposited. For example, when using Figure 3A and Figure 4AIn the case of the structure shown in FIG. 1 , microwave treatment may be performed after depositing the insulating film to be the insulator 250a and the insulating film to be the insulator 250b, and then the insulating film to be the insulator 250c may be deposited. Figure 3B and Figure 4B In the case of the structure shown, microwave treatment may be performed after depositing the insulating film to be the insulator 250a and the insulating film to be the insulator 250b, and then microwave treatment may be performed after depositing the insulating film to be the insulator 250d, and then the insulating film to be the insulator 250c may be deposited. In this way, microwave treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice or more).

[0310] Microwave treatment, for example, preferably uses a microwave processing device including a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device is preferably set to be above 300 MHz and below 300 GHz, more preferably above 2.4 GHz and below 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves in the microwave processing device is preferably above 1000 W and below 10000 W, preferably above 2000 W and below 5000 W. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide 230 b.

[0311] In addition, the microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10Pa or more and 1000Pa or less, more preferably 300Pa or more and 700Pa or less. In addition, the treatment temperature is preferably 750°C or less, more preferably 500°C or less, for example, about 250°C. In addition, it is also possible to continuously perform heat treatment without being exposed to the outside air after the oxygen plasma treatment. The temperature of the heat treatment is, for example, preferably 100°C or more and 750°C or less, more preferably 300°C or more and 500°C or less.

[0312] In addition, for example, the microwave treatment can be performed using oxygen gas and argon gas. 2 / (O 2 +Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O 2 / (O 2 More preferably, the oxygen flow rate ratio (O 2 / (O 2 More preferably, the oxygen flow rate ratio (O 2 / (O2 +Ar)) is 10% or more and 30% or less. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in the oxide 230b can be reduced. In addition, by preventing excessive oxygen from being introduced into the treatment chamber during microwave treatment, the carrier concentration in the oxide 230b can be prevented from being excessively reduced.

[0313] By performing microwave treatment in an oxygen-containing atmosphere, microwaves or high frequencies such as RF can be used to convert oxygen gas into plasma and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. The V O H is separated into oxygen vacancies and hydrogen, and hydrogen is removed from the region. Figure 3A or Figure 3B In the case of the structure shown in FIG. 1 , it is preferable to use an insulating film having a function of capturing and fixing hydrogen (e.g., aluminum oxide) as the insulating film to be the insulator 250a. By adopting the above structure, the insulator 250a can capture or fix hydrogen generated by the microwave treatment. In this way, the V contained in the channel formation region can be reduced. O H. Thus, oxygen vacancies and V O H and thus reduce the carrier concentration. In addition, by supplying oxygen radicals generated in the above oxygen plasma to oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, thereby reducing the carrier concentration.

[0314] As oxygen injected into the channel formation region, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions and oxygen free radicals (also called O free radicals, atoms, molecules or ions containing unpaired electrons). The oxygen injected into the channel formation region can be any one or more of the above forms, and oxygen free radicals are particularly preferred. In addition, since the film quality of the insulator 250 can be improved, the reliability of the transistor is improved.

[0315] On the other hand, the oxide 230b has a region overlapping with any one of the conductors 242a and 242b. This region can be used as a source region or a drain region. Here, the conductors 242a and 242b are preferably used as a shielding film to protect against microwaves, RF and other high frequencies or oxygen plasma when microwave treatment is performed in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0316] The conductors 242a and 242b shield the microwaves, high frequencies such as RF, oxygen plasma, etc., and thus do not act on the region of the oxide 230b that overlaps with any of the conductors 242a and 242b. Thus, the microwave treatment does not cause V to occur in the source region and the drain region. O The decrease in H and the supply of excessive oxygen can prevent the decrease in carrier concentration.

[0317] In addition, an insulator 250 having oxygen barrier properties is provided in contact with the side surfaces of the conductors 242a and 242b. Therefore, it is possible to suppress the formation of oxide films on the side surfaces of the conductors 242a and 242b due to the microwave treatment.

[0318] Since the film quality of the insulator 250 can be improved, the reliability of the transistor is improved.

[0319] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of the oxide semiconductor. O H makes the channel formation region i-type or substantially i-type. In addition, it is possible to suppress the region used as the source region or the drain region from being supplied with excessive oxygen and maintain the conductivity (the state of the low resistance region) before the microwave treatment. Thus, it is possible to suppress the change of the electrical characteristics of the transistor and suppress the non-uniformity of the electrical characteristics of the transistor within the substrate surface.

[0320] In addition, during the microwave treatment, sometimes the microwave and the molecules in the oxide 230b directly transfer heat energy to the oxide 230b due to electromagnetic interaction. Sometimes the oxide 230b is heated by the heat energy. Sometimes this heat treatment is called microwave annealing. By performing the microwave treatment in an oxygen-containing atmosphere, sometimes an effect equivalent to oxygen annealing can be obtained. In addition, it is considered that: when the oxide 230b contains hydrogen, the above heat energy is transferred to the hydrogen in the oxide 230b and the activated hydrogen is released from the oxide 230b.

[0321] Alternatively, microwave treatment may be performed before the insulating film 250A is deposited instead of microwave treatment after the insulating film is deposited.

[0322] In addition, heat treatment can be performed while maintaining a reduced pressure state after microwave treatment after the deposition of the insulating film 250A. By performing such treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be efficiently removed. In addition, a portion of the hydrogen is sometimes doped by the conductors 242a and 242b. In addition, the step of maintaining a reduced pressure state for heat treatment after microwave treatment can be repeated. By repeatedly performing heat treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be further efficiently removed. Note that the heat treatment temperature is preferably above 300°C and below 500°C. The above-mentioned microwave treatment, i.e., microwave annealing, can also serve as the heat treatment. When the oxide 230b, etc. is sufficiently heated by microwave annealing, the heat treatment may not be performed.

[0323] Furthermore, by performing microwave treatment to change the film quality of the insulating film 250A, diffusion of hydrogen, water, impurities, etc. can be suppressed. Thus, diffusion of hydrogen, water, impurities, etc. through the insulator 250 to the oxide 230b, the oxide 230a, etc. due to post-processes such as deposition of the conductive film to be the conductor 260 or post-processes such as heat treatment can be suppressed.

[0324] Next, a conductive film 260A to be the conductor 260a and a conductive film 260B to be the conductor 260b are sequentially deposited (see FIG. 10A to FIG. 10D ). The conductive film 260A and the conductive film 260B can be deposited by sputtering, CVD, MBE, PLD, electroplating, ALD, etc. In this embodiment, titanium nitride is deposited as the conductive film 260A by ALD, and tungsten is deposited as the conductive film 260B by CVD.

[0325] Next, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. That is, a portion of the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the above-mentioned opening is removed. As a result, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) are formed in the opening overlapping with the conductor 205 (see FIG. 11A to FIG. 11D ).

[0326] Thus, the insulator 250 is provided in contact with the inner wall and side surface of the opening overlapping the oxide 230b. In addition, the conductor 260 is arranged so as to be embedded in the opening via the insulator 250. Thus, the transistor 200 is formed. Through the above steps, the transistor 200 is manufactured.

[0327] Next, an insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0328] In this embodiment, aluminum oxide is deposited as the insulator 282 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen. By using pulsed DC sputtering, the thickness can be made more uniform, thereby improving the sputtering rate and film quality. In addition, the RF power applied to the substrate is set to 1.86 W / cm 2 Below. Preferably 0W / cm 2 Above and 0.62W / cm 2 Note that the RF power is 0W / cm 2 It means that RF power is not applied to the substrate. The amount of oxygen injected into the lower layer of the insulator 282 can be controlled according to the size of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is injected into the lower layer of the insulator 282, and the oxygen amount is easily saturated even if the insulator 282 is thin. In addition, the greater the RF power, the more oxygen is injected into the lower layer of the insulator 282. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. Alternatively, an insulator 282 having a two-layer stacked structure can be deposited. At this time, for example, the RF power applied to the substrate is set to 0W / cm 2 To deposit the lower layer of the insulator 282, the RF power applied to the substrate was set to 0.62 W / cm 2 To deposit an upper layer of insulator 282.

[0329] In addition, the frequency of RF is preferably 10 MHz or higher, and is typically 13.56 MHz. The higher the frequency of RF, the less damage to the substrate can be caused.

[0330] In addition, by depositing the insulator 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulator 280 while being deposited. Thus, excess oxygen can be contained in the insulator 280. In this case, the insulator 282 is preferably deposited while the substrate is heated.

[0331] In addition, heat treatment may be performed before depositing the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be continuously deposited without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen attached to the surface of the insulator 280 may be removed, and the moisture concentration and hydrogen concentration in the insulator 280 may be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is set to 250° C.

[0332] Next, an insulator 283 is formed on the insulator 282. The insulator 283 can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably deposited by a sputtering method. By using a sputtering method that does not require molecules containing hydrogen to be used for a deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is deposited by a sputtering method as the insulator 283.

[0333] Here, it is preferable to continuously deposit insulator 282 and insulator 283 without exposing them to the atmosphere. By depositing the oxide film without exposing them to the atmosphere, impurities or moisture from the atmosphere can be prevented from adhering to insulator 282 and insulator 283, so that the vicinity of the interface between insulator 282 and insulator 283 can be kept clean.

[0334] Through the above steps, the semiconductor device shown in FIG. 2 can be manufactured.

[0335] By using the method for processing the stacked body according to this embodiment, an island-shaped stacked body in which the side ends of the conductor and the side ends of the oxide semiconductor are roughly aligned can be manufactured. By manufacturing an OS transistor using such a stacked body having a microstructure, miniaturization and high integration of semiconductor devices can be achieved.

[0336] The semiconductor device according to this embodiment includes an OS transistor. The off-state current of the OS transistor is small, so a semiconductor device or a storage device with low power consumption can be realized. In addition, since the frequency characteristics of the OS transistor are high, a semiconductor device or a storage device with a fast operating speed can be realized. In addition, by using the OS transistor, a semiconductor device with good electrical characteristics, a semiconductor device with small uneven electrical characteristics of the transistor, a semiconductor device with large on-state current, and a semiconductor device or a storage device with high reliability can be realized.

[0337] This embodiment mode can be appropriately combined with other embodiment modes. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be appropriately combined.

[0338] (Implementation Method 2) In this embodiment, refer to Fig.12A memory device using a transistor according to one embodiment of the present invention is described below through FIG. 18 .

[0339] In this embodiment mode, a structural example of a memory device using a memory cell including the transistor described in the above embodiment mode is described. In this embodiment mode, a structural example of a memory device is described in which a layer including a functional circuit having a function of amplifying and outputting a data potential held in the memory cell is provided between layers including stacked memory cells.

[0340] [Configuration Example of Storage Device] Fig.12 This is a block diagram showing a storage device according to one embodiment of the present invention.

[0341] Fig.12 The memory device 300 shown includes a driving circuit 21 and a memory array 20. The memory array 20 includes a functional layer 50 having a plurality of memory cells 10 and a plurality of functional circuits 51.

[0342] Fig.12 The example in which the memory array 20 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2) is shown. Fig.12 An example is shown in which a functional circuit 51 is provided for each wiring BL serving as a bit line, and an example is also shown in which the functional layer 50 includes a plurality of functional circuits 51 provided corresponding to n wirings BL.

[0343] exist Fig.12 , the 1st row and 1st column storage cell 10 is represented as storage cell 10[1, 1], and the mth row and nth column storage cell 10 is represented as storage cell 10[m, n]. In addition, in the present embodiment, etc., sometimes "row i" is written to represent an arbitrary row. In addition, sometimes "column j" is written to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the i-th row and j-th column storage cell 10 is represented as storage cell 10[i, j]. Note that in the present embodiment, etc., when expressed as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when expressed as "j+α", "j+α" is not less than 1 and not greater than n.

[0344] In addition, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In the present embodiment and the like, the first (1st row) wiring WL is represented as wiring WL[1], and the mth (mth row) wiring WL is represented as wiring WL[m]. Similarly, the first (1st row) wiring PL is represented as wiring PL[1], and the mth (mth row) wiring PL is represented as wiring PL[m]. Similarly, the first (1st column) wiring BL is represented as wiring BL[1], and the nth (nth column) wiring BL is represented as wiring BL[n].

[0345] The plurality of memory cells 10 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 10 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0346] The memory array 20 can use DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM including 1T (transistor) 1C (capacitor) type memory cells, and is a memory in which the access transistor is an OS transistor. The current flowing between the source and the drain of the OS transistor in the off state, that is, the leakage current is extremely small. In DOSRAM, by turning off the access transistor (making it non-conductive), the charge according to the data stored in the capacitor can be maintained for a long time. Therefore, compared with a DRAM composed of a transistor (Si transistor) containing silicon in the channel formation region, the refresh operation frequency of the DOSRAM can be lower. As a result, low power consumption can be achieved. In addition, since the frequency characteristics of the OS transistor are high, high-speed reading and writing of the storage device can be performed. Thus, a storage device with a high operating speed can be provided.

[0347] For example, Fig.12 The memory array 20 shown may include a plurality of memory arrays 20[1] to 20[m] stacked together. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is disposed, the memory density of the memory cell 10 may be increased.

[0348] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the opening or closing (conduction state or non-conduction state) of the access transistor used as a switch. Wiring PL is used as a constant potential line connected to the capacitor. In addition, wiring CL (not shown) can be separately provided as a wiring for transmitting the back gate potential to the back gate of the OS transistor of the access transistor. In addition, a structure in which wiring PL also serves as a transmission back gate potential can also be adopted.

[0349] The memory cells 10 included in the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 through the wiring BL. The wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the driving circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the bit line can be shortened and the resistance and parasitic capacitance of the bit line can be greatly reduced, the power consumption and signal delay can be reduced. In addition, the operation can be performed even if the capacitance of the capacitor included in the memory cell 10 is reduced.

[0350] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 through the wiring GBL (not shown) described later. By adopting this structure, a small potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, similarly to the wiring BL. By arranging the wiring BL and the wiring GBL extending from the memory cell 10 included in the memory array 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the wiring GBL can be shortened and the resistance and parasitic capacitance of the wiring GBL can be greatly reduced, power consumption and signal delay can be reduced.

[0351] Furthermore, the wiring BL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the memory cell 10 that is used as a source or a drain. Alternatively, the wiring BL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the memory cell 10 that is used as a source or a drain. That is, the wiring BL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0352] The memory array 20 can be overlapped on the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal transmission distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 300 can be miniaturized.

[0353] By forming the functional circuit 51 with OS transistors similarly to the transistors included in the memory cell 10 of the DOSRAM, the functional circuit 51 can be freely arranged on a circuit using Si transistors similarly to the memory arrays 20[1] to 20[m], thereby making it easy to integrate. By adopting a structure in which the functional circuit 51 amplifies the signal, the circuits such as the sense amplifier 46 of the subsequent circuit can be miniaturized, thereby miniaturizing the memory device 300.

[0354] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23 and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32 (control circuit) and a voltage generation circuit 33.

[0355] In the storage device 300, each circuit, each signal, and each voltage can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0356] In addition, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signal PON1 and the signal PON2 are power gating control signals. In addition, the signal PON1 and the signal PON2 can also be generated in the control circuit 32.

[0357] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above operation mode.

[0358] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0359] The peripheral circuit 41 is a circuit for writing and reading data to the memory cell 10. In addition, the peripheral circuit 41 is a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42 (RowDecoder), a column decoder 44 (Column Decoder), a row driver 43 (Row Driver), a column driver 45 (ColumnDriver), an input circuit 47 (Input Cir.), an output circuit 48 (Output Cir.), and a sense amplifier 46 (SenseAmplifier).

[0360] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the following functions: a function of writing data to the memory cell 10; a function of reading data from the memory cell 10; a function of holding the read data, etc.

[0361] The input circuit 47 has a function of holding the signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is the signal RDA.

[0362] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high level, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. Fig.12 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0363] The memory array 20 includes memory arrays 20[1] to 20[m] (m is an integer greater than or equal to 2) and a functional layer 50. A plurality of layers of memory arrays 20 may be overlapped on the drive circuit 21. By overlapping a plurality of layers of memory arrays 20, the memory density of the memory cell 10 may be increased. Fig.13A 1 is a perspective view of a storage device 300 in which a functional layer 50 and five-layer (m=5) memory arrays 20 [ 1 ] to 20 [ 5 ] are stacked on a drive circuit 21 .

[0364] exist Fig.13A In the embodiment, the memory array 20 provided in the first layer is referred to as the memory array 20[1], the memory array 20 provided in the second layer is referred to as the memory array 20[2], and the memory array 20 provided in the fifth layer is referred to as the memory array 20[5]. Fig.13A The wiring WL, wiring CL, and wiring PL extending in the X direction and the wiring BL extending in the Z direction (a direction perpendicular to the substrate surface on which the driver circuit is provided) are shown. Note that in order to make the drawings easier to understand, description of a part of the wiring WL and wiring PL included in each of the memory arrays 20 is omitted.

[0365] Fig. 13B Show instructions Fig.13A FIG. 1 is a schematic diagram showing an example of a structure of a functional circuit 51 connected to the wiring BL and a memory cell 10 included in the memory array 20 [1] to 20 [5] connected to the wiring BL. Fig. 13B The wiring GBL provided between the functional circuit 51 and the driving circuit 21 is shown. In addition, a structure that electrically connects one wiring BL to a plurality of memory cells (memory cells 10) is also referred to as a "memory string." Note that in the drawings, the wiring GBL is sometimes shown with a thick line for improved visibility.

[0366] Fig. 13B An example of a circuit structure of a memory cell 10 connected to a wiring BL is shown. The memory cell 10 includes a transistor 11 and a capacitor 12. Regarding the transistor 11, the capacitor 12, and each wiring (wiring BL, wiring WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc. Here, the transistor 11 corresponds to the transistor 200 described in Embodiment 1.

[0367] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to the wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of the capacitor 12. The other electrode of the capacitor 12 is connected to the wiring PL. The gate of the transistor 11 is connected to the wiring WL. The back gate of the transistor 11 is connected to the wiring CL.

[0368] Wiring PL is a wiring for supplying a constant potential for maintaining the potential of capacitor 12. Wiring CL is a constant potential for controlling the threshold voltage of transistor 11. Wiring PL and wiring CL may also be at the same potential. In this case, by connecting the two wirings, the number of wirings connected to memory cell 10 can be reduced.

[0369] Fig. 13B The wiring GBL shown is provided so as to electrically connect the driving circuit 21 and the functional layer 50 . Fig.14A FIG. 3 is a schematic diagram of a memory device 300 with a functional circuit 51 and memory arrays 20 [ 1 ] to 20 [ m ] as a repeating unit 70 . Fig.14A One wiring GBL is shown in the figure, but the wiring GBL may be appropriately provided according to the number of functional circuits 51 in the functional layer 50 .

[0370] Furthermore, the wiring GBL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as a source or a drain. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as a source or a drain. That is, the wiring GBL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the functional circuit 51 of the functional layer 50 to the drive circuit 21 in the vertical direction.

[0371] Alternatively, a structure may be provided in which a repeating unit 70 including a functional circuit 51 and memory arrays 20[1] to 20[m] is stacked. Fig. 14B The repeating units 70 [1] to 70 [p] (p is an integer greater than or equal to 2) may be included. The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be appropriately provided according to the number of the functional circuits 51.

[0372] In one embodiment of the present invention, while stacking OS transistors, wiring used as a bit line is arranged in a direction perpendicular to the substrate surface provided with the driver circuit 21. By providing wiring used as a bit line extending from the memory array 20 in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be greatly reduced.

[0373] In addition, one embodiment of the present invention includes a functional layer 50 in a layer provided with a memory array 20, and the functional layer 50 includes a functional circuit 51 having a function of amplifying the data potential held in the memory cell 10 and outputting it. By adopting this structure, a small potential difference of the wiring BL used as a bit line when reading data can be amplified to drive the sense amplifier 46 included in the drive circuit 21. Since the circuit such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. In addition, the operation can be performed even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0374] Note that, in the above, an example in which the memory cell 10 has a 1T (transistor) 1C (capacitor) type structure is shown, but the present invention is not limited to this. Fig.18A As shown, a 3T1C type memory cell can also be used for the memory device. Fig.18A The memory cell shown includes transistors 11a, 11b, 11c and a capacitor 12a. Here, the transistors 11a, 11b, 11c may have the same structure as the transistor 11, and the capacitor 12a may have the same structure as the capacitor 12. In addition, a RAM having the above structure is sometimes referred to as a NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM: non-volatile oxide semiconductor RAM).

[0375] like Fig.18A As shown, one of the source and drain of transistor 11a is electrically connected to one electrode of capacitor 12a and the first gate of transistor 11b. In addition, one of the source and drain of transistor 11b is electrically connected to one of the source and drain of transistor 11c. In addition, wiring can be appropriately provided on the first gate, the other of the source and drain, and the second gate of transistor 11a, the other of the source and drain, and the second gate of transistor 11b, the first gate, the other of the source and drain, and the second gate of transistor 11c, and the other electrode of capacitor 12a. In addition, the structure of the storage device can be appropriately deformed corresponding to the above wiring.

[0376] In addition, if Fig.18B As shown, a 2T1C type memory cell may be used in which transistor 11a, 11b and capacitor 12a are provided instead of transistor 11c.

[0377] In addition, when the parasitic capacitance of transistor 11a and transistor 11b is sufficiently large, as shown in FIG. Fig. 18C As shown, the capacitor 12a may not be provided. In this case, the memory cell is constituted by only the transistor 11a and the transistor 11b.

[0378] [Configuration Example of Memory Array 20 and Functional Circuit 51] Reference Fig.15 illustrate Fig.12 The configuration examples of the functional circuit 51 and the configuration examples of the sense amplifier 46 included in the memory array 20 and the driver circuit 21 described above are described in detail in FIG. 14 . Fig.15 The driving circuit 21 is shown, and the driving circuit 21 is connected to the wiring GBL (wiring GBL_A, wiring GBL_B), and the wiring GBL is connected to the functional circuit 51 (functional circuit 51_A, functional circuit 51_B), and the functional circuit 51 is connected to the memory cell 10 (memory cell 10_A, memory cell 10_B) connected to the different wiring BL (wiring BL_A, wiring BL_B). Fig.15 The driving circuit 21 shown in the figure shows a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write / read circuit 73 in addition to the sense amplifier 46 .

[0379] Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are shown as the functional circuits 51_A and 51_B. Fig.15 The transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b shown are OS transistors like the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked like the memory arrays 20[1] to 20[m].

[0380] The wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b. The wiring GBL_A is connected to one of the source and drain of the transistors 53_a and 54_a. The wiring GBL_B is connected to one of the source and drain of the transistors 53_b and 54_b. Similar to the wiring BL_A and BL_B, the wiring GBL_A and GBL_B are arranged in the vertical direction and connected to the transistors included in the driving circuit 21. Fig.15 As shown, the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are supplied with the selection signal MUX, the control signal WE, or the control signal RE.

[0381] constitute Fig.15The transistors 81_1 to 81_6 and 82_1 to 82_4 of the sense amplifier 46, the precharge circuit 71_A and the precharge circuit 71_B shown are composed of Si transistors. The switches 83_A to 83_D constituting the switch circuit 72_A and the switch circuit 72_B can also be composed of Si transistors. One of the source and drain of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistor or switch constituting the precharge circuit 71_A, the precharge circuit 71_B, the sense amplifier 46, and the switch circuit 72_A.

[0382] Precharge circuit 71_A includes n-channel transistors 81_1 to 81_3 and precharges wiring BL_A and wiring BL_B to an intermediate potential VPC corresponding to VDD / 2 between high power supply potential (VDD) and low power supply potential (VSS) according to a precharge signal supplied to precharge line PCL1.

[0383] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6 and precharges the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in accordance with a precharge signal supplied to the precharge line PCL2.

[0384] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to the wiring VHH or the wiring VLL. The wiring VHH or the wiring VLL is a wiring having a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors constituting an inverter loop. The potential of the wiring BL_A and the wiring BL_B precharged by selecting the memory cells 10_A and 10_B changes, and the potential of the wiring GBL_A and the wiring GBL_B is set to VDD or VSS according to the change. The potential of the wiring GBL_A and the wiring GBL_B can be output to the outside through the switch 83_C and the switch 83_D and the write-read circuit 73. The wiring BL_A and the wiring BL_B and the wiring GBL_A and the wiring GBL_B are equivalent to a bit line pair. The write-read circuit 73 is controlled to write a data signal according to the signal EN_data.

[0385] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and the wiring GBL_B. The switch circuit 72_A can be switched on or off by controlling the switching signal CSEL1. In the case where the switches 83_A and 83_B are n-channel transistors, they are turned on when the switching signal CSEL1 is at a high level, and are turned off when the switching signal CSEL1 is at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B can be switched on or off by controlling the switching signal CSEL2. The switches 83_C and 83_D can be the same as the switches 83_A and 83_B.

[0386] like Fig.15 As shown, the memory device 300 may have a structure in which the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected by the wiring BL and the wiring GBL arranged in the shortest vertical direction. Although the functional layer 50 including the transistor constituting the functional circuit 51 increases, the load of the wiring BL is reduced, so that the writing time can be shortened and the data can be easily read.

[0387] In addition, if Fig.15 As shown, each transistor included in the functional circuit 51_A, 51_B is controlled by the control signal WE, RE and the selection signal MUX. Each transistor can output the potential of the wiring BL to the driving circuit 21 through the wiring GBL according to the control signal and the selection signal. The functional circuits 51_A, 51_B can be used as a sense amplifier composed of OS transistors. By adopting this structure, a small potential difference of the wiring BL can be amplified during reading, and the sense amplifier 46 using Si transistors can be driven.

[0388] <Structure example of storage unit> use Fig.16 A configuration example of the storage unit 10 used in the above-mentioned storage device will be described.

[0389] Note that Fig.16 In the figure, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X direction and the Y direction.

[0390] like Fig.16As shown, the memory cell 10 includes a transistor 11 and a capacitor 12. An insulator 285 is provided on the transistor 11, and an insulator 284 is provided on the insulator 285. The insulator 285 and the insulator 284 can use an insulator that can be used as the insulator 216. In addition, the transistor 11 has the same structure as the transistor 200 shown in the above embodiment, and the same symbols are attached to the same components. For details of the transistor 200, refer to the above embodiment. In addition, the conductor 240 is provided in a manner of contacting one of the source and the drain of the transistor 11 (conductor 242a). The conductor 240 extends in the Z direction and is used as the wiring BL.

[0391] The capacitor 12 includes a conductor 153 on the conductor 242 b , an insulator 154 on the conductor 153 , and a conductor 160 (a conductor 160 a and a conductor 160 b ) on the insulator 154 .

[0392] At least a portion of each of the conductor 153, the insulator 154, and the conductor 160 is disposed inside the opening provided in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285. An end portion of each of the conductor 153, the insulator 154, and the conductor 160 is located at least on the insulator 282, preferably on the insulator 285. The insulator 154 is provided so as to cover the end portion of the conductor 153. Thus, the conductor 153 and the conductor 160 can be electrically insulated.

[0393] The deeper the depth of the openings provided in the insulators 271b, 275, 280, 282, 283, and 285 (that is, the thickness of one or more of the insulators 271b, 275, 280, 282, 283, and 285 is made thicker), the greater the electrostatic capacitance of the capacitor 12 can be. By increasing the electrostatic capacitance of the capacitor 12 per unit area, miniaturization or high integration of the semiconductor device can be achieved.

[0394] The conductor 153 has a region serving as one electrode (lower electrode) of the capacitor 12. The insulator 154 has a region serving as a dielectric of the capacitor 12. The conductor 160 has a region serving as the other electrode (upper electrode) of the capacitor 12. The capacitor 12 forms a MIM (Metal-Insulator-Metal) capacitor.

[0395] The conductor 242 b provided on the oxide 230 so as to overlap with the oxide 230 is used as a wiring electrically connected to the conductor 153 of the capacitor 12 .

[0396] The conductor 153 and the conductor 160 included in the capacitor 12 can be formed using various conductors that can be used for the conductor 205, the conductor 242, or the conductor 260. It is preferable that both the conductor 153 and the conductor 160 are deposited using a deposition method with good coverage such as the ALD method or the CVD method. For example, titanium nitride or tantalum nitride deposited by the ALD method or the CVD method can be used as the conductor 153.

[0397] The bottom surface of the conductor 153 is in contact with the top surface of the conductor 242b. Here, by using a conductive material with good conductivity as the conductor 242b, the contact resistance between the conductor 153 and the conductor 242b can be reduced.

[0398] Alternatively, titanium nitride deposited by ALD or CVD may be used as conductor 160a, and tungsten deposited by CVD may be used as conductor 160b. Here, when the adhesion of tungsten to insulator 154 is sufficiently high, a single layer structure of tungsten deposited by CVD may be used as conductor 160.

[0399] A high-k material (a material with a relatively high dielectric constant) is preferably used for the insulator 154 in the capacitor 12. The insulator 154 is preferably deposited by a deposition method having good coverage, such as ALD or CVD.

[0400] As insulators of high dielectric constant (high-k) materials, for example, oxides, oxynitrides, oxynitrides and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium and gallium can be cited. In addition, the above oxides, oxynitrides, nitrided oxides or nitrides can also contain silicon. Insulators composed of the above materials can also be used in a stacked manner.

[0401] For example, examples of insulators of high dielectric constant (high-k) materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium. By using such high-k materials, the insulator 154 can be thickened to a degree that can suppress leakage current, and the electrostatic capacitance of the capacitor 12 can also be sufficiently ensured.

[0402] In addition, it is preferred to stack an insulator composed of the above materials, and it is preferred to use a laminated structure of a material having a high dielectric constant (high-k) material and a dielectric strength greater than that of the high dielectric constant (high-k) material. For example, as the insulator 154, an insulator stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. In addition, for example, an insulator stacked in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. In addition, for example, an insulating film stacked in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By stacking an insulator with a relatively large dielectric strength such as aluminum oxide, the dielectric strength is increased, and thus the electrostatic destruction of the capacitor 12 can be suppressed.

[0403] The deeper the depth of the openings provided in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 (that is, the thickness of one or more of the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 is made thicker), the greater the electrostatic capacitance of the capacitor 12 can be. Here, since the insulator 271b, the insulator 275, the insulator 282, and the insulator 283 are used as blocking insulators, it is preferable to set the thickness according to the blocking property required for the semiconductor device. In addition, since the thickness of the conductor 260 used as the gate electrode is determined according to the thickness of the insulator 280, the thickness of the insulator 280 is preferably set according to the thickness of the conductor 260 required for the semiconductor device.

[0404] Therefore, it is preferable to set the electrostatic capacitance of the capacitor 12 by adjusting the thickness of the insulator 285. For example, the thickness of the insulator 285 is set within a range of 50 nm to 250 nm, and the depth of the above-mentioned opening is about 150 nm to 350 nm. By forming the capacitor 12 within the above-mentioned range, the capacitor 12 has a sufficient electrostatic capacitance, and in a semiconductor device having a layer of stacked multiple memory cells, the height of one layer can be prevented from being excessively increased. In each of the multiple memory cell layers, the electrostatic capacitance of the capacitor provided in each memory cell can be made different. When adopting this structure, for example, the thickness of the insulator 285 provided in the layer of each memory cell can be made different.

[0405] In the opening provided in the insulator 285 etc. where the capacitor 12 is arranged, the side wall of the opening may be substantially perpendicular to the top surface of the insulator 222, or may have a tapered shape. The tapered side wall can improve the coverage of the conductor 153 etc. provided in the opening of the insulator 285 etc., thereby reducing defects such as voids.

[0406] The conductor 242a provided on the oxide 230 so as to overlap with the oxide 230 is used as a wiring electrically connected to the conductor 240. For example, Fig.16 In the figure, the top surface and side ends of the conductor 242a are electrically connected to the conductor 240 extending in the Z direction.

[0407] Since the conductor 240 directly contacts at least one of the top surface and the side end of the conductor 242a, it is not necessary to set up an electrode for connection separately, so the occupied area of ​​the memory array can be reduced. In addition, the integration of the memory cell is improved, and the storage capacity of the memory device can be increased. In addition, the conductor 240 is preferably in contact with a part of the top surface and the side end of the conductor 242a. By the conductor 240 contacting multiple surfaces of the conductor 242a, the contact resistance between the conductor 240 and the conductor 242a can be reduced.

[0408] The conductor 240 is disposed in the openings formed in the insulator 216 , the insulator 222 , the insulator 275 , the insulator 280 , the insulator 282 , the insulator 283 , the insulator 285 , and the insulator 284 .

[0409] The conductor 240 preferably has a laminated structure of a conductor 240a and a conductor 240b. Fig.16 As shown in FIG. 1 , the conductor 240 may have a structure in which the conductor 240a is provided in contact with the inner wall of the opening and the conductor 240b is provided inside the conductor 240a. That is, the conductor 240a is arranged near the insulator 216, the insulator 222, the insulator 275, the insulator 280, the insulator 282, the insulator 283, the insulator 285, and the insulator 284 compared with the conductor 240b. In addition, the conductor 240a is in contact with the top surface and the side end of the conductor 242a.

[0410] As the conductor 240a, it is preferable to use a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen. The conductor 240a may have a single-layer structure or a stacked-layer structure using, for example, one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Thus, impurities such as water and hydrogen can be inhibited from mixing into the oxide 230 through the conductor 240.

[0411] In addition, since the conductor 240 is also used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used for the conductor 240b.

[0412] For example, it is preferable to use titanium nitride as the conductor 240a and to use tungsten as the conductor 240b. In this case, the conductor 240a is a conductor containing titanium and nitrogen, and the conductor 240b is a conductor containing tungsten.

[0413] Furthermore, the conductor 240 may have a single-layer structure or a stacked-layer structure of three or more layers.

[0414] In addition, if Fig.16 As shown, it is preferable to provide the insulator 241 in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner wall of the openings of the insulator 216, the insulator 222, the insulator 275, the insulator 280, the insulator 282, the insulator 283, the insulator 285, and the insulator 284. In addition, the insulator 241 is also formed on the side surface of the insulator 224, the oxide 230, and the conductor 242a formed to protrude in the opening. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. That is, the conductor 240 is provided in a manner embedded in the inside of the above-mentioned opening via the insulator 241.

[0415] like Fig.16 As shown in FIG. 1 , the uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the top surface of the conductor 242a. By adopting this structure, the conductor 240 can be in contact with at least a portion of the side end portion of the conductor 242a. In addition, the insulator 241 formed below the conductor 242a preferably includes a region in contact with the side surface of the oxide 230. By adopting this structure, impurities such as water and hydrogen contained in the insulator 280 and the like can be suppressed from mixing into the oxide 230 through the conductor 240.

[0416] As the insulator 241, a blocking insulating film that can be used for the insulator 275 or the like can be used. For example, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride can be used for the insulator 241. By adopting this structure, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 or the like from being mixed into the oxide 230 through the conductor 240. In particular, silicon nitride is preferred because it has a high barrier property against hydrogen. In addition, it is possible to suppress the absorption of oxygen contained in the insulator 280 by the conductor 240.

[0417] Fig.16 The insulator 241 is shown as a single-layer structure, but the present invention is not limited thereto. The insulator 241 may also have a stacked structure of two or more layers.

[0418] When the insulator 241 has a two-layer stacked structure, the first layer of the inner wall of the opening in contact with the insulator 280 or the like may be an oxygen blocking insulating film and the second layer inside thereof may be a hydrogen blocking insulating film. For example, aluminum oxide deposited by the ALD method may be used as the first layer and silicon nitride deposited by the PEALD method may be used as the second layer. By adopting this structure, oxidation of the conductor 240 can be suppressed, and mixing of hydrogen from the conductor 240 into the oxide 230 or the like can be reduced. Thus, the electrical characteristics and reliability of the transistor 11 can be improved.

[0419] The sidewalls of the opening where the conductor 240 and the insulator 241 are arranged may be substantially perpendicular to the top surface of the insulator 222 or may be tapered. The tapered sidewalls improve coverage of the insulator 241 and the like provided in the opening.

[0420] <Configuration Example of Storage Device 300> use Fig.17 A configuration example of the above-mentioned storage device 300 will be described.

[0421] The memory device 300 includes: a driver circuit 21 including a layer of transistors 310 and the like; a functional layer 50 including a layer of transistors 52, 53, 54, 55 and the like on the driver circuit 21; and a memory array 20[1] to 20[m] ( Fig.17 Only memory arrays 20[1] and 20[2] are shown. Transistor 52 corresponds to the above-mentioned transistors 52_a and 52_b, transistor 53 corresponds to the above-mentioned transistors 53_a and 53_b, transistor 54 corresponds to the above-mentioned transistors 54_a and 54_b, and transistor 55 corresponds to the above-mentioned transistors 55_a and 55_b.

[0422] Fig.17 2 shows a transistor 310 included in the driving circuit 21. The transistor 310 is provided on a substrate 311 and includes a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 including a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 310 may be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate may be used.

[0423] Here, in Fig.17In the transistor 310 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, the conductor 316 can use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 310 is also referred to as a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the upper surface of the convex portion may also be provided. In addition, although a case where a part of the semiconductor substrate is processed to form a convex portion is shown here, an SOI substrate may also be processed to form a semiconductor film having a convex shape.

[0424] Notice, Fig.17 The structure of the transistor 310 shown is just an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0425] A wiring layer including an interlayer film, wiring, and plugs may be provided between the structures. In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be one component. That is, a part of the conductor may be used as wiring, and a part of the conductor may be used as a plug.

[0426] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 310. In addition, a conductor 328 and the like are embedded in the insulator 320 and the insulator 322. In addition, a conductor 330 and the like are embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as a connection plug or wiring.

[0427] Furthermore, the insulator used as an interlayer film may also be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 322, planarization may be achieved by a planarization process such as chemical mechanical polishing (CMP).

[0428] also, Fig.17 Transistors 52, 53, and 55 are shown in the functional layer 50. The transistors 52, 53, and 55 have the same structure as the transistor 11 in the memory cell 10. The sources and drains of the transistors 52, 53, and 55 are connected in series.

[0429] An insulator 208 is provided on transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Furthermore, an insulator 210 is provided on the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Furthermore, an insulator 212 is provided on the insulator 210, and an insulator 214 is provided on the insulator 212. A portion of the conductor 240 provided in the memory array 20[1] is embedded in the openings formed in the insulators 212 and 214. Here, an insulator that can be used as the insulator 216 can be used as the insulator 208 and the insulator 210. In addition, an insulator that can be used as the insulator 283 can be used as the insulator 212. In addition, an insulator that can be used as the insulator 282 can be used as the insulator 214.

[0430] The bottom surface of the conductor 207 is provided in contact with the top surface of the conductor 260 of the transistor 52. In addition, the top surface of the conductor 207 is provided in contact with the bottom surface of the conductor 209. In addition, the top surface of the conductor 209 is in contact with the bottom surface of the conductor 240 provided in the memory array 20[1]. By adopting this structure, the conductor 240 corresponding to the wiring BL can be electrically connected to the gate of the transistor 52.

[0431] Each of the memory arrays 20[1] to 20[m] includes a plurality of memory cells 10. The conductor 240 included in each memory cell 10 is electrically connected to the conductor 240 of the upper layer and the conductor 240 of the lower layer.

[0432] like Fig.17 As shown, the adjacent memory cells 10 share the conductor 240. In addition, in the adjacent memory cells 10, the structure on the right and the structure on the left are arranged symmetrically with the conductor 240 as the boundary.

[0433] Here, the conductor 160 used as the upper electrode of the capacitor 12 of the lower layer (e.g., the layer of the memory array 20[1]) and the conductor 261 used as the second gate electrode of the transistor 11 of the upper layer (e.g., the layer of the memory array 20[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitor 12 of the lower layer and the conductor 261 of the transistor 11 of the upper layer are formed in a manner embedded in the same opening formed in the insulator 216. The conductor 160 of the capacitor 12 of the lower layer and the conductor 261 of the transistor 11 of the upper layer are formed by processing a conductive film, and have the above-mentioned structure. At this time, the conductor 160 of the capacitor 12 of the lower layer contains the same material as the conductor 261 of the transistor 11 of the upper layer.

[0434] As described above, by forming the conductor 160 of the lower capacitor 12 and the conductor 261 of the upper transistor 11 at the same time, the manufacturing process of the memory device according to this embodiment can be shortened, thereby improving the productivity of the memory device.

[0435] In the memory array 20, a plurality of memory arrays 20[1] to 20[m] may be stacked. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is disposed, the memory density of the memory cell 10 may be increased. In addition, the memory array 20 may be manufactured repeatedly using the same manufacturing process in the vertical direction. The memory device 300 may reduce the manufacturing cost of the memory array 20.

[0436] This embodiment mode can be combined with other embodiment modes as appropriate.

[0437] (Implementation 3) In this embodiment, an example of a chip on which a memory device according to one embodiment of the present invention is mounted is described with reference to FIG. 19 .

[0438] exist Fig.19A and Fig.19B A plurality of circuits (systems) are mounted on the illustrated chip 1200. The technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC).

[0439] like Fig.19A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0440] Bumps (not shown) are provided on the chip 1200. Fig.19B As shown in FIG. 1 , the first surface of the package substrate 1201 is connected to the first surface of the package substrate 1201 . In addition, a plurality of bumps 1202 are provided on the back side of the first surface of the package substrate 1201 , and the bumps 1202 are connected to the motherboard 1203 .

[0441] In addition, a storage device such as DRAM 1221 and flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM described in the above embodiment may be used for DRAM 1221. Thus, the DRAM 1221 can have low power consumption, high speed, and large capacity.

[0442] The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. In addition, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory commonly used by the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above-mentioned DOSRAM may be used for the memory. In addition, the GPU 1212 is suitable for parallel calculation of a plurality of data, which may be used for image processing or product-sum operations. By providing an image processing circuit or product-sum operation circuit using the OS transistor shown in the above-mentioned embodiment as the GPU 1212, image processing or product-sum operations may be performed with low power consumption.

[0443] In addition, since CPU1211 and GPU1212 are provided on the same chip, the wiring between CPU1211 and GPU1212 can be shortened, and data can be transferred from CPU1211 to GPU1212, data can be transferred between memories possessed by CPU1211 and GPU1212, and calculation results can be transferred from GPU1212 to CPU1211 after calculations in GPU1212 are completed at high speed.

[0444] The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. In addition, the analog operation unit 1213 may also include the above-mentioned product-sum operation circuit.

[0445] The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0446] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, a controller, etc. The controller includes a mouse, a keyboard, a game console controller, etc. As the above-mentioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc. can be used.

[0447] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network) and may also include a network security circuit.

[0448] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at a low cost.

[0449] The motherboard 1203 including the package substrate 1201 provided with the chip 1200 having the GPU 1212 , the DRAM 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0450] The GPU module 1204 can reduce its size due to having the chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles due to its high image processing capabilities. In addition, by utilizing a product-sum operation circuit using the GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recursive neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be performed, thereby enabling the chip 1200 to be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0451] This embodiment mode can be combined with other embodiment modes as appropriate.

[0452] (Implementation 4) This embodiment shows an example of an electronic component in which a storage device according to one embodiment of the present invention is mounted.

[0453] [Electronic components] Fig. 20A The electronic component 700 and a substrate (circuit board 704 ) on which the electronic component 700 is mounted are shown in a perspective view. Fig. 20A The electronic component 700 shown includes the storage device 300 of one embodiment of the present invention in a mold 711. Fig. 20A 700 is omitted to show the inside. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the storage device 300 through the lead 714. The electronic component 700 is mounted on a printed circuit board 702, for example. By combining a plurality of electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0454] As shown in the above embodiment, the memory device 300 includes a driving circuit 21 and a memory array 20 .

[0455] Fig. 20BThe electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 300 are provided on the interposer 731.

[0456] Furthermore, an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used as the semiconductor device 735. By using the OS transistor described in the above embodiment mode in the integrated circuit such as the CPU, the GPU, or the FPGA, low power consumption can be achieved.

[0457] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0458] The plug board 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are arranged in a single layer or in multiple layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit arranged on the plug board 731 to the electrode arranged on the package substrate 732. Therefore, the plug board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, a through electrode is sometimes arranged in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon plug board is used, TSV (Through Silicon Via: silicon through hole) can also be used as a through electrode.

[0459] A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring formation of the silicon interposer can be performed in a semiconductor process, so it is easy to form fine wiring that is difficult to form when using a resin interposer.

[0460] In order to achieve a wide memory bandwidth in the memory device 300, many wirings need to be connected. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the memory device 300 is mounted. Therefore, it is preferable to use a silicon interposer as the interposer on which the memory device 300 is mounted.

[0461] In addition, in SiP, MCM, etc. using a silicon interposer, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, poor connection between the integrated circuit disposed on the silicon interposer and the silicon interposer is not likely to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0462] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the height of the integrated circuit provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the height of the storage device 300 and the semiconductor device 735 consistent.

[0463] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig. 20B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0464] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. As mounting methods, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package) and QFN (Quad Flat Non-leaded package) can be cited.

[0465] This embodiment mode can be combined with other embodiment modes as appropriate.

[0466] (Implementation method 5) In this embodiment, an application example of a storage device which is one embodiment of the present invention will be described.

[0467] A storage device of one embodiment of the present invention can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smart phones, e-book reader terminals, digital still cameras, video cameras, video playback devices, navigation systems, and game consoles). In addition, it can be used for image sensors, IoT (Internet of Things), and medical equipment, etc. Thus, power saving of electronic devices can be achieved. By using the OS transistor shown in the above embodiment in an integrated circuit such as a CPU or GPU of the above electronic device, power saving can be further achieved. Note that here, computers include tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0468] An example of an electronic device including a storage device according to one embodiment of the present invention is described. Note that FIG. 21A to FIG. 21J , FIG. 22A to FIG. 22E The electronic component 700 or the electronic component 730 having the storage device described in the above embodiment is shown as being included in each electronic device.

[0469] [Mobile phone] Fig.21A The information terminal 5500 shown is a mobile phone (smartphone) which is one of the information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511 . The display portion 5511 has a touch panel as an input interface, and the housing 5510 is provided with buttons.

[0470] By applying the storage device of one embodiment of the present invention to the information terminal 5500, it is possible to store documents that are temporarily generated when a program is executed (for example, a cache when a web browser is used).

[0471] [Wearable terminal] Fig. 21B An information terminal 5900 as an example of a wearable terminal is shown. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a strap 5905, and the like.

[0472] Similar to the above-mentioned information terminal 5500, by applying the storage device of one embodiment of the present invention to a wearable terminal, it is possible to store documents temporarily generated when a program is executed.

[0473] [Information Terminal] Fig. 21C 1 shows a desktop information terminal 5300. The desktop information terminal 5300 includes an information terminal body 5301, a display portion 5302, and a keyboard 5303.

[0474] Similar to the above-described information terminal 5500 , by applying the storage device of one embodiment of the present invention to the desktop information terminal 5300 , it is possible to store a document temporarily generated when a program is executed.

[0475] exist FIG. 21A to FIG. 21C In the description, as electronic devices, smartphones, wearable terminals, and desktop information terminals are described, but as other information terminals, for example, PDAs (Personal Digital Assistants), notebook information terminals, and workstations can be cited.

[0476] [Electrical products] Fig.21D An electric refrigerator-freezer 5800 is shown as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer that supports IoT (Internet of Things).

[0477] The storage device of one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. By using the Internet or the like, the electric refrigerator-freezer 5800 can send information such as food stored in the electric refrigerator-freezer 5800 or the expiration date of the food to an information terminal or the like. The electric refrigerator-freezer 5800 can store a document temporarily generated when sending the information in the storage device of one embodiment of the present invention.

[0478] exist Fig.21D In the description, an electric refrigerator-freezer is described as an electrical appliance, and other electrical appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, an electric rice cooker, a water heater, an IH cooker, a water dispenser, a heating and cooling air conditioner including an air conditioner, a washing machine, a dryer, and audio-visual equipment.

[0479] [Game console] Fig.21E A portable game machine 5200 as an example of a game machine is shown. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0480] also, Fig.21F The following is a stationary game machine 7500 as an example of a game machine. The stationary game machine 7500 can be said to be a stationary game machine for home use. The stationary game machine 7500 includes a main body 7520 and a controller 7522. The main body 7520 can be connected to the controller 7522 wirelessly or by wire. Fig.21FAlthough not shown in the figure, the controller 7522 may include a display unit for displaying game images, a touch panel as an input interface other than buttons, a joystick, a rotating grip or a sliding grip, etc. In addition, the controller 7522 is not limited to Fig.21F The shape of the controller 7522 may be changed according to the type of game. For example, in shooting games such as FPS (First Person Shooter), a controller that imitates the shape of a gun may be used as a trigger button. In addition, for example, in music games, a controller that imitates the shape of a musical instrument or a musical device may be used. Furthermore, a fixed game console may be provided with one or more of a camera, a depth sensor, and a microphone, and may be operated by gestures or voice of the game player instead of using a controller.

[0481] In addition, the images of the above-mentioned game machine can be output by a display device such as a television device, a personal computer monitor, a game monitor, or a head-mounted display.

[0482] The storage device of one embodiment of the present invention can be used in the portable game machine 5200 or the stationary game machine 7500 to reduce power consumption. In addition, the heat generated by the circuit can be reduced by reducing power consumption, thereby reducing the impact of heat on the circuit itself, peripheral circuits and modules.

[0483] Furthermore, by using the storage device of one embodiment of the present invention in the portable game machine 5200 or the stationary game machine 7500, it is possible to store a calculation file temporarily generated when a game is executed.

[0484] exist Fig.21E and Fig.21F In the embodiment, a portable game machine and a fixed game machine for home use are described as an example of a game machine. As other game machines, for example, arcade game machines arranged in recreational facilities (game centers, amusement parks, etc.) and pitching machines for batting practice arranged in sports facilities can be cited.

[0485] [Mobile body] A storage device according to one embodiment of the present invention can be applied to a vehicle as a moving object and the vicinity of a driver's seat of the vehicle.

[0486] Figure 21G A car 5700 is shown as an example of a moving object.

[0487] A dashboard that can display a speedometer, a tachometer, a travel distance, a refueling amount, a gear state, an air-conditioning setting, etc. to provide various information is provided near the driver's seat of the automobile 5700. In addition, a storage device that represents the above information may also be provided near the driver's seat.

[0488] In particular, by displaying the image captured by the camera device (not shown) installed on the automobile 5700 on the above-mentioned display device, the field of vision blocked by pillars, etc., the blind spot of the driver's seat, etc. can be supplemented, thereby improving safety. In other words, by displaying the image captured by the camera device installed outside the automobile 5700, the blind spot can be supplemented to improve safety.

[0489] The storage device of one embodiment of the present invention can temporarily store data. For example, the storage device can be applied to the automatic driving system of the automobile 5700, the system for performing navigation, danger prediction, etc., to temporarily store necessary data. In addition, the navigation, danger prediction, etc. information can also be temporarily displayed on the display device. In addition, the recording of the driving recorder installed in the automobile 5700 can also be stored.

[0490] In addition, although the above example describes a car as an example of a mobile body, the mobile body is not limited to the car. For example, a tram, a monorail, a ship, and a flying object (a helicopter, an unmanned aerial vehicle (UAV), an airplane, a rocket) can also be cited as a mobile body.

[0491] [camera] A storage device according to one embodiment of the present invention can be applied to a camera.

[0492] Fig.21H A digital camera 6240 is shown as an example of an image pickup device. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and is equipped with a detachable lens 6246. Note that here, the digital camera 6240 adopts a structure in which the lens 6246 can be detached from the housing 6241, but the lens 6246 and the housing 6241 may be formed as one body. In addition, the digital camera 6240 may also have a flash device and a viewfinder, etc. that are separately installed.

[0493] The use of a storage device according to one embodiment of the present invention in a digital camera 6240 can reduce power consumption. In addition, the heat generated by the circuit can be reduced by reducing power consumption, thereby reducing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0494] [Video Camera] A storage device according to one embodiment of the present invention can be applied to a video camera.

[0495] Fig.21IA video camera 6300 as an example of an image pickup device is shown. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 can also be switched according to the angle between the first housing 6301 and the second housing 6302 in the connection unit 6306.

[0496] When recording images captured by the video camera 6300, encoding is required according to a data recording method. With the storage device of one embodiment of the present invention, the video camera 6300 can store files temporarily generated during encoding.

[0497] [ICD] The storage device according to one embodiment of the present invention can be applied to an implantable cardioverter-defibrillator (ICD).

[0498] Fig.21J 1 is a schematic cross-sectional view showing an example of an ICD. An ICD main body 5400 includes at least a battery 5401, an electronic component 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0499] The ICD body 5400 is surgically placed in the body, and two metal wires pass through the subclavian vein 5405 and the superior vena cava 5406 of the human body, and the tip of one metal wire is placed in the right ventricle, and the tip of the other metal wire is placed in the right atrium.

[0500] ICD main body 5400 has the function of a pacemaker, and paces the heart when the heart rhythm is out of a predetermined range. In addition, when the heart rhythm does not improve even with pacing (rapid ventricular frequency or ventricular fibrillation, etc.), treatment using electric shock is performed.

[0501] In order to properly perform pacing and electric shock, the ICD main body 5400 needs to constantly monitor the heart rhythm. Therefore, the ICD main body 5400 includes a sensor for detecting the heart rhythm. In addition, the ICD main body 5400 can store the heart rhythm data measured by the sensor, the number of times and time of treatment using pacing, etc. in the electronic component 700.

[0502] In addition, power can be received by antenna 5404 and charged to battery 5401. In addition, safety can be improved by including a plurality of batteries in ICD main body 5400. Specifically, even if some batteries in ICD main body 5400 fail, other batteries can function and be used as auxiliary power sources.

[0503] In addition, in addition to the antenna 5404 capable of receiving power, an antenna capable of sending physiological signals may also be included. For example, a system for monitoring cardiac activity in which physiological signals such as pulse, respiratory rate, heart rhythm, and body temperature can be confirmed by an external monitoring device may be constructed.

[0504] [Expansion unit for PC] A storage device according to one embodiment of the present invention can be applied to a computer such as a PC (Personal Computer) or an expansion device for an information terminal.

[0505] Fig.22A An example of such an expansion device is an expansion device 6100 that is portable and has a chip capable of storing information installed outside a PC. The expansion device 6100 can be connected to a PC via a USB or the like, and can use the chip to store data. Fig.22A A portable expansion device 6100 is shown, but the expansion device according to one embodiment of the present invention is not limited thereto. For example, a larger expansion device with a cooling fan or the like installed may be used.

[0506] The expansion device 6100 includes a housing 6101, a cover 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is accommodated in the housing 6101. The substrate 6104 is provided with a circuit for driving a storage device or the like of one embodiment of the present invention. For example, the substrate 6104 is mounted with an electronic component 700 and a controller chip 6106. The USB connector 6103 is used as an interface for connecting to an external device.

[0507] [SD card] A storage device according to one embodiment of the present invention can be applied to an SD card that can be mounted on electronic devices such as information terminals and digital cameras.

[0508] Fig. 22B This is a schematic diagram of the appearance of an SD card. Fig. 22C51 is a schematic diagram of the internal structure of an SD card. An SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 has the function of an interface connected to an external device. The substrate 5113 is accommodated in the housing 5111. The substrate 5113 is provided with a storage device and a circuit that drives the storage device. For example, the substrate 5113 is installed with an electronic component 700 and a controller chip 5115. In addition, the circuit structures of the electronic component 700 and the controller chip 5115 are not limited to the above description, and the circuit structure can be appropriately changed according to the situation. For example, the write circuit, row driver, read circuit, etc. possessed by the electronic component can also be installed on the controller chip 5115 instead of the electronic component 700.

[0509] The capacity of the SD card 5110 can be increased by also providing the electronic component 700 on the back side of the substrate 5113. In addition, a wireless chip having a wireless communication function can be provided on the substrate 5113. Thus, wireless communication between an external device and the SD card 5110 can be performed, and data of the electronic component 700 can be read and written.

[0510] [SSD] A storage device according to one embodiment of the present invention can be applied to an SSD (Solid State Drive) that can be mounted on an electronic device such as an information terminal.

[0511] Fig.22D This is a schematic diagram of the appearance of SSD. Fig.22E 5150 is a schematic diagram of the internal structure of the SSD. The SSD5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 has the function of connecting to an interface of an external device. The substrate 5153 is accommodated in the housing 5151. The substrate 5153 is provided with a storage device and a circuit that drives the storage device. For example, the substrate 5153 is installed with an electronic component 700, a memory chip 5155, and a controller chip 5156. By also providing the electronic component 700 on the back side of the substrate 5153, the capacity of the SSD5150 can be increased. A working memory is installed in the memory chip 5155. For example, a DRAM chip can be used for the memory chip 5155. A processor, an ECC (Error Check and Correct) circuit, etc. are installed in the controller chip 5156. Note that the circuit structures of the electronic component 700, the memory chip 5155, and the controller chip 5155 are not limited to the above description, and the circuit structure can be appropriately changed according to the situation. For example, a memory used as a working memory can also be provided in the controller chip 5156.

[0512] [computer] Fig.23AThe computer 5600 shown is an example of a large-scale computer. In the computer 5600 , a plurality of rack-mounted computers 5620 are housed in a rack 5610 .

[0513] Computer 5620 may have, for example, Fig. 23B The structure of the stereogram is shown. Fig. 23B In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0514] Fig.23C The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.23C Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0515] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0516] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, etc. As examples of the specifications of the connection terminals 5623, 5624, and 5625, USB, SATA (Serial ATA), and SCSI (Small Computer System Interface) can be cited. In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as examples of the specifications.

[0517] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0518] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by soldering the terminals to wiring provided on the board 5622 by reflow soldering. As the semiconductor device 5627, for example, an FPGA (Field Programmable Gate Array), a GPU, a CPU, etc. can be cited. As the semiconductor device 5627, for example, an electronic component 730 can be used.

[0519] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by soldering the terminals to wirings provided on the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0520] The computer 5600 can be used as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0521] By using a storage device of one embodiment of the present invention in the above-mentioned various electronic devices, miniaturization and low power consumption of the electronic devices can be achieved. In addition, the power consumption of the storage device of one embodiment of the present invention is low, thereby reducing the heating of the circuit. Thus, the negative impact of the heating on the circuit itself, the peripheral circuit and the module can be reduced. In addition, by using a storage device of one embodiment of the present invention, an electronic device that can work stably even in a high temperature environment can be realized. Thus, the reliability of the electronic device can be improved.

[0522] This embodiment mode can be combined with other embodiment modes as appropriate.

[0523] (Implementation 6) In this embodiment, using Fig.24 A specific example in which a semiconductor device according to one embodiment of the present invention is applied to space equipment will be described.

[0524] A semiconductor device of one embodiment of the present invention includes an OS transistor. The electrical characteristics of the OS transistor due to exposure to radiation change little. In other words, the resistance to radiation is high, so it can be appropriately used in an environment where radiation may be incident. For example, the OS transistor can be appropriately used when used in outer space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. In addition, outer space refers to, for example, a place above 100 km in altitude, but the outer space described in this specification may also include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0525] exist Fig.24 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.24 An example of a planet 6804 in outer space is shown.

[0526] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0527] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to set a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes called a solar cell module.

[0528] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0529] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, a semiconductor device including an OS transistor in one embodiment of the present invention is preferably used. Compared with Si transistors, the electrical characteristics of OS transistors change less due to exposure to radiation. Therefore, OS transistors are highly reliable and can be appropriately used even in an environment where radiation may be incident.

[0530] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0531] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0532] Alternatively, for example, the OS transistor can be used as a transistor constituting a semiconductor device in a working robot provided in a nuclear power plant or a radioactive waste processing or disposal site. In particular, the OS transistor can be suitably used as a transistor constituting a semiconductor device provided in a remotely operated robot that is remotely operated during the removal of a reactor facility, the removal of nuclear fuel or fuel fragments, or field investigations in a space with a large amount of radioactive materials.

[0533] This embodiment mode can be combined with other embodiment modes as appropriate. [Example 1]

[0534] In this embodiment, the manufacturing Figures 1A to 1F The structure including the oxide 230 is shown in FIG.

[0535] In this embodiment, a sample is prepared in which a base silicon oxide film, a hafnium oxide film (hereinafter referred to as an HfOx film), a silicon oxide film (hereinafter referred to as an SiOx film), an In-Ga-Zn oxide film (hereinafter referred to as an IGZO film), a stacked film of tantalum nitride and tungsten (hereinafter referred to as a TaNx\W film), a stacked film of silicon nitride and silicon oxide (hereinafter referred to as a SiNx\SiOx film), a tungsten film (hereinafter referred to as a W film), an SOC film, and an SOG film are stacked in the following order on a silicon substrate. A resist mask is set on the sample and a resist is formed. Figures 1A to 1F The etching process is shown.

[0536] Here, the base silicon oxide film corresponds to Figures 1A to 1F The insulator 216 shown. The HfOx film corresponds to the insulator 222. The SiOx film corresponds to the insulating film 224f and the insulator 224. The IGZO film corresponds to the stacked film of the oxide film 230af and the oxide film 230bf and the stacked film of the oxide 230a and the oxide 230b. The TaNx\W film corresponds to the conductive film 242f and the conductive body 242. The SiNx\SiOx film corresponds to the stacked film of the insulating film 271_1f and the insulating film 271_2f and the stacked film of the insulator 271_1 and the insulator 271_2. The W film corresponds to the inorganic film 276f and the inorganic film 276. The SOC film corresponds to the coating film 277f and the coating film 277. The SOG film corresponds to the coating film 278f and the coating film 278.

[0537] First, select Figures 1A to 1F The etching conditions required in the process shown are Figure 1C Similarly, when etching the TaNx\W film, the SOC film needs to be used as a mask. If the SOC film is removed when etching the TaNx\W film, the W film disposed under the SOC film is also removed.

[0538] Therefore, the SOC film and the TaNx film and the W film constituting the TaNx\W film were dry-etched and their etching rates were measured. In addition, the etching selectivity ratio of the TaNx film relative to the SOC film (hereinafter referred to as the TaNx / SOC selectivity ratio) and the etching selectivity ratio of the W film relative to the SOC film (hereinafter referred to as the W / SOC selectivity ratio) were calculated.

[0539] The dry etching process was performed using a CCP etching device. The etching conditions were as follows: CHF 3 Gas 35sccm, Cl 2 Gas 15 sccm and Ar gas 10 sccm; pressure 0.6 Pa; inter-electrode distance 80 mm; upper electrode power 1000 W; substrate temperature 60° C. The etching rate was measured under the conditions where the lower electrode power was set to 10 W, 25 W, 50 W, and 100 W.

[0540] Fig.25A The measurement results of etching rate are shown. Fig.25B Here, the etching selectivity is shown. Fig.25A In the figure, the horizontal axis represents the lower electrode power (Btm Power [W]), and the vertical axis represents the etching rate [nm / min]. Fig.25B In FIG. 1 , the horizontal axis represents the lower electrode power (Btm Power [W]), and the vertical axis represents the etching selectivity.

[0541] like Fig.25A As shown in FIG. 1 , when the lower electrode power is 25 W or more, the etching rates of the TaNx film and the W film are approximately equal to or lower than the etching rate of the SOC film. Fig.25B In the case of the lower electrode power of 10 W, the TaNx / SOC selectivity ratio and the W / SOC selectivity ratio are less than 1.0. In contrast, under the condition that the lower electrode power is 10 W, the etching rates of the TaNx film and the W film are greater than the etching rate of the SOC film. Under the condition that the lower electrode power is 10 W, the TaNx / SOC selectivity ratio is 1.38, and the W / SOC selectivity ratio is 1.42.

[0542] Thus, in etching the TaNx\W film, the lower electrode power may be at least less than 25 W, preferably less than 10 W. By etching the TaNx\W film under the above conditions, the TaNx\W film can be removed without causing the SOC film to disappear.

[0543] Next, a method for manufacturing the sample 1A and the sample 1B that form the above-mentioned structure will be described.

[0544] First, a silicon substrate is prepared, and a base silicon oxide film is deposited on the silicon substrate by CVD method. Then, a HfOx film with a thickness of 20 nm is deposited on the base silicon oxide film by ALD method.

[0545] Next, a SiOx film was deposited on the HfOx film, and then an IGZO film was deposited on the SiOx film. The SiOx film and the IGZO film were continuously deposited without being exposed to the outside air. The SiOx film was deposited to a thickness of 20 nm by sputtering using a Si target.

[0546] Here, the IGZO film has a stacked structure of a 10 nm thick IGZO (132) film and a 15 nm thick IGZO (111) film on the IGZO (132) film. Figures 1A to 1F The oxide film 230af and the oxide 230a are shown. In addition, the IGZO (111) film corresponds to Figures 1A to 1F The oxide film 230bf and the oxide 230b are shown. The IGZO film (132) is deposited by sputtering using a target with an In:Ga:Zn ratio of 1:3:2 [atomic ratio], and the IGZO film (111) is deposited by sputtering using a target with an In:Ga:Zn ratio of 1:1:1.2 [atomic ratio].

[0547] Next, a TaNx\W film is deposited on the IGZO film by sputtering. The TaNx\W film is a stacked film of a 5nm thick TaNx film and a 15nm thick W film on the TaNx film. The TaNx film is deposited using a tantalum target in an atmosphere containing nitrogen gas. The W film is deposited using a tungsten target.

[0548] Next, a SiNx\SiOx film is deposited on the TaNx\W film by sputtering. The SiNx\SiOx film is a stacked film of a 5nm thick SiNx film and a 10nm thick SiOx film on the SiNx film. The SiNx film is deposited using a silicon target in an atmosphere containing nitrogen gas. The SiOx film is deposited using a silicon target in an atmosphere containing oxygen gas.

[0549] Next, a W film with a thickness of 15 nm is deposited on the SiNx\SiOx film by sputtering, and then a SOC film is deposited on the W film by spin coating, and then a SOG film is deposited on the SOC film by spin coating.

[0550] and Figure 1A Similarly, a negative resist film is formed on the laminated film manufactured as described above. By irradiating the resist film with an electron beam, an island-shaped resist mask is formed. In addition, in each of the samples 1A and 1B, a region with a width of 30 nm and a region with a width of 60 nm of the island-shaped resist mask are formed.

[0551] Next, an island resist mask is used to perform the corresponding Figures 1B to 1F The dry etching process is performed using a CCP etching device. Table 1 shows the conditions of the dry etching process. Table 1 shows the electrode distance (Gap (mm)), top electrode power (Top Power (W)), lower electrode power (Btm Power (W)), pressure (Press (Pa)), gas flow rate (Gas (sccm)), and substrate temperature (Tsub (°C)) in the dry etching of each film.

[0552] [Table 1]

[0553] First, with Figure 1B Similarly, the SOG film was etched under the conditions shown in Table 1, and then the SOC film was etched.

[0554] Then, with Figure 1C Similarly, the W film (indicated by W_1 in Table 1), SiNx\SiOx film, and TaNx\W film were etched in sequence under the conditions shown in Table 1. Here, when etching the TaNx\W film of sample 1A, the lower electrode power was 10W, and when etching the TaNx\W film of sample 1B, the lower electrode power was 25W.

[0555] Then, with Figure 1D Similarly, the etching of the IGZO film was performed under the conditions shown in Table 1. Figure 1E Similarly, etching of the SiOx film was performed under the conditions shown in Table 1.

[0556] Finally, with Figure 1F Similarly, the W film remaining on the SiNx\SiOx film (represented by W_2 in Table 1) is removed by etching under the conditions shown in Table 1.

[0557] Cross-sectional SEM images were taken of the samples 1A and 1B manufactured as described above. The cross-sectional SEM images were taken using "SU8030" manufactured by Hitachi High-Technologies Corporation at an accelerating voltage of 5 kV.

[0558] FIG. 26A to FIG. 27B The cross-sectional SEM images of sample 1A and sample 1B are shown. Fig.26A is a cross-sectional SEM image of a region with a width of 30 nm in the structure of sample 1A. Fig.26B This is a cross-sectional SEM image of a region with a width of 30 nm in the structure of sample 1B. Fig.27A is a cross-sectional SEM image of a region with a width of 60 nm in the structure of sample 1A. Fig.27B This is a cross-sectional SEM image of a region having a width of 60 nm in the structure of Sample 1B.

[0559] like FIG. 26A to FIG. 27B As shown in FIG. 1B , in which the lower electrode power is 25 W, the TaNx\W film is significantly retreated and the width of the structure is narrowed compared to the sample 1A , in which the lower electrode power is 10 W. In other words, Fig.25A and Fig.25B As shown in FIG. 1 , it can be inferred that by reducing the power of the lower electrode, the SOC film remains when etching the TaNx\W film, and thus the W film is not etched. Therefore, one embodiment of the present invention is to Figures 1A to 1F The method shown can process TaNx\W film and IGZO film at one time, so the productivity of semiconductor devices can be improved.

[0560] In particular, the TaNx\W film retreats more in the region where the width of the structure of sample 1B is 30 nm, but the retreat of the TaNx\W film is suppressed in the region where the width of the structure of sample 1A is 30 nm. Therefore, as shown in the above embodiment, in a semiconductor device having a microstructure, by performing processing under the conditions shown in this embodiment, processing can also be performed as designed.

[0561] This embodiment can be combined with other implementation modes and other embodiments as appropriate. [Example 2]

[0562] In this embodiment, the manufacturing FIG. 8A to FIG. 8D The results for the structure shown (hereinafter referred to as sample 2A) are shown.

[0563] Sample 2A was formed by depositing a silicon nitride film (hereinafter referred to as a barrier SiNx film) and a silicon oxide film (hereinafter referred to as an interlayer SiOx film) in sequence on the same structure as sample 1A, and FIG. 8A to FIG. 8D Here, the barrier SiNx film corresponds to the insulator 275, and the interlayer SiOx film corresponds to the insulator 280. In addition, the components corresponding to the sample 1A are referred to in the same way as in the first embodiment.

[0564] First, select FIG. 8A to FIG. 8D The etching conditions required in the process shown are as follows. FIG. 8A to FIG. 8D As shown, when etching the TaNx\W film, it is necessary to prevent the surface of the IGZO film from being etched. Therefore, it is necessary to perform etching in such a way that the etching selectivity ratio between the TaNx\W film and the IGZO film becomes large.

[0565] Therefore, the IGZO film and the TaNx film and W film constituting the TaNx\W film were dry-etched and their etching rates were measured. In addition, the etching selectivity ratio of the TaNx film relative to the IGZO film (hereinafter referred to as the TaNx / IGZO selectivity ratio) and the etching selectivity ratio of the W film relative to the IGZO film (hereinafter referred to as the W / IGZO selectivity ratio) were calculated.

[0566] The dry etching process was performed using an ICP etching device. The etching conditions were as follows: CH 4 Gas 40sccm and Cl 2 Gas: 60 sccm; pressure: 0.67 Pa; ICP power: 1000 W; substrate temperature: -10° C. The etching rate was measured under the conditions where the bias power was set to 10 W, 50 W, and 100 W.

[0567] Fig.28A The measurement results of etching rate are shown. Fig.28B Here, the etching selectivity is shown. Fig.28A In the figure, the horizontal axis represents the bias power (Bias [W]), and the vertical axis represents the etching rate [nm / min]. Fig.28B In the figure, the horizontal axis represents the bias power (Bias [W]), and the vertical axis represents the etching selectivity.

[0568] like Fig.28A As shown in , as the bias power increases, the etching rates of the TaNx film and the W film also increase, but the etching rate of the IGZO film remains almost unchanged. Fig.28BAs shown in the figure, the TaNx / IGZO selectivity and the W / IGZO selectivity are greater than 1.0 under any condition. Under the condition of 100W, where the etching rate of the TaNx film and the W film is the maximum, the TaNx / IGZO selectivity and the W / IGZO selectivity are also significantly large. Therefore, in the manufacture of sample 2A, the bias power when etching the TaNx\W film is set to 100W.

[0569] Next, a method for manufacturing the sample 2A forming the above-mentioned structure will be described.

[0570] First, a structure similar to that of sample 1A was prepared, and a barrier SiNx film was deposited so as to cover the structure composed of a stacked film of SiOx film, IGZO film, TaNx\W film, and SiNx\SiOx film. A barrier SiNx film with a thickness of 5 nm was deposited by the PEALD method. In addition, sample 2A had a region with a width of 30 nm and a region with a width of 60 nm in the structure similarly to sample 1A.

[0571] Next, an interlayer SiOx film is deposited on the barrier SiNx film by sputtering. The interlayer SiOx film is deposited using a silicon target in an oxygen-containing gas atmosphere. The deposited interlayer SiOx film is subjected to CMP treatment to flatten its top surface. The interlayer SiOx film is formed in such a way that the thickness of the film on the SiNx\SiOx film is 45 nm.

[0572] Next, a dry etching process is performed to process the interlayer SiOx film, the barrier SiNx film, and the SiNx\SiOx film to form an opening reaching the TaNx\W film.

[0573] Next, dry etching is performed to separate the TaNx\W film to form Figure 8B The conductors 242a and 242b shown are the source electrode and the drain electrode. Here, the dry etching process is performed using an ICP etching device. The etching conditions are as follows: CF 4 Gas 40sccm and Cl 2 Gas 60 sccm; pressure 0.67 Pa; ICP power 1000 W; bias power 100 W; substrate temperature -10°C.

[0574] In addition, as the above-mentioned opening, the opening width is set to 30nm in the region where the width of the structure is 30nm, and the opening width is set to 60nm in the region where the width of the structure is 60nm. In other words, in the region where the width of the structure is 30nm, it is assumed that the channel length L / channel width W of the transistor is 30nm / 30nm, and in the region where the width of the structure is 60nm, it is assumed that the channel length L / channel width W of the transistor is 60nm / 60nm.

[0575] A cross-sectional SEM image was taken of the sample 2A manufactured as described above. The cross-sectional SEM image was taken using "SU8030" manufactured by Hitachi High-Technologies Corporation at an accelerating voltage of 5 kV.

[0576] FIG. 29A to FIG. 30B A cross-sectional SEM image of sample 2A is shown. Fig.29A This is a cross-sectional SEM image of a region with a width of 30 nm in the channel length direction of the structure. Fig.29B This is a cross-sectional SEM image of a region with a width of 30 nm in the channel width direction of the structure. Fig. 30A This is a cross-sectional SEM image of a region with a width of 60 nm in the channel length direction of the structure. Fig. 30B This is a cross-sectional SEM image of a region of the structure having a width of 60 nm in the channel width direction.

[0577] like Fig.29A and Fig.29B As shown in FIG. 1 , no TaNx\W film remains in the region with a width of 30 nm, and no IGZO film is overetched. Fig. 30A and Fig. 30B As shown, in the region where the width of the structure is 60 nm, no portion where the TaNx\W film remains is observed, and no portion where the IGZO film is over-etched is observed.

[0578] Therefore, by processing the TaNx\W film under the above conditions, the source electrode and the drain electrode can be formed as designed.

[0579] This embodiment can be appropriately combined with other implementation schemes and other embodiments. [Explanation of symbols]

[0580] BL[1]: wiring, BL[j]: wiring, BL[n]: wiring, BL_A: wiring, BL_B: wiring, BL: wiring, BW: signal, CE: signal, CLK: signal, EN_data: signal, GBL_A: wiring, GBL_B: wiring, GBL: wiring, GW: signal, MUX: selection signal, PL[1]: wiring, PL[i]: wiring, PL[m]: wiring, PL: wiring, RDA: signal, RE: control signal, VHH: wiring, VLL: wiring, VPC: intermediate potential, WAKE: signal, WDA: signal, WE: control signal, WL[1]: wiring, WL[i]: wiring, WL[m]: wiring, WL: wiring, 10[ 1,1]: memory cell, 10[i,j]: memory cell, 10[m,n]: memory cell, 10_A: memory cell, 10_B: memory cell, 10: memory cell, 11a: transistor, 11b: transistor, 11c: transistor, 11: transistor, 12a: capacitor, 12: capacitor, 20[1]: memory array, 20[2]: memory array, 20[5]: memory array, 20[m]: memory array, 20: memory array, 21: driver circuit, 22: PSW, 23: PSW, 31: peripheral circuit, 32: controller circuit, 33: voltage generating circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: 5: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: functional layer, 51_A: functional circuit, 51_B: functional circuit, 51: functional circuit, 52_a: transistor, 52_b: transistor, 52: transistor, 53_a: transistor, 53_b: transistor, 53: transistor, 54_a: transistor, 54_b: transistor, 54: transistor, 55_a: transistor, 55_b: transistor, 55: transistor, 70[1]: repeating unit, 70: repeating unit, 71_A: precharge circuit, 71_B: precharge circuit, 72_A: switch circuit, 72_B: switch circuit, 73: write / read circuit, 81_1: transistor, 81 _3: transistor, 81_4: transistor, 81_6: transistor, 82_1: transistor, 82_2: transistor, 82_3: transistor, 82_4: transistor, 83_A: switch, 83_B: switch, 83_C: switch, 83_D: switch, 153: conductor, 154: insulator, 160a: conductor, 160b: conductor, 160: conductor, 200: transistor, 205a: conductor, 205b: conductor, 205: conductor, 207: conductor, 208: insulator, 209: conductor, 210: insulator, 212: insulator, 214: insulator, 215: insulator, 216: insulator, 222: insulator, 224f: insulating film,224: insulator, 230a: oxide, 230af: oxide film, 230b: oxide, 230ba: region, 230bb: region, 230bc: region, 230bf: oxide film, 230: oxide, 240a: conductor, 240b: conductor, 240: conductor, 241: insulator, 242a: conductor, 242a1: conductor, 242a2: conductor, 242b: conductor, 242b1: conductor, 242b2: conductor, 242f: conductive film, 242: conductor, 250a: insulator, 250A: insulating film, 250b: insulator, 250c: insulator, 250d: insulator, 250: insulator, 260a: conductive body, 260A: conductive film, 260b: conductor, 260B: conductive film, 260: conductor, 261: conductor, 271_1: insulator, 271_1f: insulating film, 271_2: insulator, 271_2f: insulating film, 271a: insulator, 271a1: insulator, 271a2: insulator, 271b: insulator, 271b1: insulator, 271b2: insulator, 271: insulator, 275: insulator, 276f: inorganic film, 276: inorganic film, 277f: coating film, 277: coating film, 278f: coating film, 278: coating film, 279: resist mask, 280: insulator, 282: insulator, 283: insulator, 284: Insulator, 285: Insulator, 300A: Memory device, 300: Memory device, 310: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 700: Electronic component, 702: Printed circuit board 704: Circuit board, 711: Mold, 712: Connection pad, 713: Electrode pad, 714: Lead, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 1200: Chip, 1 201: Package substrate, 1202: Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: Analog operation unit, 1214: Storage controller, 1215: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 5110: SD card, 5111: Housing, 5112: Connector, 5113: Substrate, 5115: Controller chip, 5150: SSD, 5151: Housing, 5152: Connector, 5153: Substrate, 5155: Memory chip, 5156: Controller chip, 5200: Portable game console, 5201: Housing, 5202: Display unit, 5203: Button,5300: desktop information terminal, 5301: main body, 5302: display unit, 5303: keyboard, 5400: ICD main body, 5401: battery, 5402: metal wire, 5403: metal wire, 5404: antenna, 5405: subclavian vein, 5406: superior vena cava, 5500: information terminal, 5510: housing, 5511: display unit, 5600: computer, 5610: rack, 5620: computer, 562 1: computer card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 5700: automobile, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator door, 5803: freezer door, 5900: information terminal , 5901: Housing, 5902: Display, 5903: Operation switch, 5904: Operation switch, 5905: Band, 6100: Extension device, 6101: Housing, 6102: Cover, 6103: USB connector, 6104: Substrate, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 63 00: Video camera, 6301: First housing, 6302: Second housing, 6303: Display unit, 6304: Operation switch, 6305: Lens, 6306: Connecting unit, 6800: Artificial satellite, 6801: Main body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7500: Stationary game machine, 7520: Main body, 7522: Controller,

Claims

1. A method for manufacturing a laminate, comprising the following steps: Depositing an oxide semiconductor, a first conductor, a first insulator including a nitride, a second insulator including an oxide, an inorganic film, a first coating film, and a second coating film in sequence on a substrate; forming a resist mask on the second coating film; processing the second coating film by dry etching using the resist mask as a mask to form an island-shaped second coating film; processing the first coating film by dry etching using the island-shaped second coating film as a mask to form an island-shaped first coating film and removing the resist mask; Using the island-shaped first coating film as a mask, the inorganic film, the second insulator, the first insulator, and the first conductor are processed in sequence by dry etching to form an island-shaped inorganic film, an island-shaped second insulator, an island-shaped first insulator, and an island-shaped first conductor, and the island-shaped second coating film is removed; processing the oxide semiconductor by dry etching using the island-shaped inorganic film as a mask to form an island-shaped oxide semiconductor and removing the island-shaped first coating film; as well as The island-shaped inorganic film is removed by dry etching.

2. The method for producing a laminate according to claim 1, The oxide semiconductor includes indium, gallium and zinc.

3. The method for producing a laminate according to claim 1, The first conductor includes tantalum nitride.

4. The method for producing a laminate according to claim 1, The first conductor has a stacked-layer structure of a layer containing tantalum nitride and a layer containing tungsten on the layer containing tantalum nitride.

5. The method for producing a laminate according to claim 1, The first insulator comprises silicon nitride.

6. The method for producing a laminate according to claim 1, The second insulator comprises silicon oxide.

7. The method for producing a laminate according to claim 1, The inorganic film includes tungsten.

8. The method for producing a laminate according to claim 1, The first coating film includes carbon.

9. The method for producing a laminate according to claim 1, The second coating film includes silicon and oxygen.

10. The method for producing a laminate according to claim 1, wherein a third insulator and a fourth insulator are sequentially deposited between the substrate and the oxide semiconductor, After forming the island-shaped oxide semiconductor, the fourth insulator is processed by dry etching using the island-shaped inorganic film as a mask to form the island-shaped fourth insulator.

11. The method for producing a laminate according to claim 10, wherein the third insulator comprises hafnium oxide, And the fourth insulator includes silicon oxide.

12. A method for manufacturing a semiconductor device, comprising the following steps: Manufacturing a laminate using the method for manufacturing a laminate according to any one of claims 1 to 11; Then, dividing the first conductive body into a second conductive body and a third conductive body; and A fifth insulator and a fourth conductor on the fifth insulator are formed so as to overlap with a region between the second conductor and the third conductor.

Images