Fault monitoring method and system for analog integrated circuit

Abstract

The invention discloses a fault monitoring method and system for an analog integrated circuit, and relates to the technical field of integrated circuits, and the method comprises the steps: collecting and recording the electrical parameter data of the analog integrated circuit; preprocessing the electrical parameter data, calculating the resource utilization rate of each subunit and extracting fault feature information; constructing a digital twinborn model corresponding to the analog integrated circuit, and simulating and predicting a fault based on the digital twinborn model; according to the electrical parameter data, the resource utilization rate and the fault feature information, a reinforcement learning algorithm is introduced, and a fault early warning strategy is optimized based on a simulated predicted fault; and according to the fault early warning strategy, early warning thresholds and early warning levels of different fault types are dynamically adjusted, and fault monitoring is realized. According to the invention, abnormal conditions can be found in time, greater damage to the system caused by potential faults is avoided, the real-time performance and accuracy of the monitoring system are ensured, fault information is rapidly provided for maintenance personnel, and the maintenance efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fault monitoring method and system for analog integrated circuits. Background Art

[0002] With the rapid development of electronic technology, analog integrated circuits are playing an increasingly important role in many fields. From automotive electronics, medical equipment to spacecraft, the stability and reliability of analog integrated circuits have a direct impact on the performance and safety of products in these industries. However, when analog integrated circuits operate in complex actual environments, they are often affected by various internal and external factors, such as temperature, humidity, voltage fluctuations, etc., which can cause them to malfunction.

[0003] Traditional analog integrated circuit fault monitoring methods usually rely on manual inspections and periodic testing, which is not only inefficient but also difficult to detect and handle potential faults in a timely manner. In addition, due to the complexity and diversity of analog integrated circuits, traditional rule-based fault diagnosis methods often have difficulty accurately identifying fault types and causes. Summary of the invention

[0004] In view of the above-mentioned problems that the analog integrated circuit fault monitoring method usually relies on manual inspection and regular detection, which is inefficient and difficult to detect, the present invention is proposed.

[0005] Therefore, the technical problems solved by the present invention are:

[0006] To solve the above technical problems, the present invention provides the following technical solutions: a fault monitoring method for an analog integrated circuit, comprising: collecting and recording electrical parameter data of the analog integrated circuit; preprocessing the electrical parameter data, calculating the resource utilization of each subunit and extracting fault feature information; constructing a digital twin model corresponding to the analog integrated circuit, and simulating and predicting faults based on the digital twin model; introducing a reinforcement learning algorithm based on the electrical parameter data, resource utilization and fault feature information, and optimizing the fault warning strategy based on the simulated predicted faults; dynamically adjusting the warning thresholds and warning levels of different fault types according to the fault warning strategy to achieve fault monitoring.

[0007] As a preferred solution of the fault monitoring method of the analog integrated circuit of the present invention, wherein: collecting and recording the electrical parameter data of the analog integrated circuit includes: determining the electrical parameters to be monitored, and selecting corresponding sensors according to the electrical parameters to be monitored; programming the selected sensors into the integrated circuit self-monitoring module, and determining the data collection frequency and data accuracy, and collecting and recording the electrical parameter data of the analog integrated circuit in real time through the self-monitoring module; and converting the collected analog signals into digital signals through the built-in ADC in the analog integrated circuit.

[0008] As a preferred solution of the fault monitoring method of the analog integrated circuit of the present invention, the formula for calculating the resource utilization rate of each sub-unit is as follows:

[0009]

[0010] Among them, U is the resource utilization rate, which indicates the computing resource utilization of the subunit, j is the index of the subunit, s is the number of subunits, P i is the computational power of the subunit, M i is the memory capacity of subunit i, ξ represents the resource weight of the subunit, and T represents the time requirement of the task.

[0011] As a preferred solution of the fault monitoring method of analog integrated circuits of the present invention, wherein: extracting fault-related characteristic information includes classifying the electrical parameter data converted into digital signals according to parameter types, compressing the classified electrical parameter data, and transmitting the compressed electrical parameter data to the central processing unit through a multi-channel transmission protocol; the central processing unit decompresses the received compressed electrical parameter data, and stores the decompressed electrical parameter data into the corresponding sub-unit according to the parameter type; the sub-unit pre-processes the received electrical parameter data through a parallel processor, and extracts features from the pre-processed electrical parameter data through signal processing and feature engineering, and selects and reduces the extracted features through a feature selection algorithm to obtain fault-related characteristic information.

[0012] As a preferred solution of the fault monitoring method of analog integrated circuits of the present invention, wherein: simulating and predicting faults includes constructing relevant mathematical models based on the physical structure and working principle of the analog integrated circuits; constructing a digital twin model based on the relevant mathematical models; mapping the collected electrical parameter data into the digital twin model, and establishing a data transmission interface; inputting the extracted fault feature information into the digital twin model, and using machine learning methods to classify and locate faults; using a prediction algorithm based on the historical data of the integrated circuit and the current state of the integrated circuit to predict faults, and simulating and predicting faults in the digital twin model.

[0013] As a preferred solution of the fault monitoring method of the analog integrated circuit of the present invention, wherein: optimizing the fault warning strategy includes taking the working state, fault characteristics, and resource utilization of the integrated circuit as the input of the state space; taking the warning threshold and the warning level as the action space; designing the reward function based on the accuracy and timeliness of the warning; constructing a deep neural network, training the main Q network, and calculating the target Q value, and the calculation formula of the target Q value is as follows:

[0014] Q′=rt+γ*max(Q′(st+1,a))

[0015] Where Q′ represents the target Q value, rt represents the timely reward obtained in the current step, γ represents the discount factor used to balance the immediate reward and future reward, max(Q′(st+1,a)) represents the maximum Q value of all possible actions a in the next state st+1, and st+1 represents the next state; update the main Q network, evaluate the performance of the main Q network, and adjust the hyperparameters; integrate the trained main Q network and use the main Q network to predict the optimal action; update the experience replay buffer, analyze the performance of the main Q network, adjust the reward function or the main Q network structure according to the performance results of the main Q network, and output the optimized early warning strategy; evaluate and provide feedback on the effectiveness of the optimized early warning strategy based on the impact of simulated predicted failures.

[0016] As a preferred solution of the fault monitoring method of the analog integrated circuit of the present invention, wherein: dynamically adjusting the warning threshold and warning level of different fault types includes: obtaining the latest fault warning strategy from the main Q network, identifying the fault type, and obtaining the corresponding warning threshold reference value according to the identified fault type; using the main Q network, according to the warning threshold reference value, calculating the new warning threshold, and setting the upper and lower limits of the warning threshold; obtaining the default warning level of the current fault type, and adjusting the warning level according to the output of the main Q network; applying the new warning threshold and the adjusted warning level, and triggering the warning of the corresponding warning level when a situation exceeding the new warning threshold is detected; calculating the accuracy, timeliness and false alarm rate of the warning, and using the feedback information for the reward calculation of the next round of reinforcement learning.

[0017] Another object of the present invention is to provide a fault monitoring system for an analog integrated circuit, comprising: a data acquisition module for collecting and recording electrical parameter data of the analog integrated circuit; a feature extraction module for preprocessing the electrical parameter data, calculating the resource utilization of each subunit and extracting fault feature information; a model construction module for constructing a digital twin model corresponding to the analog integrated circuit, and simulating and predicting faults based on the digital twin model; an optimization module for introducing a reinforcement learning algorithm based on electrical parameter data, resource utilization and fault feature information, and optimizing a fault warning strategy based on simulated predicted faults; and a warning module for dynamically adjusting the warning thresholds and warning levels of different fault types according to the fault warning strategy to achieve fault monitoring.

[0018] A computer device includes a memory and a processor, wherein the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the fault monitoring method of the simulated integrated circuit are implemented.

[0019] A computer-readable storage medium stores a computer program thereon, characterized in that when the computer program is executed by a processor, the steps of the above-mentioned method for fault monitoring of an analog integrated circuit are implemented.

[0020] The beneficial effects of the present invention are as follows: through preprocessing and feature extraction, feature information related to faults can be identified and extracted, thereby improving the accuracy of fault diagnosis; by calculating resource utilization and applying load balancing technology, the system can efficiently utilize computing resources and improve overall performance and stability; the constructed digital twin model can accurately reflect and simulate the behavior of the real system; the use of the digital twin model for fault simulation and prediction helps to give timely warnings before a fault occurs and reduce potential losses; the introduction of reinforcement learning algorithms to optimize fault warning strategies enables the system to learn and adapt autonomously, thereby improving the intelligence and reliability of fault monitoring; the warning thresholds and levels are dynamically adjusted according to real-time data and fault characteristics, thereby improving the adaptability and accuracy of the warning system; through optimized warning strategies, false alarms are reduced while ensuring rapid response when a fault occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0022] Figure 1 It is a flow chart of the present invention.

[0023] Figure 2 This is a working mode scenario diagram of the computer device of the present invention.

[0024] Figure 3 Schematic diagram of the self-monitoring module of the present invention.

[0025] Figure 4 A schematic diagram of the structure of the computer device of the present invention. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0027] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0028] Example 1

[0029] like Figures 1 to 3 As shown, an embodiment of the present invention provides a fault monitoring method for an analog integrated circuit, comprising the following steps:

[0030] S1: Collect and record the electrical parameter data of the analog integrated circuit.

[0031] Specifically, a self-monitoring module is embedded in the analog integrated circuit, which can collect and record the electrical parameter data of the analog integrated circuit in real time. The collected data includes but is not limited to parameters such as voltage, current, power consumption, and temperature.

[0032] S2: Preprocess the electrical parameter data, calculate the resource utilization of each subunit and extract fault feature information.

[0033] Specifically, the self-monitoring module is composed of multiple sensors and data acquisition circuits, which can continuously collect parameter data when the analog integrated circuit is running. The collected electrical parameter data is initially processed by the signal processing circuit and then sent to the central processing unit for further analysis and processing.

[0034] Furthermore, electrical parameters that need to be monitored are determined, and corresponding sensors are selected according to the determined electrical parameters that need to be monitored. The electrical parameter data include voltage and current. The voltage is collected by a voltage sensor, and the current is collected by a current sensor.

[0035] Furthermore, the selected sensor is programmed into the self-monitoring module, the data acquisition frequency and accuracy requirements are determined, and the electrical parameter data of the analog integrated circuit is collected and recorded in real time through the self-monitoring module.

[0036] Furthermore, the analog signal of the electrical parameter data of the analog integrated circuit collected and recorded in real time by the self-monitoring module is converted into a digital signal through the built-in ADC. The digital signal can be processed and analyzed more conveniently.

[0037] Furthermore, the electrical parameter data converted into digital signals are classified according to parameter types, and the classified electrical parameter data are compressed, and the compressed electrical parameter data are transmitted to the central processing unit through a multi-channel transmission protocol; the central processing unit decompresses the received electrical parameter data, and stores the decompressed electrical parameter data into different sub-units according to parameter types.

[0038] Furthermore, the sub-unit preprocesses the received electrical parameter data through a parallel processor, and extracts features from the preprocessed electrical parameter data through signal processing and feature engineering, and selects and reduces the dimensionality of the extracted features through a feature selection algorithm to eliminate redundant information and reduce the complexity of the feature space. The feature selection algorithm includes variance threshold and correlation analysis.

[0039] Furthermore, when the subunit preprocesses the received electrical parameter data through the parallel processor, the resource usage rate of each subunit is monitored in real time through the resource manager, and the computing resources of the subunit are balanced through the load balancing technology. The calculation formula of the resource usage rate U is:

[0040]

[0041] Among them, U is the resource utilization rate, which indicates the computing resource utilization of the subunit, j is the index of the subunit, and the value range is 1 to s, where s is the number of subunits, P i is the computing power of the subunit, which indicates the ability of the subunit to perform computing tasks per unit time, M i is the memory capacity of subunit i, indicating the capacity of the subunit that can be used to store data, ξ represents the resource weight of the subunit, which is used to adjust the proportional relationship between computing resources and memory capacity, and T represents the time requirement of the task, that is, the maximum time required to complete the task.

[0042] Furthermore, the above formula, combined with load balancing technology and resource management, helps to achieve effective utilization of system resources and efficient processing of tasks, thereby improving the performance and stability of the entire system. At the same time, through this formula, the resource utilization rate of each sub-unit can be accurately evaluated, so as to timely discover and solve the problem of unbalanced computing resources; using this formula to calculate the resource utilization rate, the computing resources of the sub-units can be balanced and allocated to ensure that the task can be completed in the best way; combined with load balancing technology, the overall resource utilization of the system can be higher and the overall performance of the system can be improved; by considering the task time requirement T, it can ensure that the task is completed within the specified time, improving processing efficiency and real-time performance.

[0043] Furthermore, the central processing unit processes the collected data using signal processing algorithms, statistical analysis methods, etc., to extract characteristic information related to the fault. The statistical analysis algorithms that can be used include but are not limited to spectrum analysis, time domain analysis, frequency domain analysis, etc., which can extract characteristic signals of faults from complex parameter data.

[0044] In summary, the integrity and accuracy of the original data are ensured by classifying, compressing and transmitting the electrical parameter data, as well as decompressing and storing it. In the central processing unit, the parallel processor is used to preprocess the data and extract features, and the feature information related to the fault is extracted through signal processing and feature engineering methods. The feature selection algorithm is used for selection and dimension reduction to eliminate redundant information, thereby improving the accuracy of fault diagnosis; by classifying and compressing the electrical parameter data according to the parameter type and adopting a multi-channel transmission protocol, the bandwidth requirement for data transmission can be effectively reduced, and the transmission time and cost can be reduced; by preprocessing and extracting features from the received electrical parameter data through a parallel processor, hardware resources can be fully utilized to improve processing efficiency and speed; the feature selection algorithm is used for feature selection and dimension reduction processing, which can eliminate redundant information, reduce the complexity of the feature space, and improve the efficiency and accuracy of the fault diagnosis model.

[0045] S3: Build a digital twin model corresponding to the analog integrated circuit, and simulate and predict faults based on the digital twin model.

[0046] Specifically, a detailed mathematical model is constructed based on the physical structure and working principle of the analog integrated circuit, including key information such as circuit topology, component parameters, and operating frequency. The mathematical model includes node equations and loop equations, component models (mathematical models of active and passive devices), state equations (a set of differential equations of circuit state variables changing with time), transfer functions (complex frequency domain expressions of the circuit input-output relationship), frequency response models (amplitude-frequency and phase-frequency characteristics of circuits at different frequencies), noise models (mathematical representations of various noise sources in circuits), temperature effect models (mathematical relationships that describe the impact of temperature changes on circuit parameters and performance), parasitic effect models (including mathematical descriptions of the impact of parasitic capacitance, inductance, etc. on circuit performance), power consumption models, and reliability models (mathematical models of the impact of component aging, fatigue, and other factors on circuit performance).

[0047] Preferably, the mathematical model can be used to predict the performance of the circuit under different operating conditions, such as gain, phase margin, bandwidth, etc. It can also be used to simulate the circuit behavior under fault conditions to help identify factors that may cause the fault.

[0048] Furthermore, a digital twin model is constructed based on the mathematical model. The mathematical model provides a precise mathematical description of the physical system, so that the digital twin model can accurately reflect and simulate the behavior of the real system. The detailed mathematical model includes all key parameters and behaviors of the circuit, ensuring the comprehensiveness and completeness of the digital twin model. The mathematical model enables the digital twin model to predict the performance and behavior of the system under different conditions, including normal operation and fault conditions. It can also help analyze the system's adaptability to environmental changes. The digital twin model can simulate the impact of these changes on system performance.

[0049] Furthermore, the electrical parameter data collected in real time is mapped to the digital twin model to ensure that the digital twin model can accurately reflect the working status of the actual circuit. The digital twin model is synchronized with the real-time data of the actual circuit, and a data transmission interface is established to ensure that the digital twin model can reflect circuit status changes in a timely manner.

[0050] Furthermore, a fault simulation unit is added to the digital twin model to simulate various possible fault types, such as short circuit, open circuit, parameter offset, etc., to analyze the impact of different faults on circuit performance, and the extracted fault feature information is input into the digital twin model, and the support vector machine or decision tree algorithm is used to classify and locate the fault.

[0051] Furthermore, based on historical data and current status, prediction algorithms (such as time series analysis, neural networks, etc.) are used to predict possible failures and simulate the predicted failures in the digital twin model.

[0052] Furthermore, the digital twin model is optimized according to the actual diagnosis results, and the parameters of the digital twin model are adjusted to improve the accuracy and predictive ability of the model.

[0053] S4: According to the electrical parameter data, resource utilization and fault characteristic information, the reinforcement learning algorithm is introduced, and the fault is predicted based on simulation to optimize the fault warning strategy.

[0054] Specifically, the working state, fault characteristics, resource utilization and other parameters of the integrated circuit are used as inputs of the state space, state = [electrical parameter data, fault characteristic information, resource utilization]; the adjustable warning threshold and warning level are used as the action space, action = [warning threshold adjustment amount, warning level adjustment].

[0055] Furthermore, a reward function is designed based on the accuracy and timeliness of the warning, and reward = w1*warning accuracy + w2*warning timeliness - w3*false alarm rate, where w1, w2, and w3 are weight coefficients.

[0056] Furthermore, a deep neural network is designed. The input layer corresponds to the state space dimension; multiple hidden layers are set according to the complexity of the problem; and the output layer corresponds to the action space dimension.

[0057] Furthermore, the DQN algorithm is used to initialize the main Q network and the target Q′ network, the structures of the main Q network and the target Q′ network are the same, and an experience revisit buffer is created.

[0058] Furthermore, for each training round, the current state is obtained, an action is selected (adjusting the warning value and level) using the main Q network and the ε-greedy strategy (a common exploration strategy in reinforcement learning); the action is executed, the new state st+1 and reward rt are observed, the experience (state, action, reward, new state) is stored in the experience replay buffer, a batch of experience is randomly sampled from the experience replay buffer, and the target Q network is calculated to calculate the target Q value. The calculation formula of the target Q value is as follows:

[0059] Q′=rt+γ*max(Q′(st+1,a))

[0060] Among them, Q′ represents the target Q value, rt represents the timely reward obtained in the current step, γ represents the discount factor, which is used to balance the immediate reward and future reward, max(Q′(st+1,a)) represents the maximum Q value of all possible actions a in the next state st+1, and st+1 represents the next state.

[0061] Further, update the main Q network to minimize the loss function L = (Q′-Q(st,at)) 2 , Q′ represents the target Q value, Q(st, at) represents the Q value predicted by the current network for state st and action at, (Q′-Q(st, at)) 2 Represents the square of the difference between the predicted value and the target value (mean square error).

[0062] Furthermore, every N (self-set) steps, the parameters of the main Q network are copied to the target Q network, and the parameters of the main Q network are saved. The performance of the main Q network is evaluated on the validation set, and the hyperparameters (learning rate, discount factor γ, ε, etc.) are adjusted, and training and validation are repeated until the performance meets the requirements.

[0063] Furthermore, the trained main Q network is integrated into the fault monitoring system to obtain status information (electrical parameters, fault characteristics, resource utilization) in real time, and the main Q network is used to predict the optimal action (warning threshold and level adjustment), and the predicted optimal action is applied to the early warning system.

[0064] Furthermore, new operating data is collected regularly and the experience replay buffer is updated with the new data; the main Q network is continuously trained in the background to adapt to new failure modes and environmental changes, the main Q network in the production environment is regularly updated, key performance indicators such as early warning accuracy, timeliness, and false alarm rate are tracked, the performance of the main Q network in different failure types and environments is analyzed, performance reports are generated, and improvement space is identified. Based on the performance analysis results, the reward function or the main Q network structure is adjusted, and the optimized early warning strategy is output.

[0065] Preferably, the optimized early warning strategy is applied to the simulated fault scenario, and the early warning threshold and level are adjusted to observe the system's response to the fault. When the simulated fault occurs, the fault-related data is collected, including the response time, accuracy and false alarm rate of the early warning system, and the accuracy, timeliness and false alarm rate of the early warning are evaluated. The performance of the early warning strategy is quantified using the designed reward function, and the early warning strategy is adjusted according to the simulation results and the feedback of the reward function. This may include adjusting the threshold, warning level or parameters of the deep neural network to further optimize the early warning strategy.

[0066] Preferably, the reinforcement learning method can optimize the early warning strategy as the working environment and conditions of the analog integrated circuit change, so that the system can respond to new failure modes or changing failure characteristics. The reinforcement learning method is used to learn the best early warning time, give warnings in time before the failure occurs, optimize the lead time of the early warning, and leave enough response time for maintenance personnel.

[0067] Furthermore, reinforcement learning is used to learn the complex nonlinear relationship between fault characteristics, circuit parameters and warning decisions, and to discover potential failure modes and warning laws when traditional rules are difficult to define.

[0068] In summary, by introducing reinforcement learning algorithms, the fault warning system can learn and adapt autonomously, continuously optimize its performance, and thus achieve more intelligent, efficient and reliable fault monitoring. This approach enables the system to handle complex failure modes, adapt to dynamically changing environments, and continuously improve in long-term operation, ultimately improving the reliability and maintenance efficiency of analog integrated circuits.

[0069] S5: Dynamically adjust the warning thresholds and warning levels of different fault types according to the fault warning strategy to achieve fault monitoring.

[0070] Specifically, obtain the optimized early warning strategy from the main Q network, analyze the strategy, extract the early warning threshold adjustment amount and early warning level adjustment information, analyze the current circuit status and fault characteristics in real time, use the classification algorithm to identify the current fault type, obtain the corresponding early warning threshold reference value according to the identified fault type, apply the adjustment amount given by the reinforcement learning model, calculate the new early warning threshold, the new threshold = reference threshold + early warning threshold adjustment amount. Set the upper and lower limits of the threshold to ensure that the adjusted threshold is within a reasonable range.

[0071] Furthermore, the default warning level of the current fault type is obtained, and the warning level is adjusted according to the output of the reinforcement learning model, where the new level = default level + warning level adjustment, ensuring that the adjusted level is within a predefined level range (such as level 1-5).

[0072] Furthermore, the new warning thresholds and levels are applied to the real-time monitoring system, the relevant parameters in the fault detection algorithm are updated, real-time monitoring and warning are carried out, the circuit status is continuously monitored, the real-time data is compared with the adjusted warning thresholds, and when a situation exceeding the threshold is detected, the corresponding level of warning is triggered.

[0073] Furthermore, the triggering of each warning, the actual fault situation and the maintenance response are recorded, the accuracy, timeliness and false alarm rate of the warning are calculated, and the feedback information is used for the reward calculation of the next round of reinforcement learning; a fine-tuning cycle is set (such as every hour or every day), and at the end of each fine-tuning cycle, the warning effect is evaluated, and according to the evaluation results, small adjustments are made using the preset fine-tuning rules; thresholds and level change limits are set, and when abnormally large adjustments are detected, the manual review mechanism is triggered.

[0074] Furthermore, a rollback mechanism is set up to allow quick recovery to a previous stable configuration.

[0075] Furthermore, the adjustment process of each threshold and level is recorded in detail, and a summary report of the optimization effect is generated. The warning effect data is fed back to the reinforcement learning model, and the experience playback buffer is updated with this data to continuously optimize the reinforcement learning model without affecting real-time monitoring.

[0076] Preferably, a reinforcement learning algorithm is used to automatically adjust the trigger threshold of the fault warning according to different fault types and operating environments; enable the warning system to adapt to changes in the working state of the integrated circuit and improve the accuracy of the warning; learn and adjust the severity classification of different fault types to ensure that more important or urgent faults receive a higher warning level; through continuous learning, while reducing the false alarm rate and maintaining a high detection rate, the best balance can be found to avoid overly sensitive or overly conservative warnings.

[0077] In summary, through the above steps, the system can dynamically adjust the warning threshold and warning level of different fault types according to the fault warning strategy to achieve adaptive fault monitoring and warning. It can improve the accuracy and timeliness of warning, reduce false alarms, and improve the efficiency and reliability of the entire analog integrated circuit fault monitoring system.

[0078] Example 2

[0079] Reference Figure 1 to Figure 3 , as an embodiment of the present invention, provides a fault monitoring system for an analog integrated circuit, comprising:

[0080] A data acquisition module, used to collect and record electrical parameter data of analog integrated circuits;

[0081] Feature extraction module, used to pre-process electrical parameter data, calculate resource utilization of each sub-unit and extract fault feature information;

[0082] A model building module is used to build a digital twin model corresponding to the analog integrated circuit, and simulate and predict faults based on the digital twin model;

[0083] The optimization module is used to introduce reinforcement learning algorithms based on electrical parameter data, resource utilization, and fault characteristic information, and optimize fault warning strategies based on simulated predicted faults;

[0084] The early warning module is used to dynamically adjust the early warning thresholds and early warning levels of different fault types according to the fault early warning strategy to achieve fault monitoring.

[0085] Example 3

[0086] Reference Figure 4 , which is the third embodiment of the present invention. Based on the first two embodiments, the embodiment of the present invention provides a computer device, which may be a server, and its internal structure diagram may be as shown in FIG. Figure 4 As shown. The computer device includes a processor, a memory and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium.

[0087] The database of the computer device is used to store action detection data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps in any of the above-mentioned sparse tensor operation acceleration method embodiments are implemented.

[0088] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0089] In one embodiment, an embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in any of the above-mentioned sparse tensor operation acceleration method embodiments are implemented.

[0090] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0091] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A fault monitoring method for an analog integrated circuit, characterized in that: include: Collect and record electrical parameter data of analog integrated circuits; Preprocessing the electrical parameter data, calculating the resource utilization of each subunit and extracting fault characteristic information; Build a digital twin model corresponding to the analog integrated circuit, and simulate and predict faults based on the digital twin model; According to the electrical parameter data, resource utilization and fault characteristic information, the reinforcement learning algorithm is introduced, and the fault warning strategy is optimized based on the simulated predicted faults; According to the fault warning strategy, the warning thresholds and warning levels of different fault types are dynamically adjusted to achieve fault monitoring.

2. The fault monitoring method for an analog integrated circuit according to claim 1, wherein: The collecting and recording of electrical parameter data of the analog integrated circuit includes: Determine the electrical parameters that need to be monitored and select the corresponding sensors according to the electrical parameters that need to be monitored; The selected sensor is programmed into the integrated circuit self-monitoring module, and the data acquisition frequency and data accuracy are determined, and the electrical parameter data of the analog integrated circuit is collected and recorded in real time through the self-monitoring module; The collected analog signal is converted into a digital signal through the ADC built into the analog integrated circuit.

3. The fault monitoring method for an analog integrated circuit as claimed in claim 2, wherein: The formula for calculating the resource utilization of each subunit is as follows: Among them, U is the resource utilization rate, which indicates the computing resource utilization of the subunit, j is the index of the subunit, s is the number of subunits, P i is the computational power of the subunit, M i is the memory capacity of subunit i, ξ represents the resource weight of the subunit, and T represents the time requirement of the task.

4. The fault monitoring method of an analog integrated circuit as claimed in claim 3, characterized in that: The extraction of fault-related characteristic information includes: Classifying the electrical parameter data converted into digital signals according to parameter types, compressing the classified electrical parameter data, and transmitting the compressed electrical parameter data to a central processing unit through a multi-channel transmission protocol; The central processing unit decompresses the received compressed electrical parameter data and stores the decompressed electrical parameter data into the corresponding sub-unit according to the parameter type; The subunit preprocesses the received electrical parameter data through a parallel processor, extracts features from the preprocessed electrical parameter data through signal processing and feature engineering, selects and reduces the dimensions of the extracted features through a feature selection algorithm, and obtains fault-related feature information.

5. The fault monitoring method for an analog integrated circuit as claimed in claim 4, characterized in that: The simulation prediction failure includes: Construct relevant mathematical models based on the physical structure and working principle of analog integrated circuits; Build a digital twin model based on relevant mathematical models; Map the collected electrical parameter data into the digital twin model and establish a data transmission interface; The extracted fault feature information is input into the digital twin model, and the fault classification and location are performed using machine learning methods; Based on the historical data of the integrated circuit and the current status of the integrated circuit, a prediction algorithm is used to predict failures, and the predicted failures are simulated in the digital twin model.

6. The fault monitoring method of an analog integrated circuit as claimed in claim 5, characterized in that: The optimized fault warning strategy includes: The working state, fault characteristics and resource utilization of the integrated circuit are used as inputs of the state space; Use warning thresholds and warning levels as action space; Design reward functions based on warning accuracy and timeliness; Construct a deep neural network, train the main Q network, and calculate the target Q value. The calculation formula of the target Q value is as follows: Q′=rt+γ*max(Q′(st+1,a)) Where Q′ represents the target Q value, rt represents the immediate reward obtained in the current step, γ represents the discount factor, which is used to balance the immediate reward and future reward, max(Q′(st+1,a)) represents the maximum Q value of all possible actions a in the next state st+1, and st+1 represents the next state; Update the main Q network, evaluate the performance of the main Q network, and adjust hyperparameters; Integrate the trained main Q network and use it to predict the optimal action; Update the experience replay buffer, analyze the performance of the main Q network, adjust the reward function or the main Q network structure according to the performance results of the main Q network, and output the optimized early warning strategy; Based on simulation prediction of faults, the effectiveness of the optimized early warning strategy is evaluated and feedback is given.

7. The fault monitoring method of an analog integrated circuit as claimed in claim 6, characterized in that: The dynamic adjustment of the warning thresholds and warning levels of different fault types includes: Get the latest fault warning strategy from the main Q network, Identify the fault type, and obtain the corresponding warning threshold reference value according to the identified fault type; Use the main Q network to calculate the new warning threshold according to the warning threshold reference value, and set the upper and lower limits of the warning threshold; Get the default warning level of the current fault type and adjust the warning level according to the output of the main Q network; The new warning threshold and the adjusted warning level are applied, and when a situation exceeding the new warning threshold is detected, a warning of the corresponding warning level is triggered; The accuracy, timeliness and false alarm rate of the early warning are calculated, and the feedback information is used for reward calculation in the next round of reinforcement learning.

8. A system using the fault monitoring method of an analog integrated circuit as claimed in any one of claims 1 to 7, characterized in that: include, A data acquisition module, used to collect and record electrical parameter data of analog integrated circuits; A feature extraction module, used to pre-process the electrical parameter data, calculate the resource utilization of each sub-unit and extract fault feature information; A model building module is used to build a digital twin model corresponding to the analog integrated circuit, and simulate and predict faults based on the digital twin model; The optimization module is used to introduce reinforcement learning algorithms based on electrical parameter data, resource utilization, and fault characteristic information, and optimize fault warning strategies based on simulated predicted faults; The early warning module is used to dynamically adjust the early warning thresholds and early warning levels of different fault types according to the fault early warning strategy to achieve fault monitoring.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the fault monitoring method for an analog integrated circuit according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the fault monitoring method for an analog integrated circuit according to any one of claims 1 to 7 are implemented.

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