Thermal resistance testing method, device and equipment for silicon optical chip packaging structure

Abstract

The embodiment of the invention provides a thermal resistance testing method, device and equipment for a silicon optical chip packaging structure, and the method comprises the steps: taking a heating fixed-value resistor in a silicon optical chip as a heat source, enabling a substrate of the silicon optical chip packaging structure to be pasted on a constant-temperature heat sink, enabling transient thermal resistance testing equipment to be connected to the silicon optical chip and the constant-temperature heat sink, and testing the thermal resistance of the silicon optical chip packaging structure. Testing to obtain a first integral structure function curve; replacing the material of a heat conduction layer to be tested in the packaging structure of the silicon optical chip, and testing to obtain a second integral structure function curve; according to the separation point of the first integral structure function curve and the second integral structure function curve, determining the thermal resistance value of the upper surface and the thermal resistance value of the lower surface of the to-be-measured heat conduction layer; and calculating the thermal resistance value of the to-be-measured heat conduction layer according to the thermal resistance value of the upper surface and the thermal resistance value of the lower surface of the to-be-measured heat conduction layer. According to the scheme, testing of local thermal resistance of each different heat conduction layer in the silicon optical chip packaging structure is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and in particular to a method, device and equipment for testing the thermal resistance of a silicon photonic chip packaging structure. Background Art

[0002] The integrated silicon-based optoelectronic chip (also known as silicon photonic chip) packaging is achieved by integrating optical paths and circuits into a single packaging structure to reduce costs and shorten the transmission distance required for electrical signals, thereby realizing the integration of silicon photonic chips. However, as the interconnection scale of the chip decreases, the regional thermal effect inside the silicon photonic chip packaging structure will increase, and the chip junction temperature will rise as the thermal effect increases. The increase in junction temperature will lead to a decrease in the optical performance, stability, and life of the silicon photonic chip.

[0003] The transient thermal resistance test based on the T3ster system is an effective way to test the thermal resistance of semiconductor devices, with the advantages of non-destructive detection and high test accuracy. In actual operation, the transient thermal resistance test of semiconductor devices can obtain a structure function curve with a relatively obvious slope change. The structure function curve can be partitioned by the inflection point on the structure function curve, and then the thermal resistance of each area in the package structure can be determined.

[0004] The existing patent CN114544699A proposes a method for testing the thermal resistance and thermal conductivity of a material. The method uses a MOSFET power device as a heating source, and successively mounts the MOSFET power device on the material to be tested and a constant temperature heat sink. A thermal resistance testing device is used to record the first heating curve and the second heating curve respectively, and the thermal resistance of the material to be tested is calculated based on the fitting of the first and second heating curves.

[0005] The existing patent CN103837822A proposes a method for junction-to-case thermal resistance testing of a very large-scale integrated circuit. There is no need to use a dedicated thermal resistance test chip. Instead, a heating unit and a temperature sensitive unit for thermal resistance testing are established according to the characteristics of the integrated circuit being tested to perform thermal resistance testing. For example, the isolation diode between the core power supply and ground of the integrated circuit is used as a heating unit, and the isolation diode between the peripheral power supply and ground is used as a temperature sensitive unit.

[0006] However, using MOSFET power devices as heating sources has the problem that the power consumption of the heat source is difficult to control, and its measurement range and accuracy are limited; and the method of establishing a heating unit and a temperature sensitive unit for thermal resistance testing based on the characteristics of the integrated circuit under test has the problem that it can only test the overall thermal resistance of the temperature sensitive unit, and cannot test the thermal resistance of the local area; and the above two test methods are not compatible when applied to silicon photonic chip packaging.

[0007] Therefore, there is currently no thermal resistance testing method for silicon photonic chip packaging modules. Summary of the invention

[0008] In view of this, an embodiment of the present invention provides a method for testing the thermal resistance of a silicon photonic chip packaging structure to solve the technical problem that the local thermal resistance of a silicon photonic chip packaging structure cannot be tested in the prior art. The method includes:

[0009] A heating constant value resistor in a silicon photonic chip is used as a heat source, the package structure to be tested of the silicon photonic chip is referred to as a first package structure, a substrate of the first package structure is mounted on a constant temperature heat sink, a transient thermal resistance test device is connected to the silicon photonic chip and the constant temperature heat sink, and a first integral structure function curve is obtained by testing;

[0010] After replacing the material of the heat-conducting layer to be tested in the packaging structure of the silicon photonic chip, a second packaging structure is obtained, a substrate of the second packaging structure is mounted on the constant temperature heat sink, the transient thermal resistance test equipment is connected to the silicon photonic chip and the constant temperature heat sink, and a second integral structure function curve is obtained by testing;

[0011] Determining a thermal resistance value at an upper surface and a thermal resistance value at a lower surface of the thermal conductive layer to be measured in the first packaging structure according to a separation point of the first integrated structure function curve and the second integrated structure function curve;

[0012] The thermal resistance value of the thermal conductive layer to be measured in the first packaging structure is calculated according to the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured.

[0013] The embodiment of the present invention also provides a thermal resistance testing device for a silicon photonic chip packaging structure to solve the technical problem that the local thermal resistance of a silicon photonic chip packaging structure cannot be tested in the prior art. The device includes:

[0014] A first testing unit is used for testing and obtaining a first integral structure function curve when a heating fixed value resistor in a silicon photonic chip is used as a heat source, a substrate of a first packaging structure is mounted on a constant temperature heat sink, and a transient thermal resistance testing device is connected to the silicon photonic chip and the constant temperature heat sink, wherein the packaging structure to be tested of the silicon photonic chip is referred to as the first packaging structure;

[0015] A second testing unit is used to obtain a second packaging structure after replacing the material of the heat-conducting layer to be tested in the first packaging structure, and to obtain a second integral structure function curve by testing when the substrate of the second packaging structure is mounted on the constant temperature heat sink and the transient thermal resistance testing device is connected to the silicon photonic chip and the constant temperature heat sink;

[0016] a first calculation unit, configured to determine a thermal resistance value at an upper surface and a thermal resistance value at a lower surface of the thermal conductive layer to be measured in the first packaging structure according to a separation point of the first integral structure function curve and the second integral structure function curve;

[0017] The second calculation unit is used to calculate the thermal resistance value of the thermal conductive layer to be measured in the first packaging structure according to the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured.

[0018] An embodiment of the present invention further provides a computer device, comprising a thermal resistance testing device for any of the above-mentioned silicon photonic chip packaging structures.

[0019] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least: it is proposed to use the heating constant value resistor in the silicon photonic chip as the heat source, to mount the substrate in the first packaging structure on the constant temperature heat sink, to connect the transient thermal resistance test equipment to the silicon photonic chip and the constant temperature heat sink for thermal resistance test, to obtain a first integral structure function curve, and to replace the material of the thermal conductive layer to be tested in the packaging structure of the silicon photonic chip to obtain a second packaging structure, to mount the substrate of the second packaging structure on the constant temperature heat sink, to connect the transient thermal resistance test equipment to the silicon photonic chip and the constant temperature heat sink, to test and obtain a second integral structure function curve, and then to obtain a second integral structure function curve according to the first integral structure function curve and the second integral structure function curve. The separation point of the integral structure function curve is determined, the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure are determined, and the thermal resistance value of the thermal conductive layer to be measured in the first packaging structure is calculated according to the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured, so that the thermal resistance of each thermal conductive layer in the packaging structure of the silicon photonic chip can be tested, and then the thermal resistance of different local areas in the silicon photonic chip packaging structure can be determined, which is conducive to providing data basis for targeted heat dissipation optimization of the silicon photonic chip packaging structure; at the same time, the thermal resistance test uses the heating fixed value resistor in the silicon photonic chip as the heat source, without introducing an additional heat source, so as to avoid the problem of difficult control of power consumption of the additional heat source, which is conducive to improving the convenience and measurement accuracy of the thermal resistance test. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1It is a flow chart of a thermal resistance testing method of a silicon photonic chip packaging structure provided by an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a packaging structure of a silicon photonic chip provided by an embodiment of the present invention;

[0023] Figure 3 This is a simplified schematic diagram of a packaging structure of a silicon photonic chip provided by an embodiment of the present invention before and after material replacement and addition of a thermally conductive silicone layer;

[0024] Figure 4 is a schematic diagram of a first integral structure function curve and a second integral structure function curve provided by an embodiment of the present invention drawn in the same coordinate system;

[0025] Figure 5 It is a schematic diagram of a first integral structure function curve being translated and overlapping with the tail of a second integral structure function curve provided by an embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of multiple separation points on the same first integral structure function curve provided by an embodiment of the present invention;

[0027] Figure 7 It is a schematic diagram of a first integral structure function curve and a third integral structure function curve provided by an embodiment of the present invention drawn in the same coordinate system;

[0028] Figure 8 It is a structural block diagram of a thermal resistance testing device for a silicon photonic chip packaging structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0030] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0031] In an embodiment of the present invention, a method for testing the thermal resistance of a silicon photonic chip packaging structure is provided. Figure 1 As shown, the method includes:

[0032] Step S101: using a heating constant value resistor in a silicon photonic chip as a heat source, calling the package structure to be tested of the silicon photonic chip a first package structure, mounting a substrate of the first package structure on a constant temperature heat sink, connecting a transient thermal resistance test device to the silicon photonic chip and the constant temperature heat sink, and obtaining a first integral structure function curve through testing;

[0033] Step S102: After replacing the material of the thermal conductive layer to be tested in the first packaging structure, a second packaging structure is obtained, a substrate of the second packaging structure is mounted on the constant temperature heat sink, the transient thermal resistance test equipment is connected to the silicon photonic chip and the constant temperature heat sink, and a second integral structure function curve is obtained by testing;

[0034] Step S103: determining the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure according to the separation point of the first integrated structure function curve and the second integrated structure function curve;

[0035] Step S104: calculating the thermal resistance value of the thermal conductive layer to be measured in the first packaging structure according to the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured.

[0036] Depend on Figure 1 It can be seen from the shown process that in the embodiment of the present invention, it is possible to test the thermal resistance of each different thermal conductive layer in the packaging structure of the silicon photonic chip, and thus it is possible to determine the thermal resistance of different local areas in the silicon photonic chip packaging structure, which is beneficial for providing data basis for targeted heat dissipation optimization of the silicon photonic chip packaging structure; at the same time, the thermal resistance test uses the heating fixed value resistor in the silicon photonic chip as the heat source, without the need to introduce additional heat sources, thereby avoiding the problem of difficult to control the power consumption of additional heat sources, which is beneficial for improving the convenience and measurement accuracy of the thermal resistance test.

[0037] When implementing it, Figure 2 As shown in FIG. 1 , the packaging structure of the silicon photonic chip includes a silicon photonic chip 11, a TiN fixed resistor 12, a waveguide 13, a chip pad 14, a gold wire 15, a thermal adhesive 16, a ceramic substrate pad 17, and a ceramic substrate 18. The silicon photonic chip 11 is mounted on the ceramic substrate 18 through the thermal adhesive 16 to achieve heat conduction. The chip pad 14 is connected to the ceramic substrate pad 17 through the gold wire 15 to achieve electrical connection. In order to facilitate the illustration of the thermal resistance test process, the packaging structure of the silicon photonic chip is simplified to the silicon photonic chip 11, the thermal adhesive 16, and the ceramic substrate 18. Figure 3(a) is referred to as the first packaging structure A. After replacing the material of the thermal conductive layer to be tested in the first packaging structure A, the second packaging structure B is obtained. That is, the first packaging structure A and the second packaging structure B are different only in the material of the thermal conductive layer to be tested. For example, when the thermal conductive adhesive 16 is used as the thermal conductive layer to be tested, the simplified structure of the packaging structure of the silicon photonic chip (i.e., the second packaging structure B) after replacing the material of the thermal conductive adhesive 16 is as follows Figure 3 (c) shows the thermal conductive adhesive 161 after the material is replaced.

[0038] In a specific implementation, through the thermal resistance testing method of the silicon photonic chip packaging structure, the thermal resistance of any thermal conductive layer to be tested in the silicon photonic chip packaging structure can be tested based on the first integral structure function curve and the second integral structure function curve. In the process of obtaining the first integral structure function curve and the second integral structure function curve, the substrates of the first packaging structure A and the second packaging structure B can be directly mounted on the constant temperature heat sink 21, or can be mounted on the constant temperature heat sink 21 through the same thermal conductive silicone 22, such as Figure 3 (b) and 3(c).

[0039] In specific implementation, the ceramic substrate 18 of the first packaging structure A is attached to the constant temperature heat sink 21, and the thermal resistance test is performed using the T3ster thermal resistance testing equipment to obtain a first integral structure function curve, the horizontal coordinate of the integral structure function curve is the thermal resistance (in K / W), and the vertical coordinate is the thermal capacitance (in K / Ws); when the thermal conductive adhesive 16 is taken as the thermal conductive layer to be tested as an example, after replacing the material of the thermal conductive adhesive 16, the ceramic substrate 18 of the second packaging structure B is attached to the constant temperature heat sink 21, and the thermal resistance test is performed using the T3ster thermal resistance testing equipment to obtain the second integral structure function curve.

[0040] In specific implementation, the process of testing the thermal resistance of materials or semiconductor devices using the transient thermal resistance test method in the prior art is to test the thermal resistance curve including the material or semiconductor device and the thermal resistance curve without the material or semiconductor device, respectively. In this way, the difference between the two thermal resistance curves can be calculated to obtain the thermal resistance of the entire material or semiconductor device. However, this test method cannot be used to test the local thermal resistance of the packaging structure of the silicon photonic chip. In order to test the thermal resistance of different local thermal conductive layers in the packaging structure of the silicon photonic chip, it is proposed to test two integral structure function curves before and after the material of the thermal conductive layer to be tested is replaced, and then a method for determining the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be tested based on the separation point of the two integral structure function curves is proposed. For example,

[0041] The first integral structure function curve and the second integral structure function curve are plotted in the same coordinate system, and a first separation point α of the first integral structure function curve and the second integral structure function curve is obtained, such as Figure 4 As shown, the horizontal coordinate value of the first separation point α is the thermal resistance value at the upper surface of the thermal conductive layer to be measured;

[0042] The first integral structure function curve is translated (i.e., the horizontal and vertical coordinates of the first integral structure function curve are translated) so that the first integral structure function curve after translation coincides with the tail of the second integral structure function curve, such as Figure 5 As shown, a second separation point β is obtained, and the abscissa value of the second separation point β is the thermal resistance value at the lower surface of the thermal conductive layer to be measured after the material is replaced;

[0043] The thermal resistance value at the lower surface of the heat-conducting layer to be measured in the first packaging structure is determined according to the first integrated structure function curve and the coordinate value of the second separation point.

[0044] In specific implementation, in order to determine the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure (i.e., the thermal conductive layer to be measured before the material is replaced) according to the thermal resistance at the lower surface of the thermal conductive layer to be measured after the material is replaced, the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure can be calculated or determined through a neural network model according to the coordinate value of the second separation point, the relevant thermal resistance parameters of the replacement material, the relevant thermal resistance parameters of the raw material of the thermal conductive layer to be measured, and the slope of the first integral structure function curve. However, in order to conveniently, efficiently, and accurately determine the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure, this embodiment proposes the following method:

[0045] The coordinate value of the second separation point is translated (i.e., the horizontal and vertical coordinates of the second separation point are translated, and the second separation point can be translated in the reverse direction with reference to the translation amount of the first integral structure function curve), so that the second separation point β' and the first separation point α after translation are on the same first integral structure function curve (i.e., the first integral structure function curve before translation), such as Figure 6 As shown;

[0046] Based on the first integral structure function curve, the coordinate value of the first separation point α is subtracted from the coordinate value of the second separation point β' after translation, and the obtained horizontal coordinate difference is determined as the thermal resistance of the thermal conductive layer to be measured (before material replacement) in the first packaging structure.

[0047] In specific implementation, in order to improve the efficiency of thermal resistance testing, this embodiment proposes a method for efficiently and accurately selecting a replacement material for the thermal conductive layer to be tested in the first packaging structure, for example,

[0048] Based on the dimensional characteristics of the thermally conductive layer to be measured (e.g., longitudinal dimension, transverse dimension, etc.), selecting a thermally conductive material having a transverse thermal conductivity and / or a longitudinal thermal conductivity greater than a preset threshold value;

[0049] The selected thermally conductive material is used to replace the material of the thermally conductive layer to be tested in the first packaging structure.

[0050] In specific implementation, in order to effectively select a thermally conductive material whose lateral thermal conductivity and / or longitudinal thermal conductivity is greater than a preset threshold value (the value of the preset threshold value can be determined according to the actual thermal resistance requirement of the packaging structure) at low cost, the following method is proposed:

[0051] Comsol transient heat transfer simulation is performed on multiple candidate thermal conductive materials to determine the transverse thermal conductivity and longitudinal thermal conductivity of each candidate thermal conductive material.

[0052] Among the plurality of candidate thermally conductive materials, a thermally conductive material having a transverse thermal conductivity and / or a longitudinal thermal conductivity greater than a preset threshold is selected.

[0053] In specific implementation, the transverse thermal conductivity and longitudinal thermal conductivity of multiple candidate thermal conductive materials can be confirmed based on the COMSOL transient heat transfer simulation. For example, for thermal conductive adhesives, the longitudinal dimension is small and the heat transfer is fast, so the screening is mainly based on the transverse thermal conductivity, and thermal conductive adhesive materials with larger transverse thermal conductivity are given priority. For substrates or PCB boards, their longitudinal dimensions are large, and it is necessary to give priority to the longitudinal thermal conductivity of the substrate material, while taking into account the transverse thermal conductivity, and give priority to materials with larger longitudinal and transverse thermal conductivity. Therefore, after simulating the transverse thermal conductivity and longitudinal thermal conductivity of the selected material through COMSOL transient heat transfer simulation, it can provide effective and reliable data basis for thermal resistance test replacement materials, which is conducive to achieving high thermal conductivity and low thermal resistance of the overall material of the packaging structure.

[0054] In specific implementation, in order to further realize the use of an intrinsic, stable heating constant value resistor as a heat source, this embodiment proposes using a TiN heating constant value resistor in the silicon photonic chip as a heat source.

[0055] In specific implementation, in order to improve the efficiency of thermal resistance testing, reduce the testing process, and strive to determine the thermal resistances of multiple different thermal conductive layers with fewer tests, this embodiment proposes the following method:

[0056] In the process of testing and obtaining the first integral structure function curve, the substrate of the first packaging structure is pasted on the constant temperature heat sink through a thermally conductive silicone layer;

[0057] The substrate of the first packaging structure is directly mounted on the constant temperature heat sink (such as Figure 3(a), connecting a transient thermal resistance test device to the silicon photonic chip and the constant temperature heat sink, and testing to obtain a third integral structure function curve;

[0058] A third separation point γ is determined based on the first integral structure function curve and the third integral structure function curve (for example, Figure 7 As shown, the first integral structure function curve and the third integral structure function curve are plotted in the same coordinate system to obtain a third separation point γ), and the abscissa value of the third separation point is the thermal resistance value at the upper surface of the thermally conductive silicone layer;

[0059] The thermal resistance value of the substrate is calculated according to the thermal resistance value at the lower surface of the thermally conductive layer to be measured and the thermal resistance value at the upper surface of the thermally conductive silicone layer (for example, Figure 6 As shown, based on the first integral structure function curve, the thermal conductive layer to be measured takes thermal conductive adhesive as an example, and the thermal resistance of the substrate can be obtained by subtracting the horizontal coordinate of the second separation point β' after translation from the horizontal coordinate of the third separation point γ, wherein the thermal conductive layer to be measured is located on the upper surface of the substrate.

[0060] In this way, on the basis of obtaining the first integral structure function curve in the process of testing the thermal resistance of the thermal conductive layer to be tested located on the upper surface of the substrate, after directly mounting the substrate of the first packaging structure on the constant temperature heat sink to test the third integral structure function curve, the thermal resistance value of the upper surface of the thermal conductive silicone layer (i.e., the lower surface of the substrate) can be tested based on the third separation point determined by the first integral structure function curve and the third integral structure function curve, and then the thermal resistance of the substrate can be calculated in combination with the thermal resistance value of the lower surface of the thermal conductive layer to be tested located on the upper surface of the substrate, which can avoid the process of replacing the material of the substrate and performing two tests before and after the replacement of the material.

[0061] In the packaging structure of silicon photonic chips, the thermal conductive layer can be made of materials other than thermal conductive adhesive, such as ceramic substrates and PCB boards. The thermal resistance of each of these thermal conductive layers can be tested using the thermal resistance test method of the silicon photonic chip packaging structure described above, and then the thermal resistance of different thermal conductive layers in the entire packaging structure can be calculated. After obtaining the thermal resistance of different thermal conductive layers, the heat dissipation of the silicon photonic chip packaging structure can be optimized in a targeted manner. For example, if the thermal resistance of the thermal conductive adhesive is large, the thermal resistance of the thermal conductive adhesive layer can be reduced by replacing it with a thermal conductive adhesive with higher thermal conductivity or by improving the thermal conductive adhesive patch process.

[0062] Based on the same inventive concept, a thermal resistance testing device for a silicon photonic chip packaging structure is also provided in an embodiment of the present invention, as described in the following embodiments. Since the principle of solving the problem by the thermal resistance testing device for a silicon photonic chip packaging structure is similar to that of the thermal resistance testing method for a silicon photonic chip packaging structure, the implementation of the thermal resistance testing device for a silicon photonic chip packaging structure can refer to the implementation of the thermal resistance testing method for a silicon photonic chip packaging structure, and the repeated parts will not be repeated. As used below, the terms "unit" or "module" may be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation in hardware, or a combination of software and hardware, is also possible and conceivable.

[0063] Figure 8 is a structural block diagram of a thermal resistance testing device for a silicon photonic chip packaging structure according to an embodiment of the present invention. Figure 8 As shown, including:

[0064] The first test unit 801 is used to test and obtain a first integral structure function curve when a heating fixed value resistor in a silicon photonic chip is used as a heat source, a substrate of a first packaging structure is mounted on a constant temperature heat sink, and a transient thermal resistance test device is connected to the silicon photonic chip and the constant temperature heat sink, wherein the packaging structure to be tested of the silicon photonic chip is referred to as the first packaging structure;

[0065] A second testing unit 802 is configured to obtain a second packaging structure after replacing the material of the heat-conducting layer to be tested in the first packaging structure, and obtain a second integral structure function curve by testing when the substrate of the second packaging structure is mounted on the constant temperature heat sink and the transient thermal resistance testing device is connected to the silicon photonic chip and the constant temperature heat sink;

[0066] A first calculation unit 803 is used to determine the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure according to the separation point of the first integral structure function curve and the second integral structure function curve;

[0067] The second calculation unit 804 is used to calculate the thermal resistance value of the thermal conductive layer to be measured in the first packaging structure according to the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured.

[0068] In a specific implementation, the first test unit 801 and the first test unit 802 may be transient thermal resistance test equipment, and the first calculation unit 803 and the second calculation unit 804 may be any equipment with calculation function, such as a computer, a server, etc.

[0069] In one embodiment, the first calculating unit 803 is used to plot the first integral structure function curve and the second integral structure function curve in the same coordinate system, obtain a first separation point of the first integral structure function curve and the second integral structure function curve, the abscissa value of the first separation point is the thermal resistance value at the upper surface of the thermal conductive layer to be measured; translate the first integral structure function curve so that the translated first integral structure function curve and the tail of the second integral structure function curve coincide with each other, obtain a second separation point, the abscissa value of the second separation point is the thermal resistance value at the lower surface of the thermal conductive layer to be measured after material replacement; determine the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure according to the coordinate values ​​of the first integral structure function curve and the second separation point.

[0070] In one embodiment, the first calculation unit 803 is used to translate the coordinate value of the second separation point so that the second separation point and the first separation point after translation are on the same first integral structure function curve, and the horizontal coordinate value of the second separation point after translation is determined as the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure.

[0071] In one embodiment, the first testing unit 801 is used to test and obtain the first integral structure function curve when the substrate of the first packaging structure is placed on the constant temperature heat sink through a thermally conductive silicone layer patch;

[0072] The second testing unit 802 is further used to test and obtain a third integral structure function curve when the substrate of the first packaging structure is directly mounted on the constant temperature heat sink and a transient thermal resistance testing device is connected to the silicon photonic chip and the constant temperature heat sink;

[0073] The first calculation unit 803 is further used to determine a third separation point according to the first integral structure function curve and the third integral structure function curve, wherein the abscissa value of the third separation point is the thermal resistance value at the upper surface of the thermally conductive silicone layer;

[0074] The second calculation unit 804 is further used to calculate the thermal resistance value of the substrate according to the thermal resistance value at the lower surface of the thermal conductive layer to be measured and the thermal resistance value at the upper surface of the thermal conductive silicone layer, wherein the thermal conductive layer to be measured is located on the upper surface of the substrate.

[0075] In this embodiment, a computer device is provided, including any of the above-mentioned thermal resistance testing devices for the silicon photonic chip packaging structure.

[0076] Specifically, the computer device may be a computer terminal, a server or a similar computing device.

[0077] The embodiments of the present invention achieve the following technical effects: it is possible to test the thermal resistance of each different thermal conductive layer in the packaging structure of the silicon photonic chip, and thus it is possible to determine the thermal resistance of different local areas in the silicon photonic chip packaging structure, which is beneficial for providing data basis for targeted heat dissipation optimization of the silicon photonic chip packaging structure; at the same time, the thermal resistance test uses the heating fixed value resistor in the silicon photonic chip as the heat source, without the need to introduce additional heat sources, thereby avoiding the problem of difficult to control the power consumption of additional heat sources, and thus is beneficial for improving the convenience and measurement accuracy of the thermal resistance test.

[0078] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the embodiments of the present invention are not limited to any specific combination of hardware and software.

[0079] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for testing the thermal resistance of a silicon photonic chip packaging structure, characterized in that: include: A heating constant value resistor in a silicon photonic chip is used as a heat source, the package structure to be tested of the silicon photonic chip is referred to as a first package structure, a substrate of the first package structure is mounted on a constant temperature heat sink, a transient thermal resistance test device is connected to the silicon photonic chip and the constant temperature heat sink, and a first integral structure function curve is obtained by testing; After replacing the material of the heat-conducting layer to be tested in the first packaging structure, a second packaging structure is obtained, a substrate of the second packaging structure is mounted on the constant temperature heat sink, the transient thermal resistance test equipment is connected to the silicon photonic chip and the constant temperature heat sink, and a second integral structure function curve is obtained by testing; Determining a thermal resistance value at an upper surface and a thermal resistance value at a lower surface of the thermal conductive layer to be measured in the first packaging structure according to a separation point of the first integrated structure function curve and the second integrated structure function curve; The thermal resistance value of the thermal conductive layer to be measured in the first packaging structure is calculated according to the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured.

2. The thermal resistance testing method of the silicon photonic chip packaging structure according to claim 1, characterized in that: Determining the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure according to the separation point of the first integrated structure function curve and the second integrated structure function curve, comprising: Plotting the first integral structure function curve and the second integral structure function curve in the same coordinate system, obtaining a first separation point between the first integral structure function curve and the second integral structure function curve, wherein the abscissa value of the first separation point is a thermal resistance value at the upper surface of the thermal conductive layer to be measured; The first integral structure function curve is translated so that the first integral structure function curve after translation coincides with the tail of the second integral structure function curve, and a second separation point is obtained, wherein the abscissa value of the second separation point is the thermal resistance value at the lower surface of the thermal conductive layer to be measured after the material is replaced; The thermal resistance value at the lower surface of the heat-conducting layer to be measured in the first packaging structure is determined according to the first integrated structure function curve and the coordinate value of the second separation point.

3. The thermal resistance testing method of the silicon photonic chip packaging structure according to claim 2, characterized in that: Determining the thermal resistance value of the lower surface of the thermal conductive layer to be measured in the first packaging structure according to the first integral structure function curve and the coordinate value of the second separation point includes: The coordinate value of the second separation point is translated so that the second separation point and the first separation point after the translation are on the same first integral structure function curve, and the horizontal coordinate value of the second separation point after the translation is determined as the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure.

4. The thermal resistance testing method of the silicon photonic chip packaging structure according to claim 1, characterized in that: The TiN heating constant value resistor in the silicon photonic chip is used as a heat source.

5. The thermal resistance testing method of the silicon photonic chip packaging structure according to any one of claims 1 to 4, characterized in that: Replacing the material of the thermal conductive layer to be tested in the first packaging structure includes: Based on the dimensional characteristics of the heat-conducting layer to be measured, selecting a heat-conducting material having a transverse thermal conductivity and / or a longitudinal thermal conductivity greater than a preset threshold; The selected thermally conductive material is used to replace the material of the thermally conductive layer to be tested in the first packaging structure.

6. The thermal resistance testing method of the silicon photonic chip packaging structure according to claim 5, characterized in that: The thermally conductive material having a transverse thermal conductivity and / or a longitudinal thermal conductivity greater than a preset threshold is selected, comprising: Comsol transient heat transfer simulation is performed on multiple candidate thermal conductive materials to determine the transverse thermal conductivity and longitudinal thermal conductivity of each candidate thermal conductive material. Among the plurality of candidate thermally conductive materials, a thermally conductive material having a transverse thermal conductivity and / or a longitudinal thermal conductivity greater than a preset threshold is selected.

7. The thermal resistance testing method of the silicon photonic chip packaging structure according to any one of claims 1 to 4, characterized in that: Also includes: In the process of obtaining the first integral structure function curve through testing, the substrate of the first packaging structure is placed on the constant temperature heat sink through a thermally conductive silicone layer patch; Directly mount the substrate of the first packaging structure on the constant temperature heat sink, connect a transient thermal resistance test device to the silicon photonic chip and the constant temperature heat sink, and obtain a third integral structure function curve through testing; Determine a third separation point according to the first integral structure function curve and the third integral structure function curve, wherein the abscissa value of the third separation point is the thermal resistance value at the upper surface of the thermally conductive silicone layer; The thermal resistance value of the substrate is calculated according to the thermal resistance value at the lower surface of the thermally conductive layer to be measured and the thermal resistance value at the upper surface of the thermally conductive silicone layer, wherein the thermally conductive layer to be measured is located on the upper surface of the substrate.

8. A thermal resistance testing device for a silicon photonic chip packaging structure, characterized in that: include: A first testing unit is used for testing and obtaining a first integral structure function curve when a heating fixed value resistor in a silicon photonic chip is used as a heat source, a substrate of a first packaging structure is mounted on a constant temperature heat sink, and a transient thermal resistance testing device is connected to the silicon photonic chip and the constant temperature heat sink, wherein the packaging structure to be tested of the silicon photonic chip is referred to as the first packaging structure; A second testing unit is used to obtain a second packaging structure after replacing the material of the heat-conducting layer to be tested in the first packaging structure, and to obtain a second integral structure function curve by testing when the substrate of the second packaging structure is mounted on the constant temperature heat sink and the transient thermal resistance testing device is connected to the silicon photonic chip and the constant temperature heat sink; a first calculation unit, configured to determine a thermal resistance value at an upper surface and a thermal resistance value at a lower surface of the thermal conductive layer to be measured in the first packaging structure according to a separation point of the first integral structure function curve and the second integral structure function curve; The second calculation unit is used to calculate the thermal resistance value of the thermal conductive layer to be measured in the first packaging structure according to the thermal resistance value at the upper surface and the thermal resistance value at the lower surface of the thermal conductive layer to be measured.

9. The thermal resistance testing device for the silicon photonic chip packaging structure according to claim 8, characterized in that: The first calculation unit is used to plot the first integral structure function curve and the second integral structure function curve in the same coordinate system, obtain a first separation point of the first integral structure function curve and the second integral structure function curve, the abscissa value of the first separation point is the thermal resistance value at the upper surface of the thermal conductive layer to be measured; translate the first integral structure function curve so that the translated first integral structure function curve and the tail of the second integral structure function curve coincide with each other, obtain a second separation point, the abscissa value of the second separation point is the thermal resistance value at the lower surface of the thermal conductive layer to be measured after material replacement; and determine the thermal resistance value at the lower surface of the thermal conductive layer to be measured in the first packaging structure according to the coordinate values ​​of the first integral structure function curve and the second separation point.

10. A computer device, comprising the thermal resistance testing device of the silicon photonic chip packaging structure according to claim 8 or 9.

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