Tester precision self-calibration method and tester

Abstract

The invention discloses a tester precision self-calibration method and a tester, and the method comprises the steps: determining a temperature drift coefficient of a high-precision reference source device under an instant temperature value through obtaining the instant temperature value read by a temperature sensor; whether the high-precision reference source device is in a normal working state or not is judged based on the temperature drift coefficient, the first theoretical working value and a first ADC conversion value obtained when the self-checking access is connected, and then when it is determined that the high-precision reference source device is in the normal working state, a first sampling loop is connected; and reading a second ADC conversion value output by the multi-channel high-speed ADC circuit in the first sampling loop, calibrating the multi-channel high-speed ADC circuit in the tester according to the first ADC conversion value obtained when the self-checking access is connected, and calibrating the multi-channel DAC circuit in the tester according to the calibrated multi-channel high-speed ADC circuit. Therefore, the precision self-calibration of the tester is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of testers, and in particular to a tester precision self-calibration method and a tester. Background Art

[0002] At present, with the large-scale access of new energy, the application of multi-terminal differential protection for distribution networks is gradually being piloted. Since the models, parameters and protocols used by different manufacturers of differential system equipment are different, the differential terminals of different suppliers are not interoperable and replaceable. Only differential terminal equipment provided by a single supplier can be used on the same line, which faces greater risks and inconveniences for the later system operation and maintenance.

[0003] The multi-terminal differential protection consistency tester fundamentally solves the incompatibility problem of distribution terminals from different manufacturers on the same line of the multi-terminal differential protection system through consistency testing. However, after the tester has been running for a period of time, the test error may become larger, thereby affecting the accuracy of the consistency test. Summary of the invention

[0004] The present invention provides a tester precision self-calibration method and a tester. The method first calculates a first ADC conversion value through a self-checking path, and then calibrates a multi-channel high-speed ADC circuit and a multi-channel high-speed ADC circuit in sequence according to the first ADC conversion value. Therefore, even in different working environments, the precision self-calibration of the tester can be completed based on the temperature value of the current working environment.

[0005] An embodiment of the present invention provides a tester accuracy self-calibration method, comprising:

[0006] When receiving the calibration signal, reading the instantaneous temperature value of the current working environment from the temperature sensor, obtaining the temperature drift coefficient of the high-precision reference source device at the instantaneous temperature value and the first theoretical working value of the high-precision reference source device at the standard room temperature;

[0007] When it is determined that the self-checking path is in a connected state, a first ADC conversion value output by the single-channel high-precision ADC circuit is obtained; wherein the self-checking path is composed of the temperature sensor, the high-precision reference source device and the single-channel high-precision ADC circuit connected in sequence;

[0008] judging whether the high-precision reference source device is in a normal working state according to the temperature drift coefficient, the first theoretical working value and the first ADC conversion value;

[0009] When it is determined that the high-precision reference source device is in a normal working state, the self-test path is in a disconnected state, and the first sampling loop is in a connected state, reading a second ADC conversion value output by a multi-channel high-speed ADC circuit in the first sampling loop, and calibrating the multi-channel high-speed ADC circuit in the first sampling loop according to the second ADC conversion value and the first ADC conversion value;

[0010] When it is determined that the first sampling loop is in a disconnected state and the second sampling loop is in a connected state, a digital signal is sent to the second sampling loop so that the second sampling loop outputs a corresponding third ADC conversion value according to the received digital signal; wherein the second sampling loop is composed of a multi-channel DAC circuit, a DAC conditioning circuit, and a calibrated multi-channel high-speed ADC circuit connected in sequence;

[0011] The multi-channel DAC circuit in the second sampling loop is calibrated according to the third ADC conversion value and the digital signal.

[0012] Further, judging whether the high-precision reference source device is in a normal working state according to the temperature drift coefficient, the first theoretical working value and the first ADC conversion value includes:

[0013] According to the temperature drift coefficient and the first theoretical working value, a second theoretical working value of the high-precision reference source device at the instantaneous temperature value is calculated;

[0014] When it is determined that the self-test path is in a connected state, reading a first ADC conversion value output by a single-channel high-precision ADC circuit in the self-test circuit;

[0015] Calculating a sampling error according to the first ADC conversion value and the second theoretical working value;

[0016] Determine whether the sampling error is within a preset error range,

[0017] If yes, it is determined that the high-precision reference source device is in normal working condition.

[0018] If not, it is determined that the high-precision reference source device is not in a normal working state.

[0019] Further, calibrating the multi-channel high-speed ADC circuit in the first sampling loop according to the second ADC conversion value and the first ADC conversion value includes:

[0020] Calculate a first precision calibration value according to the second ADC conversion value and the first ADC conversion value;

[0021] The first historical precision calibration value existing in the first calibration parameter is replaced with the first precision calibration value to obtain a calibrated multi-channel high-speed ADC circuit; wherein the first calibration parameter is used to calibrate the multi-channel high-speed ADC circuit.

[0022] Further, the calibrating the multi-channel DAC circuit in the second sampling loop according to the third ADC conversion value and the digital signal includes:

[0023] Calculate a second precision calibration value according to the third ADC conversion value and the digital signal;

[0024] The second historical precision calibration value existing in the second calibration parameter is replaced with the second precision calibration value to obtain a calibrated multi-channel DAC circuit; wherein the second calibration parameter is used to calibrate the multi-channel DAC circuit.

[0025] Furthermore, the tester accuracy self-calibration method further includes:

[0026] Retrieving a historical temperature value detected by the temperature sensor when solving the first historical accuracy calibration value;

[0027] According to the first precision calibration value, the first historical precision calibration value, the instantaneous temperature value, the historical temperature value and a preset first temperature drift compensation constant, a first coefficient and a second coefficient for measuring the relationship between temperature and a calibration parameter are obtained by solving;

[0028] According to the first coefficient, the second coefficient and the first temperature drift compensation constant, the original first calibration equation is updated to obtain an updated second calibration equation; wherein the first calibration equation is used to calibrate the first calibration parameter of the multi-channel high-speed ADC circuit.

[0029] Furthermore, the tester accuracy self-calibration method further includes:

[0030] According to the second precision calibration value, the second historical precision calibration value, the instantaneous temperature value, the historical temperature value and a preset second temperature drift compensation constant, a third coefficient and a fourth coefficient for measuring the relationship between temperature and the calibration parameter are obtained by solving;

[0031] According to the third coefficient, the fourth coefficient and the second temperature drift compensation constant, the original third calibration equation is updated to obtain an updated fourth calibration equation; wherein the third calibration equation is used to calibrate the second calibration parameter of the multi-channel DAC circuit.

[0032] Furthermore, the tester accuracy self-calibration method further includes:

[0033] When it is determined that the high-precision reference source device is not in a normal working state, the precision self-calibration is terminated.

[0034] An embodiment of the present invention further provides a tester, comprising: an FPGA main controller, a temperature sensor, a high-precision reference source device, a single-channel high-precision ADC circuit, a multi-channel high-speed ADC circuit, an ADC conditioning circuit, a multi-channel DAC circuit, a DAC conditioning circuit, a first single-pole double-throw switch, a second single-pole double-throw switch, and a single-pole triple-throw switch;

[0035] One end of the temperature sensor is connected to the FPGA main controller, and the other end is connected to the high-precision reference source device; the first moving end of the first single-pole double-throw switch is connected to the high-precision reference source device, the first fixed end of the first single-pole double-throw switch is connected to the input end of the single-channel high-precision ADC circuit, and the second fixed end of the first single-pole double-throw switch is connected to the third fixed end of the single-pole three-throw switch; the output end of the single-channel high-precision ADC circuit is connected to the FPGA main controller; the second moving end of the single-pole three-throw switch is connected to the input end of the ADC conditioning circuit, and the fourth fixed end of the single-pole three-throw switch is connected to the fifth fixed end of the second single-pole double-throw switch; the input end of the multi-channel high-speed ADC circuit is connected to the output end of the ADC conditioning circuit, and the output end of the multi-channel high-speed ADC circuit is connected to the FPGA main controller; the input end of the multi-channel DAC circuit is connected to the FPGA main controller, and the output end of the multi-channel DAC circuit is connected to the input end of the DAC conditioning circuit; the third moving end of the second single-pole double-throw switch is connected to the output end of the DAC conditioning circuit;

[0036] The FPGA main controller is used to read the instantaneous temperature value of the current working environment from the temperature sensor when receiving the calibration signal, obtain the temperature drift coefficient of the high-precision reference source device at the instantaneous temperature value and the first theoretical working value of the high-precision reference source device at standard room temperature; when the first moving end is connected to the first fixed end, obtain the first ADC conversion value output by the single-channel high-precision ADC circuit, and judge whether the high-precision reference source device is in a normal working state according to the temperature drift coefficient, the first theoretical working value and the first ADC conversion value; when it is determined that the high-precision reference source device is in a normal working state, the first moving end is connected to the second fixed end and the second moving end When connected to the third fixed end, the second ADC conversion value output by the multi-channel high-speed ADC circuit is read, and the multi-channel high-speed ADC circuit is calibrated according to the second ADC conversion value and the first ADC conversion value to obtain a calibrated multi-channel high-speed ADC circuit; when the third movable end is connected to the fifth fixed end and the second movable end is connected to the fourth fixed end, a first digital signal is sent to the multi-channel DAC circuit, and the third ADC conversion value output by the calibrated multi-channel high-speed ADC circuit is read, and the multi-channel DAC circuit is calibrated according to the third ADC conversion value and the first digital signal to obtain a calibrated multi-channel DAC circuit.

[0037] Furthermore, the tester further comprises: an input port and an output port; the input port is connected to the sixth fixed end of the single-pole triple-throw switch; the output port is connected to the seventh fixed end of the second single-pole double-throw switch;

[0038] The input port is used to receive a first initial analog signal when the sixth fixed end is connected to the second movable end and the seventh fixed end is connected to the third movable end, and transmit the first initial analog signal to the ADC conditioning circuit;

[0039] The ADC conditioning circuit is used to condition the first initial analog signal to obtain a conditioned first analog signal, and transmit the first analog signal to the calibrated multi-channel high-speed ADC circuit;

[0040] The calibrated multi-channel high-speed ADC circuit is used to convert the first analog signal into a second digital signal to be processed, and transmit the second digital signal to the FPGA main controller;

[0041] The FPGA main controller is further used to process the second digital signal according to a preset processing logic to obtain a processed third digital signal, and transmit the third digital signal to the calibrated multi-channel DAC circuit;

[0042] The calibrated multi-channel DAC circuit is used to convert the third digital signal into a second analog signal and transmit the second analog signal to the DAC conditioning circuit;

[0043] The DAC conditioning circuit is used to condition the second analog signal to obtain a conditioned third analog signal, and transmit the third analog signal to the output port;

[0044] The output port is used to output the third analog signal.

[0045] Furthermore, the tester further comprises: an ADC protection circuit and a DAC protection circuit; one end of the ADC protection circuit is connected to the input port, and one end is connected to the sixth fixed end; one end of the DAC protection circuit is connected to the output port, and one end is connected to the seventh fixed end;

[0046] The input port is further used to receive a second initial analog signal when the sixth fixed end is connected to the second movable end and the seventh fixed end is connected to the third movable end, and transmit the second initial analog signal to the ADC protection circuit;

[0047] The ADC protection circuit is used to filter out noise in the second initial analog signal to obtain a fourth analog signal after filtering, and transmit the fourth analog signal to the ADC conditioning circuit;

[0048] The ADC conditioning circuit is further used to condition the fourth analog signal to obtain a conditioned fifth analog signal, and transmit the fifth analog signal to the calibrated multi-channel high-speed ADC circuit;

[0049] The calibrated multi-channel high-speed ADC circuit is further used to convert the fifth analog signal into a fourth digital signal to be processed, and transmit the fourth digital signal to the FPGA main controller;

[0050] The FPGA main controller is further used to process the fourth digital signal according to a preset processing logic to obtain a processed fifth digital signal, and transmit the fifth digital signal to the calibrated multi-channel DAC circuit;

[0051] The calibrated multi-channel DAC circuit is further used to convert the fifth digital signal into a sixth analog signal, and transmit the sixth analog signal to the DAC conditioning circuit;

[0052] The DAC conditioning circuit is further used to condition the sixth analog signal to obtain a conditioned seventh analog signal, and transmit the seventh analog signal to the DAC protection circuit;

[0053] The DAC protection circuit is used to filter out noise in the seventh analog signal to obtain an eighth analog signal after filtering, and transmit the eighth analog signal to the output port;

[0054] The output port is also used to output the eighth analog signal.

[0055] The following beneficial effects are achieved by implementing the present invention:

[0056] The present invention provides a tester precision self-calibration method and a tester, wherein the method obtains the instantaneous temperature value of the current working environment read by a temperature sensor, thereby determining the temperature drift coefficient of a high-precision reference source device under the instantaneous temperature value, and judges whether the high-precision reference source device is in a normal working state based on the temperature drift coefficient, a first theoretical working value, and a first ADC conversion value obtained when a self-checking path is connected, samples the high-precision reference source device through a single-channel high-precision ADC circuit, and performs comparison and calculation with data pre-stored in an FPGA main controller, thereby avoiding the occurrence of self-calibration failure due to abnormality of the high-precision reference source device;

[0057] Then, when it is determined that the high-precision reference source device is in a normal working state, the first sampling loop is connected, and the second ADC conversion value output by the multi-channel high-speed ADC circuit in the first sampling loop is read, and the multi-channel high-speed ADC circuit is calibrated according to the first ADC conversion value obtained when the self-test path is connected, and the multi-channel DAC circuit is calibrated according to the calibrated multi-channel high-speed ADC circuit; because temperature is a key factor affecting the accuracy of the tester, the multi-channel high-speed ADC circuit and the multi-channel DAC circuit are calibrated based on the current operating temperature of the tester, so as to achieve the purpose of self-calibration of the tester accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the implementation manner will be briefly introduced below. Obviously, the drawings described below are only some implementation manners of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0059] Figure 1 It is a flowchart of a tester accuracy self-calibration method provided by a certain embodiment of the present application;

[0060] Figure 2 is a first connection schematic diagram of a tester provided in a certain embodiment of the present application;

[0061] Figure 3is a second connection schematic diagram of a tester provided in a certain embodiment of the present application;

[0062] Figure 4 is a third connection schematic diagram of a tester provided in a certain embodiment of the present application;

[0063] Figure 5 is a fourth connection schematic diagram of a tester provided in a certain embodiment of the present application;

[0064] Figure 6 This is the fifth connection diagram of the tester provided in another embodiment of the present application. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0067] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0068] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0069] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0070] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0071] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0072] See also Figure 1 , is a flow chart of a tester accuracy self-calibration method provided by an embodiment of the present invention, comprising:

[0073] S1. upon receiving a calibration signal, reading the instantaneous temperature value of the current working environment from the temperature sensor, obtaining the temperature drift coefficient of the high-precision reference source device at the instantaneous temperature value and the first theoretical working value of the high-precision reference source device at standard room temperature;

[0074] Specifically, when the calibration signal is received, the self-test process is started, and the FPGA main controller reads the instantaneous temperature value T1 sensed by the temperature detection chip in the temperature sensor under the current working environment, wherein the temperature sensor is located next to the high-precision reference source device, and the ambient temperatures of the two are consistent;

[0075] Then, the pre-stored temperature drift curve of the high-precision reference source device is retrieved, and the temperature drift coefficient k corresponding to the high-precision reference source device at the instantaneous temperature value T1 is determined according to the temperature drift curve. T1 ;

[0076] At the same time, the first theoretical working value of the high-precision reference source device at standard room temperature is obtained, that is, the actual output voltage value V0 of the high-precision reference source device at a normal temperature of 25°C.

[0077] S2, when it is determined that the self-checking path is in a connected state, obtaining a first ADC conversion value output by the single-channel high-precision ADC circuit; wherein the self-checking path is composed of the temperature sensor, the high-precision reference source device and the single-channel high-precision ADC circuit connected in sequence;

[0078] S3, judging whether the high-precision reference source device is in a normal working state according to the temperature drift coefficient, the first theoretical working value and the first ADC conversion value;

[0079] In a preferred embodiment, judging whether the high-precision reference source device is in a normal working state according to the temperature drift coefficient, the first theoretical working value and the first ADC conversion value includes:

[0080] Calculating a second theoretical operating value of the high-precision reference source device at the instantaneous temperature value according to the temperature drift coefficient and the first theoretical operating value;

[0081] When it is determined that the self-test path is in a connected state, reading a first ADC conversion value output by a single-channel high-precision ADC circuit in the self-test circuit;

[0082] Calculating a sampling error according to the first ADC conversion value and the second theoretical working value;

[0083] Determine whether the sampling error is within a preset error range,

[0084] If yes, it is determined that the high-precision reference source device is in normal working condition.

[0085] If not, it is determined that the high-precision reference source device is not in a normal working state;

[0086] In a preferred embodiment, the tester accuracy self-calibration method further includes:

[0087] When it is determined that the high-precision reference source device is not in a normal working state, terminating the precision self-calibration;

[0088] Specifically, when it is determined that the self-test path is in a connected state, a first ADC conversion value V2 output by a single-channel high-precision ADC circuit in the self-test circuit is read;

[0089] Then according to the temperature drift coefficient and the first theoretical working value V0, the second theoretical working value V1 of the high-precision reference source device at the instantaneous temperature value T1 is calculated, and the calculation formula is as follows:

[0090]

[0091] After the second theoretical working value V1 is calculated, the sampling error η is calculated according to the first ADC conversion value V2 and the second theoretical working value V1, and it is determined whether the sampling error η is within a preset error range. The specific calculation formula is as follows:

[0092] η=|(V2-V1) / V2×100%|; (2)

[0093] Specifically, if the sampling error η exceeds 5%, it is determined that the high-precision reference source device is not in a normal working state and there is an abnormality, and then when it is determined that the high-precision reference source device is not in a normal working state, the precision self-calibration is terminated;

[0094] Specifically, if the sampling error η does not exceed 5%, it is determined that the high-precision reference source device is in a normal working state.

[0095] S4, when it is determined that the high-precision reference source device is in a normal working state, the self-test path is in a disconnected state, and the first sampling loop is in a connected state, reading a second ADC conversion value output by the multi-channel high-speed ADC circuit in the first sampling loop, and calibrating the multi-channel high-speed ADC circuit in the first sampling loop according to the second ADC conversion value and the first ADC conversion value;

[0096] In a preferred embodiment, calibrating the multi-channel high-speed ADC circuit in the first sampling loop according to the second ADC conversion value and the first ADC conversion value includes:

[0097] Calculate a first precision calibration value according to the second ADC conversion value and the first ADC conversion value;

[0098] Replacing the first historical precision calibration value existing in the first calibration parameter with the first precision calibration value to obtain a calibrated multi-channel high-speed ADC circuit; wherein the first calibration parameter is used to calibrate the multi-channel high-speed ADC circuit;

[0099] Specifically, when it is determined that the high-precision reference source device is in a normal working state, the self-test path is in a disconnected state, and the first sampling loop is in a connected state, the second ADC conversion value V3 output by the multi-channel high-speed ADC circuit in the first sampling loop is read, and the first precision calibration value K1 is calculated based on the second ADC conversion value V3 and the first ADC conversion value V2. The calculation formula is as follows:

[0100] K1=(V3-V2) / V2×100%;(3)

[0101] After calculating the first precision calibration value K1, the FPGA controller will save the first precision calibration value K1, replace the first historical precision calibration value existing in the first calibration parameter with the first precision calibration value K1, and complete the calibration of the multi-channel high-speed ADC circuit.

[0102] S5. When it is determined that the first sampling loop is in a disconnected state and the second sampling loop is in a connected state, a digital signal is sent to the second sampling loop, so that the second sampling loop outputs a corresponding third ADC conversion value according to the received digital signal; wherein the second sampling loop is composed of a multi-channel DAC circuit, a DAC conditioning circuit, and a calibrated multi-channel high-speed ADC circuit connected in sequence;

[0103] Specifically, when it is determined that the first sampling loop is in a disconnected state and the second sampling loop is in a connected state, the FPGA main controller sends a digital signal V4 to the second sampling loop. The digital signal V4 is converted into an analog signal after passing through the multi-channel DAC circuit, and then input into the calibrated multi-channel high-speed ADC circuit through the DAC conditioning circuit. The third ADC conversion value V4' is obtained by sampling through the calibrated multi-channel high-speed ADC circuit.

[0104] S6. Calibrate the multi-channel DAC circuit in the second sampling loop according to the third ADC conversion value and the digital signal.

[0105] In a preferred embodiment, calibrating the multi-channel DAC circuit in the second sampling loop according to the third ADC conversion value and the digital signal includes:

[0106] Calculate a second precision calibration value according to the third ADC conversion value and the digital signal;

[0107] Replacing the second historical precision calibration value already existing in the second calibration parameter with the second precision calibration value to obtain a calibrated multi-channel DAC circuit; wherein the second calibration parameter is used to calibrate the multi-channel DAC circuit;

[0108] Specifically, after obtaining the third ADC conversion value V4', the FPGA main controller calculates the second precision calibration value K2 using formula (4), and the calculation formula is as follows:

[0109] K2=(V4'-V4) / V4×100%; (4)

[0110] After calculating the second precision calibration value K2, the FPGA controller will save the second precision calibration value K2, replace the second historical precision calibration value already existing in the second calibration parameter with the second precision calibration value, and complete the calibration of the multi-channel DAC circuit.

[0111] In a preferred embodiment, the tester accuracy self-calibration method further includes:

[0112] Retrieving a historical temperature value detected by the temperature sensor when solving the first historical accuracy calibration value;

[0113] According to the first precision calibration value, the first historical precision calibration value, the instantaneous temperature value, the historical temperature value and a preset first temperature drift compensation constant, a first coefficient and a second coefficient for measuring the relationship between temperature and a calibration parameter are obtained by solving;

[0114] According to the first coefficient, the second coefficient and the first temperature drift compensation constant, the original first calibration equation is updated to obtain an updated second calibration equation; wherein the first calibration equation is used to calibrate the first calibration parameter of the multi-channel high-speed ADC circuit;

[0115] Indicatively, after obtaining the first precision calibration value K1, it is necessary to call the first historical precision calibration value K1 in solving the first historical precision calibration value K 1_HIST The historical temperature value T detected by the temperature sensor at HIST Then, according to the first precision calibration value K1 and the first historical precision calibration value K 1_HIST , the instantaneous temperature value T1, the historical temperature value T HIST And the preset first temperature drift compensation constant C1, solve to obtain the first coefficient used to measure the relationship between temperature and calibration parameters and the second coefficient β1;

[0116] Specifically, according to the first historical accuracy calibration value K 1_HIST , the historical temperature value T HIST And the preset first temperature drift compensation constant C1, construct formula (5), as follows:

[0117]

[0118] Similarly, according to the first precision calibration value K1, the instantaneous temperature value T1 and the preset first temperature drift compensation constant C1, equation (6) is constructed, which is as follows:

[0119]

[0120] It should be noted that the first temperature drift compensation constant C1 is an empirical value;

[0121] Combining equations (5) and (6), we can solve for the first coefficient and the second coefficient β1, then according to the first coefficient The second coefficient β1 and the first temperature drift compensation constant C1 are used to update the original first calibration equation to obtain an updated second calibration equation. The second calibration equation is specifically as follows:

[0122]

[0123] It should be noted that when T HIST ≤T1, T i Conditions T must be met HIST ≤T i ≤T1; when T1≤T HIST When T i The condition T1≤T must be met i ≤T HIST ; When the above conditions are met, the relationship between the tester operating temperature and the first precision calibration value satisfies equation (7);

[0124] It should be noted that K i_1 The meaning is: when the temperature read by the temperature sensor is T i When the first calibration parameter corresponds to the updated specific value.

[0125] In a preferred embodiment, the tester accuracy self-calibration method further includes:

[0126] According to the second precision calibration value, the second historical precision calibration value, the instantaneous temperature value, the historical temperature value and a preset second temperature drift compensation constant, a third coefficient and a fourth coefficient for measuring the relationship between temperature and the calibration parameter are obtained by solving;

[0127] According to the third coefficient, the fourth coefficient and the second temperature drift compensation constant, the original third calibration equation is updated to obtain an updated fourth calibration equation; wherein the third calibration equation is used to calibrate the second calibration parameter of the multi-channel DAC circuit;

[0128] In an exemplary manner, after obtaining the second precision calibration value K2, according to the second precision calibration value K2 and the second historical precision calibration value K 2_HIST , the instantaneous temperature value T1, the historical temperature value T HIST And the preset second temperature drift compensation constant C2, the third coefficient used to measure the relationship between temperature and calibration parameters is obtained by solving and the fourth coefficient β2;

[0129] Specifically, according to the second historical accuracy calibration value K 2_HIST , the historical temperature value T HIST And the preset second temperature drift compensation constant C2, construct formula (8), as follows:

[0130]

[0131] Similarly, according to the second precision calibration value K2, the instantaneous temperature value T1 and the preset second temperature drift compensation constant C2, formula (9) is constructed, which is as follows:

[0132]

[0133] It should be noted that the second temperature drift compensation constant C2 is an empirical value;

[0134] Combining equations (8) and (9), we can solve for the third coefficient and the fourth coefficient β2, then according to the third coefficient The fourth coefficient β2 and the second temperature drift compensation constant C2 are used to update the original third calibration equation to obtain an updated fourth calibration equation. The second calibration equation is specifically as follows:

[0135]

[0136] It should be noted that when T HIST ≤T1, T i Conditions T must be met HIST ≤T i ≤T1; when T1≤T HIST When T i The condition T1≤T must be met i ≤T HIST ; When the above conditions are met, the relationship between temperature and the second precision calibration value satisfies formula (10);

[0137] It should be noted that K i_2 The meaning is: when the temperature read by the temperature sensor is T i When the second calibration parameter corresponds to the updated specific value.

[0138] See also Figure 2 , is a tester provided by an embodiment of the present invention, comprising: an FPGA main controller 1, a temperature sensor 2, a high-precision reference source device 3, a single-channel high-precision ADC circuit 4, an ADC conditioning circuit 5, a multi-channel high-speed ADC circuit 6, a multi-channel DAC circuit 7, a DAC conditioning circuit 8, a first single-pole double-throw switch S1, a second single-pole double-throw switch S2, and a single-pole triple-throw switch S3;

[0139] One end of the temperature sensor 2 is connected to the FPGA main controller 1, and the other end is connected to the high-precision reference source device 3; the first moving end of the first single-pole double-throw switch S1 is connected to the high-precision reference source device 3, the first fixed end of the first single-pole double-throw switch S1 is connected to the input end of the single-channel high-precision ADC circuit 4, and the second fixed end of the first single-pole double-throw switch S1 is connected to the third fixed end of the single-pole triple-throw switch S3; the output end of the single-channel high-precision ADC circuit 4 is connected to the FPGA main controller 1; the second moving end of the single-pole triple-throw switch S3 is connected to the ADC conditioning circuit 5, the fourth fixed end of the single-pole three-throw switch S3 is connected to the fifth fixed end of the second single-pole double-throw switch S2; the input end of the multi-channel high-speed ADC circuit 6 is connected to the output end of the ADC conditioning circuit 5, and the output end of the multi-channel high-speed ADC circuit 6 is connected to the FPGA main controller 1; the input end of the multi-channel DAC circuit 7 is connected to the FPGA main controller 1, and the output end of the multi-channel DAC circuit 7 is connected to the input end of the DAC conditioning circuit 8; the third movable end of the second single-pole double-throw switch S2 is connected to the output end of the DAC conditioning circuit 8;

[0140] The FPGA main controller 1 is used to read the instantaneous temperature value of the current working environment from the temperature sensor 2 when receiving the calibration signal, obtain the temperature drift coefficient of the high-precision reference source device 3 at the instantaneous temperature value and the first theoretical working value of the high-precision reference source device 3 at the standard room temperature; when the first moving end is connected to the first fixed end, obtain the first ADC conversion value output by the single-channel high-precision ADC circuit 4, and judge whether the high-precision reference source device 3 is in a normal working state according to the temperature drift coefficient, the first theoretical working value and the first ADC conversion value; when it is determined that the high-precision reference source device 3 is in a normal working state, the first moving end is connected to the second fixed end and the second moving end is When connected to the third fixed end, the second ADC conversion value output by the multi-channel high-speed ADC circuit 6 is read, and the multi-channel high-speed ADC circuit 6 is calibrated according to the second ADC conversion value and the first ADC conversion value to obtain a calibrated multi-channel high-speed ADC circuit 6; when the third movable end is connected to the fifth fixed end and the second movable end is connected to the fourth fixed end, a first digital signal is sent to the multi-channel DAC circuit 7, and the third ADC conversion value output by the calibrated multi-channel high-speed ADC circuit 6 is read, and the multi-channel DAC circuit 7 is calibrated according to the third ADC conversion value and the first digital signal to obtain a calibrated multi-channel DAC circuit 7;

[0141] Specifically, see Figure 2, when the first moving end of the first single-pole double-throw switch S1 is connected to the first fixed end of the first single-pole double-throw switch S1, the self-test path is connected, and the first ADC conversion value V2 output by the single-channel high-precision ADC circuit 4 is read through the FPGA main controller 1;

[0142] Specifically, see Figure 3 , when it is determined that the high-precision reference source device 3 is in a normal working state, the first moving end of the first single-pole double-throw switch S1 is connected to the second fixed end of the first single-pole double-throw switch S1, and the second moving end of the single-pole triple-throw switch S3 is connected to the third fixed end of the single-pole triple-throw switch S3, the second ADC conversion value V3 output by the multi-channel high-speed ADC circuit 6 is read, and according to the second ADC conversion value V3 and the first ADC conversion value V2, the multi-channel high-speed ADC circuit 6 is calibrated to obtain a calibrated multi-channel high-speed ADC circuit 6;

[0143] Specifically, see Figure 4 , when the third moving end of the second single-pole double-throw switch S2 is connected to the fifth fixed end of the second single-pole double-throw switch S2 and the second moving end of the single-pole triple-throw switch S3 is connected to the fourth fixed end of the single-pole triple-throw switch S3, the first digital signal V4 is sent to the multi-channel DAC circuit 7, and the third ADC conversion value V4' output by the calibrated multi-channel high-speed ADC circuit 6 is read, and the multi-channel DAC circuit 7 is calibrated according to the third ADC conversion value V4' and the first digital signal V4 to obtain the calibrated multi-channel DAC circuit 7.

[0144] See also Figure 5 In a preferred embodiment, the tester further comprises: an input port 9 and an output port 10; the input port 9 is connected to the sixth fixed end of the single-pole triple-throw switch S3; the output port 10 is connected to the seventh fixed end of the second single-pole double-throw switch S2;

[0145] The input port 9 is used to receive the first initial analog signal when the sixth fixed end of the single-pole three-throw switch S3 is connected to the second movable end of the single-pole three-throw switch S3 and the seventh fixed end of the second single-pole double-throw switch S2 is connected to the third movable end of the second single-pole double-throw switch S2, and transmit the first initial analog signal to the ADC conditioning circuit 5;

[0146] The ADC conditioning circuit 5 is used for conditioning the first initial analog signal to obtain a conditioned first analog signal, and transmitting the first analog signal to the calibrated multi-channel high-speed ADC circuit 6;

[0147] The calibrated multi-channel high-speed ADC circuit 6 is used to convert the first analog signal into a second digital signal to be processed, and transmit the second digital signal to the FPGA main controller 1;

[0148] The FPGA main controller 1 is further used to process the second digital signal according to a preset processing logic to obtain a processed third digital signal, and transmit the third digital signal to the calibrated multi-channel DAC circuit 7;

[0149] The calibrated multi-channel DAC circuit 7 is used to convert the third digital signal into a second analog signal, and transmit the second analog signal to the DAC conditioning circuit 8;

[0150] The DAC conditioning circuit 8 is used to condition the second analog signal to obtain a conditioned third analog signal, and transmit the third analog signal to the output port 10;

[0151] The output port 10 is used to output the third analog signal.

[0152] See also Figure 6 , the tester further includes: an ADC protection circuit 11 and a DAC protection circuit 12; one end of the ADC protection circuit 11 is connected to the input port 9, and one end is connected to the sixth fixed end; one end of the DAC protection circuit 12 is connected to the output port 10, and one end is connected to the seventh fixed end;

[0153] The input port 9 is further used for receiving a second initial analog signal when the sixth fixed end of the single-pole triple-throw switch S3 is connected to the second movable end of the single-pole triple-throw switch S3 and the seventh fixed end of the second single-pole double-throw switch S2 is connected to the third movable end of the second single-pole double-throw switch S2, and transmitting the second initial analog signal to the ADC protection circuit 11;

[0154] The ADC protection circuit 11 is used to filter out noise in the second initial analog signal to obtain a fourth analog signal after filtering, and transmit the fourth analog signal to the ADC conditioning circuit 5;

[0155] The ADC conditioning circuit 5 is further used for conditioning the fourth analog signal to obtain a conditioned fifth analog signal, and transmitting the fifth analog signal to the calibrated multi-channel high-speed ADC circuit 6;

[0156] The calibrated multi-channel high-speed ADC circuit 6 is further used to convert the fifth analog signal into a fourth digital signal to be processed, and transmit the fourth digital signal to the FPGA main controller 1;

[0157] The FPGA main controller 1 is further used to process the fourth digital signal according to a preset processing logic to obtain a processed fifth digital signal, and transmit the fifth digital signal to the calibrated multi-channel DAC circuit 7;

[0158] The calibrated multi-channel DAC circuit 7 is further used to convert the fifth digital signal into a sixth analog signal, and transmit the sixth analog signal to the DAC conditioning circuit 8;

[0159] The DAC conditioning circuit 8 is further used to condition the sixth analog signal to obtain a conditioned seventh analog signal, and transmit the seventh analog signal to the DAC protection circuit 12;

[0160] The DAC protection circuit 12 is used to filter out noise in the seventh analog signal to obtain a filtered eighth analog signal, and transmit the eighth analog signal to the output port 10;

[0161] The output port 10 is also used to output the eighth analog signal.

Claims

1. A tester accuracy self-calibration method, characterized in that: For testers including: When receiving the calibration signal, reading the instantaneous temperature value of the current working environment from the temperature sensor, obtaining the temperature drift coefficient of the high-precision reference source device at the instantaneous temperature value and the first theoretical working value of the high-precision reference source device at the standard room temperature; When it is determined that the self-checking path is in a connected state, a first ADC conversion value output by the single-channel high-precision ADC circuit is obtained; wherein the self-checking path is composed of the temperature sensor, the high-precision reference source device and the single-channel high-precision ADC circuit connected in sequence; judging whether the high-precision reference source device is in a normal working state according to the temperature drift coefficient, the first theoretical working value and the first ADC conversion value; When it is determined that the high-precision reference source device is in a normal working state, the self-test path is in a disconnected state, and the first sampling loop is in a connected state, reading a second ADC conversion value output by a multi-channel high-speed ADC circuit in the first sampling loop, and calibrating the multi-channel high-speed ADC circuit in the first sampling loop according to the second ADC conversion value and the first ADC conversion value; When it is determined that the first sampling loop is in a disconnected state and the second sampling loop is in a connected state, a digital signal is sent to the second sampling loop so that the second sampling loop outputs a corresponding third ADC conversion value according to the received digital signal; wherein the second sampling loop is composed of a multi-channel DAC circuit, a DAC conditioning circuit, and a calibrated multi-channel high-speed ADC circuit connected in sequence; The multi-channel DAC circuit in the second sampling loop is calibrated according to the third ADC conversion value and the digital signal.

2. The tester accuracy self-calibration method according to claim 1, characterized in that: The determining, according to the temperature drift coefficient, the first theoretical working value, and the first ADC conversion value, whether the high-precision reference source device is in a normal working state comprises: Calculating a second theoretical operating value of the high-precision reference source device at the instantaneous temperature value according to the temperature drift coefficient and the first theoretical operating value; When it is determined that the self-test path is in a connected state, reading a first ADC conversion value output by a single-channel high-precision ADC circuit in the self-test circuit; Calculating a sampling error according to the first ADC conversion value and the second theoretical working value; Determine whether the sampling error is within a preset error range, If yes, it is determined that the high-precision reference source device is in normal working condition. If not, it is determined that the high-precision reference source device is not in a normal working state.

3. The tester accuracy self-calibration method according to claim 1, characterized in that: The step of calibrating the multi-channel high-speed ADC circuit in the first sampling loop according to the second ADC conversion value and the first ADC conversion value includes: Calculate a first precision calibration value according to the second ADC conversion value and the first ADC conversion value; The first historical precision calibration value existing in the first calibration parameter is replaced with the first precision calibration value to obtain a calibrated multi-channel high-speed ADC circuit; wherein the first calibration parameter is used to calibrate the multi-channel high-speed ADC circuit.

4. The tester accuracy self-calibration method according to claim 3, characterized in that: The calibrating the multi-channel DAC circuit in the second sampling loop according to the third ADC conversion value and the digital signal includes: Calculate a second precision calibration value according to the third ADC conversion value and the digital signal; The second historical precision calibration value existing in the second calibration parameter is replaced with the second precision calibration value to obtain a calibrated multi-channel DAC circuit; wherein the second calibration parameter is used to calibrate the multi-channel DAC circuit.

5. The tester accuracy self-calibration method according to claim 4, characterized in that: Also includes: Retrieving a historical temperature value detected by the temperature sensor when solving the first historical accuracy calibration value; According to the first precision calibration value, the first historical precision calibration value, the instantaneous temperature value, the historical temperature value and a preset first temperature drift compensation constant, a first coefficient and a second coefficient for measuring the relationship between temperature and a calibration parameter are obtained by solving; According to the first coefficient, the second coefficient and the first temperature drift compensation constant, the original first calibration equation is updated to obtain an updated second calibration equation; wherein the first calibration equation is used to calibrate the first calibration parameter of the multi-channel high-speed ADC circuit.

6. The tester accuracy self-calibration method according to claim 5, characterized in that: Also includes: According to the second precision calibration value, the second historical precision calibration value, the instantaneous temperature value, the historical temperature value and a preset second temperature drift compensation constant, a third coefficient and a fourth coefficient for measuring the relationship between temperature and the calibration parameter are obtained by solving; According to the third coefficient, the fourth coefficient and the second temperature drift compensation constant, the original third calibration equation is updated to obtain an updated fourth calibration equation; wherein the third calibration equation is used to calibrate the second calibration parameter of the multi-channel DAC circuit.

7. The tester accuracy self-calibration method according to claim 1, characterized in that: Also includes: When it is determined that the high-precision reference source device is not in a normal working state, the precision self-calibration is terminated.

8. A tester, characterized in that: include: FPGA main controller, temperature sensor, high-precision reference source device, single-channel high-precision ADC circuit, multi-channel high-speed ADC circuit, ADC conditioning circuit, multi-channel DAC circuit, DAC conditioning circuit, first single-pole double-throw switch, second single-pole double-throw switch and single-pole triple-throw switch; One end of the temperature sensor is connected to the FPGA main controller, and the other end is connected to the high-precision reference source device; the first moving end of the first single-pole double-throw switch is connected to the high-precision reference source device, the first fixed end of the first single-pole double-throw switch is connected to the input end of the single-channel high-precision ADC circuit, and the second fixed end of the first single-pole double-throw switch is connected to the third fixed end of the single-pole three-throw switch; the output end of the single-channel high-precision ADC circuit is connected to the FPGA main controller; the second moving end of the single-pole three-throw switch is connected to the input end of the ADC conditioning circuit, and the fourth fixed end of the single-pole three-throw switch is connected to the fifth fixed end of the second single-pole double-throw switch; the input end of the multi-channel high-speed ADC circuit is connected to the output end of the ADC conditioning circuit, and the output end of the multi-channel high-speed ADC circuit is connected to the FPGA main controller; the input end of the multi-channel DAC circuit is connected to the FPGA main controller, and the output end of the multi-channel DAC circuit is connected to the input end of the DAC conditioning circuit; the third moving end of the second single-pole double-throw switch is connected to the output end of the DAC conditioning circuit; The FPGA main controller is used to read the instantaneous temperature value of the current working environment from the temperature sensor when receiving the calibration signal, obtain the temperature drift coefficient of the high-precision reference source device at the instantaneous temperature value and the first theoretical working value of the high-precision reference source device at standard room temperature; when the first moving end is connected to the first fixed end, obtain the first ADC conversion value output by the single-channel high-precision ADC circuit, and judge whether the high-precision reference source device is in a normal working state according to the temperature drift coefficient, the first theoretical working value and the first ADC conversion value; when it is determined that the high-precision reference source device is in a normal working state, the first moving end is connected to the second fixed end and the second moving end When connected to the third fixed end, the second ADC conversion value output by the multi-channel high-speed ADC circuit is read, and the multi-channel high-speed ADC circuit is calibrated according to the second ADC conversion value and the first ADC conversion value to obtain a calibrated multi-channel high-speed ADC circuit; when the third movable end is connected to the fifth fixed end and the second movable end is connected to the fourth fixed end, a first digital signal is sent to the multi-channel DAC circuit, and the third ADC conversion value output by the calibrated multi-channel high-speed ADC circuit is read, and the multi-channel DAC circuit is calibrated according to the third ADC conversion value and the first digital signal to obtain a calibrated multi-channel DAC circuit.

9. The tester according to claim 8, characterized in that: It also includes: an input port and an output port; the input port is connected to the sixth fixed end of the single-pole triple-throw switch; the output port is connected to the seventh fixed end of the second single-pole double-throw switch; The input port is used to receive a first initial analog signal when the sixth fixed end is connected to the second movable end and the seventh fixed end is connected to the third movable end, and transmit the first initial analog signal to the ADC conditioning circuit; The ADC conditioning circuit is used to condition the first initial analog signal to obtain a conditioned first analog signal, and transmit the first analog signal to the calibrated multi-channel high-speed ADC circuit; The calibrated multi-channel high-speed ADC circuit is used to convert the first analog signal into a second digital signal to be processed, and transmit the second digital signal to the FPGA main controller; The FPGA main controller is further used to process the second digital signal according to a preset processing logic to obtain a processed third digital signal, and transmit the third digital signal to the calibrated multi-channel DAC circuit; The calibrated multi-channel DAC circuit is used to convert the third digital signal into a second analog signal and transmit the second analog signal to the DAC conditioning circuit; The DAC conditioning circuit is used to condition the second analog signal to obtain a conditioned third analog signal, and transmit the third analog signal to the output port; The output port is used to output the third analog signal.

10. The tester according to claim 9, characterized in that: Also includes: An ADC protection circuit and a DAC protection circuit; one end of the ADC protection circuit is connected to the input port, and one end is connected to the sixth fixed end; one end of the DAC protection circuit is connected to the output port, and one end is connected to the seventh fixed end; The input port is further used to receive a second initial analog signal when the sixth fixed end is connected to the second movable end and the seventh fixed end is connected to the third movable end, and transmit the second initial analog signal to the ADC protection circuit; The ADC protection circuit is used to filter out noise in the second initial analog signal to obtain a fourth analog signal after filtering, and transmit the fourth analog signal to the ADC conditioning circuit; The ADC conditioning circuit is further used to condition the fourth analog signal to obtain a conditioned fifth analog signal, and transmit the fifth analog signal to the calibrated multi-channel high-speed ADC circuit; The calibrated multi-channel high-speed ADC circuit is further used to convert the fifth analog signal into a fourth digital signal to be processed, and transmit the fourth digital signal to the FPGA main controller; The FPGA main controller is further used to process the fourth digital signal according to a preset processing logic to obtain a processed fifth digital signal, and transmit the fifth digital signal to the calibrated multi-channel DAC circuit; The calibrated multi-channel DAC circuit is further used to convert the fifth digital signal into a sixth analog signal, and transmit the sixth analog signal to the DAC conditioning circuit; The DAC conditioning circuit is further used to condition the sixth analog signal to obtain a conditioned seventh analog signal, and transmit the seventh analog signal to the DAC protection circuit; The DAC protection circuit is used to filter out noise in the seventh analog signal to obtain an eighth analog signal after filtering, and transmit the eighth analog signal to the output port; The output port is also used to output the eighth analog signal.

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