A method for improving the photolithography process window

Abstract

This invention discloses a method for improving the lithography process window, comprising: providing a layout design including patterns of functional devices and patterns of non-functional virtual structures; iteratively optimizing the layout design using a first optical proximity correction; wherein the pattern of the virtual structure is treated as a pattern of functional devices for optimization; performing weakness detection on the layout design after the first optical proximity correction and filtering out process weaknesses caused by the pattern of the virtual structure; optimizing the process weaknesses caused by the pattern of the virtual structure using a second optical proximity correction; wherein the second optical proximity correction operates on the pattern of the virtual structure; and performing weakness detection on the layout design again to determine whether the process weaknesses caused by the pattern of the virtual structure have been optimized. The technical solution of this invention optimizes the process introduced by the virtual structure, reduces process complexity, and improves the lithography process window.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a method for improving the photolithography process window. Background Technology

[0002] Optical proximity effect correction (OPC) is an important component of photolithography resolution enhancement technology. By adjusting the topology of the light-transmitting areas on the photomask, it enables the exposed wafer image to meet circuit design requirements to the greatest extent possible, which is crucial for improving the production quality and performance of semiconductor devices.

[0003] In circuit design layouts, there exist virtual structures unrelated to actual electronic components. These virtual component structures have the same layout graphic size as the main devices and play roles such as filling and stress dispersion in the process. In OPC process operations, they are assigned the same status as the layout of the main devices and are treated as the main graphic. When these virtual structures exhibit or introduce process weaknesses, OPC needs to adjust auxiliary graphics for optimization. No special operations are performed on the graphics themselves; scattering bar modules are commonly used as auxiliary graphics to balance the imaging differences between dense and sparse graphic areas and improve the common process window. As the complexity of the layout environment increases, the rules for adding scattering bars also become extremely complex. The parameter settings for adding scattering bars often need to be adjusted according to layout changes, and the principle of avoiding exposure must be followed. Under specified process fluctuation conditions, a high level of computation is often required to obtain the optimal parameter combination.

[0004] Therefore, a new method is needed to improve the lithography process window in order to reduce process complexity and improve process efficiency. Summary of the Invention

[0005] The purpose of this invention is to provide a method for improving the photolithography process window, so as to solve the problem of excessive process complexity when adjusting auxiliary patterns for optimization when virtual structures introduce process weaknesses.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] A layout design is provided, the layout design including graphics of functional devices and graphics of non-functional virtual structures;

[0008] The layout design is iteratively optimized using a first optical proximity effect correction; wherein, the graphic of the virtual structure is optimized as a graphic of the functional device;

[0009] Weakness detection is performed on the layout design after the first optical proximity effect correction, and process weaknesses caused by the graphics of the virtual structure are screened out.

[0010] To address the process weaknesses caused by the graphics of the virtual structure, a second optical proximity effect correction is employed for optimization; wherein, the second optical proximity effect correction operates on the graphics of the virtual structure;

[0011] The layout design is then subjected to another weakness detection to determine whether the process weaknesses caused by the graphics of the virtual structure have been optimized.

[0012] Optionally, before providing a layout design, the method further includes:

[0013] The virtual structure's graphic representation is identified during the layout design phase;

[0014] The virtual structure is identified using a specific layer.

[0015] Optionally, the iterative optimization of the layout design using the first optical proximity effect correction includes:

[0016] A photolithography model is established, which includes an optical model and a photoresist photochemical reaction model.

[0017] Identify the graphic edges of the functional devices and the graphic edges of the virtual structures in the layout design, and allow each edge to move freely;

[0018] The edge position is continuously moved, and the corresponding post-exposure pattern is calculated based on the lithography model. The result is compared with the layout design to obtain the corresponding edge placement error until the calculated edge placement error reaches the set value.

[0019] Optionally, the step of performing weakness detection on the layout design includes:

[0020] Build a rule base based on experience;

[0021] Weakness detection is performed on the layout design based on the established rule base.

[0022] Optionally, the step of performing weakness detection on the layout design after optical proximity correction and filtering out process weaknesses caused by the graphics of the virtual structure includes:

[0023] Weakness detection is performed on the layout design, and the detected process weaknesses are categorized; wherein, the categorized categories include process weaknesses caused by the graphics of the virtual structure.

[0024] Optionally, the parameters used for weakness detection include:

[0025] Mask error enhancement factor, normalized graph log slope, depth of field, key dimension variation, and key dimension uniformity.

[0026] Optionally, the optimization of process weaknesses caused by the graphics of the virtual structure using a second optical proximity effect correction includes:

[0027] A photolithography model is established, which includes an optical model and a photoresist photochemical reaction model.

[0028] Obtain the adjustment range of the virtual structure's graphic;

[0029] The virtual structure's shape is adjusted within the adjustment range, and the corresponding simulated process morphology is obtained based on the lithography model.

[0030] Optionally, adjusting the graphics of the virtual structure within the adjustment range includes:

[0031] Adjust the geometric dimensions, spacing from surrounding graphics, area, and position of the virtual structure.

[0032] The present invention also provides a readable storage medium storing a computer program, which, when executed by a processor, implements the method for improving the photolithography process window described above.

[0033] The present invention also provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when executed by the processor, the computer program implements the method for improving the photolithography process window described above.

[0034] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0035] The method for improving the lithography process window provided by this invention distinguishes between the patterns of functional devices and the patterns of virtual structures with sub-functionality in the layout design. First, iterative optimization of the layout design is performed using a first optical proximity correction, where the virtual structure patterns are treated as functional device patterns for optimization. Then, process weaknesses caused by the virtual structure patterns are identified. Next, a second optical proximity correction is performed on these weaknesses, operating only on the virtual structure patterns. Finally, a weakness detection is performed on the optimized layout design to determine whether the process weaknesses caused by the virtual structure patterns have been optimized. This invention addresses process weaknesses caused by virtual structure patterns by directly operating on the virtual structure patterns, instead of adding auxiliary patterns (e.g., scattering bars), thus reducing process complexity and improving the lithography process window. Attached Figure Description

[0036] Figure 1This is a schematic diagram of a process for improving the photolithography window according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the second optical proximity effect correction process according to an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the layout design provided in an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of the optimized layout design provided for an embodiment of the present invention. Detailed Implementation

[0040] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for improving the photolithography process window proposed by the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of the present invention. Please refer to the drawings to make the objectives, features, and advantages of the present invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0041] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating an embodiment of the present invention for improving the photolithography process window. The method includes:

[0042] Step S1: Provide a layout design, which is a mask design file including graphics of functional devices and graphics of non-functional dummy structures. A dummy structure is a non-functional semiconductor element or structure, typically used to fill unused areas in a chip to ensure that the structure and performance of other parts are maintained. These fillers are usually made of the same material as the chip, but they are not used for any circuitry or logic functions.

[0043] Step S2: The layout design is iteratively optimized using the first optical proximity effect correction; wherein, the graphic of the virtual structure is optimized as the graphic of the functional device.

[0044] Optical proximity effect refers to the discrepancy between the pattern projected onto the wafer and the pattern on the mask during photolithography due to interference and diffraction between adjacent patterns on the mask. As the size of the pattern on the mask decreases, these interference and diffraction effects become more pronounced, leading to greater deviations in the exposed pattern. The optical proximity effect correction mechanism compensates for these distortions by altering the shape of the pattern on the mask, ensuring that the pattern on the wafer closely matches the intended shape.

[0045] Step S3: Perform weakness detection on the layout design after the first optical proximity effect correction, and screen out the process weaknesses caused by the graphics of the virtual structure;

[0046] Step S4: For the process weaknesses caused by the pattern of the virtual structure, a second optical proximity effect correction is used for optimization; wherein, the second optical proximity effect correction operates on the pattern of the virtual structure.

[0047] Step S5: Perform a weakness detection on the layout design again to determine whether the process weaknesses caused by the graphics of the virtual structure have been optimized.

[0048] In the above embodiments, by distinguishing between the graphics of functional devices and the graphics of virtual structures with sub-functionality in the layout design, the layout design is first iteratively optimized using a first optical proximity correction. This first optical proximity correction treats the graphics of virtual structures as graphics of functional devices for optimization. Then, process weaknesses caused by the graphics of virtual structures are identified. Next, a second optical proximity correction is performed on these process weaknesses, operating only on the graphics of virtual structures. Finally, a weakness detection is performed on the optimized layout design to determine whether the process weaknesses caused by the graphics of virtual structures have been optimized. The technical solution of this invention addresses process weaknesses caused by the graphics of virtual structures by directly operating on the graphics of the virtual structures, instead of adding auxiliary graphics (e.g., scattering stripes), thus reducing process complexity and increasing the lithography process window.

[0049] In some embodiments, prior to providing a layout design, the method further includes:

[0050] The virtual structure's graphic representation is identified during the layout design phase;

[0051] The virtual structure is identified using a specific layer.

[0052] In the above embodiments, by identifying the graphics of the virtual structure during the layout design stage and using a specific layer to mark the graphics of the virtual structure, the graphics of the virtual structure can be manipulated in a targeted manner in step S4.

[0053] In some embodiments, the iterative optimization of the layout design using a first optical proximity correction includes:

[0054] A photolithography model is established, which includes an optical model and a photoresist photochemical reaction model.

[0055] Identify the graphic edges of the functional devices and the graphic edges of the virtual structures in the layout design, and allow each edge to move freely;

[0056] The edge position is continuously moved, and the corresponding post-exposure pattern is calculated based on the lithography model. The pattern is then compared with the layout design to obtain the corresponding edge placement error (EPE) until the calculated edge placement error reaches the set value.

[0057] In the above embodiments, the optical proximity correction software uses the lithography model to predict the pattern of the mask after exposure corresponding to the current layout design, compares it with the target pattern, and calculates the difference between the two. The difference between the current result and the target pattern is called the edge placement error (EPE). The smaller the edge placement error value, the closer it is to the target. This process is continuously iterated until the calculated edge placement error reaches the set specification range.

[0058] It should be noted that the first optical proximity effect correction treats the virtual structure's pattern as the pattern of a functional device and performs iterative optimization.

[0059] In some embodiments, the weakness detection of the layout design includes:

[0060] Build a rule base based on experience;

[0061] Weakness detection is performed on the layout design based on the established rule base.

[0062] In the above embodiments, specifically, the post-exposure pattern corresponding to the last calculated layout design can be corrected according to the first optical proximity effect, and based on the post-exposure pattern, it can be determined which process weaknesses exist, and further determine which process weaknesses are caused by the pattern of the virtual structure.

[0063] It should be noted that the rule base is established based on experience, and different rules are required for vulnerability detection depending on the process node. Rules can be classified according to their formation reasons. For example, a certain type of rule can be written to specifically detect process weaknesses caused by the virtual structure.

[0064] In some embodiments, the step of performing weakness detection on the layout design after optical proximity correction and filtering out process weaknesses caused by the graphics of the virtual structure includes:

[0065] Weakness detection is performed on the layout design, and the detected process weaknesses are categorized; wherein, the categorized categories include process weaknesses caused by the graphics of the virtual structure.

[0066] In the above embodiments, process weaknesses caused by the graphics of the virtual structure are screened out by classification.

[0067] In some embodiments, the parameters upon which the vulnerability detection is based include:

[0068] Mask error enhancement factor, normalized pattern log slope, depth of focus, critical dimension variation, and critical dimension uniformity.

[0069] Specifically, the Mask Error Enhancement Factor (MEEF) is the slope of the photoresist linewidth on the wafer as a function of the mask pattern linewidth; the Normalized Image Log Slope (NILS) is an important parameter for measuring the spatial image quality in photolithography; a larger NILS value indicates higher spatial imaging contrast and better imaging quality; the Depth of Focus (DOF) refers to the maximum range of focal length variation within the allowable range of linewidth variation; the Critical Dimension Variation (CDV) refers to the variation of the critical dimension (i.e., the smallest feature size on the chip, Critical Dimension, CD) at different locations or between different wafers during semiconductor manufacturing due to various factors; and the Critical Dimension Uniformity (CDU) is a key parameter for measuring the control performance of photolithography, used to describe the consistency of critical dimensions across the entire wafer during photolithography.

[0070] In the above embodiments, the existence and type of process weaknesses can be determined based on one or a combination of parameters.

[0071] In some embodiments, please refer to Figure 2 The optimization of process weaknesses caused by the graphics of the virtual structure using a second optical proximity effect correction includes:

[0072] Step S41: Establish a photolithography model, which includes an optical model and a photoresist photochemical reaction model;

[0073] Step S42: Obtain the adjustment range of the virtual structure's graphic;

[0074] Step S43: Adjust the graphic of the virtual structure within the adjustment range, and obtain the corresponding simulation process morphology based on the photolithography model.

[0075] It should be noted that, in the above embodiments, the second optical proximity effect correction only adjusts the graphic of the virtual structure.

[0076] Specifically, adjusting the graphics of the virtual structure within the adjustment range includes:

[0077] Adjust the geometric dimensions, spacing from surrounding graphics, area, and position of the virtual structure.

[0078] Please see Figure 3 , Figure 3 This is a schematic diagram of the layout design provided in an embodiment of the present invention, such as... Figure 3 As shown, the virtual structure is represented within the dashed box. Figure 3 The mask corresponding to the layout design shown, after the first optical proximity correction, has a relatively close proximity between the virtual structure and the functional devices on both sides in the calculated exposed image (not shown), which may pose a risk. Therefore, during the second optical proximity correction, the image of the virtual structure can be optimized, for example, by adjusting the area of ​​the virtual structure. (See [reference needed]). Figure 4 In the design layout, break the graphic of the virtual structure (refer to...). Figure 4 The structure enclosed by the dashed box is positioned to create a certain distance from the functional components on the left and right sides, reducing risk. In other embodiments, the virtual structure's shape can be optimized by adjusting its position and spacing from surrounding graphics; specific limitations are not specified here.

[0079] The present invention also provides a readable storage medium storing a computer program, which, when executed by a processor, implements the method for improving the photolithography process window as described in any of the preceding claims.

[0080] The present invention also provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the method for improving the photolithography process window as described in any of the preceding claims.

[0081] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0082] It should be noted that the apparatus and methods disclosed in the embodiments herein can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments herein. In this regard, each block in a flowchart or block diagram may represent a module, program, or part of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system to perform the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0083] In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0084] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for improving the photolithography process window, characterized in that, include: A layout design is provided, the layout design including graphics of functional devices and graphics of non-functional virtual structures; The layout design is iteratively optimized using a first optical proximity effect correction; wherein, the graphic of the virtual structure is optimized as a graphic of the functional device; Weakness detection is performed on the layout design after the first optical proximity effect correction, and process weaknesses caused by the graphics of the virtual structure are screened out. To address the process weaknesses caused by the graphics of the virtual structure, a second optical proximity effect correction is employed for optimization; wherein, the second optical proximity effect correction operates on the graphics of the virtual structure; The layout design is then subjected to another weakness detection to determine whether the process weaknesses caused by the graphics of the virtual structure have been optimized.

2. The method for improving the photolithography process window as described in claim 1, characterized in that, Before providing a layout design, the following are also included: The virtual structure's graphic representation is identified during the layout design phase; The virtual structure is identified using a specific layer.

3. The method for improving the photolithography process window as described in claim 1, characterized in that, The iterative optimization of the layout design using the first optical proximity effect correction includes: A photolithography model is established, which includes an optical model and a photoresist photochemical reaction model. Identify the graphic edges of the functional devices and the graphic edges of the virtual structures in the layout design, and allow each edge to move freely; The edge position is continuously moved, and the corresponding post-exposure pattern is calculated based on the lithography model. The result is compared with the layout design to obtain the corresponding edge placement error until the calculated edge placement error reaches the set value.

4. The method for improving the photolithography process window as described in claim 1, characterized in that, The vulnerability detection of the layout design includes: Build a rule base based on experience; Weakness detection is performed on the layout design based on the established rule base.

5. The method for improving the photolithography process window as described in claim 1, characterized in that, The process of performing weakness detection on the layout design after optical proximity correction and screening out process weaknesses caused by the graphics of the virtual structure includes: Weakness detection is performed on the layout design, and the detected process weaknesses are categorized; wherein, the categorized categories include process weaknesses caused by the graphics of the virtual structure.

6. The method for improving the photolithography process window as described in claim 1, characterized in that, The parameters used for weakness detection include: Mask error enhancement factor, normalized graph log slope, depth of field, key dimension variation, and key dimension uniformity.

7. The method for improving the photolithography process window as described in claim 1, characterized in that, The optimization of process weaknesses caused by the graphics of the virtual structure using a second optical proximity effect correction includes: A photolithography model is established, which includes an optical model and a photoresist photochemical reaction model. Obtain the adjustment range of the virtual structure's graphic; The virtual structure's shape is adjusted within the adjustment range, and the corresponding simulated process morphology is obtained based on the lithography model.

8. The method for improving the photolithography process window as described in claim 7, characterized in that, Adjusting the virtual structure's graphics within the adjustment range includes: Adjust the geometric dimensions, spacing from surrounding graphics, area, and position of the virtual structure.

9. A readable storage medium, characterized in that, The readable storage medium stores a computer program, which, when executed by a processor, implements the method for improving the photolithography process window as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, The device includes a processor and a memory, wherein the memory stores a computer program that, when executed by the processor, implements the method for improving the photolithography process window as described in any one of claims 1 to 8.

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