Overlay accuracy measurement method

Abstract

The present invention discloses a method for measuring overlay accuracy, comprising the following steps: Step 1, providing an underlying structure on which a previous layer overlay mark has been formed. Step 2, defining a step area that is larger than the previous layer overlay mark area. Step 3, performing etching to form a platform structure surrounded by a first step in the step area. Step 4, coating a first photoresist layer, wherein the first photoresist layer has a first thickness on the top surface of the platform structure and a larger second thickness on the top surface of the first step peripheral area, wherein the second thickness is a target thickness. Step 5, forming a current layer overlay mark in the first photoresist layer in the step area, utilizing the feature of the smaller first thickness to reduce the graphic asymmetry caused by the graphic stress asymmetry, and improve the symmetry of the graphic of the current layer overlay mark. Step 6, performing measurement to obtain overlay accuracy. The present invention can eliminate the adverse effects of thick films on overlay accuracy measurement, can effectively monitor online product quality and improve yield.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit manufacturing method, in particular to an overlay accuracy measurement method. Background Art

[0002] In integrated circuit manufacturing, photolithography involves replicating the mask pattern onto the wafer through a series of steps. Typical photolithography processes include wafer surface coating, baking, exposure, post-baking, development, and inspection. Ion implantation layer photolithography primarily provides a masking layer for ion implantation. Photoresist is used as a shield for the ion implantation layer. Areas of the wafer where ion implantation is not desired are covered with photoresist, while areas where ion implantation is desired are removed through development. Deeper ion implantation layers require thicker photoresist to prevent ion breakdown and device performance. Thick photoresist can lead to asymmetric patterns in the open areas, a phenomenon particularly pronounced with non-chemically amplified photoresist. Poor photoresist pattern symmetry can even affect lithography overlay accuracy measurements, leading to measurement distortion and ineffective online product quality monitoring, potentially impacting product yield.

[0003] like Figure 1 As shown, it is a schematic diagram of the device structure after the existing overlay accuracy measurement method completes the photolithography process of the current layer overlay mark; the photoresist 104 is coated on the wafer 101, and a front layer overlay mark 102 is formed on the wafer 101, and the front layer overlay mark 102 is formed by arranging multiple graphics 103.

[0004] In the photoresist 104 , in addition to forming a photoresist mask pattern 107 for defining a product pattern such as a masking layer pattern for ion implantation, a current layer overlay mark 105 also needs to be formed. Figure 1 In the embodiment, the photoresist mask pattern 107 includes a plurality of trenches 108 and stripes between the trenches 108. The pattern 106 of the current layer overlay mark 105 in the photoresist 104 is also a trench.

[0005] Because photoresist mask pattern 107 needs to serve as a shielding layer, or mask layer, the thickness of photoresist 104 is determined by the function it performs. For example, when used as a mask layer for ion implantation, a greater thickness is required. In this case, pattern 106 of the current layer's overlay mark 105 may have an asymmetric structure. For example, the top width of a pattern represented by mark 106a alone may increase, meaning the opening of pattern 106a may extend outside the defined area. This can distort the measured overlay accuracy, defined by the spacing between pattern 106a and the underlying pattern 103.

[0006] like Figure 2A As shown, Figure 1A cross-sectional structural photograph of the current layer with overlay marks; Figure 2B yes Figure 1 A top-view structural photograph of the current layer with overlay marks; Figure 2B In the figure, dotted line 106a2 is the bottom surface of graphic 106a, i.e., the structure of the photolithography defined area, and dotted line 106a1 is the structure of the top surface of graphic 106a. Therefore, it can be seen that one side of graphic 106a extends outside the defined area, thereby increasing the top opening.

[0007] Figure 1 The asymmetry of the pattern 106a is more obvious when the photoresist 104 is a non-chemically amplified photoresist. The mechanism of the asymmetry of the pattern opening area of ​​the non-chemically amplified photoresist is further explained below:

[0008] like Figure 3A The figure shows the nitrogen volatilization during the photochemical reaction of conventional non-chemically amplified photoresists during photolithography. During the photolithography process of forming the spacer region 202, the photoresist 201 generates outgassing, which is formed by the volatilization of N2. Unlike chemically amplified photoresists (CARs), non-chemically amplified photoresists do not rely on acid catalysis. They undergo photolysis reaction directly after exposure, resulting in a change in solubility. Figure 3B As shown, it is the chemical equation of the photochemical reaction when using the existing non-chemical amplification glue for photolithography. It can be deduced that nitrogen gas will be emitted during the photolithography process.

[0009] Therefore, the main reason for the asymmetry of the graphic opening area of ​​non-chemical amplification glue is that the reaction of non-chemical amplification glue will produce N2. The produced N2 will squeeze the existing photoresist during the elimination process. When the opened area is asymmetric on the left and right, the photoresist opening area will also become asymmetric. Solving this left-right asymmetry caused by graphic device design requires a large investment of resources. How to solve this asymmetry problem has become a more urgent matter at present.

[0010] Some existing improvement methods include:

[0011] One method is to increase the photoresist baking temperature during the photolithography process. By increasing the photoresist baking temperature, the asymmetry of the photoresist morphology can be partially alleviated.

[0012] One method is to change the design of the graphics when the previous method cannot effectively solve the problem, but this is time-consuming and laborious. Summary of the Invention

[0013] The technical problem to be solved by the present invention is to provide a method for measuring overlay accuracy, which can eliminate the adverse effect of the larger photoresist film thickness corresponding to the overlay mark of the current layer on the overlay accuracy measurement, thereby effectively monitoring the online product quality and improving the product yield.

[0014] To solve the above technical problems, the present invention provides an overlay accuracy measurement method comprising the following steps:

[0015] Step 1: providing a bottom layer structure on which a front layer overlay mark has been formed.

[0016] Step 2: defining a step area, wherein the step area is larger than the previous layer overlay mark area and the previous layer overlay mark area is located inside the step area.

[0017] Step 3: Etching is performed to form a platform structure in the step region, wherein the peripheral side of the platform structure is surrounded by the first step.

[0018] Step 4: Apply a first photoresist layer, wherein the first photoresist layer has a first thickness on the top surface of the platform structure, and has a second thickness on the top surface of the first step side area of ​​the platform structure, wherein the second thickness is the target thickness that the first photoresist layer needs to reach during the coating; the first thickness is less than the second thickness.

[0019] Step 5: forming a current layer overlay mark in the first photoresist layer in the step region.

[0020] During the process of forming the overlay mark of the current layer, the feature of the first thinner thickness is utilized to reduce the pattern asymmetry caused by the pattern stress asymmetry, thereby improving the pattern symmetry of the overlay mark of the current layer.

[0021] Step 6: Obtain overlay accuracy by measuring the offset between the overlay mark of the current layer and the overlay mark of the previous layer.

[0022] A further improvement is that the distance between the peripheral edge of the step area and the peripheral edge of the front layer overlay mark area is 5 μm to 300 μm.

[0023] A further improvement is that the first thickness is determined by the height of the first step, and the optimal height of the first step is determined by the following steps:

[0024] In step 1, n underlying structures are provided, and all of the n underlying structures are test wafers;

[0025] Then, repeating the process steps from step 2 to step 6 for each of the underlying structures;

[0026] For each of the bottom structures, the height of the first step in step 3 is set separately, so that n bottom structures have a total of n first steps of height;

[0027] The same second thickness is used in step 4 of each of the bottom structures;

[0028] After completing step 6 of n bottom structures, obtain n groups of data on the heights of the first steps and the corresponding overlay accuracy;

[0029] An optimal data group is selected from n groups of data on the heights of the first steps and the corresponding overlay accuracy, wherein the overlay accuracy is optimal in the optimal data group, and the first step height corresponding to the optimal overlay accuracy is taken as the optimal height.

[0030] A further improvement is that after the optimal height of the first step is selected, in the subsequent process steps of steps one to six on the underlying structure, in step three, the height of the first step adopts the optimal height.

[0031] A further improvement is that the subsequent underlying structure includes a product wafer.

[0032] A further improvement is to select the optimal data set from n sets of data on the heights of the first steps and the corresponding overlay accuracies by a curve fitting method.

[0033] A further improvement is that, in step 2, the step region is defined by a first mask.

[0034] A further improvement is that the first mask is prepared according to the coordinate values ​​of the front layer overlay mark area.

[0035] A further improvement is that step 2 includes the following sub-steps:

[0036] A zeroth photoresist layer is applied.

[0037] The first photomask is used to perform photolithography on the zeroth photoresist layer to form a pattern of the zeroth photoresist layer.

[0038] In step three, the etching is performed using the pattern of the zeroth photoresist layer as a mask, and the zeroth photoresist layer is removed after the etching is completed.

[0039] A further improvement is that the photolithography steps performed on the zeroth photoresist layer include: exposure, baking and development.

[0040] A further improvement is that, in step 2, the step region is covered by the zeroth photoresist layer, and the zeroth photoresist layer outside the step region is removed.

[0041] A further improvement is that the front layer overlay mark includes a plurality of patterns, the patterns of the front layer overlay mark include a dielectric layer filled in a groove, and the groove is formed in the bottom structure.

[0042] A further improvement is that each pattern of the front layer overlay mark includes a bar.

[0043] A further improvement is that the graphic of the current layer overlay mark includes a bar.

[0044] A further improvement is that the current layer overlay mark area is smaller than the previous layer overlay mark area and the current layer overlay mark area is located inside the previous layer overlay mark area.

[0045] A further improvement is that the material of the first photoresist layer includes non-chemical photoresist.

[0046] A further improvement is that when the underlying structure is the product wafer, step five further includes a photoresist mask pattern in the first photoresist layer outside the step area.

[0047] The photoresist mask pattern is used to define an ion implantation or etching area, and the second thickness is set according to the ion implantation or etching process defined by the photoresist mask pattern.

[0048] The present invention predefines a step region and etches to form a platform structure surrounded by the first step before coating the first photoresist layer of the current layer overlay mark. The step region covers the previous layer overlay mark region and is larger than the previous layer overlay mark region. Since the top surface of the platform structure is higher than the top surface outside the platform structure, after the first photoresist layer is coated, the first photoresist layer on the top surface of the platform structure has a thinner first thickness. In this way, even if the target thickness of the first photoresist layer needs to reach a larger second thickness, the first thickness of the first photoresist layer in the step region can still be kept at a smaller value. Since the current layer overlay mark is formed in the step region, In the first photoresist layer of the domain, the pattern of the current layer's overlay mark will only be affected by the first thickness, and will not be affected by the larger second thickness; at the same time, the first step itself will also improve the stress symmetry of the pattern of the current layer's overlay mark. The combined effect of the first thickness and the first step can ensure that the symmetry of the pattern of the current layer's overlay mark will not be adversely affected by the second thickness, so that the overlay accuracy can accurately reflect the actual overlay situation, thereby achieving effective monitoring of the product process. Therefore, the present invention can eliminate the adverse effect of the larger photoresist film thickness corresponding to the current layer's overlay mark on the overlay accuracy measurement, thereby effectively monitoring the online product quality and improving the product yield.

[0049] In addition, the present invention does not require changing the graphic design, which can save time and manpower consumption caused by changing the graphic design, and can save time and labor. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0051] Figure 1 It is a schematic diagram of the device structure after the current layer overlay mark lithography process is completed using the existing overlay accuracy measurement method;

[0052] Figure 2A yes Figure 1 A cross-sectional structural photograph of the current layer with overlay marks;

[0053] Figure 2B yes Figure 1 A top-view structural photograph of the current layer with overlay marks;

[0054] Figure 3A This is a schematic diagram of the volatilization of nitrogen during photochemical reaction in conventional photolithography using non-chemical amplification resin;

[0055] Figure 3B It is the chemical equation of the photochemical reaction when using non-chemical amplification glue for photolithography;

[0056] Figure 4 is a flow chart of a method for measuring overlay accuracy according to an embodiment of the present invention;

[0057] Figure 5 2 is a schematic diagram of the device structure after the overlay accuracy measurement method according to an embodiment of the present invention completes the photolithography process of the overlay mark of the current layer;

[0058] Figure 6 1. It is a top view structural diagram of the current layer overlay mark and the previous layer overlay mark formed by the overlay accuracy measurement method according to an embodiment of the present invention;

[0059] Figure 7 It is a curve formed by data of the heights of n groups of first steps and the corresponding overlay accuracies obtained by the overlay accuracy measurement method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0060] like Figure 4 FIG. 1 is a flow chart of a method for measuring overlay accuracy according to an embodiment of the present invention; FIG. Figure 5 FIG. 2 is a schematic diagram of a device structure after the photolithography process of the current layer overlay mark 306 is completed by the overlay accuracy measurement method according to an embodiment of the present invention. The overlay accuracy measurement method according to an embodiment of the present invention includes the following steps:

[0061] Step 1: Provide a bottom layer structure 301 , on which a front layer overlay mark 302 has been formed.

[0062] In some embodiments, as Figure 5 As shown, the front layer overlay mark 302 includes a plurality of patterns, and the pattern 303 of the front layer overlay mark 302 includes a dielectric layer filled in a groove, and the groove is formed in the bottom structure 301.

[0063] Each graphic 303 of the front layer overlay mark 302 includes a bar.

[0064] like Figure 6 , which is a top view of the structure of the current layer overlay mark 306 and the previous layer overlay mark 302 formed by the overlay accuracy measurement method according to an embodiment of the present invention; it can be seen that Figure 6 In some specific embodiments shown, the front layer overlay mark 302 is formed by four patterns 303 surrounding each other to form a square structure. In other embodiments, the structure and arrangement of the patterns 303 of the front layer overlay mark 302 can also be set as needed. Figure 6 The structure in which the four graphics 303 are arranged in a square is only used as an example to facilitate a more intuitive understanding of the embodiment of the present invention, but is not intended to limit the structure of the current layer overlay mark 306 in the embodiment of the present invention.

[0065] Step 2: define a step area, wherein the step area is larger than the front layer overlay mark 302 area and the front layer overlay mark 302 area is located inside the step area.

[0066] In some embodiments, a distance between a peripheral edge of the step region and a peripheral edge of the front layer overlay mark 302 region is 5 μm to 300 μm.

[0067] In the embodiment of the present invention, the step region is defined by a first mask.

[0068] The first mask is prepared according to the coordinate values ​​of the front layer overlay mark 302 area.

[0069] Step 2 includes the following sub-steps:

[0070] A zeroth photoresist layer (not shown) is applied.

[0071] The first photomask is used to perform photolithography on the zeroth photoresist layer to form a pattern of the zeroth photoresist layer.

[0072] The photolithography steps performed on the zeroth photoresist layer include: exposure, baking and development.

[0073] In some embodiments, the step region is covered by the zeroth photoresist layer, and the zeroth photoresist layer outside the step region is removed.

[0074] Step 3: Etching is performed to form a platform structure 301 a in the step region. The periphery of the platform structure 301 a is surrounded by the first step 304 .

[0075] In the embodiment of the present invention, the etching is performed using the pattern of the zeroth photoresist layer as a mask, and the zeroth photoresist layer is removed after the etching is completed.

[0076] Step 4: Apply a first photoresist layer 305. The first photoresist layer 305 has a first thickness D1 on the top surface of the platform structure 301a, and has a second thickness D2 on the top surface of the peripheral area of ​​the first step 304 of the platform structure 301a. The second thickness D2 is the target thickness that the first photoresist layer 305 needs to reach during the coating; the first thickness D1 is less than the second thickness D2.

[0077] In an embodiment of the present invention, the material of the first photoresist layer 305 includes a non-chemical photoresist. In other embodiments, the material of the first photoresist layer 305 may also be other types of photoresists, such as chemical photoresists. Because non-chemical photoresists produce more severe pattern asymmetry when they are thicker, the embodiments of the present invention are particularly capable of resolving the technical problem of overlay accuracy measurement distortion caused by pattern asymmetry of non-chemical photoresists during the photolithography process.

[0078] Step five: forming a current layer overlay mark 306 in the first photoresist layer 305 in the step region.

[0079] During the process of forming the current layer overlay mark 306 , the smaller characteristic of the first thickness D1 is utilized to reduce pattern asymmetry caused by pattern stress asymmetry, thereby improving the symmetry of the pattern 307 of the current layer overlay mark 306 .

[0080] like Figure 6 As shown, in some embodiments, the pattern 307 of the current layer overlay mark 306 includes a bar. Figure 5 In the embodiment, the pattern 307 of the current layer overlay mark 306 is a groove or trench structure.

[0081] like Figure 6 As shown, the current layer overlay mark 306 area is smaller than the previous layer overlay mark 302 area and the current layer overlay mark 306 area is located inside the previous layer overlay mark 302 area. Figure 6 In FIG. 3 , the current layer overlay mark 306 also has four patterns 307 , and the four patterns 307 surround to form a square structure.

[0082] Step 6: Obtain overlay accuracy by measuring the offset between the current layer overlay mark 306 and the previous layer overlay mark 302 .

[0083] like Figure 7 3 is a graph showing the heights of n groups of first steps and the corresponding overlay accuracy data obtained by the overlay accuracy measurement method according to an embodiment of the present invention. In the embodiment of the present invention, the first thickness D1 is determined by the height H of the first step 304. The optimal height of the first step 304 is determined by the following steps:

[0084] In step 1, n underlying structures 301 are provided, and all of the n underlying structures 301 are test wafers. In some embodiments, the test wafers include silicon wafers.

[0085] Then, the process steps from step 2 to step 6 are repeated for each of the bottom structures 301;

[0086] For each of the underlying structures 301 , the height H of the first step 304 in step 3 is set individually, so that n underlying structures 301 have n first steps 304 of a total height. Figure 7 In the example, n is 24, and a total of 24 heights H of the first steps 304 are obtained. The 24 heights H of the first steps 304 are represented by H1, H2 to H24 respectively.

[0087] In step 4, each of the bottom structures 301 uses the same second thickness D2;

[0088] After step 6 of n bottom structures 301 is completed, data of the height H of n groups of the first steps 304 and the corresponding overlay accuracy are obtained.

[0089] An optimal data group is selected from n groups of data on the height H of the first step 304 and the corresponding overlay accuracy, wherein the overlay accuracy is optimal. The height of the first step 304 corresponding to the optimal overlay accuracy is taken as the optimal height.

[0090] In some embodiments, the optimal data set is selected from n sets of data on the height H of the first step 304 and the corresponding overlay accuracy by a curve fitting method. Figure 7 As shown, curve 401 is the curve obtained by fitting. Figure 7 The middle vertical coordinate is represented by the overlay accuracy index. It can be seen that the overlay accuracy at the dotted circle 402 can reach the minimum value, and the measured value of the overlay accuracy is the best, so the height H11 at the dotted circle 402 can be selected as the optimal height.

[0091] After the optimal height of the first step 304 is selected, in the subsequent process steps of step 1 to step 6 on the bottom structure 301, in step 3, the height H of the first step 304 adopts the optimal height.

[0092] In an embodiment of the present invention, the subsequent underlying structure 301 comprises a product wafer. Thus, after the optimal height is selected, the overlay accuracy of the product wafer can be effectively monitored online, effectively monitoring online product quality and improving product yield. In some embodiments, the product wafer comprises a silicon wafer.

[0093] When the bottom structure 301 is the product wafer, Figure 5 As shown, step five also includes forming a photoresist mask pattern 308 in the first photoresist layer 305 outside the step area. Figure 5 In the embodiment, the photoresist mask pattern 308 includes a plurality of trenches 309 .

[0094] In some embodiments, the photoresist mask pattern 308 is used to define an ion implantation or etching region, and the second thickness D2 is set according to the ion implantation or etching process defined by the photoresist mask pattern 308. For example, in some ion implantation processes, the photoresist mask pattern 308 is used as a mask, the trench 309 defines the ion implantation region, and the outside of the trench 309 is covered by the first photoresist layer 305 to prevent ions from being implanted into the underlying structure 301. When the implantation energy of the ion implantation increases, the second thickness D2 of the first photoresist layer 305 needs to be increased to prevent ions from being implanted into the underlying structure 301.

[0095] In the embodiment of the present invention, before coating the first photoresist layer 305 of the current layer overlay mark 306, a step region is pre-defined and etching is performed to form a platform structure 301a surrounded by the first step 304 in the step region. The step region covers the previous layer overlay mark 302 region and is larger than the previous layer overlay mark 302 region. Since the top surface of the platform structure 301a is higher than the top surface outside the platform structure 301a, after the first photoresist layer 305 is coated, the first photoresist layer 305 on the top surface of the platform structure 301a has a thinner first thickness D1. In this way, even if the target thickness of the first photoresist layer 305 needs to reach a larger second thickness D2, the first thickness of the step region can still be kept thinner. The first thickness D1 of the photoresist layer 305 is kept at a small value, and since the current layer overlay mark 306 is formed in the first photoresist layer 305 in the step area, the graphic 307 of the current layer overlay mark 306 will only be affected by the first thickness D1, and will not be affected by the larger second thickness D2; at the same time, the first step 304 itself will also improve the stress symmetry of the graphic 307 of the current layer overlay mark 306. The combined effect of the first thickness D1 and the first step 304 can ensure that the symmetry of the graphic 307 of the current layer overlay mark 306 will not be adversely affected by the second thickness D2, so that the overlay accuracy can accurately reflect the actual overlay situation, thereby realizing effective monitoring of the product process.

[0096] Therefore, the embodiment of the present invention can eliminate the adverse effect of the larger photoresist film thickness corresponding to the current layer overlay mark 306 on overlay accuracy measurement, thereby effectively monitoring online product quality and improving product yield.

[0097] In addition, the embodiment of the present invention does not require changing the graphic design, which can save time and manpower consumption caused by changing the graphic design, and can save time and labor.

[0098] The embodiments of the present invention can improve the measurement accuracy of thick film overlay accuracy and alleviate the problem of distortion in photolithography overlay accuracy measurement caused by pattern asymmetry in thick film photolithography.

[0099] The embodiment of the present invention prepares a mask that only covers the area at the overlay mark through the overlay accuracy coordinate value of the current layer relative to the previous layer, so that a wafer with different etching steps is obtained through etching. The platform structure and the step sidewalls can effectively prevent the asymmetry of the pattern caused by the asymmetry of the stress on the left and right sides, and then optimize the measurement, measure the overlay accuracy index of the current layer relative to the previous layer, and find the optimal solution of the etching step corresponding to the overlay accuracy. Finally, it can effectively solve the problem of distortion of the overlay accuracy measurement due to the asymmetric overlay accuracy morphology caused by the thick film process, effectively monitor the quality of online products, and improve the yield of products.

[0100] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A method for measuring overlay accuracy, characterized in that: The steps include: Step 1: providing a bottom layer structure, on which a front layer overlay mark has been formed; Step 2: defining a step area, wherein the step area is larger than the previous layer overlay mark area and the previous layer overlay mark area is located inside the step area; Step 3: Etching is performed to form a platform structure in the step area, wherein the periphery of the platform structure is surrounded by the first step; Step 4: coating a first photoresist layer, wherein the first photoresist layer has a first thickness on the top surface of the platform structure and a second thickness on the top surface of the first step peripheral region of the platform structure, wherein the second thickness is a target thickness that the first photoresist layer needs to achieve during the coating; the first thickness is less than the second thickness; Step 5: forming a current layer overlay mark in the first photoresist layer in the step area; In the process of forming the overetch mark of the current layer, the feature of the first thickness being relatively small is utilized to reduce the pattern asymmetry caused by the pattern stress asymmetry, thereby improving the pattern symmetry of the overetch mark of the current layer; Step 6: Obtain overlay accuracy by measuring the offset between the overlay mark of the current layer and the overlay mark of the previous layer.

2. The overlay accuracy measurement method according to claim 1, wherein: The distance between the peripheral edge of the step area and the peripheral edge of the front layer overlay mark area is 5 μm to 300 μm.

3. The overlay accuracy measurement method according to claim 1, wherein: The first thickness is determined by the height of the first step, and the optimal height of the first step is determined by the following steps: In step 1, n underlying structures are provided, and all of the n underlying structures are test wafers; Then, repeating the process steps from step 2 to step 6 for each of the underlying structures; For each of the bottom structures, the height of the first step in step 3 is set separately, so that n bottom structures have a total of n first steps of height; The same second thickness is used in step 4 of each of the bottom structures; After completing step 6 of n bottom structures, obtain n groups of data on the heights of the first steps and the corresponding overlay accuracy; An optimal data group is selected from n groups of data on the heights of the first steps and the corresponding overlay accuracy, wherein the overlay accuracy is optimal in the optimal data group, and the first step height corresponding to the optimal overlay accuracy is taken as the optimal height.

4. The overlay accuracy measurement method according to claim 3, wherein: After the optimal height of the first step is selected, in the subsequent process steps of step 1 to step 6 for the underlying structure, in step 3, the height of the first step adopts the optimal height.

5. The overlay accuracy measurement method according to claim 4, wherein: The subsequent underlying structure includes a product wafer.

6. The overlay accuracy measurement method according to claim 4, wherein: The optimal data set is selected from n sets of data on the heights of the first steps and the corresponding overlay accuracies by a curve fitting method.

7. The overlay accuracy measurement method according to claim 2, wherein: In step 2, the step region is defined using a first mask.

8. The overlay accuracy measurement method according to claim 7, wherein: The first mask is prepared according to the coordinate values ​​of the front layer overlay mark area.

9. The overlay accuracy measurement method according to claim 7, wherein: Step 2 includes the following steps: coating a zeroth photoresist layer; Performing photolithography on the zeroth photoresist layer using the first photomask to form a pattern of the zeroth photoresist layer; In step three, the etching is performed using the pattern of the zeroth photoresist layer as a mask, and the zeroth photoresist layer is removed after the etching is completed.

10. The overlay accuracy measurement method according to claim 9, wherein: The photolithography steps performed on the zeroth photoresist layer include: exposure, baking and development.

11. The overlay accuracy measurement method according to claim 9, wherein: In step 2, the step region is covered by the zeroth photoresist layer, and the zeroth photoresist layer outside the step region is removed.

12. The overlay accuracy measurement method according to claim 1, wherein: The front layer overlay mark includes a plurality of patterns. The patterns of the front layer overlay mark include a dielectric layer filled in a groove. The groove is formed in the bottom layer structure.

13. The overlay accuracy measurement method according to claim 12, wherein: Each graphic of the front layer overlay mark includes a bar.

14. The overlay accuracy measurement method according to claim 13, wherein: The graphic of the current layer overlay mark includes a bar.

15. The overlay accuracy measurement method according to claim 1, wherein: The current layer overlay mark area is smaller than the previous layer overlay mark area and the current layer overlay mark area is located inside the previous layer overlay mark area.

16. The overlay accuracy measurement method according to claim 1, wherein: The material of the first photoresist layer includes non-chemical photoresist.

17. The overlay accuracy measurement method according to claim 5, wherein: When the underlying structure is the product wafer, step five further includes forming a photoresist mask pattern in the first photoresist layer outside the step area; The photoresist mask pattern is used to define an ion implantation or etching area, and the second thickness is set according to the ion implantation or etching process defined by the photoresist mask pattern.

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