A system, method, electronic device and storage medium for status monitoring

Abstract

The present application provides a system, method, electronic device and storage medium for state monitoring, the system comprising: a device under test, a field programmable gate array (FPGA) and a host computer; the host computer is connected to the FPGA, and the FPGA is connected to the device under test; the device under test is used to generate a sampled signal and multiple drive trigger signals; the FPGA is used to determine a target acquisition interval according to the multiple drive trigger signals; and to perform data acquisition on the sampled signal in the target acquisition interval; the host computer is used to issue control parameters, determine target acquisition parameters, save and analyze the collected data, and determine the working state of the device under test. The present application comprehensively monitors the device under test, analyzes operating efficiency, optimizes energy consumption, and predicts possible abnormal conditions in advance.

Description

Technical Field

[0001] The present application relates to the technical field of condition monitoring, and in particular to a system, method, electronic device and storage medium for condition monitoring. Background Art

[0002] With the continuous development of industrial technology, the intelligence of industrial equipment is increasing. In intelligent industrial equipment, the working efficiency, operation stability and health of the equipment are key factors affecting the overall production quality and benefits. In order to ensure the smooth progress of work, it is necessary to monitor the working status of industrial equipment.

[0003] In the prior art, when monitoring the working status of industrial equipment, the relevant operating parameters of the industrial equipment are directly analyzed. This method analyzes the operating parameters in the entire operating cycle, and does not consider the relationship between the operating parameters and other signals generated by the industrial equipment. Not only does it require processing a large amount of data, but the accuracy of the results obtained is not enough. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a system, method, electronic device and storage medium for status monitoring to overcome the problems in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a method for state monitoring, a system for state monitoring, the system comprising: a device under test, a field programmable gate array FPGA and a host computer; the host computer is connected to the FPGA, and the FPGA is connected to the device under test;

[0006] The device under test is used to generate a sampled signal and a plurality of drive trigger signals;

[0007] The FPGA is used to determine a target acquisition interval according to the multiple drive trigger signals; and perform data acquisition on the sampled signal within the target acquisition interval;

[0008] The host computer is used to send control parameters, determine target acquisition parameters, save and analyze the acquired data, and determine the working status of the device under test.

[0009] In some technical solutions of the present application, the above-mentioned multiple driving trigger signals include a first driving trigger signal and a second driving trigger signal; wherein the first driving trigger signal corresponds to a first acquisition interval, and the second driving trigger signal corresponds to a second acquisition interval;

[0010] The FPGA is used to determine a target acquisition interval according to the multiple drive trigger signals, including:

[0011] A combination of the first acquisition interval and the second acquisition interval is used as the target acquisition interval.

[0012] In some technical solutions of the present application, the above-mentioned target acquisition parameters include a first acquisition parameter and a second acquisition parameter; the device under test includes a motor;

[0013] The device under test is used to generate multiple drive trigger signals, including:

[0014] The operation range of the motor is calibrated according to the first acquisition parameter to obtain a first drive trigger signal.

[0015] The peak value or the zero-crossing point of the quasi-sine signal generated by the actual operating state of the device under test is detected according to the second acquisition parameter to generate the second drive trigger signal.

[0016] In some technical solutions of the present application, the above-mentioned multiple drive trigger signals include a first drive trigger signal and a second drive trigger signal; a first transmission channel, a second transmission channel and a third transmission channel are arranged between the FPGA and the device under test; wherein the first transmission channel is used to transmit the first drive trigger signal, the second transmission channel is used to transmit the second drive trigger signal; the third transmission channel is used to transmit the sampled signal;

[0017] The first transmission channel includes a motor encoder, a CAN bus and a CAN transceiver; the host computer is used to send control parameters, determine target acquisition parameters, save and analyze the acquired data, and determine the working status of the device under test.

[0018] The second transmission channel and the third transmission channel both include a signal conditioning module and an analog-to-digital conversion module; wherein the signal conditioning module is connected to the device under test and the analog-to-digital conversion module respectively, and the analog-to-digital conversion module is connected to the FPGA.

[0019] In some technical solutions of the present application, the motor encoder is mounted on the motor and is used to provide a closed-loop feedback signal by tracking the speed and / or position of the motor shaft;

[0020] The sampled signal is a DC jitter signal within a preset voltage range; the second drive trigger signal is a quasi-sinusoidal signal;

[0021] The signal conditioning module is used to adjust the sampled signal and the second drive trigger signal so that the sampled signal and the second drive trigger signal are adapted to the analog-to-digital conversion module;

[0022] The analog-to-digital conversion module is used to convert the adjusted sampled signal and the second drive trigger signal into corresponding digital signals.

[0023] In some technical solutions of the present application, the above-mentioned multiple driving trigger signals include a first driving trigger signal and a second driving trigger signal;

[0024] The FPGA includes: a signal recovery module, a filtering module, a trigger detection module, a sampling module, an AXI read-write module and a CAN protocol analysis module; wherein the signal recovery module is used to receive the sampled signal and the second drive trigger signal; the signal recovery module is respectively connected to the filtering module and the trigger detection module; the filtering module and the trigger detection module are both connected to the sampling module; the sampling module is connected to the AXI read-write module; the AXI read-write module is also connected to the filtering module and the trigger detection module; the CAN protocol analysis module is used to receive the first drive trigger signal; the CAN protocol analysis module is respectively connected to the sampling module and the AXI read-write module.

[0025] In a second aspect, an embodiment of the present application provides a method for state monitoring, which acts on a system for state monitoring, the system comprising: a device under test, a field programmable gate array FPGA and a host computer; the host computer is connected to the FPGA, and the FPGA is connected to the device under test; the method comprises:

[0026] The device under test generates a sampled signal and a plurality of drive trigger signals;

[0027] The FPGA determines a target acquisition interval according to the multiple drive trigger signals; and performs data acquisition on the sampled signal in the target acquisition interval;

[0028] The host computer is used to send control parameters, determine target acquisition parameters, save and analyze the acquired data, and determine the working status of the device under test.

[0029] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned status monitoring method when executing the computer program.

[0030] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned state monitoring method are executed.

[0031] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0032] The status monitoring system in the present application includes a device under test, a field programmable gate array (FPGA) and a host computer; the host computer is connected to the FPGA, and the FPGA is connected to the device under test; the device under test is used to generate a sampled signal and multiple drive trigger signals; the FPGA is used to determine a target acquisition interval based on the multiple drive trigger signals; and to perform data acquisition on the sampled signal in the target acquisition interval to obtain acquisition data; the host computer is used to issue control parameters, determine target acquisition parameters, save acquisition data and analyze the acquisition data to determine the working status of the device under test. The present application comprehensively monitors the device under test, analyzes operating efficiency, optimizes energy consumption, and predicts possible abnormal conditions in advance.

[0033] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of a status monitoring system provided by an embodiment of the present application is shown;

[0036] Figure 2 A schematic diagram of an overall functional block diagram provided by an embodiment of the present application is shown;

[0037] Figure 3 A schematic diagram of smoothing mean filtering of a sampled signal provided in an embodiment of the present application is shown;

[0038] Figure 4 A schematic diagram of a quasi-sine signal provided in an embodiment of the present application is shown;

[0039] Figure 5 A schematic diagram of a filtering module provided in an embodiment of the present application is shown;

[0040] Figure 6 A schematic diagram of a dual-trigger acquisition process provided by an embodiment of the present application is shown;

[0041] Figure 7 A schematic diagram of a flow chart of a method for status monitoring provided in an embodiment of the present application is shown;

[0042] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0044] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0045] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0046] With the continuous development of industrial technology, the intelligence of industrial equipment is increasing. In intelligent industrial equipment, the working efficiency, operation stability and health of the equipment are key factors affecting the overall production quality and benefits. In order to ensure the smooth progress of work, it is necessary to monitor the working status of industrial equipment.

[0047] In the prior art, when monitoring the working status of industrial equipment, the relevant operating parameters of the industrial equipment are directly analyzed. This method analyzes the operating parameters in the entire operating cycle, and does not consider the relationship between the operating parameters and other signals generated by the industrial equipment. Not only does it require processing a large amount of data, but the accuracy of the results obtained is not enough.

[0048] Based on this, the embodiments of the present application provide a system, method, electronic device and storage medium for state monitoring, and some implementation methods of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0049] Figure 1 A schematic diagram of the structure of a state monitoring device provided in an embodiment of the present application is shown, wherein the system comprises: a device under test, a field programmable gate array FPGA and a host computer; the host computer is connected to the FPGA, and the FPGA is connected to the device under test;

[0050] The device under test is used to generate a sampled signal and a plurality of drive trigger signals;

[0051] The FPGA is used to determine a target acquisition interval according to the multiple drive trigger signals; and perform data acquisition on the sampled signal in the target acquisition interval;

[0052] The host computer is used to send control parameters, determine target acquisition parameters, save and analyze the acquired data, and determine the working status of the device under test.

[0053] The device under test in the embodiment of the present application can be an industrial device including a motor, such as a high-precision CNC machine tool, an industrial robot, an electric vehicle motor, etc. The host computer here can be a device such as a computer that has data input and data processing functions.

[0054] When the user monitors the device under test, the target acquisition parameters need to be determined. The target acquisition parameters here can be determined according to the test requirements of the actual device under test. After determining the target acquisition parameters, the target acquisition parameters are input into the host computer by performing data input operations on the host computer. The host computer sends the target acquisition parameters to the field programmable gate array (FPGA). The FPGA processes the multiple drive trigger signals generated by the device under test according to the target acquisition parameters, determines the target acquisition interval, and performs data acquisition on the sampled signal in the target acquisition interval. The host computer is used to send down control parameters, determine the target acquisition parameters, save the collected data, analyze the collected data, and determine the working status of the device under test.

[0055] Specifically, the target acquisition parameters include a first acquisition parameter, a second acquisition parameter and a third acquisition parameter, wherein the first acquisition parameter acts on the first drive trigger signal, the second acquisition parameter acts on the second drive trigger signal, and the third acquisition parameter is the length of a single acquisition signal.

[0056] Furthermore, the first acquisition parameter calibrates the operating range of the motor to obtain the first drive trigger signal. The second acquisition parameter detects the peak value and zero crossing point of the quasi-sinusoidal signal generated by the actual operating state of the device under test to generate the second drive trigger signal. The first drive trigger signal is an angle interval trigger signal through the motor encoder to realize the calibration of the operating range. For example, each rotation is divided into 4 angle intervals, and each angle interval corresponds to a trigger acquisition process. The second drive trigger signal is a quasi-sinusoidal signal, and the user needs to set the peak or edge detection method.

[0057] This application analyzes the motor's operating efficiency, optimizes energy consumption, and predicts possible abnormal conditions of the motor in advance by monitoring the current characteristics in different angle intervals and the overall vibration signal of the motor.

[0058] In an optional embodiment, if Figure 2 As shown, a first transmission channel, a second transmission channel and a third transmission channel are provided between the FPGA and the device under test; wherein the first transmission channel is used to transmit the first drive trigger signal, the second transmission channel is used to transmit the second drive trigger signal; and the third transmission channel is used to transmit the sampled signal;

[0059] The first transmission channel includes a motor encoder, a CAN bus and a CAN transceiver; wherein the motor encoder is connected to the motor rotating shaft through a hard connection, the rotation of the motor will drive the encoder to change, and the motor encoder is connected to the CAN bus interface of the FPGA through the CAN bus for transmitting the data of the motor encoder.

[0060] The second transmission channel and the third transmission channel both include a signal conditioning module and an analog-to-digital conversion module; wherein the signal conditioning module is connected to the device under test and the analog-to-digital conversion module, respectively, and the analog-to-digital conversion module is connected to the FPGA. The motor encoder is mounted on the motor and is used to provide a closed-loop feedback signal by tracking the speed and / or position of the motor shaft;

[0061] The sampled signal is a DC jitter signal within a preset voltage range; the second drive trigger signal is a quasi-sinusoidal signal;

[0062] The signal conditioning module is used to adjust the sampled signal and the second drive trigger signal so that the sampled signal and the second drive trigger signal are adapted to the analog-to-digital conversion module;

[0063] The analog-to-digital conversion module is used to convert the adjusted sampled signal and the second drive trigger signal into corresponding digital signals.

[0064] CAN bus data is used to synchronously obtain the real-time operating status of the motor (such as speed and torque). The CAN bus signal is managed through the ARM board, and the trigger timing is precisely controlled in conjunction with the FPGA.

[0065] The sampled signals are the key operating parameters of the equipment (such as vibration, temperature, current, etc.). High-frequency data is obtained through a high sampling rate ADC (such as above 100MSPS), and the sampling rate is reduced through mean filtering (such as 800KSPS) to meet the needs of background storage and long-term monitoring. In specific applications (such as dynamic analysis of high-frequency equipment operation), higher bandwidth sampling capabilities (such as 200MSPS or 300MSPS) are required to meet future complex signal acquisition needs.

[0066] The quasi-sine signal in the second drive trigger signal is superimposed on the DC signal to achieve higher-precision sampling triggering. Within a certain angle range of the motor operation, the quasi-sine signal's zero crossing, peak, or trough is used to trigger ADC sampling. For example, when the quasi-sine signal frequency is 800kHz, the sampling time interval can reach 1.25us, achieving high-precision capture of key events.

[0067] Specifically, the signal conditioning module: the sampled signal is a DC jitter signal with a voltage range of about ±500mV, and the second drive trigger signal is a quasi-sinusoidal signal, which is a DC offset voltage superimposed with a sinusoidal wave signal, and is a non-negative value. These two signals need to use the ADC chip AD9467 to complete the analog-to-digital conversion. The two channels of collected signals need to use a signal conditioning circuit to adapt the analog signal to the amplitude range required by the analog input of the ADC chip.

[0068] AD9467: Single channel sampling, sampling rate is 250MSPS, 16bit. Two AD9467s realize dual channel sampling. AD9467 transmits the sampled digital signal to FPGA through LVDS interface.

[0069] Motor Encoder: A motor encoder is a rotary encoder mounted on a motor that provides a closed-loop feedback signal by tracking the speed and / or position of the motor shaft. The parameter monitored is determined by the type of application and can include speed, distance, RPM, position, etc. Applications that utilize an encoder or other sensor to control a specific parameter are called closed-loop feedback or closed-loop control systems. The environment in which the motor encoder is used will determine the motor encoder technology that needs to be used. Two broad motor encoder technologies are: The output of an incremental motor encoder is used to control the speed of the motor shaft. The output of an absolute motor encoder indicates the motion and position of the motor shaft. Absolute motor encoders are most commonly used on servo motors in applications that require position accuracy.

[0070] CAN transceiver: The first drive trigger signal generated by the motor encoder is a standard CAN bus signal, which is used to transmit information such as motor mechanical angle, speed, current, temperature, etc. The signal is converted into a two-wire CAN bus signal suitable for FPGAIO through the CAN transceiver.

[0071] The FPGA includes: a signal recovery module, a filtering module, a trigger detection module, a sampling module, an AXI read-write module and a CAN protocol analysis module; wherein the signal recovery module is used to receive the sampled signal and the second drive trigger signal; the signal recovery module is respectively connected to the filtering module and the trigger detection module; the filtering module and the trigger detection module are both connected to the sampling module; the sampling module is connected to the AXI read-write module; the AXI read-write module is also connected to the filtering module and the trigger detection module; the CAN protocol analysis module is used to receive the first drive trigger signal; the CAN protocol analysis module is respectively connected to the sampling module and the AXI read-write module.

[0072] Signal recovery module (adc_intf): restores the digital sampling signal output by the AD9467 LVDS interface to sampling points with a sampling rate of 250MSPS.

[0073] Filter module (filter_avg): This module is used for filtering, decimation and multi-point mean smoothing of the sampled DC jitter signal. The sampling rate of the sampled signal is 250MSPS, while the frequency characteristic of the sampled signal is 1.5kHz~200KHz, and the oversampling rate is as high as 1250~166667 times. The sampling rate is too high, resulting in too much sampled data and too much useless information. According to the Nyquist sampling theorem, the signal sampling rate can be controlled at 800KSPS~1MSPS. Therefore, it is necessary to perform decimation filtering (not used yet) or multi-point mean smoothing filtering (for example, averaging every 250 sample points).

[0074] The host computer configures the parameters of the module through AXI. The configurable parameters are: the number of samples for mean smoothing filtering. It is recommended to configure it as 100 / 125 / 200 / 250. When configured as 100, every 100 250MSPS sampling points are averaged and filtered, and the output signal sampling rate is 250MSPS / 100=2.5MSPS; when configured as 125, every 125 250MSPS sampling points are averaged and filtered, and the output signal sampling rate is 250MSPS / 125=2MSPS; when configured as 250, every 250 250MSPS sampling points are averaged and filtered, and the output signal sampling rate is 250MSPS / 250=1MSPS; and so on.

[0075] The sampled signal has a sampling rate of 250MSPS, and the mean smoothing filter is implemented by accumulating and averaging n consecutive sample points. At the same time, the signal sampling rate is reduced to an appropriate sampling rate, and the mean smoothing filter is implemented:

[0076] Combine n consecutive sampling points into a segment, such as Figure 3 As shown, S0 / S1 / S2 / … / Sn-1 are n consecutive sample points; the cumulative sum of S0 / S1 / S2 / … / Sn-1 sample points is calculated; the average of the cumulative sum of n sample points is calculated; the smoothing filtering scheme for n consecutive sample points can handle the frequency of the sampled signal as low as 1.5kHz~200KHz and as high as 80MHz. For example, when the sampling rate of the signal after smoothing filtering is expected to drop to around 800KSPS. When n is 250, the signal sampling rate is reduced to 1MSPS, which meets the requirements. When the frequency of the sampled signal is high, around 80MHz, and the sampling rate is 250MSPS, you can consider using an FIR filter to filter out noise and keep the signal sampling rate unchanged.

[0077] Detection module (peak_edge): This module is used for peak detection and zero-crossing detection of the second drive trigger signal. The second drive trigger signal is a quasi-sine signal. This signal superimposes a sine signal on a DC voltage. The frequency range of the quasi-sine signal is 0~800KHz. The quasi-sine signal is used to generate a fine trigger acquisition pulse signal, and the trigger time accuracy can reach 1.25us (when the quasi-sine signal period is 800KHz). Within one cycle of the quasi-sine signal, the time point of the fine trigger pulse can be obtained in four ways: the peak, trough, rising edge of the mean shift, and falling edge of the mean shift of the sine signal.

[0078] Peak or trough: By detecting the peak value or trough value of the signal, the sampling point position of the peak or trough is used as the time point of the trigger pulse.

[0079] Rising edge or falling edge: First, perform cumulative average of the second drive trigger signal within a time length of 10ms to 100ms to obtain the DC offset voltage value; then use this DC voltage value as the zero-crossing offset value of the quasi-sine signal. Then use the zero-crossing rising edge or falling edge of the quasi-sine signal as the time point of the trigger pulse.

[0080] Based on the motor encoder CAN bus, when the motor rotates to the set mechanical angle area, the can_proc module generates a coarse trigger timing with an accuracy of 1ms; based on the quasi-sine signal of the second drive trigger signal, the peak_edge module generates a fine trigger timing with an accuracy of about 1us. The two are combined to generate a trigger pulse signal. When the motor rotates to the specified mechanical angle area, the fine trigger signal generated by the quasi-sine signal is used to trigger the acquisition of the sampled DC jitter signal.

[0081] This module is used to process the second drive trigger signal-like sinusoidal signal. Detect its peak / trough and zero-crossing time position, and generate a trigger pulse at this time position. Figure 4 As shown in , the quasi-sinusoidal signal is a sine signal with a certain bias voltage. Inside the FPGA, the signal period is estimated. Figure 5 As shown, in order to calculate the peak, trough, and zero-crossing position of a quasi-sine signal, the waveform maximum value detection module, minimum value detection module, average value module, peak detection, trough detection, zero-crossing detection and other modules are required to cooperate.

[0082] Maximum value detection module: Set a period of n sample points as the detection period, and find the maximum value in the waveform of n consecutive sample points. The value of n should preferably be twice the number of sample points included in the quasi-sine signal period. For example: the sampling rate is 250MSPS, and the quasi-sine signal period is 500KHz, then the value of n should be at least 2*250 / 0.5=1000.

[0083] Minimum detection module: Similar to the maximum detection module described above. Set a period of n samples as the detection period, and find the minimum value in the waveform of n consecutive samples. The value of n should preferably be twice the number of sampling points included in the quasi-sine signal period. For example: the sampling rate is 250MSPS, and the quasi-sine signal period is 500KHz, then the value of n should be at least 2*250 / 0.5=1000.

[0084] Mean value module: This module realizes the average value calculation of n consecutive sample points within the set time. It is mainly used to calculate the bias voltage of the quasi-sinusoidal signal. The value of n should preferably be 20 times the number of sampling points included in the quasi-sinusoidal signal period. For example: the sampling rate is 250MSPS, and the quasi-sinusoidal signal period is 500KHz, then the value of n should be at least 20*250 / 0.5=10000. Properly increasing the value of n can improve the accuracy of the bias voltage calculation. In addition, the calculation results of the maximum value detection and minimum value detection modules can be used to obtain the mean value. The maximum and minimum values ​​of the waveform calculated by the maximum value detection module and the minimum value module within the set time are summed and then divided by 2 to obtain the bias voltage value of the quasi-sinusoidal signal.

[0085] Zero-crossing point detection: Based on the bias voltage value of the quasi-sinusoidal signal obtained by the above-mentioned mean module, the zero-crossing point position can be quickly calculated. When the waveform signal changes from small to large, and the signal amplitude contains the bias voltage value during this period, the zero-crossing point of the rising process can be determined; when the waveform signal changes from large to small, and the signal amplitude contains the bias voltage value during this period, the zero-crossing point of the falling process can be determined. Zero-crossing point detection based on the bias voltage value, if there is a lot of noise in the waveform, will cause the signal amplitude to be near the bias voltage, and the problem of frequent detection of zero crossings will occur. This requires increasing processing redundancy during calculations.

[0086] The sample point length in the above modules, as well as the selection of one of the peak, trough, and zero-crossing point as the trigger time point, are all configured by the host computer.

[0087] CAN protocol parsing module (can_proc): This module is used to implement the parsing of the CAN bus protocol inside the FPGA, and parse out the motor mechanical angle, speed, current, temperature and other information generated by the motor encoder. It mainly focuses on the instantaneous mechanical angle information during the motor rotation process. By parsing the CAN bus signal of the first drive trigger signal, the trigger sampling timing with a time accuracy of 1ms can be obtained. The host computer configures the four area information of the motor rotation angle through AXI. Each angle area includes a starting angle value and an ending angle value, and the angle value range is 0~8191 (0~360°). The four angle areas do not overlap. Since the motor encoder sends the motor status information once every 1ms, the module needs to parse out the motor working status information with a lower delay. After the motor starts to rotate, it will rotate and scan four different angle areas in turn. The can_proc module will parse out the corresponding motor mechanical angle value every 1ms, and determine whether the value is consistent with the angle area set by the user. If it is consistent, the effective angle area indication signal will be pulled high; when the motor mechanical angle value parsed by the can_proc module is not within the angle area set by the user, the effective angle area indication signal will be pulled low. When the effective angle area indication signal is at a high level, combined with the fine trigger provided by the second drive trigger signal (quasi-sinusoidal signal), the sampled signal is triggered and sampled, and the collected data is reported to the host computer for display and storage.

[0088] Sampling module (trig_acq_proc): This module is used to trigger sampling of the sampled signal. When the motor rotates to the set mechanical angle area, the fine trigger signal generated by the quasi-sine signal is used as a trigger pulse to start collecting the sampled DC jitter signal for a period of time, store the signal in PL DDR through the AXI bus, and then move it to PS DDR. Finally, the sampled signal points are sent to the host computer through Ethernet for display, storage, and processing. The host computer configures the length value of the sampled signal points after each trigger pulse is generated through the AXI bus.

[0089] AXI read / write module (AXI module): used to pass the operation control command parameters of the host computer to each module of the FPGA: set the four mechanical angle intervals of the can_proc module, read the motor operating parameters (temperature, current, speed, mechanical angle, etc.), set the number of smoothing samples of the filter_avg module. Configure the length of the sample points collected after each trigger. Used to store the sampled DC jitter sample point signal into the PL DDR, then move it to the PS DDR, and finally send the sample points collected in the PS DDR to the Ethernet data transmission BUF.

[0090] When implementing it, Figure 6 As shown, after the sampled device is powered on, the host computer sets four different intervals of the motor rotation mechanical angle, and sets the peak value or rising and falling edge detection mode of the second drive trigger signal (quasi-sinusoidal signal).

[0091] After the motor starts working, it rotates at a certain speed. The first drive trigger signal output by the motor is transmitted through the CAN bus, and the motor working status information is periodically output at a time interval of 1ms. At the same time, the second drive trigger signal is also generated by the sampled device, and is sampled by the acquisition board ADC and sent to the FPGA.

[0092] FPGA analyzes the motor mechanical angle information in the CAN bus. When the motor rotates to the set angle range, the trigger acquisition valid indication 1 signal is immediately pulled high. When the motor rotates out of the angle range, the trigger acquisition valid indication 1 signal is immediately pulled low.

[0093] The second driving trigger signal is a quasi-sine signal. After the sampled quasi-sine signal is sent to the FPGA, the FPGA detects the peak value or edge according to the peak value or edge detection method set by the host computer ( Figure 6 The trigger acquisition signal is valid when the trigger acquisition valid indication 1 is high level.

[0094] When the trigger acquisition pulse signal is valid, the acquisition of the sampled signal begins. The length of the sampled signal for each trigger acquisition is also set by the host computer. Each segment of the sampled signal needs to be transmitted to the host computer for storage and subsequent calculation and processing.

[0095] Figure 7 A flow chart of a method for state monitoring provided in an embodiment of the present application is shown, wherein the method acts on a system for state monitoring, the system comprising: a device under test, a field programmable gate array FPGA and a host computer; the host computer is connected to the FPGA, and the FPGA is connected to the device under test; comprising steps S101-S103; specifically:

[0096] S101, the device under test generates a sampled signal and a plurality of drive trigger signals;

[0097] S102, the FPGA determines a target acquisition interval according to the multiple drive trigger signals; and performs data acquisition on the sampled signal in the target acquisition interval to obtain acquisition data;

[0098] S103: The host computer is used to send control parameters, determine target acquisition parameters, save and analyze the acquired data, and determine the working status of the device under test.

[0099] The multiple driving trigger signals include a first driving trigger signal and a second driving trigger signal; wherein the first driving trigger signal corresponds to a first acquisition interval, and the second driving trigger signal corresponds to a second acquisition interval;

[0100] The FPGA determines a target acquisition interval according to the multiple drive trigger signals, including:

[0101] A combination of the first acquisition interval and the second acquisition interval is used as the target acquisition interval.

[0102] In some technical solutions of the present application, the above-mentioned target acquisition parameters include a first acquisition parameter and a second acquisition parameter; the device under test includes a motor;

[0103] The device under test is used to generate multiple drive trigger signals, including:

[0104] The operation range of the motor is calibrated according to the first acquisition parameter to obtain a first drive trigger signal.

[0105] The peak value or the zero-crossing point of the quasi-sine signal generated by the actual operating state of the device under test is detected according to the second acquisition parameter to generate the second drive trigger signal.

[0106] The multiple drive trigger signals include a first drive trigger signal and a second drive trigger signal; a first transmission channel, a second transmission channel and a third transmission channel are arranged between the FPGA and the device under test; wherein the first transmission channel is used to transmit the first drive trigger signal, the second transmission channel is used to transmit the second drive trigger signal; and the third transmission channel is used to transmit the sampled signal;

[0107] The first transmission channel includes a motor encoder, a CAN bus and a CAN transceiver; wherein the motor encoder is connected to the motor rotating shaft through a hard connection, the rotation of the motor will drive the encoder to change, and the motor encoder is connected to the CAN bus interface of the FPGA through the CAN bus for transmitting the data of the motor encoder.

[0108] The second transmission channel and the third transmission channel both include a signal conditioning module and an analog-to-digital conversion module; wherein the signal conditioning module is connected to the device under test and the analog-to-digital conversion module, respectively, and the analog-to-digital conversion module is connected to the FPGA. The motor encoder is installed on the motor to provide a closed-loop feedback signal by tracking the speed and / or position of the motor shaft;

[0109] The sampled signal is a DC jitter signal within a preset voltage range; the second drive trigger signal is a quasi-sinusoidal signal;

[0110] The signal conditioning module adjusts the sampled signal and the second drive trigger signal so that the sampled signal and the second drive trigger signal are adapted to the analog-to-digital conversion module;

[0111] The analog-to-digital conversion module converts the adjusted sampled signal and the second driving trigger signal into corresponding digital signals.

[0112] The multiple driving trigger signals include a first driving trigger signal and a second driving trigger signal;

[0113] The FPGA includes: a signal recovery module, a filtering module, a trigger detection module, a sampling module, an AXI read-write module and a CAN protocol analysis module; wherein the signal recovery module is used to receive the sampled signal and the second drive trigger signal; the signal recovery module is respectively connected to the filtering module and the trigger detection module; the filtering module and the trigger detection module are both connected to the sampling module; the sampling module is connected to the AXI read-write module; the AXI read-write module is also connected to the filtering module and the trigger detection module; the CAN protocol analysis module is used to receive the first drive trigger signal; the CAN protocol analysis module is respectively connected to the sampling module and the AXI read-write module.

[0114] like Figure 8 As shown, an embodiment of the present application provides an electronic device to execute a method for status monitoring in the present application, the device includes a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the status monitoring method when executing the computer program.

[0115] Specifically, the above-mentioned memory and processor may be general-purpose memory and processor, which are not specifically limited here. When the processor runs the computer program stored in the memory, the above-mentioned state monitoring method can be executed.

[0116] Corresponding to the condition monitoring method in the present application, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned condition monitoring method are executed.

[0117] Specifically, the storage medium can be a general storage medium, such as a mobile disk, a hard disk, etc. When the computer program on the storage medium is executed, the above-mentioned state monitoring method can be executed.

[0118] In the embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. The system embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0122] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0123] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A system for condition monitoring, characterized in that: The system comprises: a device under test, a field programmable gate array FPGA and a host computer; the host computer is connected to the FPGA, and the FPGA is connected to the device under test; The device under test is used to generate a sampled signal and a plurality of drive trigger signals; The FPGA is used to determine a target acquisition interval according to the multiple drive trigger signals; and perform data acquisition on the sampled signal in the target acquisition interval; The host computer is used to issue control parameters, determine target acquisition parameters, save and analyze the acquired data, and determine the working status of the device under test; The multiple driving trigger signals include a first driving trigger signal and a second driving trigger signal; wherein the first driving trigger signal corresponds to a first acquisition interval, and the second driving trigger signal corresponds to a second acquisition interval; The FPGA is used to determine a target acquisition interval according to the multiple drive trigger signals, including: taking a combination of the first acquisition interval and the second acquisition interval as the target acquisition interval; The target acquisition parameter includes a first acquisition parameter; the device under test includes a motor; The device under test is used to generate multiple drive trigger signals, including: Calibrate the operation range of the motor according to the first acquisition parameter to obtain a first drive trigger signal; The target acquisition parameters include second acquisition parameters; the second drive trigger signal is a quasi-sine signal; The device under test is used to generate multiple drive trigger signals, including: The peak value or the zero-crossing point of the quasi-sine signal generated by the actual operating state of the device under test is detected according to the second acquisition parameter to generate the second drive trigger signal.

2. The system according to claim 1, characterized in that The multiple drive trigger signals include a first drive trigger signal and a second drive trigger signal; a first transmission channel, a second transmission channel and a third transmission channel are arranged between the FPGA and the device under test; wherein the first transmission channel is used to transmit the first drive trigger signal, the second transmission channel is used to transmit the second drive trigger signal; and the third transmission channel is used to transmit the sampled signal; The first transmission channel includes a motor encoder, a CAN bus and a CAN transceiver; wherein the motor encoder is connected to the motor rotating shaft through a hard connection, the rotation of the motor will drive the encoder to change, and the motor encoder is connected to the CAN bus interface of the FPGA through the CAN bus for transmitting the data of the motor encoder; The second transmission channel and the third transmission channel both include a signal conditioning module and an analog-to-digital conversion module; wherein the signal conditioning module is connected to the device under test and the analog-to-digital conversion module respectively, and the analog-to-digital conversion module is connected to the FPGA.

3. The system according to claim 2, characterized in that The motor encoder is mounted on the motor and is used to provide a closed-loop feedback signal by tracking the speed and / or position of the motor shaft; The sampled signal is a DC jitter signal within a preset voltage range; the second drive trigger signal is a quasi-sinusoidal signal; The signal conditioning module is used to adjust the sampled signal and the second drive trigger signal so that the sampled signal and the second drive trigger signal are adapted to the analog-to-digital conversion module; The analog-to-digital conversion module is used to convert the adjusted sampled signal and the second drive trigger signal from analog signals into corresponding digital signals.

4. The system according to claim 1, characterized in that The multiple driving trigger signals include a first driving trigger signal and a second driving trigger signal; The FPGA includes: a signal recovery module, a filtering module, a trigger detection module, a sampling module, an AXI read-write module and a CAN protocol analysis module; wherein the signal recovery module is used to receive the sampled signal and the second drive trigger signal; the signal recovery module is respectively connected to the filtering module and the trigger detection module; the filtering module and the trigger detection module are both connected to the sampling module; the sampling module is connected to the AXI read-write module; the AXI read-write module is also connected to the filtering module and the trigger detection module; the CAN protocol analysis module is used to receive the first drive trigger signal; the CAN protocol analysis module is respectively connected to the sampling module and the AXI read-write module.

5. A method for condition monitoring, characterized in that: A system for state monitoring, the system comprising: a device under test, a field programmable gate array FPGA and a host computer; the host computer is connected to the FPGA, and the FPGA is connected to the device under test; the method comprises: The device under test generates a sampled signal and a plurality of drive trigger signals; The FPGA determines a target acquisition interval according to the multiple drive trigger signals; and performs data acquisition on the sampled signal in the target acquisition interval; The host computer is used to issue control parameters, determine target acquisition parameters, save and analyze the acquired data, and determine the working status of the device under test; The multiple driving trigger signals include a first driving trigger signal and a second driving trigger signal; wherein the first driving trigger signal corresponds to a first acquisition interval, and the second driving trigger signal corresponds to a second acquisition interval; The FPGA determines a target acquisition interval according to the multiple drive trigger signals, including: taking a combination of the first acquisition interval and the second acquisition interval as the target acquisition interval; The target acquisition parameter includes a first acquisition parameter; the device under test includes a motor; The device under test generates a plurality of drive trigger signals, including: Calibrate the operation range of the motor according to the first acquisition parameter to obtain a first drive trigger signal; The target acquisition parameters include second acquisition parameters; the second drive trigger signal is a quasi-sine signal; The device under test generates a plurality of drive trigger signals, including: The peak value or the zero-crossing point of the quasi-sine signal generated by the actual operating state of the device under test is detected according to the second acquisition parameter to generate the second drive trigger signal.

6. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the method for status monitoring as described in claim 5 are performed.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the condition monitoring method as claimed in claim 5 are executed.

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