Data management method of solid state storage device

Abstract

The invention discloses a data management method of a solid-state storage device. The solid state storage device may selectively initiate a timeline compensation write operation. When a time axis compensation write operation is performed, the control circuit determines a specific time interval in which the write data volume is maximum, and transfers a part of the write data stored in the specific time interval to other positions of the non-volatile memory. Therefore, when the solid-state storage device performs the data remedy program according to the data storage time, the time for executing the data remedy program can be greatly shortened, so that the solid-state storage device can maintain better efficiency.

Description

Technical Field

[0001] The present invention relates to a data management method for a solid-state storage device, and in particular to a solid-state storage device with a time axis compensator write operation (TACW operation for short) and a related data management method thereof. Background Art

[0002] As we all know, solid state devices have been widely used in various data storage products, such as SD cards, solid state hard drives, etc. Figure 1A , which is a schematic diagram of a solid-state storage device in the prior art. The solid-state storage device 100 includes: a controller 110, a volatile memory 130, and a non-volatile memory 140. The volatile memory 130 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Furthermore, the volatile memory 130 in the solid-state storage device 100 is described below by taking DRAM as an example.

[0003] The controller 110 of the solid-state storage device 100 is connected to a host 120 via an external bus 105, wherein the external bus 105 may be a USB bus, a SATA bus, a PCIe bus, an M2 bus, etc. The controller 110 is connected to a DRAM 130. Furthermore, the controller 110 is connected to a non-volatile memory 140 via an internal bus 115.

[0004] The controller 110 can temporarily store the write data provided by the host 120 in the DRAM 130 according to a write command issued by the host 120. Then, after an error correction (ECC) procedure, the controller 110 performs a write operation to store the write data from the DRAM 130 to the non-volatile memory 140. Alternatively, the controller 110 can obtain the read data from the non-volatile memory 140 and temporarily store it in the DRAM 130 according to a read command issued by the host 120. Then, after an error correction (ECC) procedure, the read data is transmitted from the DRAM 130 to the host 120.

[0005] Furthermore, the non-volatile memory 140 includes a plurality of blocks, and each block includes a plurality of pages. When performing a write operation, the controller 110 stores the write data in the non-volatile memory 140 in units of pages. When performing an erase operation, the controller 110 erases the write data in the non-volatile memory 140 in units of blocks. After the host 120 performs multiple write operations, there will be invalid pages and valid pages in the used blocks in the non-volatile memory 140, and the valid pages store valid write data, and the invalid pages store invalid write data. Furthermore, the controller 110 will start a garbage collection (GC) operation at an appropriate time.

[0006] When performing a GC operation, the controller 110 collects the write data of all valid pages in the used block and moves them to a blank block. When the GC operation is completed, the used block no longer has any valid pages, that is, all pages of the used block store invalid write data. At this time, the controller 110 can perform an erase operation on the used block to make it a blank block, and the blank block can be used by the controller 110 to store new write data again. The process including the above-mentioned GC operation and erase operation can be called a reclaim operation.

[0007] Basically, when there are many blank blocks in the non-volatile memory 140, that is, when there is a lot of storage space in the non-volatile memory 140, the controller 110 will not perform a recycling operation. When there are few blank blocks in the non-volatile memory 140, that is, when there is little storage space in the non-volatile memory 140, the controller 110 will perform a recycling operation. Taking a non-volatile memory 140 with a capacity of 1 (Terabyte, TB) as an example, when there is 0.2TB of storage space left in the non-volatile memory 140, the controller 110 will perform a recycling operation at an appropriate time. Of course, the aforementioned 0.2TB is just an example for illustration. In fact, the controller 110 can selectively determine the timing of executing the recycling operation, for example, when there is 0.1TB or 0.3TB of storage space left.

[0008] Please refer to Figure 1B, is a schematic diagram of a data source (datasource) for a write operation of a solid-state storage device in the prior art. When the solid-state storage device 100 operates normally, when the controller 110 performs a write operation, the source of the data can be the write data 150 provided by the host 120, or the write data 155 generated by a recycling operation. Basically, the host's write data 150 are all valid data. Furthermore, after the controller 110 performs a GC operation on the non-volatile memory 140, the data collected are also all valid data. That is, the write data 155 of the recycling operation is also valid data. In other words, when the controller 110 of the conventional solid-state storage device 100 performs a write operation, the controller 110 stores the valid write data in the non-volatile memory 140.

[0009] Furthermore, the controller 110 of the solid-state storage device 100 processes write data from two different sources at different times. For example, when the solid-state storage device 100 receives write data 150 provided by the host 120, the controller 110 stores the write data 150 of the host in the non-volatile memory 140. When the controller 110 does not execute a write command or a read command of the host 120 (i.e., in standby), the controller 110 can perform a recycling operation (i.e., a GC operation and an erase operation), and store the write data 155 of the recycling operation in the non-volatile memory 140. In this way, the performance of the solid-state storage device 100 can be ensured not to be affected.

[0010] Due to the characteristics of the memory cells in the non-volatile memory 140, the manufacturer of the non-volatile memory 140 defines a data retention time. After the written data is stored in the non-volatile memory 140, the accuracy and integrity of the written data can be ensured within the data retention time. When the storage time of the written data stored in the non-volatile memory 140 exceeds the data retention time, the accuracy and integrity of the written data cannot be guaranteed. In other words, the written data may be lost or become erroneous written data.

[0011] Due to the characteristics of the memory cells in the non-volatile memory 140, the controller 110 needs to monitor the storage time of the write data in the non-volatile memory 140. For example, after a write data is stored in the non-volatile memory 140, if the write data is not read, moved or replaced, the write data is regarded as valid non-accessed write data. When the storage time of the valid non-accessed write data reaches the data retention time, the controller 110 must immediately start the data recovery process and process the valid non-accessed write data with a higher priority, otherwise the write data may be lost or become erroneous write data.

[0012] Basically, the data recovery procedure performed by the controller 110 can be a recovery operation to move the valid unaccessed write data to other locations in the non-volatile memory 140. Alternatively, the controller 110 can also perform a touch read operation on the valid unaccessed write data. Both of these operations can recalculate the storage time of the valid unaccessed write data and ensure the accuracy and integrity of the write data. However, in some special cases, the above data recovery procedure may cause a significant decrease in the performance of the solid-state storage device 100. This is explained below.

[0013] Please refer to Figure 1C , is a schematic diagram of the relationship between the amount of written data and time in a solid-state storage device in the prior art. In the solid-state storage device 100, it is assumed that the storage capacity of the non-volatile memory 140 is 1 TB, and the data retention time of the non-volatile memory 140 is one week.

[0014] like Figure 1C As shown, the time axis is divided into a plurality of time intervals with a day as a unit. On the first day, the host 120 provides a large amount of write data, such as 0.6TB, to be stored in the non-volatile memory 140. In the subsequent 6 days (2nd to 7th), the host 120 only provides a small amount of write data, about 0.03TB to 0.1TB, to be stored in the non-volatile memory 140.

[0015] For example, the subsequent 6 days (2nd to 7th) of written data include the first part of written data and the second part of written data. The first part of written data has the same logical block address (LBA) as the first day of written data, which means that the old written data with the same logical block address in the first day of written data will become invalid data (the slashed part) and will be replaced by the first part of written data. In addition, the second part of written data has a different logical block address (LBA) from the first day of written data, which means that the second part of written data is new written data stored in the non-volatile memory 140.

[0016] Since the amount of data written on the first day is very large, the amount of data written on the following 6 days (the 2nd to the 7th) is very small. It can be expected that when the data retention time (the 7th) is reached, the data written on the first day will include a large amount of valid unaccessed written data and a small amount of invalid data (the oblique line part). In order to prevent the loss or error of written data, when the data retention time is reached, the controller 110 must immediately perform a data recovery procedure for the written data on the first day with a higher priority. In other words, the controller 110 must start at the 8th day (time point t A ), the data recovery process is performed with a higher priority on the data written on the first day.

[0017] like Figure 1C As shown, at time point t A , the controller 110 performs a data recovery procedure on the data written on the 1st day, such as a recycling operation. First, the controller 110 performs a GC operation to collect valid data (white part) in the data written on the 1st day, while invalid data (diagonal part) will not be collected. Then, the valid data (white part) is moved to another location of the non-volatile memory 140. That is, in the recycling operation performed on the 8th day, the controller 110 stores the written data 180 after the recycling operation in another location of the non-volatile memory 140 again.

[0018] Since the write data of the first day includes a large amount of valid unaccessed write data, the controller 110 needs to spend a long time to perform the data recovery procedure to store the collected write data 180 in the non-volatile memory 140. However, during the data recovery procedure, if the host 120 also issues a write command to store (for example, 0.35TB) write data 190 in the non-volatile memory 140. Since the data recovery procedure has a higher priority, the controller 110 needs to perform a recovery operation first before being able to store the write data 190 provided by the host 120 in the non-volatile memory 140. This will cause the solid-state storage device 100 to have a very serious write latency, which greatly reduces the performance of the solid-state storage device 100. Summary of the invention

[0019] In view of the shortcomings of the prior art, the present invention provides a data management method for a solid-state storage device, which overcomes the defect that the performance of the solid-state storage device is greatly reduced.

[0020] In order to achieve the above-mentioned purpose, the present invention provides a data management method for a solid-state storage device, which includes a non-volatile memory, and the data management method includes the following steps: calculating a first average write speed in an (N-2)th time interval; calculating a second average write speed in an (N-1)th time interval, wherein N is a positive integer, and the first average write speed minus the second average write speed equals an average write speed difference; when the average write speed difference is less than a threshold write speed, not starting a time axis compensation write operation in the Nth time interval; monitoring a real-time write speed; when the average write speed difference is greater than the threshold write speed and the real-time write speed is greater than the average write speed difference, not starting the time axis compensation write operation in the Nth time interval; and when the average write speed difference is greater than the threshold write speed and the real-time write speed is less than the average write speed difference, starting the time axis compensation write operation in the Nth time interval.

[0021] It can be seen from the above scheme that the advantages of the present invention are:

[0022] The solid-state storage device of the present invention can selectively start the time axis compensation writing operation. When performing the data recovery procedure according to the data storage time, the time for executing the data recovery procedure can be greatly shortened, so that the solid-state storage device can maintain better performance.

[0023] In order to have a better understanding of the above technical solutions and other aspects of the present invention, the following is a preferred embodiment, and is described in detail with reference to the accompanying drawings as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A It is a schematic diagram of a solid-state storage device in the prior art;

[0025] Figure 1B A schematic diagram of a data source for a solid-state storage device performing a write operation in the prior art;

[0026] Figure 1C A schematic diagram of the relationship between the amount of data written and time of a solid-state storage device in the prior art;

[0027] Figure 2A is a schematic diagram of a solid-state storage device of the present invention;

[0028] Figure 2B A schematic diagram of a data source for performing a write operation on a solid-state storage device of the present invention;

[0029] Figure 2C A data management method for a solid-state storage device of the present invention; and

[0030] 3A to 3H A schematic diagram showing the relationship between the amount of data written and time of the solid-state storage device of the present invention;

[0031] Among them, the reference numerals

[0032] 100- solid state storage device;

[0033] 105-external bus;

[0034] 110 - controller;

[0035] 115-internal bus;

[0036] 120-Host;

[0037] 130-Volatile memory;

[0038] 140- non-volatile memory;

[0039] 150,190,390-host write data;

[0040] 155,180,380-Written data of the recovery operation;

[0041] 200-The solid state storage device of the present invention;

[0042] 210-control circuit;

[0043] 220-Written data of the time axis compensation write operation;

[0044] 301-Written data on the first day;

[0045] 302-Written data on the second day;

[0046] 303-Written data on the 3rd day;

[0047] 304-Written data on the 4th day;

[0048] 305-Written data on the 5th day;

[0049] 306-Written data on the 6th day;

[0050] 307-Written data on the 7th day;

[0051] S230~S242-steps. DETAILED DESCRIPTION

[0052] Since the solid-state storage device 100 in the prior art may take a long time to perform the data recovery process, the performance of the solid-state storage device 100 is greatly reduced. Therefore, the present invention designs a data management method for a time axis compensator write operation (TACW operation) in the solid-state storage device. The data management method for the time axis compensator write operation of the present invention is introduced below.

[0053] Please refer to Figure 2A , is a schematic diagram of a solid-state storage device of the present invention. The solid-state storage device 200 of the present invention comprises: a controlling circuit 210, a volatile memory 130 and a non-volatile memory 140. The volatile memory 130 may be a DRAM, a SRAM or the like.

[0054] Compared to Figure 1A The control circuit 210 in the solid-state storage device 200 of the present invention can perform a time axis compensation write operation. Furthermore, other operation modes of the solid-state storage device 200 of the present invention, such as a write operation, a read operation, and a GC operation, are similar to Figure 1A The solid state storage device 100 is not described in detail here.

[0055] Please refer to Figure 2B , is a schematic diagram of a data source for a solid-state storage device of the present invention to perform a write operation. When the solid-state storage device 200 operates normally, when the control circuit 210 performs a write operation, the source of the data may be the host's write data 150, the write data 155 of the recycling operation, or the write data 220 of the time axis compensation write operation.

[0056] Basically, the host's write data 150 and the write data 155 of the recycling operation are both valid data. Similarly, the control circuit 210 of the solid-state storage device 200 processes the host's write data 150 and the write data 155 of the recycling operation at different times. For example, when the control circuit 210 does not execute a write command or a read command of the host 120 (i.e., in standby), the control circuit 210 can perform a recycling operation (i.e., a GC operation and an erase operation), write the write data 155 of the recycling operation, and store it in the non-volatile memory 140. In this way, the performance of the solid-state storage device 200 can be ensured not to be affected.

[0057] Furthermore, when the control circuit 210 performs a time axis compensation write operation (TACW operation), the write data 220 of the time axis compensation write operation may include valid data and invalid data. According to an embodiment of the present invention, when the control circuit 210 performs a write operation on the write data 150 of the host and stores it in the non-volatile memory 140, the control circuit 210 monitors the instant write speed of the write operation. Furthermore, according to the instant write speed, the control circuit 210 determines whether to enable the time axis compensation write operation. Therefore, when the time axis compensation write operation is enabled, the control circuit 210 performs a write operation on the write data 150 of the host and the write data 220 of the time axis compensation write operation. For example, after a write data is stored in the non-volatile memory 140, before its storage time reaches the data retention time, the control circuit 210 can selectively start the time axis compensation write operation and move part of the write data to other locations in the non-volatile memory 140 within a specific time interval.

[0058] Please refer to Figure 2C , is a data management method for a solid-state storage device of the present invention. First, the average write speed S of the (N-2)th time interval is calculated. AV(N-2) (Step S230) and calculate the average writing speed S of the (N-1)th time interval AV(N-1) (Step S232). The Nth time interval represents the current time interval, the (N-2)th time interval and the (N-1)th time interval represent two consecutive time intervals before the Nth time interval, and N is a positive integer. Of course, the (-1)th interval and the (0th interval do not store write data, and the average write speed can be regarded as 0.

[0059] Next, the average write speed difference between the first two consecutive time intervals is calculated (ie,

[0060] [S AV(N-2) -S AV(N-1) ]), and determine whether the average write speed difference between two consecutive time intervals is greater than a default threshold write speed S TH (Step S234), that is, judging ([S AV(N-2) -S AV(N-1) ]>S TH ) is true. When the average writing speed difference between two consecutive time intervals is less than the threshold writing speed S TH When the time axis compensation writing operation is not started (disabled) in the Nth time interval (step S240).

[0061] Furthermore, when the average writing speed difference between two consecutive time intervals is greater than the threshold writing speed S TH Then monitor the real-time writing speed S IST(N) (Step S236). That is, in the Nth time interval, when the control circuit 210 performs a write operation on the write data 150 of the host, the control circuit 210 further monitors the real-time write speed S during the write operation. IST(N) (instantwrite speed).

[0062] Next, determine the real-time writing speed S IST(N) Is it less than the average writing speed difference of two consecutive time intervals (step S238), that is, judging (S IST(N) <[S AV(N-2) -S AV(N-1) ]) is true. When the real-time writing speed S IST(N) When the real-time writing speed S is greater than the average writing speed difference between two consecutive time intervals, the time axis compensation writing operation is disabled in the Nth time interval (step S240). IST(N) When the writing speed is smaller than the average writing speed difference between two consecutive time intervals, a time axis compensation writing operation is enabled in the Nth time interval (step S242 ).

[0063] According to an embodiment of the present invention, when performing a time axis compensation write operation, the control circuit 210 determines a specific time interval before the Nth time interval. For example, the specific time interval has the largest amount of write data. Then, a portion of the write data stored in the specific time interval is moved to other locations of the non-volatile memory 140. Furthermore, the interval between the specific time interval and the Nth time interval is less than the data retention time.

[0064] Please refer to 3A to 3H, is a schematic diagram of the relationship between the amount of written data and time of the solid-state storage device of the present invention. The solid-state storage device 200 of the present invention can selectively start the time axis compensation write operation (TACW operation). In addition, assuming that the storage capacity of the non-volatile memory 140 is 1TB, the data retention time of the non-volatile memory 140 is one week, and the threshold write speed S TH is 0.1 (Gigabyte, GB) / min.

[0065] like Figure 3A As shown, the time axis is divided into multiple time intervals with one day as the time interval unit. On the first day, the host 120 provides about 0.5T of write data 301 to be stored in the non-volatile memory 140, so the average write speed S on the first day is AV(1) About 0.356GB / min.

[0066] like Figure 3B As shown, the host 120 provides about 0.05T of write data 302 to be stored in the non-volatile memory 140 on the second day, so the average write speed S on the second day is AV(2) is about 0.036GB / min. Basically, part of the data written 302 on the second day will replace the data written 301 on the first day, making part of the data written 301 invalid data (the oblique line part). In addition, since the average writing speed difference between the two consecutive time intervals is [S AV(1) -S AV(2) ]=0.32GB / min, which means that the amount of data written on the second day is less than that written on the first day. AV(1) -S AV(2) ]>S TH (0.1 GB / min), so the control circuit 210 will monitor the real-time writing speed S on the third day. IST(3) To decide whether to enable the timeline compensation write operation.

[0067] Furthermore, assuming that on the third day, the control circuit 210 monitors the real-time writing speed S IST(3) is greater than the average write speed difference (0.32 GB / min) of the previous two consecutive time intervals. This means that the amount of write data provided by the host 120 is large, and the control circuit 210 does not start (disable) the time axis compensation write operation. On the contrary, if Figure 3C As shown, on the third day, assuming that the control circuit 210 monitors the real-time writing speed S IST(3)This is smaller than the average write speed difference (0.32 GB / min) of the previous two consecutive time intervals. This means that the amount of write data provided by the host 120 is not much, so the control circuit 210 enables the time axis compensation write operation.

[0068] According to an embodiment of the present invention, when performing a time axis compensation write operation, the control circuit 210 determines a specific time interval with the largest amount of written data, and moves a portion of the written data stored in the specific time interval to other locations of the non-volatile memory 140. Figure 3C As shown, the amount of written data on the first day is the largest. Therefore, when the time axis compensation write operation is performed on the third day, a portion (portion a) of the written data stored on the first day will be moved by the control circuit 210 to another location of the non-volatile memory 140. After the move, the portion (portion a) of the written data stored on the first day will become invalid data (the oblique line portion).

[0069] like Figure 3C As shown, on day 3, the written data includes the host's written data 303 of about 0.04TB and the written data (part a) of about 0.17TB of the time axis compensation write operation. In addition, the 0.17TB written data (part a) of the time axis compensation write operation includes valid data (blank part) and invalid data (slashed part).

[0070] Furthermore, the written data on the third day is about 0.21 TB stored in the non-volatile memory 140, and the average writing speed on the third day is S AV(3) About 0.149GB / min. Since the average writing speed difference between two consecutive time intervals is [S AV(2) -S AV(3) ]=-0.113GB / min, which means that the amount of data written on the third day is greater than that written on the second day. AV(2) -S AV(3) ] TH (0.1GB / min), so the time axis compensation writing operation is not started in the time interval of the 4th day.

[0071] like Figure 3D As shown, the host 120 provides about 0.03T of write data 304 to be stored in the non-volatile memory 140 on the 4th day, so the average write speed S on the 4th day is AV(4) About 0.021GB / min. In addition, since the average writing speed difference between two consecutive time intervals is [S AV(3) -S AV(4) ]=0.128GB / min, which means that the amount of data written on the 4th day is less than that written on the 3rd day. AV(3) -S AV(4) ]>S​TH (0.1 GB / min), so the control circuit 210 will monitor the real-time writing speed S on the 5th day. IST(5) To decide whether to start the timeline compensation write operation.

[0072] Similarly, assuming that on the fifth day, the control circuit 210 monitors the real-time writing speed S IST(5) is greater than the average write speed difference (0.128 GB / min) of the previous two consecutive time intervals. This means that the amount of write data provided by the host 120 is large, and the control circuit 210 does not start (disable) the time axis compensation write operation. On the contrary, if Figure 3E As shown, on the 5th day, assuming that the control circuit 210 monitors the real-time writing speed S IST(5) This is smaller than the average write speed difference (0.128 GB / min) of the previous two consecutive time intervals. This means that the amount of write data provided by the host 120 is not much, so the control circuit 210 enables the time axis compensation write operation.

[0073] like Figure 3E As shown, since the amount of written data on the first day is the largest, when the time axis compensation write operation is performed on the fifth day, a portion of the written data stored on the first day (portion b) will be moved by the control circuit 210 to another location of the non-volatile memory 140. After the move, the portion of the written data stored on the first day (portion b) will become invalid data (the oblique line portion).

[0074] like Figure 3E As shown, on day 5, the written data includes about 0.02TB of the host's written data 305 and about 0.15TB of the written data (part b) of the time axis compensation write operation. In addition, the 0.15TB of the written data (part b) of the time axis compensation write operation includes valid data (blank part) and invalid data (slashed part).

[0075] Furthermore, the written data on the 5th day is about 0.17 TB stored in the non-volatile memory 140, and the average writing speed on the 5th day is S AV(5) About 0.121GB / min. Since the average writing speed difference between two consecutive time intervals is [S AV(4) -S AV(5) ]=-0.1GB / min, which means that the amount of data written on the 5th day is greater than that written on the 4th day. AV(4) -S AV(5) ] TH (0.1GB / min), so the time axis compensation writing operation is not started in the time interval of the 6th day.

[0076] like Figure 3F ​As shown, the host 120 provides about 0.02T of write data 306 to be stored in the non-volatile memory 140 on the 6th day, so the average write speed S on the 6th day is AV(6) About 0.014GB / min. In addition, since the average writing speed difference between two consecutive time intervals is [S AV(5) -S AV(6) ]=0.107GB / min, which means that the amount of data written on the 6th day is less than that written on the 5th day. AV(5) -S AV(6) ]>S TH (0.1 GB / min), so the control circuit 210 will monitor the real-time writing speed S on the 7th day. IST(7) To decide whether to start the timeline compensation write operation.

[0077] Similarly, assuming that on the 7th day, the control circuit 210 monitors the real-time writing speed S IST(7) is greater than the average write speed difference (0.107 GB / min) of the previous two consecutive time intervals. This means that the amount of write data provided by the host 120 is large, and the control circuit 210 does not start (disable) the time axis compensation write operation. On the contrary, if Figure 3G As shown, on the 7th day, assuming that the control circuit 210 monitors the real-time writing speed S IST(7) This is smaller than the average write speed difference (0.107 GB / min) of the previous two consecutive time intervals. This means that the amount of write data provided by the host 120 is not much, so the control circuit 210 enables the time axis compensation write operation.

[0078] like Figure 3G As shown, since the amount of written data on the first day is the largest, when the time axis compensation write operation is performed on the seventh day, a portion (part c) of the written data stored on the first day will be moved by the control circuit 210 to another location of the non-volatile memory 140. After the move, the portion (part c) of the written data stored on the first day will become invalid data (the oblique line portion).

[0079] like Figure 3G As shown, on day 7, the written data includes about 0.05TB of the host's written data 307 and about 0.08TB of the written data (part c) of the time axis compensation write operation. In addition, the 0.08TB of the written data (part c) of the time axis compensation write operation includes valid data (blank part) and invalid data (slashed part).

[0080] Furthermore, the written data on the 7th day is about 0.13 TB and is stored in the non-volatile memory 140, and the average writing speed on the 7th day is S AV(8)About 0.092GB / min. Since the average writing speed difference between two consecutive time intervals is [S AV(6) -S AV(7) ]=-0.078GB / min, which means that the amount of data written on the 7th day is greater than that written on the 6th day. AV(6) -S AV(7) ] TH (0.1GB / min), so the time axis compensation writing operation is not started in the time interval of the 8th day.

[0081] According to an embodiment of the present invention, the solid-state storage device 200 of the present invention can selectively perform a time axis compensation write operation (TACW operation). Therefore, the control circuit 210 performs a time axis compensation write operation on the 3rd day, and moves the first part (part a) of the write data on the 1st day. Similarly, the control circuit 210 performs a time axis compensation write operation on the 5th day, and moves the second part (part b) of the write data on the 1st day. The control circuit 210 performs a time axis compensation write operation on the 7th day, and moves the third part (part c) of the write data on the 1st day. Obviously, only the fourth part (part d) of the write data on the 1st day has about 0.1TB of valid data left.

[0082] Since the data retention time is one week. Figure 3H As shown, in order to prevent the loss or error of written data, the control circuit 210 must start at the 8th day (time point t B ), the data recovery process is immediately performed with a higher priority for the data written on the 1st day. Since only the fourth part (part d) of about 0.1TB of the data written on the 1st day remains, the remaining parts (part a, part b, part c) have become invalid data after being moved to other locations of the non-volatile memory 140. Therefore, the control circuit only needs to perform a data recovery process, such as a recycling operation or a touch read operation, on the remaining and unmoved fourth part (part d) of about 0.1TB of the data written on the 1st day.

[0083] Taking the recycling operation as an example, the control circuit 210 first performs a GC operation to collect the valid data (white part) in the fourth part (part d) of the data written on the first day, while the invalid data (the oblique line part) will not be collected. Then, the valid data (white part) is moved to other locations of the non-volatile memory 140. That is, in the recycling operation performed on the eighth day, the control circuit 210 stores the written data 380 after the recycling operation in other locations of the non-volatile memory 140 again. ​

[0084] Obviously, since the amount of data in the fourth part (part d) is small, the time for the control circuit 210 to perform the data recovery procedure will be greatly shortened. Even when the host 120 issues a write command to store the write data 390 (e.g., 0.35TB) to the non-volatile memory 140 during the data recovery procedure, the write latency time of the solid-state storage device 200 will be greatly shortened, so that the solid-state storage device 200 maintains better performance.

[0085] As can be seen from the above description, the present invention proposes a data management method for a solid-state storage device. The solid-state storage device 200 can selectively enable a time axis compensation write operation. When the control circuit 210 performs a write operation on the write data 150 of the host, the control circuit 210 monitors the instant write speed of the write operation. Furthermore, based on the instant write speed, the control circuit 210 determines whether to enable the time axis compensation write operation. When performing the time axis compensation write operation, the control circuit 210 determines a specific time interval with the largest amount of write data, and moves a portion of the write data stored in the specific time interval to other locations of the non-volatile memory 140. Therefore, when the solid-state storage device 200 performs a data recovery procedure based on the data retention time, the time for executing the data recovery procedure can be greatly shortened, so that the solid-state storage device 200 maintains better performance.

[0086] Furthermore, in the above-mentioned embodiment of the present invention, the time interval unit is described by taking 1 day as an example, but in fact the time interval unit is not limited to 1 day, and the time interval unit may also be 6 hours, 12 hours, etc. Similarly, the average writing speed and the real-time writing speed are not limited to calculating the written data volume in units of 1 minute, and may also be calculated in units of 15 minutes, half an hour, 1 hour, and half a day.

[0087] Furthermore, in the above-mentioned embodiment of the present invention, when the control circuit 210 performs the time axis compensation write operation (TACW operation), the write data 220 of the time axis compensation write operation may include valid data and invalid data (part a, part b, part c), but the write data 220 may also only include valid data. In addition, the data volume of part a, part b, and part c is determined by factors such as the real-time write speed, the average write speed difference between two consecutive time intervals, and the data volume of the maximum write data volume that has not been moved.

[0088] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the appended claims.

Claims

1. A data management method for a solid-state storage device, characterized in that: The solid-state storage device includes a non-volatile memory, and the data management method includes the following steps: Calculating a first average writing speed in an (N-2)th time interval; Calculating a second average writing speed in an (N-1)th time interval, wherein N is a positive integer, and the first average writing speed minus the second average writing speed equals an average writing speed difference; When the average write speed difference is less than a threshold write speed, a time axis compensation write operation is not started in the Nth time interval; Monitor a real-time writing speed; When the average write speed difference is greater than the threshold write speed and the real-time write speed is greater than the average write speed difference, the time axis compensation write operation is not started in the Nth time interval; as well as When the average write speed difference is greater than the threshold write speed and the real-time write speed is less than the average write speed difference, the time axis compensation write operation is started in the Nth time interval.

2. The data management method according to claim 1, characterized in that: The (N-2)th time interval and the (N-1)th time interval are two consecutive time intervals before the Nth time interval.

3. The data management method according to claim 1, characterized in that: In the Nth time interval, when a control circuit of the solid-state storage device performs a write operation on write data of a host and stores the write data of the host in a non-volatile memory, the control circuit monitors the real-time write speed during the write operation.

4. The data management method according to claim 3, characterized in that: When performing the time axis compensation writing operation, the control circuit determines a specific time interval before the Nth time interval, and moves a first portion of a writing data stored in the specific time interval to other locations of the non-volatile memory.

5. The data management method according to claim 4, characterized in that: When the time axis compensation writing operation is performed, the first part of the written data includes valid data and invalid data.

6. The data management method according to claim 4, characterized in that: The specific time interval has a maximum amount of the written data, and the interval between the specific time interval and the Nth time interval is less than a data retention time.

7. The data management method according to claim 6, characterized in that: When the storage time of the written data in the specific time interval reaches the data retention time, the control circuit performs a data recovery procedure.

8. The data management method according to claim 7, characterized in that: Among the write data stored in the specific time interval, the control circuit selects a second portion that is left and not moved to perform the data recovery procedure.

9. The data management method according to claim 7, characterized in that: The data recovery procedure is a recovery operation or a contact read operation.

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