Control chip and development board
By designing a partitioned storage and processing data on the control chip, the problem of inefficiency of existing memories when frequently reading data from different addresses is solved, and faster data processing and storage is achieved.
Patent Information
- Application Number
- CN202410519298.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-09
- Filing Date
- 2024-04-28
- Publication Date
- 2025-02-18
AI Technical Summary
When existing memory frequently reads data at different designated addresses, it will increase the time for the memory to output data, resulting in reduced efficiency.
A control chip is designed, including a first memory, a second memory, an access circuit and a processing circuit. The first memory is divided into two areas for storing sensing data and processing parameters. The access circuit generates read data and stores it in the second memory by reading continuous data and processing parameters. The processing circuit processes the sensing data according to the processing parameters and stores the result back to the second memory.
By partitioning and batching data, the address jump of the access circuit when reading data is reduced, the data reading time is shortened, and the overall efficiency is improved.
Smart Images
Figure CN119473125A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of control chips, and in particular to a control chip and a development board for processing continuous data. Background Art
[0002] Generally speaking, computer memory is divided into volatile memory and non-volatile memory. Non-volatile memory includes read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM) and flash memory. Volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM).
[0003] The memory usually outputs corresponding data according to a specified address. However, if the memory frequently reads data between different specified addresses, the time for the memory to output data will be increased. Summary of the invention
[0004] One embodiment of the present invention provides a control chip, coupled to a sensing circuit, and includes a first memory, a second memory, an access circuit, and a processing circuit. The first memory has a first storage area and a second storage area. The first storage area is used to store a sensing data provided by the sensing circuit. The second storage area is used to store a plurality of first processing parameters. The access circuit reads a continuous data in the first storage area according to a first access instruction to generate a first read data, and reads at least one first processing parameter in the second storage area according to a second access instruction to generate a second read data. The second memory stores the first read data and the second read data. The processing circuit reads the second memory, and processes the first read data according to the second read data to generate a processed data. The processing circuit stores the processed data in the second memory.
[0005] The present invention further provides a development board, including a sensing circuit, a first memory, an access circuit, a second memory and a processing circuit. The sensing circuit senses an environmental feature to generate sensing data. The first memory includes a first storage area and a second storage area. The first storage area is used to store the sensing data. The second storage area is used to store a plurality of processing parameters. The access circuit reads a continuous data in the first storage area according to a first access instruction to generate a first read data, and reads at least one processing parameter in the second storage area according to a second access instruction to generate a second read data. The second memory stores the first read data and the second read data. The processing circuit reads the second memory and processes the first read data according to the second read data to generate a first processed data. The processing circuit stores the first processed data in the second memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 It is a schematic diagram of the development board of the present invention.
[0007] Figure 2 Schematic diagram of internal data of the memory of the present invention.
[0008] [Explanation of symbols]
[0009] 100: Development Board
[0010] 110: Sensing circuit
[0011] 120: Control chip
[0012] 121, 122: Memory
[0013] 123: Access circuit
[0014] 124: Processing circuit
[0015] 125: Input and output interface
[0016] 126: Capture interface
[0017] DS: sensor data
[0018] RG11~RG13, RG21~RG23: Storage area
[0019] PAT11~PAT13, PAT21: Processing parameters
[0020] CM1, CM2: access instructions
[0021] DR1~DR3, DR1_1, DR1_2, DR3_1, DR3_2: read data
[0022] 0000, 1000: Address
[0023] DP1, DP2, DP1_1, DP1_2: Processing data DETAILED DESCRIPTION
[0024] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the following examples are specifically cited and described in detail with the accompanying drawings. The present invention specification provides different examples to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the example is for illustration and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the examples are for the purpose of simplifying the description and do not mean the relevance between different examples.
[0025] Figure 1Schematic diagram of the development board of the present invention. As shown in the figure, the development board 100 includes a sensing circuit 110 and a control chip 120. The sensing circuit 110 senses an environmental feature to generate a sensing data DS. In one possible embodiment, the sensing data DS is a serial data. The present invention does not limit the type of the sensing circuit 110. In one possible embodiment, the sensing circuit 110 is a temperature sensor or a sound sensor. In another possible embodiment, the sensing circuit 110 is an image sensor, such as a complementary metal-oxide semiconductor (CMOS) image sensor. In this example, the sensing data DS is an image signal, including a plurality of pixel data.
[0026] The control chip 120 is coupled to the sensing circuit 110 to receive the sensing data DS. In the present embodiment, the control chip 120 includes memories 121, 122, an access circuit 123, and a processing circuit 124. The memory 121 includes storage areas RG11-RG13. Each of the storage areas RG11-RG13 has a plurality of memory cells. The present invention does not limit the number of storage areas. In other embodiments, the memory 121 has more or fewer storage areas.
[0027] In this embodiment, the storage area RG11 is used to store the sensing data DS, and the storage area RG13 is used to store the processing parameters PAT11-PAT13. In some embodiments, if the sensing data DS is an image signal, the sensing data DS includes a plurality of pixel data. The pixel data is continuous data. For the sensing data DS, the processing parameters PAT11-PAT13 are discontinuous data. In this example, the processing parameters PAT11-PAT13 may be continuous data or discontinuous data. The present invention does not limit the type of the memory 121. In one possible embodiment, the memory 121 is a volatile memory. For example, the memory 121 is a HyperRAM.
[0028] In other embodiments, the control chip 120 further includes a capture interface 126. The capture interface 126 writes the sensing data DS from the sensing circuit 110 into the storage region RG11. In one possible embodiment, the capture interface 126 includes at least one storage capacitor (CCAP) for storing the sensing data DS from the sensing circuit 110. In some embodiments, when the sensing circuit 110 is an image sensing circuit, the capture interface 126 is an image capture interface that receives an image signal detected by the image sensing circuit.
[0029] The memory 122 has storage areas RG21-RG23. The present invention does not limit the number of storage areas. In other embodiments, the memory 122 has more or fewer storage areas. In some embodiments, the capacity of the memory 122 is less than the capacity of the memory 121. The present invention does not limit the type of the memory 122. In one possible embodiment, the memory 122 is a volatile memory. For example, the memory 122 is a static random access memory (SRAM).
[0030] The access circuit 123 reads data from a first storage area and data from a second storage area of the memory 121, and then stores the read result in the memory 122. In one possible embodiment, the access circuit 123 reads a continuous data from a first starting address of the first storage area, and reads at least one processing parameter from a second starting address of the second storage area. The present invention does not limit how the access circuit 123 reads the memory 121. In one possible embodiment, the access circuit 123 uses a direct memory access (DMA) technology to access the memories 121 and 122.
[0031] In one possible embodiment, the access circuit 123 reads a continuous data of the storage area RG11 according to an access command CM1 to generate a read data DR1. In this example, the access circuit 123 stores the read data DR1 in the storage area RG21. In addition, the access circuit 123 reads at least one processing parameter (such as PAT11) stored in the storage area RG13 according to an access command CM2 to generate a read data DR2. In this example, the access circuit 123 stores the read data DR2 in the storage area RG23.
[0032] The processing circuit 124 reads the memory 122 and processes the read data DR1 according to the read data DR2 to generate a processed data DP1. The present invention does not limit how the processing circuit 124 processes the read data DR1. In a possible embodiment, the processing circuit 124 may perform sharpness processing, image enhancement processing, compression processing, and data format conversion processing on the read data DR1 according to the read data DR2. In some embodiments, the processing circuit 124 is a central processing unit (CPU).
[0033] The processing circuit 124 stores the processing data DP1 in the memory 122. In one embodiment, the processing circuit 124 stores the processing data DP1 in the storage area RG21 to replace the read data DR1. In some embodiments, the processing circuit 124 provides access instructions CM1 and CM2 to instruct the access circuit 123 to read the memory 121.
[0034] The access circuit 123 reads the processed data DP1 of the storage area RG21 of the memory 122 to generate a read data DR3. The access circuit 123 stores the read data DR3 in the memory 121. In one possible embodiment, the access circuit 123 stores the read data DR3 in the storage area RG11 to replace part of the sensed data DS. In another possible embodiment, the access circuit 123 stores the read data DR3 in the storage area RG12. In this example, the memory 121 has the data before processing (i.e., DS) and the data after processing (i.e., DR3). Therefore, the processing circuit 124 knows the change of the data according to the data before processing (i.e., DS) and the data after processing (i.e., DR3) stored in the memory.
[0035] For example, the memory 121 sets address 0000 as the starting address of the storage area RG11, and sets address 1000 as the starting address of the storage area RG12. Assume that the sensing data DS is an image data, and the image data includes WxH pixel data. In this example, the access circuit 123 starts from the starting address 0000, reads W data, and reads H times in total. Whenever the access circuit 123 stores W data to the memory 122, the processing circuit 124 processes the W data stored in the memory 122 and stores the processing result back to the memory 122. After the processing circuit 124 processes H times, the memory 122 stores H processing data DP1. The access circuit 123 reads the processing data WxH stored in the memory 122 to generate the read data DR3, and writes the read data DR3 back to the memory 121. The access circuit 123 may start from the address 0000 and store the read data DR3. In this example, the read data DR3 overwrites the sensing data DS of the memory 121. In another possible embodiment, the access circuit 123 starts from address 1000 and stores the read data DR3. Therefore, the processing circuit 124 can start from address 0000 and 1000 of the memory 121 to check the data changes before and after processing.
[0036] In other embodiments, the processing circuit 124 adjusts the read data DR2 stored in the storage area RG23 of the memory 122 to generate a processed data DP2. The processing circuit 124 writes the processed data DP2 back to the storage area RG23 to replace the read data DR2. In this example, the processing circuit 124 processes the read data DR1 according to the processed data DP2.
[0037] In some embodiments, the control chip 120 further includes an input / output interface 125 for receiving a processing parameter PAT21. In this example, the processing parameter PAT21 is stored in the storage area RG23. In this example, the processing parameter PAT21 may replace the read data DR2. In another possible embodiment, the processing circuit 124 processes the read data DR1 according to the processing parameter PAT21, and writes the processing result (i.e., DP1) into the storage area RG21. In this example, the access circuit 123 writes the processing result (i.e., DP1) back to the storage area RG11.
[0038] In other embodiments, the processing circuit 124 may process the same data in the storage region RG21 according to different processing parameters of the storage region RG23. In another embodiment, the processing circuit 124 may process different data in the storage region RG21 according to different processing parameters of the storage region RG23.
[0039] In some embodiments, the access circuit 123 first writes at least one of the processing parameters PAT11-PAT13 into the storage area RG23. Then, the access circuit 123 only needs to specify a starting address to read the continuous data of the storage area RG11. Since the access circuit 123 does not need to specify a short range of addresses multiple times, the time for the access circuit 123 to read data can be shortened. In addition, when the access circuit 123 writes the read data DR3 back to the memory 121, the processing circuit 124 does not need to intervene, so the processing circuit 124 can perform other processing, which greatly increases the efficiency of the control chip 120.
[0040] Figure 2 Schematic diagram of internal data of the memory 121 and 122 of the present invention. The memory 121 has storage areas RG11-RG13. The storage area RG11 stores the sensing data DS. The sensing data DS includes column data RA1-RA5. The column data RA1-RA5 are sequentially stored in the storage area RG11.
[0041] The storage region RG12 stores the read data DR3. In this embodiment, the read data DR3 includes column data RB1-RB5. The column data RB1-RB5 are sequentially stored in the storage region RG12. In one possible embodiment, the data size of the read data DR3 is the same as the data size of the sense data DS. For example, the data sizes of the read data DR3 and the sense data DS are both 640x480.
[0042] The storage area RG13 stores the processing parameters PAT11-PAT13. In one possible implementation, the processing parameters PAT11-PAT13 are continuous data or discontinuous data. In another possible embodiment, since the sensing data DS and the processing parameters PAT11-PAT13 are stored in different storage areas, the sensing data DS and the processing parameters PAT11-PAT13 are discontinuous data. In this example, the access circuit 123 needs at least two starting addresses to read the data of the two storage areas (such as RG11 and RG12).
[0043] The memory 122 includes storage areas RG21-RG23. The storage area RG21 stores continuous data from the storage area RG11. For example, the access circuit 123 reads the column data RA1 in the storage area RG11, and stores the read result as the read data DR1_1 in the storage area RG21 of the memory 122. In this example, the read data DR1_1 is the column data RA1. In some embodiments, the access circuit 123 reads the column data RA2 in the storage area RG11, and stores the read result as the read data DR1_2 in the storage area RG21 of the memory 122.
[0044] The processing circuit 124 processes the data in the storage region RG21 and stores the processed result in the storage region RG21 to replace the original read data DR1_1 and DR1_2 in the storage region RG21. In another possible embodiment, the processing circuit 124 stores the processed result in the storage region RG22.
[0045] The storage area RG23 stores at least one processing parameter. In one possible embodiment, the processing parameter of the storage area RG23 is the same as the processing parameter of the storage area RG13. For example, the access circuit 123 reads the processing parameter PAT11 of the storage area RG13 to generate the read data DR2. The access circuit 123 stores the read data DR2 in the storage area RG23. In this example, the read data DR2 is the same as the processing parameter PAT11. In other embodiments, the storage area RG13 further stores the processing parameter PAT21. In this example, the processing parameter PAT21 comes from an input / output interface.
[0046] The processing circuit 124 processes the read data DR1_1 and DR1_2 according to the read data DR2 to generate the processed data DP1_1 and DP1_2. The processing circuit 124 may write the processed data DP1_1 and DP1_2 into the storage region RG21 to replace the read data DR1_1 and DR1_2. In another possible embodiment, the processing circuit 124 writes the processed data DP1_1 and DP1_2 into the storage region RG22.
[0047] The access circuit 123 reads the processed data DP1_1 and DP1_2 of the storage region RG21 to generate the read data DR3_1 and DR3_2. The access circuit 123 writes the read data DR3_1 and DR3_2 into the storage region RG12. In this example, the read data DR3_1 is used as the column data RB1, and the read data DR3_2 is used as the column data RB2.
[0048] The present invention does not limit the amount of data stored in the storage area RG21. In one possible embodiment, the amount of data stored in the storage area RG21 is the same as the amount of data stored in the storage area RG11. In this example, the access circuit 123 reads the column data RA1-RA5 in sequence and writes the read result into the storage area RG21. In another possible embodiment, the amount of data stored in the storage area RG21 is less than the amount of data stored in the storage area RG11. In this example, the access circuit 123 reads the column data RA1 and writes the read result into the storage area RG21. After the processing circuit 124 completes the processing, the access circuit 123 stores the processing result back to the memory 121, and then reads another column of data (such as RA2) until the processing circuit 124 completes the processing of the column data RA1-RA5.
[0049] Unless otherwise defined, all words (including technical and scientific words) herein are generally understood by those skilled in the art. In addition, unless expressly indicated, the definitions of words in general dictionaries should be interpreted as consistent with the meanings in articles in the relevant technical field, and should not be interpreted as ideal or overly formal. Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.
[0050] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the definition of the claims.
Claims
1. A control chip coupled to a sensing circuit, characterized in that: include: A first memory, comprising: a first storage area for storing sensing data provided by the sensing circuit; and a second storage area for storing a plurality of first processing parameters; an access circuit, which reads a continuous data in the first storage area according to a first access instruction to generate a first read data, and reads at least a first processing parameter in the second storage area according to a second access instruction to generate a second read data; a second memory for storing the first read data and the second read data; and a processing circuit, which reads the second memory and processes the first read data according to the second read data to generate a first processed data; in: The processing circuit stores the first processing data in the second memory, The access circuit accesses the second memory to read the first processed data and write the first processed data into the first memory.
2. The control chip according to claim 1, characterized in that: The access circuit writes the first processing data into the first storage area.
3. The control chip according to claim 2, characterized in that: The first processed data covers part of the sensed data.
4. The control chip according to claim 1, characterized in that: The access circuit writes the first processed data into a third storage area of the first memory, where the third storage area is different from the first storage area.
5. The control chip according to claim 1, characterized in that: Also includes: An input / output interface is used to receive at least one second processing parameter and write the second processing parameter into the second memory.
6. The control chip according to claim 5, characterized in that: The processing circuit reads the second memory and processes the first read data according to the second processing parameter to generate second processed data. The processing circuit stores the second processed data in the second memory. The access circuit accesses the second memory to read the second processed data and writes the second processed data into the first memory.
7. A development board, characterized in that: include: A sensing circuit, sensing an environmental feature to generate sensing data; A first memory, comprising: a first storage area for storing the sensing data; and a second storage area for storing a plurality of first processing parameters; an access circuit, which reads a continuous data in the first storage area according to a first access instruction to generate a first read data, and reads at least a first processing parameter in the second storage area according to a second access instruction to generate a second read data; a second memory for storing the first read data and the second read data; and a processing circuit, which reads the second memory and processes the first read data according to the second read data to generate a first processed data; in: The processing circuit stores the first processing data in the second memory, The access circuit accesses the second memory to read the first processed data and write the first processed data into the first memory.
8. The development board according to claim 7, characterized in that: The sensing circuit is an image sensor.
9. The development board according to claim 8, characterized in that: Also includes: A capture interface writes the sensing data into the first storage area.