Data processing system, method, product, equipment and storage medium

Abstract

The embodiment of the invention relates to the technical field of data processing, in particular to a data processing system and method, a product, equipment and a storage medium, and aims to improve the data transmission speed between a central processing unit and a graphics processing unit. The data processing system comprises a central processing unit cluster which comprises a plurality of central processing unit cores and a first cluster sharing cache; the graphics processor cluster comprises a plurality of graphics processor cores and a second cluster shared cache; a shared memory; each central processing unit core in the central processing unit cluster is provided with a secondary private cache; each graphics processor core in the graphics processor cluster is provided with a first-level private cache; and writing corresponding data into the second cluster shared cache by any central processing unit core in the central processing unit cluster under the condition that an address contained in a received data writing request is a graphics processor address.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of data processing technology, and more specifically, to a data processing system, method, product, device, and storage medium. Background Art

[0002] Heterogeneous multi-core processors integrate different types of computing units such as CPU (Central Processing Unit) and GPU (Graphics Processing Unit) to provide a more flexible and efficient computing platform. This architecture uses the sequential processing capabilities of the CPU and the parallel processing capabilities of the GPU to adapt to various computing loads. In related technologies, the CPU is usually responsible for generating data and writing it back to the shared memory. The GPU reads this data from the shared memory for calculation, generates a large amount of result data, and writes it back to the memory again.

[0003] In the related technology, this data transmission mode significantly increases the transmission delay under high load because data is frequently transferred between the CPU and GPU. Especially during GPU processing, if the required data cannot be obtained in the cache in time, it will lead to a high cache miss rate, forcing the GPU to read data from the main memory, resulting in slower processing speed and affecting the overall system operation speed of the heterogeneous multi-core processor. Summary of the invention

[0004] The embodiments of the present application provide a data processing method, product, device and storage medium, which are intended to improve the data transmission speed between the central processing unit and the graphics processing unit of a heterogeneous processor.

[0005] A first aspect of an embodiment of the present application provides a data processing system, the system comprising: A central processing unit cluster, comprising: a first central processing unit core, a second central processing unit core, a third central processing unit core, a fourth central processing unit core, and a first cluster shared cache; A graphics processor cluster, comprising: a first graphics processor core, a second graphics processor core, a third graphics processor core, a fourth graphics processor core, and a second cluster shared cache; A shared memory, used to store data that can be read by both the CPU cluster and the GPU cluster; Each CPU core in the CPU cluster is provided with a secondary private cache; Each graphics processor core in the graphics processor cluster is provided with a first-level private cache; When the address included in the received data write request is a graphics processor address, any one of the CPU cores in the CPU cluster writes the corresponding data into the second cluster shared cache.

[0006] Optionally, when the storage space of the first-level private cache of each central processing unit core is insufficient, the cache line data that has not been accessed for the longest time in the first-level private cache is sent to the second-level private cache for storage; When the storage space of the second-level private cache is insufficient, the cache line data that has not been accessed for the longest time in the second-level private cache is sent to the first cluster shared cache for storage; When the storage space of the first cluster shared cache is insufficient, cache line data that has not been accessed for the longest time in the first cluster shared cache is sent to the shared memory for storage.

[0007] Optionally, when the storage space of the private cache of each graphics processor core is insufficient, the cache line data that has not been accessed for the longest time in the private cache is sent to the second cluster shared cache for storage; When the storage space of the second cluster shared cache is insufficient, cache line data that has not been accessed for the longest time in the second cluster shared cache is sent to the shared memory for storage.

[0008] Optionally, when each CPU core or GPU core writes data into the private cache, the cache state of the private cache is an exclusive state.

[0009] A second aspect of an embodiment of the present application provides a data processing method, which is based on any one of the data processing systems provided in the first aspect of the embodiment of the present application, and includes: Upon receiving a first data read request sent by any central processing unit core in the central processing unit cluster, determining a first target address corresponding to the first data read request; In the case where the first target address is a CPU address, querying corresponding caches in the CPU cluster level by level according to the first target address; When the corresponding cache is found, the data corresponding to the first data read request is read from the cache.

[0010] Optionally, the method further comprises: When the corresponding cache is not found, the data is read from the shared memory.

[0011] Optionally, the method further comprises: In the case where the first target address is a graphics processor address, determining that the first target address is in a miss state in the central processing unit cluster; The data corresponding to the first target address is read in the shared memory.

[0012] Optionally, querying corresponding caches in the CPU cluster level by level according to the first target address includes: Determining whether the first target address hits in a first-level private cache in each CPU core in the CPU cluster; When the first target address hits in the first-level private cache, determining that the first-level private cache is the cache corresponding to the first target address; In the case where the first target address does not hit in the first-level private cache, determining whether the first target address hits in the second-level private cache in the central processing unit core; When the first target address hits in the second-level private cache, determining that the second-level private cache is the cache corresponding to the first target address; If the first target address does not hit in the second-level private cache, determining whether the first target address hits in the first cluster shared cache; When the first target address hits in the first cluster shared cache, the first cluster shared cache is determined to be the cache corresponding to the first target address.

[0013] Optionally, the method further comprises: Upon receiving a second data read request sent by any graphics processor core in the graphics processor cluster, determining a second target address corresponding to the second data read request; According to the second target address, querying corresponding caches in the graphics processor cluster level by level; When the corresponding cache is found, the data corresponding to the second data read request is read from the cache.

[0014] Optionally, the method further comprises: When the corresponding cache is not found, the data is read from the shared memory.

[0015] Optionally, querying the corresponding cache in the graphics processor cluster level by level according to the second target address includes: Determining whether the second target address hits in a private cache in each graphics processor core in the graphics processor cluster; When the second target address hits the private cache, determining that the private cache is the cache corresponding to the second target address; If the second target address does not hit in the private cache, determining whether the second target address hits in the second cluster shared cache; When the second target address hits in the second cluster shared cache, the second cluster shared cache is determined to be the cache corresponding to the second target address.

[0016] Optionally, the method further comprises: Upon receiving a first data write request sent by the central processing unit core, determining a third target address corresponding to the first data write request; In the case where the third target address is a CPU address, determining whether the third target address is hit in a first-level private cache of a CPU core of the CPU cluster; When the third target address hits the first-level private cache, determining whether the cache line state of the first-level private cache is an exclusive state; When the cache line state is not the exclusive state, changing the cache line state to the exclusive state; When the cache line state is the exclusive state, the data corresponding to the first data write request is written into the first-level private cache.

[0017] Optionally, the method further comprises: In case the third target address misses, performing cache replacement includes: storing the cache line data which has not been accessed for the longest time in the first-level private cache into the second-level private cache; The data corresponding to the first data write request is written into the first-level private cache.

[0018] Optionally, the method further comprises: In the case where the third target address is a graphics processor address, determining in the second cluster shared cache whether the third target address is hit; When the third target address hits, the data corresponding to the first data write request is written into the second cluster shared cache.

[0019] Optionally, the method further comprises: In case the third target address misses, performing cache replacement includes: storing cache line data in the second cluster shared cache that has not been accessed for the longest time into the shared memory; The data corresponding to the first data write request is written into the second cluster shared cache.

[0020] Optionally, the method further comprises: When receiving a second data write request sent by any graphics processor core in the graphics processor cluster, determining a fourth target address corresponding to the second data write request; Determining whether the fourth target address is hit in the private cache of the graphics processor core; When the fourth target address hits the private cache, determining whether a cache line state of the private cache is an exclusive state; When the cache line state is not the exclusive state, changing the cache line state of the private cache to the exclusive state; When the cache line state is the exclusive state, the data corresponding to the second data write request is written into the private cache.

[0021] Optionally, the method further comprises: In case the fourth target address is not hit, performing cache replacement includes: storing the cache line data which has not been accessed for the longest time in the private cache into the second cluster shared cache; The data corresponding to the second data write request is written into the private cache.

[0022] A third aspect of an embodiment of the present application provides a data processing device, the device comprising: A first target address determination module, configured to determine a first target address corresponding to a first data read request when receiving a first data read request sent by any central processing unit core in a central processing unit cluster; A first cache query module, configured to query corresponding caches level by level in the CPU cluster according to the first target address when the first target address is a CPU address; The first data reading module is used to read the data corresponding to the first data reading request from the cache when the corresponding cache is found.

[0023] Optionally, the device further comprises: The second data reading module is used to read the data from the shared memory when the corresponding cache is not found.

[0024] Optionally, the device further comprises: a first miss state determination module, configured to determine, when the first target address is a graphics processor address, that the first target address is in a miss state in the central processing unit cluster; The third data reading module is used to read the data corresponding to the first target address in the shared memory.

[0025] Optionally, the first cache query module includes: A first hit status determination submodule, configured to determine whether the first target address is hit in a first-level private cache in each CPU core in the CPU cluster; A first cache determination submodule, configured to determine, when the first target address hits in the first-level private cache, that the first-level private cache is the cache corresponding to the first target address; a second hit status determination submodule, configured to determine whether the first target address hits in a second-level private cache in the CPU core if the first target address does not hit in the first-level private cache; A second cache determination submodule, configured to determine, when the first target address hits in the second-level private cache, that the second-level private cache is the cache corresponding to the first target address; a third hit status determination submodule, configured to determine whether the first target address hits in the first cluster shared cache when the first target address does not hit in the second-level private cache; The third cache determination submodule is configured to determine, when the first target address hits in the first cluster shared cache, that the first cluster shared cache is the cache corresponding to the first target address.

[0026] Optionally, the device further comprises: A second target address determination module, configured to determine a second target address corresponding to a second data read request when receiving a second data read request sent by any graphics processor core in the graphics processor cluster; A second cache query module, configured to query corresponding caches level by level in the graphics processor cluster according to the second target address; The fourth data reading module is used to read the data corresponding to the second data reading request from the cache when the corresponding cache is queried.

[0027] Optionally, the device further comprises: The fifth data reading module is used to read the data from the shared memory when the corresponding cache is not found.

[0028] Optionally, the second cache query module includes: a fourth hit status determination submodule, configured to determine whether the second target address is hit in a private cache in each graphics processor core in the graphics processor cluster; a fourth cache determination submodule, configured to determine, when the second target address hits the private cache, that the private cache is the cache corresponding to the second target address; a fifth hit status determination submodule, configured to determine whether the second target address hits in a second cluster shared cache when the second target address does not hit in the private cache; The fifth cache determination submodule is configured to determine, when the second target address hits in the second cluster shared cache, that the second cluster shared cache is the cache corresponding to the second target address.

[0029] Optionally, the device further comprises: A third address determination module, configured to determine a third target address corresponding to a first data write request when receiving the first data write request sent by the central processing unit core; a first hit status determination module, configured to determine whether the third target address is hit in a first-level private cache of a CPU core of the CPU cluster when the third target address is a CPU address; A first cache line state determination module, configured to determine whether the cache line state of the first-level private cache is an exclusive state when the third target address hits the first-level private cache; A first state changing module, configured to change the cache line state to the exclusive state when the cache line state is not the exclusive state; The first data writing module is used to write the data corresponding to the first data writing request into the first-level private cache when the cache line state is the exclusive state.

[0030] Optionally, the device further comprises: The first cache replacement module is used to perform cache replacement when the third target address is not hit, including: storing the cache line data which has not been accessed for the longest time in the first-level private cache into the second-level private cache; The second data writing module is used to write the data corresponding to the first data writing request into the first-level private cache.

[0031] Optionally, the device further comprises: A second hit status determination module, configured to determine whether the third target address is hit in the second cluster shared cache when the third target address is a graphics processor address; The third data writing module is used to write the data corresponding to the first data writing request into the second cluster shared cache when the third target address is hit.

[0032] Optionally, the device further comprises: The second cache replacement module is used to perform cache replacement when the third target address is not hit, including: storing cache line data in the second cluster shared cache that has not been accessed for the longest time into the shared memory; The fourth data writing module is used to write the data corresponding to the first data writing request into the second cluster shared cache.

[0033] Optionally, the device further comprises: a fourth target address determining module, configured to determine a fourth target address corresponding to a second data write request when receiving a second data write request sent by any graphics processor core in the graphics processor cluster; a third hit status determination module, configured to determine whether the fourth target address is hit in the private cache of the graphics processor core; A second cache line state determination module, configured to determine whether the cache line state of the private cache is an exclusive state when the fourth target address hits the private cache; A second state changing module, configured to change the cache line state of the private cache to the exclusive state when the cache line state is not the exclusive state; A fifth data writing module is used to write the data corresponding to the second data writing request into the private cache when the cache line state is the exclusive state.

[0034] Optionally, the device further comprises: The second cache replacement module is used to perform cache replacement when the fourth target address is not hit, including: storing the cache line data which has not been accessed for the longest time in the private cache into the second cluster shared cache; A sixth data writing module is used to write the data corresponding to the second data writing request into the private cache.

[0035] A fourth aspect of an embodiment of the present application provides a product, including a computer program / instruction, which, when executed by a processor, implements the steps of any of the methods provided in the first aspect of the present application.

[0036] A fifth aspect of an embodiment of the present application provides a readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps in the method described in the first aspect of the present application are implemented.

[0037] A sixth aspect of an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the method described in the first aspect of the present application are implemented.

[0038] Using the data processing system provided by the present application, the central processing unit cluster includes: a central processing unit cluster, including: a first central processing unit core, a second central processing unit core, a third central processing unit core, a fourth central processing unit core, and a first cluster shared cache; a graphics processing unit cluster, including: a first graphics processing unit core, a second graphics processing unit core, a third graphics processing unit core, a fourth graphics processing unit core, and a second cluster shared cache; a shared memory is used to store data that can be read by both the central processing unit cluster and the graphics processing unit cluster; each central processing unit core in the central processing unit cluster is provided with a three-level cache, including: a first-level private cache, a second-level private cache, and the first cluster shared cache; each graphics processing unit core in the graphics processing unit cluster is provided with a second-level cache, including: a private cache, and the second cluster shared cache; when any of the central processing unit cores in the central processing unit cluster receives a data write request in which the address contained in the request is a graphics processor address, the corresponding data is written into the second cluster shared cache, and the data is dirty data.

[0039] In the present application, a central processing unit cluster and a graphics processing unit cluster are set up, wherein the central processing unit cluster includes two levels of private memory and a first cluster shared cache, and the graphics processing unit cluster includes a first level of private memory and a second cluster shared cache. When storing data, any central processing unit core can store the data corresponding to the graphics processor directly in the second cluster shared cache, and the graphics processing unit core can directly obtain the data from the second cluster shared cache, without the need to store the data in the shared memory first and then obtain it from the shared memory by the graphics processing unit core, which significantly improves the performance of the graphics processor and the data access speed, thereby improving the efficiency of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0041] Figure 1 It is a schematic diagram of the data processing system architecture proposed in one embodiment of the present application; Figure 2 is a schematic diagram of an address space proposed in an embodiment of the present application; Figure 3 This is a schematic diagram of a second cluster shared cache structure proposed in an embodiment of the present application; Figure 4 This is a schematic diagram of data writing to a central processing unit proposed in an embodiment of the present application; Figure 5 is a flow chart of a data processing method proposed in one embodiment of the present application; Figure 6 is a CPU data reading flow chart proposed in one embodiment of the present application; Figure 7 is a flowchart of core data reading of a graphics processor proposed in an embodiment of the present application; Figure 8 This is a flow chart of a CPU writing data proposed in an embodiment of the present application; Fig. 9 This is a flowchart of a graphics processor writing data proposed in an embodiment of the present application; Fig.10 is a schematic diagram of a data processing device proposed in an embodiment of the present application; Fig.11 It is a schematic diagram of an electronic device proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] refer to Figure 1 , Figure 1 Schematic diagram of the data processing system architecture proposed in one embodiment of the present application. Figure 1 As shown, the system comprises: A central processing unit cluster, comprising: a first central processing unit core, a second central processing unit core, a third central processing unit core, a fourth central processing unit core, and a first cluster shared cache; a graphics processing unit cluster, comprising: a first graphics processing unit core, a second graphics processing unit core, a third graphics processing unit core, a fourth graphics processing unit core, and a second cluster shared cache; a shared memory for storing data readable by both the central processing unit cluster and the graphics processing unit cluster; each central processing unit core in the central processing unit cluster is provided with a third-level cache; each graphics processing unit core in the graphics processing unit cluster is provided with a second-level cache; when any of the central processing unit cores in the central processing unit cluster receives a data write request containing an address that is a graphics processor address, the corresponding data is written into the second cluster shared cache, and the data is dirty data.

[0044] When the storage space of the first-level private cache of each central processing unit core is insufficient, the cache line data that has not been accessed for the longest time in the first-level private cache is sent to the second-level private cache for storage; when the storage space of the second-level private cache is insufficient, the cache line data that has not been accessed for the longest time in the second-level private cache is sent to the first cluster shared cache for storage; when the storage space of the first cluster shared cache is insufficient, the cache line data that has not been accessed for the longest time in the first cluster shared cache is sent to the shared memory for storage.

[0045] When the storage space of the private cache of each graphics processor core is insufficient, the cache line data that has not been accessed for the longest time in the private cache is sent to the second cluster shared cache for storage; when the storage space of the second cluster shared cache is insufficient, the cache line data that has not been accessed for the longest time in the second cluster shared cache is sent to the shared memory for storage.

[0046] When each CPU core or GPU core writes data into the private cache, the cache state of the private cache is an exclusive state.

[0047] In this embodiment, the proposed data processing system is essentially a multi-core heterogeneous processor architecture, the central processing unit cluster (CPU cluster) is composed of 4 central processing unit cores, each central processing unit core has a three-level cache, including a first-level private cache (L1), a second-level private cache (L2), and a first cluster shared cache. The graphics processor cluster is composed of 4 graphics processor cores, and has two levels of cache, including a private cache and a second cluster shared cache. The architecture also includes a shared memory (DRAM), and all the central processing unit cores and graphics processor cores can store or read data in the shared memory.

[0048] In this embodiment, the central processing unit cluster follows the cache consistency principle when reading data. When a core wants to read data, it first queries the first-level private cache, and when the first-level private cache misses, it queries the second-level private cache. If the second-level private cache misses, the data is read from the first cluster shared cache. If there is no data in the first cluster shared cache, the data is read from the shared memory.

[0049] In this embodiment, the central processing unit cluster also follows the cache consistency principle when writing data. When a core wants to write data, it first obtains an exclusive state to ensure that the cache behavior in the corresponding level of cache in the remaining cores is invalid, and then performs the write operation, thereby ensuring the cache consistency of each core in the cluster.

[0050] In this embodiment, the graphics processor cluster follows the cache consistency principle when reading data. When a core wants to read data, it first queries the first-level private cache. If the first-level private cache does not hit, it queries the second cluster shared cache. If the second cluster shared cache does not hit, it reads data from the shared memory.

[0051] In this embodiment, the GPU cluster is similar to the CPU cluster in writing data. When a core wants to write data, it first invalidates the data of the same cache line of other cores in the cache, so that the private cache of the core is in an exclusive state, and then performs the write operation.

[0052] In this embodiment, the second cluster shared cache is a cache that all graphics processor cores can access. In addition, data generated by the central processing unit core can also be directly written into the second cluster shared cache. In this way, the graphics processor core does not need to obtain data from the shared memory when reading data, but can directly obtain data from the second cluster shared cache, thereby increasing the data reading speed.

[0053] refer to Figure 2 , Figure 2 is a schematic diagram of the address space proposed in an embodiment of the present application, such as Figure 2 As shown, the address of the data is composed of the CPU address space and the GPU address space. When a data read or data write request is received, it is necessary to determine whether the target address is the CPU address or the GPU address, and the proportion of the two spaces can be flexibly adjusted according to the actual usage scenario.

[0054] refer to Figure 3 , Figure 3 is a schematic diagram of a second cluster shared cache structure proposed in an embodiment of the present application, such as Figure 3As shown, the second cluster shared cache includes data written by the CPU cluster and data written by the GPU cluster, and the GPU cluster can read any data in the second cluster shared cache. When the CPU core recognizes the address as the GPU address, the data can be directly sent to the second cluster shared cache for caching.

[0055] In this embodiment, the data processing system uses the CHI protocol to maintain cache consistency, and defines five states for describing cache line states in the cache.

[0056] Wherein I is an invalid state, indicating that the data is invalid.

[0057] The SC state is a shared state, and the cache line data is clean (clean state data), that is, the data in the cache is the same as the data in the memory, and there may be cache line copies in other cores.

[0058] SD is a shared state, and the cache line data is dirty (dirty data), that is, the data in the cache is different from the data in the memory, and there may be cache line copies in other cores.

[0059] UC is in exclusive state, the cache line data is clean, and there is no cache line copy in other cores.

[0060] UD is in exclusive state, the cache line data is clean, and there is no cache line copy in other cores.

[0061] In order to ensure the cache consistency of the system, the cache of the core that writes data must first obtain an exclusive state (UC state or UD state). In this way, when data is written to the cache of one core, the corresponding cache lines in the caches of other cores are invalid. When the data is finally sent to the shared memory for storage, only the cache lines written by this core will be stored, thereby ensuring the cache consistency of the system.

[0062] refer to Figure 4 , Figure 4 is a schematic diagram of CPU data writing proposed in an embodiment of the present application, such as Figure 4 As shown, when the data generated by the CPU cluster wants to be written to the GPU cluster, the CPU core first checks the address field on the address. If the address is the CPU address, the data is written to the cache corresponding to the CPU. If the address is the GPU address, the data is directly written to the shared cache of the second cluster. A core of the CPU cluster writes data directly to the shared cache of the second cluster. The written data is in UD state. When the GPU core wants to read the data, it is directly obtained from the shared cache of the second cluster.

[0063] In this embodiment, in the CPU cluster, the CPU core includes two levels of private cache, the first level private cache has the fastest speed and the smallest space, the second level private cache space is larger than the first level private cache, but the speed is slightly lower, and the first cluster shared cache is slower, but has a larger space. In the GPU cluster, the private cache has the fastest speed and the smallest space, and the second cluster shared cache has a slower speed but a larger space. The shared memory has the largest space, but the data access speed is the slowest. When storing data, it is first stored in the first level private cache, and the infrequently used data is then stored in the second level private cache, and so on. The storage order of the CPU core data is the first level private cache-the second level private cache-the first cluster shared cache-the shared memory, and the storage order of the GPU core data is the private cache-the second cluster shared cache-the shared memory.

[0064] refer to Figure 5 , Figure 5 1 is a flow chart of a data processing method proposed in one embodiment of the present application. Figure 5 As shown, the method comprises the following steps: S11: upon receiving a first data read request sent by any central processing unit core in a central processing unit cluster, determining a first target address corresponding to the first data read request.

[0065] In this embodiment, the first data read request is a data read request sent by the central processing unit core, and the first target address is a data storage address included in the data read request sent by the central processing unit core.

[0066] In this embodiment, reference Figure 6 , Figure 6 is a CPU data reading flow chart proposed in an embodiment of the present application, such as Figure 6 As shown, when the system receives a data read request sent by any central processing unit core, a first target address corresponding to the data read request is determined.

[0067] S12: When the first target address is a CPU address, query corresponding caches in the CPU cluster level by level according to the first target address.

[0068] In this embodiment, the CPU address is an address corresponding to data stored in the CPU cluster.

[0069] In this embodiment, Figure 6 As shown, when the first target address is a CPU address, the corresponding cache is queried level by level in the CPU cluster according to the first target address, and the specific steps include: S12 - 1 : Determine whether the first target address hits in the first-level private cache of each central processing unit core in the central processing unit cluster.

[0070] In this embodiment, the first target address hit means that the target address is found in the cache.

[0071] In this embodiment, the first target address is first searched in the first-level private cache in each CPU core in the CPU cluster.

[0072] S12-2: When the first target address hits in the first-level private cache, determine that the first-level private cache is the cache corresponding to the first target address.

[0073] In this embodiment, when the first target address hits, that is, the first target address is found in the first-level private cache, the data required by the first data read request is stored in the first-level private cache, and the first-level private cache is determined to be the cache corresponding to the first target address.

[0074] S12-3: If the first target address does not hit in the first-level private cache, determine whether the first target address hits in the second-level private cache in the central processing unit core.

[0075] In this embodiment, when the first target address is not hit, that is, when the first target address is not found in the first-level private cache, the data required by the first data read request is not stored in the first private cache, and the data read request is sent to the cache controller of the second-level private cache to determine whether the first target address is hit in the second-level private cache in the central processing unit core.

[0076] In this embodiment, because the first-level private cache is closest to the core, has the fastest speed but the smallest storage space, the first-level private cache will send data to the second-level private cache when the storage space is insufficient. The second-level private cache has a larger space, and so on. The space in the shared memory is the largest. Therefore, when querying level by level, the query is performed in the order of first private cache-second private cache-shared cache-shared memory.

[0077] S12-4: When the first target address hits in the second-level private cache, determine that the second-level private cache is the cache corresponding to the first target address.

[0078] In this embodiment, when the first target address hits, that is, when the first target address is found in the second-level private cache, the data required by the first data read request is stored in the second-level private cache, and the second-level private cache is determined to be the cache corresponding to the second target address.

[0079] S12 - 5 : If the first target address does not hit in the second-level private cache, determine whether the first target address hits in the first cluster shared cache.

[0080] In this embodiment, when the first target address does not hit, that is, when the first target address is not found in the second-level private cache, the data required by the first data read request is not stored in the second-level private cache, and it is determined in the first cluster shared cache whether the first target address hits.

[0081] S12 - 6 : When the first target address hits in the first cluster shared cache, determine that the first cluster shared cache is the cache corresponding to the first target address.

[0082] In this embodiment, when the first target address is hit, the data required by the first data read request is stored in the first cluster shared cache, and the first cluster shared cache is determined to be the cache corresponding to the first target address.

[0083] S13: When the corresponding cache is found, the data corresponding to the data read request is read from the cache.

[0084] In this embodiment, when the first target address hits and the corresponding cache is found, the data requested by the data read request is read from the corresponding cache.

[0085] In this embodiment, the method further includes: S14: When the corresponding cache is not found, the data is read from the shared memory.

[0086] In this embodiment, Figure 6 As shown, when the corresponding cache is not found, the data is read directly from the shared memory.

[0087] In this embodiment, the method further includes: S15: When the first target address is a graphics processor address, determine that the first target address is in a miss state in the central processing unit cluster.

[0088] In this embodiment, when the first target address is a graphics processor address, it means that the data to be read by the first data read request is stored in the cache corresponding to the graphics processor cluster, but not in the cache corresponding to the central processing unit cluster. In this case, it is directly determined that the first target address is in a miss state in the central processing unit cluster.

[0089] S16: Read the data corresponding to the first target address in the shared memory.

[0090] In this embodiment, at this time, the data read request is directly sent to the shared memory controller to read the data corresponding to the first target address from the shared memory.

[0091] For example, a CPU core sends a read data request, and first determines whether the address is in the CPU address domain or the GPU address domain. If the address is in the GPU address domain, the CPU core displays a cache miss, and reads data directly from the memory. If the CPU first-level private cache hits, the data is read directly from the first-level private cache. If the first-level private cache misses, the read data request is sent to the second-level private cache controller. If the second-level private cache hits, the data is read from the hit core. If both the first-level private cache and the second-level private cache miss, the read data request is sent to the first cluster shared cache. If the first cluster shared cache misses, the read data request is sent to the shared memory controller to read data directly from the shared memory.

[0092] In another embodiment of the present application, the method further includes: S21: upon receiving a second data read request sent by any graphics processor core in a graphics processor cluster, determining a second target address corresponding to the second data read request.

[0093] In this embodiment, the second data read request is a data read request sent by the graphics processor core, and the second target address is a data storage address included in the data read request sent by the graphics processor core.

[0094] In this embodiment, reference Figure 7 , Figure 7 is a flowchart of the graphics processor core data reading proposed in an embodiment of the present application, such as Figure 7 As shown, when a second data read request sent by any graphics processor core in the graphics processor cluster is received, a second target address corresponding to the second data read request is determined.

[0095] S22: According to the second target address, query corresponding caches in the graphics processor cluster level by level.

[0096] In this embodiment, according to the second target address, the corresponding cache is queried level by level in the graphics processor cluster, and the specific steps include: S22-1: Determine whether the second target address hits in a private cache in each graphics processor core in the graphics processor cluster.

[0097] In this embodiment, it is determined whether the second target address is hit in the private cache of each graphics processor core in the graphics processor cluster, that is, whether the second target address is found in the private cache.

[0098] S22-2: When the second target address hits the private cache, determine that the private cache is the cache corresponding to the second target address.

[0099] In this embodiment, when the second target address hits, that is, when the second target address is found in the private cache, it means that the data to be read by the second data read request is stored in the private cache of the graphics processor, and the private cache is determined to be the cache corresponding to the second target address.

[0100] S22 - 3 : If the second target address does not hit in the private cache, determine whether the second target address hits in the second cluster shared cache.

[0101] In this embodiment, when the second target address is not hit, that is, when the second target address is not found in the private cache, it means that the data required to be read by the second data read request is not stored in the private cache of the graphics processor. At this time, it is necessary to determine whether the second target address is hit in the second cluster shared cache.

[0102] S22 - 4 : When the second target address hits in the second cluster shared cache, determine that the second cluster shared cache is the cache corresponding to the second target address.

[0103] In this embodiment, when the second target address hits, that is, when the second target address is found in the second cluster shared cache, it means that the data to be read by the second data read request is stored in the second cluster shared cache, and the second cluster shared cache is determined to be the cache corresponding to the second target address.

[0104] S23: When the corresponding cache is found, data corresponding to the second data read request is read from the cache.

[0105] In this embodiment, when the cache corresponding to the second target address is found, the data corresponding to the second data read request is read from the cache.

[0106] For example, a graphics processor core sends a read data request without determining the address domain. If the private cache (L1) does not hit, the data is read directly. If the private cache does not hit, the request is sent to the second cluster shared cache controller. If the second cluster shared cache hits, the data is directly replied. If both the private cache and the second cluster shared cache do not hit, the request is directly sent to the shared memory to read the data from the memory.

[0107] In another embodiment of the present application, the method further includes: S31: upon receiving a first data write request sent by the central processing unit core, determining a third target address corresponding to the first data write request.

[0108] In this embodiment, the first data write request is a data write request sent by the central processing unit core, and the third target address is an address in the storage where data needs to be written and included in the data write request sent by the central processing unit core.

[0109] In this embodiment, reference Figure 8 , Figure 8 This is a flow chart of a CPU writing data according to an embodiment of the present application. Figure 8 As shown, when a first data write request sent by a central processing unit core is received, a third target address corresponding to the first data write request is determined.

[0110] S32: When the third target address is a CPU address, determine whether the third target address is hit in a first-level private cache of a CPU core of the CPU cluster.

[0111] In this embodiment, Figure 8 As shown, in the case where the third target address is a CPU address, it is determined whether the third target address hits in the first-level private cache of the CPU core in the CPU cluster.

[0112] S33: When the third target address hits the first-level private cache, determine whether the cache line state of the first-level private cache is an exclusive state.

[0113] In this embodiment, Figure 8 As shown, when the third target address hits, that is, when the third target address exists in the first-level private cache, it is determined whether the operating state of the first-level private cache is an exclusive state.

[0114] S34: When the cache line state is not the exclusive state, change the cache line state to the exclusive state.

[0115] In this embodiment, Figure 8 As shown, when the cache line state is not exclusive, in order to ensure cache consistency, the cache line state is changed to exclusive. At this time, the first private cache obtains the exclusive state from the processor. Upon receiving the request, the processor modifies the corresponding cache lines in the remaining cores to an invalid state.

[0116] S35: When the cache line state is the exclusive state, write the data corresponding to the first data write request into the first-level private cache.

[0117] In this embodiment, when the cache line state is the exclusive state, the data corresponding to the first data write request is written into the first-level private cache.

[0118] In this embodiment, the method further includes: S36: When the third target address is not hit, performing cache replacement, including: The cache line data which has not been accessed for the longest time in the first-level private cache is stored in the second-level private cache.

[0119] In this embodiment, when the third target address is not hit, that is, when the third target address is not found in the first-level private cache, cache replacement is performed. When performing cache replacement, the cache line data that has not been accessed for the longest time in the first-level private cache is stored in the second-level private cache.

[0120] In this embodiment, a counter is set in each cache. Each time there is a data read request, the number corresponding to each cache line is increased by one. When the data read request reads a row of data, the number corresponding to the cache line is cleared. When the cache space needs to be released, the cache line data with the largest corresponding number is determined as the cache line data that has not been accessed for the longest time, and the data is sent to the next level of cache for storage until it is sent to the shared memory.

[0121] S37: Write the data corresponding to the first data write request into the first-level private cache.

[0122] In this embodiment, after the cache line data that has not been accessed for the longest time is sent to the second-level private cache, the data corresponding to the first data write request is written into the first-level private cache.

[0123] In this embodiment, the method further includes: S38: When the third target address is a graphics processor address, determine whether the third target address hits in the second cluster shared cache.

[0124] In this embodiment, Figure 8 As shown, when the third target address is a graphics processor address, it is determined whether the third target address is hit in the second cluster shared cache, that is, whether the third target address exists in the second shared cluster.

[0125] S39: When the third target address is hit, write the data corresponding to the first data write request into the second cluster shared cache.

[0126] In this embodiment, when the third target address hits, that is, when the third target address exists in the second cluster shared cache, the data corresponding to the first data write request is written into the second cluster shared cache.

[0127] In this embodiment, the method further includes: S310: When the third target address is not hit, cache replacement is performed, including: The cache line data which has not been accessed for the longest time in the shared cache of the second cluster is stored in the shared memory.

[0128] In this embodiment, when the third target address misses, that is, when the third target address does not exist in the second cluster shared cache, cache replacement is performed to store the cache line data in the second cluster shared cache that has not been accessed for the longest time in the shared memory.

[0129] S311: Write the data corresponding to the first data write request into the second cluster shared cache.

[0130] In this embodiment, after cache replacement is performed, the data corresponding to the first data write request is written into the second cluster shared cache.

[0131] In another embodiment of the present application, the method further includes: S41: upon receiving a second data write request sent by any graphics processor core in a graphics processor cluster, determining a fourth target address corresponding to the second data write request.

[0132] In this embodiment, the second data write request is a data write request sent by the graphics processor core, and the fourth target address is an address in the storage where data needs to be written and included in the data write request sent by the graphics processor core.

[0133] S42: Determine whether the fourth target address hits in the private cache of the graphics processor core.

[0134] In this embodiment, reference Fig. 9 , Fig. 9 is a flowchart of a graphics processor writing data according to an embodiment of the present application. Fig. 9 As shown, it is determined whether the fourth target address is hit in the private cache of the graphics processor core, that is, whether the fourth target address is in the private cache of the graphics processor core.

[0135] S43: When the fourth target address hits the private cache, determine whether the cache line state of the private cache is an exclusive state.

[0136] In this embodiment, when the fourth target address hits, it is determined whether the cache line state of the private cache is an exclusive state.

[0137] S44: When the cache line state is not the exclusive state, change the cache line state of the private cache to the exclusive state.

[0138] In this embodiment, when the cache line state is not an exclusive state, the cache line state of the private cache is changed to an exclusive state.

[0139] S45: When the cache line state is the exclusive state, write the data corresponding to the second data write request into the private cache.

[0140] In this embodiment, when the cache line state is an exclusive state, the data corresponding to the second data write request is written into the private cache.

[0141] In this embodiment, the method further includes: S46: When the fourth target address is not hit, performing cache replacement, including: Storing cache line data in the private cache that has not been accessed for the longest time in the second cluster shared cache.

[0142] In this embodiment, when the fourth target address misses, that is, the fourth target address does not exist in the private cache, cache replacement is performed. When performing cache replacement, the cache line data in the private cache that has not been accessed for the longest time is stored in the second cluster shared cache.

[0143] S47: Write the data corresponding to the second data write request into the private cache.

[0144] In this embodiment, after the cache replacement is completed, the data corresponding to the second data write request is written into the private cache.

[0145] In another embodiment of the present application, the architecture of the data processing system can be changed as needed, such as expanding the number of processor cores in the CPU cluster and the GPU cluster, and expanding multi-level caches in each CPU core and GPU core to ensure the data access speed of the processor core, thereby improving the operating efficiency of the system.

[0146] In the above embodiments of the present application, a data processing system is designed, namely a heterogeneous multi-core processor architecture, which follows a cache consistency mechanism, and the central processing unit core can directly store data in the shared cache of the graphics processing unit cluster, which greatly improves the speed at which the graphics processing unit core reads data, thereby improving the operating efficiency of the system.

[0147] Based on the same inventive concept, an embodiment of the present application provides a data processing device. Fig.10 , Fig.10 FIG. 1 is a schematic diagram of a data processing device 1000 proposed in an embodiment of the present application. Fig.10 As shown, the device comprises: A first target address determination module 1001 is configured to determine a first target address corresponding to a first data read request when receiving a first data read request sent by any CPU core in a CPU cluster; A first cache query module 1002 is used to query the corresponding cache in the CPU cluster level by level according to the first target address when the first target address is a CPU address; The first data reading module 1003 is used to read the data corresponding to the first data reading request from the cache when the corresponding cache is found.

[0148] Optionally, the device further comprises: The second data reading module is used to read the data from the shared memory when the corresponding cache is not found.

[0149] Optionally, the device further comprises: a first miss state determination module, configured to determine, when the first target address is a graphics processor address, that the first target address is in a miss state in the central processing unit cluster; The third data reading module is used to read the data corresponding to the first target address in the shared memory.

[0150] Optionally, the first cache query module includes: A first hit status determination submodule, configured to determine whether the first target address is hit in a first-level private cache in each CPU core in the CPU cluster; A first cache determination submodule, configured to determine, when the first target address hits in the first-level private cache, that the first-level private cache is the cache corresponding to the first target address; a second hit status determination submodule, configured to determine whether the first target address hits in a second-level private cache in the CPU core if the first target address does not hit in the first-level private cache; A second cache determination submodule, configured to determine, when the first target address hits in the second-level private cache, that the second-level private cache is the cache corresponding to the first target address; a third hit status determination submodule, configured to determine whether the first target address hits in the first cluster shared cache when the first target address does not hit in the second-level private cache; The third cache determination submodule is configured to determine, when the first target address hits in the first cluster shared cache, that the first cluster shared cache is the cache corresponding to the first target address.

[0151] Optionally, the device further comprises: A second target address determination module, configured to determine a second target address corresponding to a second data read request when receiving a second data read request sent by any graphics processor core in the graphics processor cluster; A second cache query module, configured to query corresponding caches level by level in the graphics processor cluster according to the second target address; The fourth data reading module is used to read the data corresponding to the second data reading request from the cache when the corresponding cache is queried.

[0152] Optionally, the device further comprises: The fifth data reading module is used to read the data from the shared memory when the corresponding cache is not found.

[0153] Optionally, the second cache query module includes: a fourth hit status determination submodule, configured to determine whether the second target address is hit in a private cache in each graphics processor core in the graphics processor cluster; a fourth cache determination submodule, configured to determine, when the second target address hits the private cache, that the private cache is the cache corresponding to the second target address; a fifth hit status determination submodule, configured to determine whether the second target address hits in a second cluster shared cache when the second target address does not hit in the private cache; The fifth cache determination submodule is configured to determine, when the second target address hits in the second cluster shared cache, that the second cluster shared cache is the cache corresponding to the second target address.

[0154] Optionally, the device further comprises: A third address determination module, configured to determine a third target address corresponding to a first data write request when receiving the first data write request sent by the central processing unit core; a first hit status determination module, configured to determine whether the third target address is hit in a first-level private cache of a CPU core of the CPU cluster when the third target address is a CPU address; A first cache line state determination module, configured to determine whether the cache line state of the first-level private cache is an exclusive state when the third target address hits the first-level private cache; A first state changing module, configured to change the cache line state to the exclusive state when the cache line state is not the exclusive state; The first data writing module is used to write the data corresponding to the first data writing request into the first-level private cache when the cache line state is the exclusive state.

[0155] Optionally, the device further comprises: The first cache replacement module is used to perform cache replacement when the third target address is not hit, including: storing the cache line data which has not been accessed for the longest time in the first-level private cache into the second-level private cache; The second data writing module is used to write the data corresponding to the first data writing request into the first-level private cache.

[0156] Optionally, the device further comprises: A second hit status determination module, configured to determine whether the third target address is hit in the second cluster shared cache when the third target address is a graphics processor address; The third data writing module is used to write the data corresponding to the first data writing request into the second cluster shared cache when the third target address is hit.

[0157] Optionally, the device further comprises: The second cache replacement module is used to perform cache replacement when the third target address is not hit, including: storing cache line data in the second cluster shared cache that has not been accessed for the longest time into the shared memory; The fourth data writing module is used to write the data corresponding to the first data writing request into the second cluster shared cache.

[0158] Optionally, the device further comprises: a fourth target address determining module, configured to determine a fourth target address corresponding to a second data write request when receiving a second data write request sent by any graphics processor core in the graphics processor cluster; a third hit status determination module, configured to determine whether the fourth target address is hit in the private cache of the graphics processor core; A second cache line state determination module, configured to determine whether the cache line state of the private cache is an exclusive state when the fourth target address hits the private cache; A second state changing module, configured to change the cache line state of the private cache to the exclusive state when the cache line state is not the exclusive state; A fifth data writing module is used to write the data corresponding to the second data writing request into the private cache when the cache line state is the exclusive state.

[0159] Optionally, the device further comprises: The second cache replacement module is used to perform cache replacement when the fourth target address is not hit, including: storing the cache line data which has not been accessed for the longest time in the private cache into the second cluster shared cache; A sixth data writing module is used to write the data corresponding to the second data writing request into the private cache.

[0160] Based on the same inventive concept, another embodiment of the present application provides a product, including a computer program / instruction, which, when executed by a processor, implements the steps in the signal line design method described in any of the above embodiments of the present application.

[0161] Based on the same inventive concept, another embodiment of the present application provides a readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the data processing method described in any of the above embodiments of the present application.

[0162] Based on the same inventive concept, another embodiment of the present application provides an electronic device, Fig.11 It is a schematic diagram of an electronic device 1100 proposed in one embodiment of the present application, including a memory 1102, a processor 1101 and a computer program stored in the memory and executable on the processor, and the processor, when executed, implements the steps in the data processing method described in any of the above embodiments of the present application.

[0163] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0164] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0165] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0166] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0167] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0168] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0169] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0170] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0171] The data processing system, method, product, device and storage medium provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A data processing system, characterized in that: The data processing system comprises: A central processing unit cluster, comprising: a first central processing unit core, a second central processing unit core, a third central processing unit core, a fourth central processing unit core, and a first cluster shared cache; A graphics processor cluster, comprising: a first graphics processor core, a second graphics processor core, a third graphics processor core, a fourth graphics processor core, and a second cluster shared cache; A shared memory, used to store data that can be read by both the CPU cluster and the GPU cluster; Each CPU core in the CPU cluster is provided with a three-level cache, including: a first-level private cache, a second-level private cache, and the first cluster shared cache; Each graphics processor core in the graphics processor cluster is provided with a secondary cache, including: a private cache and a second cluster shared cache; When the address included in the received data write request is a graphics processor address, any one of the CPU cores in the CPU cluster writes the corresponding data into the second cluster shared cache, and the data is dirty data.

2. The data processing system according to claim 1, characterized in that When the storage space of the first-level private cache of each central processing unit core is insufficient, the cache line data that has not been accessed for the longest time in the first-level private cache is sent to the second-level private cache for storage; When the storage space of the second-level private cache is insufficient, the cache line data that has not been accessed for the longest time in the second-level private cache is sent to the first cluster shared cache for storage; When the storage space of the first cluster shared cache is insufficient, cache line data that has not been accessed for the longest time in the first cluster shared cache is sent to the shared memory for storage.

3. The data processing system according to claim 1, characterized in that: When the storage space of the private cache of each graphics processor core is insufficient, the cache line data that has not been accessed for the longest time in the private cache is sent to the second cluster shared cache for storage; When the storage space of the second cluster shared cache is insufficient, cache line data that has not been accessed for the longest time in the second cluster shared cache is sent to the shared memory for storage.

4. The data processing system according to claim 1, characterized in that: When each CPU core or GPU core writes data into the private cache, the cache state of the private cache is an exclusive state.

5. A data processing method, characterized in that: The method is based on any of the data processing systems according to claims 1-4, and includes: Upon receiving a first data read request sent by any central processing unit core in the central processing unit cluster, determining a first target address corresponding to the first data read request; In the case where the first target address is a CPU address, querying corresponding caches in the CPU cluster level by level according to the first target address; When the corresponding cache is found, the data corresponding to the first data read request is read from the cache.

6. The data processing method according to claim 5, characterized in that: The method further comprises: In the case where the first target address is a graphics processor address, determining that the first target address is in a miss state in the central processing unit cluster; The data corresponding to the first target address is read in the shared memory.

7. The data processing method according to claim 5, characterized in that: The step of querying corresponding caches in the CPU cluster level by level according to the first target address includes: Determining whether the first target address hits in a first-level private cache in each CPU core in the CPU cluster; When the first target address hits in the first-level private cache, determining that the first-level private cache is the cache corresponding to the first target address; In the case where the first target address does not hit in the first-level private cache, determining whether the first target address hits in the second-level private cache in the central processing unit core; When the first target address hits in the second-level private cache, determining that the second-level private cache is the cache corresponding to the first target address; If the first target address does not hit in the second-level private cache, determining whether the first target address hits in the first cluster shared cache; When the first target address hits in the first cluster shared cache, the first cluster shared cache is determined to be the cache corresponding to the first target address.

8. The data processing method according to claim 5, characterized in that: The method further comprises: Upon receiving a second data read request sent by any graphics processor core in the graphics processor cluster, determining a second target address corresponding to the second data read request; According to the second target address, querying corresponding caches in the graphics processor cluster level by level; When the corresponding cache is found, data corresponding to the second data read request is read from the cache.

9. The data processing method according to claim 5 or claim 8, characterized in that: The method further comprises: When the corresponding cache is not found, the data is read from the shared memory.

10. The data processing method according to claim 8, characterized in that: The step of querying the corresponding cache in the graphics processor cluster level by level according to the second target address includes: Determining whether the second target address hits in a private cache in each graphics processor core in the graphics processor cluster; When the second target address hits the private cache, determining that the private cache is the cache corresponding to the second target address; If the second target address does not hit in the private cache, determining whether the second target address hits in the second cluster shared cache; When the second target address hits in the second cluster shared cache, the second cluster shared cache is determined to be the cache corresponding to the second target address.

11. The data processing method according to claim 5, characterized in that: The method further comprises: Upon receiving a first data write request sent by the central processing unit core, determining a third target address corresponding to the first data write request; In the case where the third target address is a CPU address, determining whether the third target address is hit in a first-level private cache of a CPU core of the CPU cluster; When the third target address hits the first-level private cache, determining whether the cache line state of the first-level private cache is an exclusive state; When the cache line state is not the exclusive state, changing the cache line state to the exclusive state; When the cache line state is the exclusive state, the data corresponding to the first data write request is written into the first-level private cache.

12. The data processing method according to claim 11, characterized in that: The method further comprises: In case the third target address misses, performing cache replacement includes: storing the cache line data which has not been accessed for the longest time in the first-level private cache into the second-level private cache; The data corresponding to the first data write request is written into the first-level private cache.

13. The data processing method according to claim 11, characterized in that: The method further comprises: In the case where the third target address is a graphics processor address, determining in the second cluster shared cache whether the third target address is hit; When the third target address hits, the data corresponding to the first data write request is written into the second cluster shared cache.

14. The data processing method according to claim 13, characterized in that: The method further comprises: In case the third target address misses, performing cache replacement includes: storing cache line data in the second cluster shared cache that has not been accessed for the longest time into the shared memory; The data corresponding to the first data write request is written into the second cluster shared cache.

15. The data processing method according to claim 5, characterized in that: The method further comprises: When receiving a second data write request sent by any graphics processor core in the graphics processor cluster, determining a fourth target address corresponding to the second data write request; Determining whether the fourth target address is hit in the private cache of the graphics processor core; When the fourth target address hits the private cache, determining whether a cache line state of the private cache is an exclusive state; When the cache line state is not the exclusive state, changing the cache line state of the private cache to the exclusive state; When the cache line state is the exclusive state, the data corresponding to the second data write request is written into the private cache.

16. The data processing method according to claim 15, characterized in that: The method further comprises: In case the fourth target address is not hit, performing cache replacement includes: storing the cache line data which has not been accessed for the longest time in the private cache into the second cluster shared cache; The data corresponding to the second data write request is written into the private cache.

17. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps in the method according to any one of claims 5 to 16 are implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the method according to any one of claims 5 to 16 are implemented.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 5 to 16 are implemented.

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