Control circuit, method and device for memory in chip and storage medium

Abstract

The invention discloses a control circuit, method and device for a memory in a chip and a storage medium. The circuit comprises a first control pin which is integrated in a microcontroller MCU chip and is used for receiving a voltage signal of the first control pin; the power supply module is connected with the MCU chip and the reset circuit and is used for determining the power supply state of a memory in the MCU chip based on the voltage signal; and the reset circuit is connected with the MCU chip and is used for determining that the memory executes reset operation based on the power supply state. According to the invention, the technical problem of low reset efficiency of the memory in the chip is solved.

Description

Technical Field

[0001] The present invention relates to the field of chip control technology, and in particular to a control circuit, method, device and storage medium for a memory in a chip. Background Art

[0002] At present, in the process of resetting a microcontroller unit chip (MCU chip for short), it is often achieved by connecting the reset port of the integrated flash memory (FLASH) inside the MCU chip to the system reset. When the MCU chip is soft reset, the internal digital circuit and the FLASH device will be reset, and the FLASH device will be reinitialized through the reset and initialization sequence. However, the de-reset time of the FLASH device itself is relatively long, so the soft reset needs to wait for the FLASH device to complete the de-reset, so the startup time of the MCU chip becomes longer, which reduces the response speed and efficiency of the system, resulting in a technical problem of low reset efficiency of the memory in the chip.

[0003] With respect to the technical problem of low reset efficiency of the memory in the above chip, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present invention provide a control circuit, method, device and storage medium of a memory in a chip, so as to at least solve the technical problem of low reset efficiency of the memory in the chip.

[0005] According to one aspect of the embodiment of the invention, a control circuit of a memory in a chip is provided. The circuit may include: a first control pin, integrated in a microcontroller MCU chip, for receiving a voltage signal of the first control pin; a power module, connected to the MCU chip and a reset circuit, for determining the power supply state of the memory in the MCU chip based on the voltage signal; a reset circuit, connected to the MCU chip, for determining that the memory performs a reset operation based on the power supply state.

[0006] Optionally, the reset circuit includes: a first resistor, one end of which is connected to the first control pin and the other end is connected to the first transistor; a second resistor, one end of which is connected to the first transistor and the other end is grounded; and a first transistor, one end of which is connected to a third resistor and is used to control the switching state of the reset circuit.

[0007] Optionally, the reset circuit includes: a third resistor, one end of which is connected to the first transistor, and the other end of which is connected to the second transistor and the fourth resistor; a fourth resistor, one end of which is connected to the power supply module, and the other end of which is connected to the third resistor; a second transistor, one end of which is connected to the second control pin, for controlling the switching state of the reset circuit.

[0008] Optionally, the reset circuit includes: a second control pin, one end of which is respectively connected to the second transistor and the fifth resistor, and the other end is connected to the memory, for controlling the power supply of the memory; a fifth resistor, one end of which is connected to the third transistor and connected in parallel with the sixth resistor, for forming a current limiting resistor; a third transistor, one end of which is connected to the seventh resistor, and the other end is connected between the second resistor and the first transistor; and a seventh resistor, one end of which is connected between the first transistor and the third resistor.

[0009] According to one aspect of an embodiment of the present invention, a method for controlling a memory in a chip is provided, the method comprising: acquiring a voltage signal received by a first control pin; controlling a power supply module based on the voltage signal to obtain a power supply status of the memory in a microcontroller MCU chip; and controlling a reset circuit based on the power supply status to perform a reset operation on the memory.

[0010] Optionally, the power supply module is controlled based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip, including: based on the voltage signal, in the reset circuit, respectively determining the first control state of the first transistor, the second control state of the second transistor, and the third control state of the third transistor; based on the first control state, the second control state and the third control state, determining the power supply state of the memory.

[0011] Optionally, based on the first control state, the second control state and the third control state, determining the power state of the memory includes: in response to the first control state being the on state, the second control state being the on state and the third control state being the off state, determining the power state to be the powered state.

[0012] Optionally, based on the first control state, the second control state and the third control state, the power supply state of the memory is determined, and the method also includes: in response to the first control state being an off-state, the second control state being an off-state and the third control state being an on-state, determining that the power supply state is a non-powered state; based on the non-powered state, controlling the memory to perform a discharge operation.

[0013] According to one aspect of an embodiment of the present invention, a control device for a memory in a chip is provided. The device may include: a first acquisition unit, used to acquire a voltage signal received by a first control pin; a first control unit, used to control a power module based on the voltage signal to obtain a power supply state of the memory in a microcontroller MCU chip; and a second control unit, used to control a reset circuit based on the power supply state to perform a reset operation on the memory.

[0014] According to another aspect of an embodiment of the present invention, there is further provided an electronic device, comprising: a memory storing an executable program; and a processor for running the program, wherein the method in each embodiment of the present invention is executed when the program is running.

[0015] According to another aspect of an embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium includes a stored executable program, wherein when the executable program is running, the device where the computer-readable storage medium is located is controlled to execute the methods in various embodiments of the present invention.

[0016] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the method in each embodiment of the present invention is implemented.

[0017] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present invention is implemented.

[0018] According to another aspect of the embodiments of the present invention, a computer program is further provided. When the computer program is executed by a processor, the methods in the embodiments of the present invention are implemented.

[0019] According to another aspect of an embodiment of the present invention, a vehicle is further provided. When the vehicle is executed, the method in each embodiment of the present invention is implemented.

[0020] In an embodiment of the present invention, a first control pin is integrated in a microcontroller MCU chip and is used to receive a voltage signal from the first control pin; a power module is connected to the MCU chip and a reset circuit and is used to determine the power supply status of the memory in the MCU chip based on the voltage signal; a reset circuit is connected to the MCU chip and is used to determine that the memory performs a reset operation based on the power supply status. That is to say, the control circuit of the memory in the chip of the embodiment of the present invention includes: a first control pin, a power module and a reset circuit, wherein the first control pin is integrated in the microcontroller MCU chip and is used to receive a voltage signal from the first control pin; the power module can be connected to the MCU chip and the reset circuit and is used to determine the power supply status of the memory in the MCU chip based on the voltage signal obtained above; the reset circuit can be connected to the MCU chip and is used to determine that the memory performs a reset operation based on the power supply status of the memory, thereby solving the technical problem of low reset efficiency of the memory in the chip and achieving the technical effect of improving the reset efficiency of the memory in the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0022] Figure 1is a schematic diagram of a control circuit of a memory in a chip according to an embodiment of the present invention;

[0023] Figure 2 is a schematic diagram of a reset circuit according to an embodiment of the present invention;

[0024] Figure 3 is a flow chart of a method for controlling a memory in a chip according to an embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of performing a reset operation on FLASH according to an embodiment of the present invention;

[0026] Figure 5 is a schematic diagram of performing power-off and fast-discharging operations on FLASH according to an embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of a detection voltage of a memory according to an embodiment of the present invention;

[0028] Figure 7 is a schematic diagram of a detection voltage of another memory according to an embodiment of the present invention;

[0029] Figure 8 is a schematic diagram of a control device for a memory in a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] According to an embodiment of the present invention, a control circuit for a memory in a chip is provided. It should be noted that in the flowchart of the accompanying drawings, the steps shown therein can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] The control circuit of the memory in the chip according to the embodiment of the present invention is introduced below.

[0034] Figure 1 is a schematic diagram of a control circuit of a memory in a chip according to an embodiment of the present invention, such as Figure 1 As shown, the control circuit includes: a first control pin 101 , a power module 102 and a reset circuit 103 .

[0035] A first control pin 101 is integrated in a microcontroller MCU chip 104 and is used to receive a voltage signal of the first control pin;

[0036] A power module 102 is connected to the MCU chip and the reset circuit, and is used to determine the power supply state of the memory 105 in the MCU chip based on the voltage signal;

[0037] The reset circuit 103 is connected to the MCU chip 104 and is used to determine whether the memory performs a reset operation based on the power supply state;

[0038] In this embodiment, the microcontroller MCU chip can also be called a microcontroller unit chip, and the first control pin can be represented by CTL, which is a common pin inside the MCU chip, such as an input / output pin (General Purpose Input / Output, referred to as GPIO pin). The memory in the MCU chip can be represented by FLASH.

[0039] In an embodiment of the present invention, the reset circuit includes: a first resistor, one end of which is connected to the first control pin and the other end is connected to the first transistor; a second resistor, one end of which is connected to the first transistor and the other end is grounded; and a first transistor, one end of which is connected to the third resistor and is used to control the switching state of the reset circuit.

[0040] Optionally, the first resistor can be represented by R7. The first transistor can be a triode, which can be represented by Q3. The second resistor can be represented by R4, which is a pull-down resistor that gives the control pin CTL an initial low level to ensure that it is in a safe state when powered on. The third resistor can be represented by R6.

[0041] In an embodiment of the present invention, the reset circuit includes: a third resistor, one end of which is connected to the first transistor, and the other end of which is connected to the second transistor and the fourth resistor; a fourth resistor, one end of which is connected to the power supply module, and the other end of which is connected to the third resistor; a second transistor, one end of which is connected to the second control pin, for controlling the switching state of the reset circuit.

[0042] Optionally, the second transistor may be a P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOS), which may be represented by Q1. The fourth resistor may be represented by R3.

[0043] In an embodiment of the present invention, the reset circuit includes: a second control pin, one end of which is respectively connected to the second transistor and the fifth resistor, and the other end is connected to the memory, for controlling the power supply of the memory; a fifth resistor, one end of which is connected to the third transistor and connected in parallel with the sixth resistor, for forming a current limiting resistor; a third transistor, one end of which is connected to the seventh resistor, and the other end is connected between the second resistor and the first transistor; and a seventh resistor, one end of which is connected between the first transistor and the third resistor.

[0044] Optionally, the fifth resistor may be represented by R2. The third transistor may be an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS), which may be represented by Q2. The sixth resistor may be represented by R5. The seventh resistor may be represented by R1.

[0045] In an embodiment of the present invention, Figure 2 is a schematic diagram of a reset circuit according to an embodiment of the present invention, such as Figure 2 As shown, one end of the PMOS tube Q1 can be connected to the power supply voltage (VCC), the other end is connected to the resistor R3 and the resistor R6, and the other end is connected to the power supply control pin VCC_FLASH of the memory FLASH. Resistor R6 can be connected to the transistor Q3, the transistor Q3 can be connected to the resistor R7 and the resistor R4, and the other end of the resistor R4 is grounded (GND1). Resistor R7 is connected to the control pin CTL in the MCU chip. The power supply control pin VCC_FLASH can be connected to the resistor R2, and the resistor R5 is connected in parallel with the resistor R2 to form a current limiting resistor. Resistor R2 can be connected to the NMOS tube Q2, the NMOS tube Q2 is connected to the resistor R1, and the resistor R1 is connected between the resistor R6 and the transistor Q3.

[0046] Optionally, the power supply voltage VCC is 3.3 volts (V). The resistance values ​​of R1 and R7 are both 1 kilo ohm (1KΩ), referred to as 1K. The resistance values ​​of R2, R5 and R6 are all 120 ohms (Ω). The resistance value of R3 is 47K. The control pin CTL can be a FLASH control pin.

[0047] Optionally, R2 and R5 are used as current limiting resistors. The resistance value should not be too small to avoid damaging the Metal-Oxide-Semiconductor Field-Effect Transistor (MOS tube). Here, two 120Ω resistors with a maximum power of 0.1 watt (w) are selected in parallel (the actual power P in the circuit can be determined by the voltage U and the resistance R in the circuit, that is, ), increase the power capacity of the circuit, discharge current, and make the current distribution balanced. In order to meet the purpose of rapid discharge, the resistance value should not be too small. At the same time, the package specification of the resistor is the target package specification (ie 0402), which saves board space.

[0048] Figure 3 is a flow chart of a method for controlling a memory in a chip according to an embodiment of the present invention. Figure 3 As shown, the method may include the following steps:

[0049] Step S301, obtaining a voltage signal received by a first control pin.

[0050] In the technical solution provided in step S301 of the present invention, a voltage signal received by the first control pin can be obtained. The voltage signal can be a high-level voltage signal, referred to as a high level, or a low-level voltage signal, referred to as a low level. The first control pin can be called a FLASH control pin, or a control pin CTL.

[0051] For example, a high level voltage signal received by the control pin CTL is obtained, or a low level voltage signal received by the control pin CTL is obtained. This is only an example, and the process and method of obtaining the voltage signal received by the first control pin are not specifically limited.

[0052] Step S302, controlling the power module based on the voltage signal to obtain the power supply status of the memory in the microcontroller MCU chip.

[0053] In the technical solution provided in the above step S302 of the present invention, after obtaining the voltage signal, the power module can be controlled according to the voltage signal to achieve the purpose of obtaining the power supply state of the memory in the microcontroller MCU chip. The power supply state of the memory can be a powered state or a non-powered state. The power module is used to provide electrical energy to various devices in the circuit.

[0054] For example, after obtaining a voltage signal at a high level, the power module can be controlled to obtain a power supply state of the memory in the microcontroller MCU chip as a powered state, indicating that the memory is powered at this time, and the next step of processing can be performed.

[0055] It should be noted that this is only a preferred implementation method for obtaining the power supply status of the memory in the microcontroller MCU chip, and the process and method for obtaining the power supply status of the memory in the microcontroller MCU chip are not specifically limited. As long as the power module is controlled according to the voltage signal, the process and method for obtaining the power supply status of the memory in the microcontroller MCU chip are within the protection scope of the present invention and are not listed here.

[0056] Step S303: Control the reset circuit based on the power supply state to perform a reset operation on the memory.

[0057] In the technical solution provided in the above step S303 of the present invention, after the power supply state of the memory is obtained, the reset circuit can be controlled according to the power supply state so as to implement a reset operation on the memory.

[0058] For example, when the power supply state of the memory is obtained as the powered state, the reset circuit can be controlled to perform a reset operation on the memory, so that the FLASH can be reset after the power supply of the FLASH is controlled.

[0059] In the above steps S301 to S303 of the present invention, the voltage signal received by the first control pin is obtained; the power supply module is controlled based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip; the reset circuit is controlled based on the power supply state to perform a reset operation on the memory. That is to say, the embodiment of the present invention can first obtain the voltage signal received by the first control pin, and then according to the voltage signal obtained above, the power supply module can be controlled to obtain the power supply state of the memory in the microcontroller MCU chip, and finally the reset circuit can be controlled according to the power supply state to perform a reset operation on the memory. Considering that the voltage module can be controlled according to the voltage signal received by the first control pin, so as to obtain the power supply state of the memory in the MCU chip, and then the reset circuit is controlled to perform a reset operation on the memory, the technical problem of low reset efficiency of the memory in the chip is solved, and the technical effect of improving the reset efficiency of the memory in the chip is achieved.

[0060] The above method of this embodiment is further introduced below.

[0061] As an optional implementation method, step S302 controls the power supply module based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip, including: based on the voltage signal, in the reset circuit, respectively determining the first control state of the first transistor, the second control state of the second transistor, and the third control state of the third transistor; based on the first control state, the second control state and the third control state, determining the power supply state of the memory.

[0062] In this embodiment, according to the obtained voltage signal, in the reset circuit, the first control state of the first transistor, the second control state of the second transistor and the third control state of the third transistor can be determined respectively, and then according to the first control state, second control state and third control state obtained above, the purpose of determining the power supply state of the memory is achieved.

[0063] Optionally, the first transistor may be a triode, which is used to control the on-off of current in the circuit to realize the processing of digital signals. The second transistor may be a PMOS tube, which is used to control the flow of current between the source and the drain based on the control gate voltage, thereby realizing the switch function. The third transistor may be an NMOS tube, which is used to control the on-off of current, amplify signals and realize various digital logic functions.

[0064] Optionally, the first control state may be an on state or an off state. The second control state may be an on state or an off state. The third control state may be an on state or an off state. Here, only the control states corresponding to the three transistors are exemplified, and the control states corresponding to the three transistors are not specifically limited.

[0065] As an optional implementation method, the power supply state of the memory is determined based on the first control state, the second control state and the third control state, including: in response to the first control state being the on state, the second control state being the on state and the third control state being the off state, determining that the power supply state is the powered state.

[0066] In this embodiment, after obtaining the first control state, the second control state and the third control state, if the first control state at this time is the on state, the second control state is the on state, and the third control state is the off state, it can be determined that the power supply state of the memory at this time is the powered state.

[0067] Optionally, after determining that the power supply state of the memory is the powered state, the voltage value of the memory may be monitored, and in response to the voltage value being equal to a voltage threshold, the reset state of the memory is obtained as the successfully reset state. The voltage threshold may be a preset voltage value, such as 3.3V.

[0068] Optionally, after responding to the voltage signal being a high level voltage signal, if the first control state is an on state, the second control state is an on state, and the third control state is an off state, it can be determined that the power supply state of the memory at this time is a powered state.

[0069] For example, Figure 4 is a schematic diagram of performing a reset operation on FLASH according to an embodiment of the present invention, such as Figure 4 As shown, when the FLASH control pin (i.e., CTL) is at a high level, the base (pole b) and emitter (pole e) of the transistor Q3 are turned on, and the current flows from the collector (pole c) to e. At this time, the voltage at point A is higher than the voltage at point B, the PMOS tube Q1 is turned on, and the NMOS tube Q2 is turned off, and the current flows from A to D, thereby powering the FLASH and performing a reset operation on the FLASH to achieve the reset of the FLASH.

[0070] As an optional implementation manner, the power supply state of the memory is determined based on the first control state, the second control state and the third control state. The method also includes: in response to the first control state being an off state, the second control state being an off state and the third control state being an on state, determining that the power supply state is a non-powered state; based on the non-powered state, controlling the memory to perform a discharge operation.

[0071] In this embodiment, after obtaining the first control state, the second control state and the third control state, if the first control state at this time is the off state, the second control state is the off state and the third control state is the on state, it can be determined that the power supply state of the memory is the unpowered state, and then according to the power supply state at this time, the memory can be controlled to perform a discharge operation.

[0072] Optionally, after responding to the voltage signal being a low-level voltage signal, if the first control state is the off state, the second control state is the off state and the third control state is the on state, then the power supply state of the memory is determined to be an unpowered state, and the memory can be controlled to perform power-off and rapid discharge operations.

[0073] For example, Figure 5 is a schematic diagram of performing power-off and fast discharge operations on FLASH according to an embodiment of the present invention, such as Figure 5 As shown, when the FLASH control pin is at a low level, the transistor Q3 and the PMOS tube Q1 are both cut off. At this time, the voltage at point A is higher than the voltage at point C, the NMOS tube Q2 is turned on, and the current flows from D to C to ground through the resistors R2 and R5, thereby realizing the power-off and rapid discharge of the FLASH.

[0074] In this embodiment, the voltage signal received by the first control pin is obtained; the power supply module is controlled based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip; the reset circuit is controlled based on the power supply state to perform a reset operation on the memory. That is to say, the embodiment of the present invention can first obtain the voltage signal received by the first control pin, and then control the power supply module according to the voltage signal obtained above, so as to obtain the power supply state of the memory in the microcontroller MCU chip, and finally control the reset circuit according to the power supply state to perform a reset operation on the memory. Considering that the voltage module can be controlled according to the voltage signal received by the first control pin, so as to obtain the power supply state of the memory in the MCU chip, and then control the reset circuit to perform a reset operation on the memory, the technical problem of low reset efficiency of the memory in the chip is solved, and the technical effect of improving the reset efficiency of the memory in the chip is achieved.

[0075] The technical solution of the embodiment of the present invention is illustrated below in conjunction with preferred implementation modes.

[0076] In the design process of embedded systems, the design of the flash memory (FLASH) reset circuit is an important link. Its main purpose is to ensure that the FLASH memory is in a stable state when the system is powered on or reset, thereby ensuring the stability of the system startup, data integrity and reliability. Through the design of a suitable reset circuit, it is possible to effectively prevent the FLASH memory from errors during power fluctuations or system reset, avoid data damage or loss, and improve the stability and reliability of the system.

[0077] At present, most technologies connect the integrated FLASH memory reset port to the system reset inside the MCU chip. When the MCU is soft reset, the internal digital circuit and FLASH device will be reset, and the FLASH device will be reinitialized through the reset and initialization sequence. However, the FLASH device itself has a long release time, so the soft reset needs to wait for the FLASH device to complete the release, resulting in a longer startup time for the MCU chip, thereby reducing the response speed and efficiency of the system, resulting in a technical problem of low reset efficiency of the memory in the chip.

[0078] In an achievable embodiment, an MCU external reset circuit is proposed, which includes a power module for powering on; an auxiliary power module for power supply; a mode switching module for power switching control; a voltage detection control module for triggering the operation of the power control module and voltage detection; a power control module for power transmission; a shaping trigger module for inverting and shaping the input signal, and performing logic processing on the processed signal and the signal output by the reset control module; a reset control module for providing a reset signal to the MCU module and controlling the operation of the power control module and the voltage detection control module; and a status detection module for resetting the display. The MCU external reset circuit of the present invention can adjust the power-on time of the power supply, and when the starting voltage is reached, the circuit is turned off to reduce the power consumption of the circuit. At the same time, the status detection module performs a reset status display to facilitate the judgment of whether the circuit is faulty. However, the above method still has the technical problem of low reset efficiency of the memory in the chip.

[0079] In another achievable embodiment, a power supply control circuit and a power supply control system are provided. The power supply control circuit is provided with a switch unit and a control module, so that when the voltage of the first input terminal of the control module is less than or equal to the voltage of the second input terminal of the control module, the output terminal of the control module outputs a low level, so that the switch unit is turned off to disconnect the connection between the mainboard and the battery, so that the battery can be powered off when the battery is not needed to power the mainboard, thereby improving the battery life, and further solving the problem that the battery is kept discharged to power the mainboard, resulting in a shorter battery life, and at the same time, the battery is charged more frequently, thereby shortening the battery life quickly. In addition, since the two input terminals of the control module are respectively input with the battery voltage and the mainboard voltage, no additional device is required to generate a signal, so as to reduce the cost of the power supply control circuit. However, the above method still has the technical problem of low reset efficiency of the memory in the chip.

[0080] Therefore, in order to solve the above problems, the present invention provides a FLASH control circuit of a chip, which adopts an external FLASH power supply reset circuit to separate the reset process from the MCU, which not only reduces the burden of the MCU, simplifies the system design, and reduces the system complexity. At the same time, it optimizes the reset process of the FLASH device, shortens the overall reset time of the system, thereby accelerating the startup speed of the system, improving the operating rate and response speed, and improving the system performance.

[0081] In the embodiment of the present invention, by independently controlling the reset and initialization timing of the FLASH device, the reset process of the FLASH device can be managed with high flexibility, and a customized optimization design can be performed according to system requirements. It has high flexibility and scalability, so that the system can maintain stability and efficiency under various working conditions, and is suitable for embedded system designs with different scenarios and requirements. This independent control feature provides greater space for system performance tuning and adaptability.

[0082] Optionally, the control circuit of the memory in the chip includes: a first control pin, a power supply module and a reset circuit, wherein the first control pin is integrated in the microcontroller MCU chip and is used to receive the voltage signal of the first control pin; the power supply module can be connected to the MCU chip and the reset circuit, and is used to determine the power supply status of the memory in the MCU chip based on the voltage signal obtained above; the reset circuit can be connected to the MCU chip, and is used to determine whether the memory performs a reset operation based on the power supply status of the memory, thereby solving the technical problem of low reset efficiency of the memory in the chip and achieving the technical effect of improving the reset efficiency of the memory in the chip.

[0083] In the embodiment of the present invention, as described above Figure 1 As shown, the control circuit of the memory in the chip includes: a first control pin 101, a power module 102 and a reset circuit 103. Among them, the first control pin 101 is integrated in the microcontroller MCU chip 104, and is used to receive the voltage signal of the first control pin. The power module 102 is connected to the MCU chip and the reset circuit, and is used to determine the power supply state of the memory 105 in the MCU chip based on the voltage signal. The reset circuit 103 is connected to the MCU chip 104, and is used to determine that the memory performs a reset operation based on the power supply state and the power supply state of the power supply pin in the MCU chip for controlling the FLASH power supply.

[0084] Optionally, CTL is a common GPIO pin inside the MCU chip, and the power supply of FLASH is controlled and the FLASH is reset through the different working states of the high and low levels of the pin and the reset circuit of the external MOS tube.

[0085] In the embodiment of the present invention, as described above Figure 2 As shown, one end of the PMOS tube Q1 can be connected to the power supply voltage (VCC), the other end is connected to the resistor R3 and the resistor R6, and the other end is connected to the power supply control pin VCC_FLASH of the memory FLASH. Resistor R6 can be connected to the transistor Q3, the transistor Q3 can be connected to the resistor R7 and the resistor R4, and the other end of the resistor R4 is grounded (GND1). Resistor R7 is connected to the control pin CTL in the MCU chip. The power supply control pin VCC_FLASH can be connected to the resistor R2, and the resistor R5 is connected in parallel with the resistor R2 to form a current limiting resistor. Resistor R2 can be connected to the NMOS tube Q2, the NMOS tube Q2 is connected to the resistor R1, and the resistor R1 is connected between the resistor R6 and the transistor Q3. Optionally, the power supply voltage VCC is 3.3V. The resistance values ​​of R1 and R7 are both 1 kiloohm. The resistance values ​​of R2, R5 and R6 are all 120 ohms. The resistance value of R3 is 47K.

[0086] Optionally, R2 and R5 are used as current limiting resistors. The resistance value should not be too small to avoid damaging the metal oxide semiconductor field effect tube. Here, two 120Ω resistors with a maximum power of 0.1 watt (w) are selected in parallel (the actual power P in the circuit can be determined by the voltage U and resistance R in the circuit, that is, ), increase the power capacity of the circuit, discharge current, and make the current distribution balanced. In order to meet the purpose of rapid discharge, the resistance value should not be too small. At the same time, the package specification of the resistor is the target package specification (ie 0402), which saves board space.

[0087] For example, as mentioned above Figure 4 As shown, when the FLASH control pin (i.e., CTL) is at a high level, the base and emitter of the transistor Q3 are turned on, and the current flows from the collector to e. At this time, the voltage at point A is higher than the voltage at point B, the PMOS tube Q1 is turned on, and the NMOS tube Q2 is turned off, and the current flows from A to D, thereby powering the FLASH and performing a reset operation on the FLASH to achieve the reset of the FLASH.

[0088] For example, as mentioned above Figure 5 As shown, when the FLASH control pin is at a low level, the transistor Q3 and the PMOS tube Q1 are both cut off. At this time, the voltage at point A is higher than the voltage at point C, the NMOS tube Q2 is turned on, and the current flows from D to C to ground through the resistors R2 and R5, thereby realizing the power-off and rapid discharge of the FLASH.

[0089] In an embodiment of the present invention, by controlling the voltage signal of the FLASH control pin (i.e., CTL), the control circuit of the memory in the chip is used to simulate the power supply condition of the memory in the chip. Different voltage signals can be controlled in the circuit to detect the voltage value of the memory, thereby achieving the purpose of simulating the power supply condition of the memory.

[0090] Optionally, Figure 6 is a schematic diagram of a detection voltage of a memory according to an embodiment of the present invention, such as Figure 6 As shown, when the FLASH control pin is at a high level, the memory detection voltage can be measured to be 3.299 V. As can be seen from the above, the standard operating voltage of the memory in the control circuit is 3.3 V, and the voltage of the memory detected at this time is 3.299 V, indicating that the memory is in normal working state and the voltage level is good.

[0091] Optionally, Figure 7 is a schematic diagram of a detection voltage of another memory according to an embodiment of the present invention, such as Figure 7 As shown in the figure, when the FLASH control pin is at a low level, the memory detection voltage is measured to be 119.356 nanovolts (nV), indicating that the charge in the memory has been completely released and the data in the memory has been cleared. This usually occurs when the memory needs to be erased or rewritten. Therefore, the extremely low voltage value monitored indicates that the memory is already in an idle state and new data writing operations can be performed.

[0092] In this embodiment, the voltage signal received by the first control pin is obtained; the power supply module is controlled based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip; the reset circuit is controlled based on the power supply state to perform a reset operation on the memory. That is to say, the embodiment of the present invention can first obtain the voltage signal received by the first control pin, and then control the power supply module according to the voltage signal obtained above, so as to obtain the power supply state of the memory in the microcontroller MCU chip, and finally control the reset circuit according to the power supply state to perform a reset operation on the memory. Considering that the voltage module can be controlled according to the voltage signal received by the first control pin, so as to obtain the power supply state of the memory in the MCU chip, and then control the reset circuit to perform a reset operation on the memory, the technical problem of low reset efficiency of the memory in the chip is solved, and the technical effect of improving the reset efficiency of the memory in the chip is achieved.

[0093] According to an embodiment of the present invention, a control device for a memory in a chip is provided. It should be noted that the control device for the memory in a chip can be used to execute a control method for a memory in a chip in an embodiment.

[0094] Figure 8 is a schematic diagram of a control device for a memory in a chip according to an embodiment of the present invention. Figure 8 As shown, a control device 800 for a memory in a chip may include: a first acquisition unit 801 , a first control unit 802 , and a second control unit 803 .

[0095] The first acquisition unit 801 is used to acquire a voltage signal received by a first control pin.

[0096] The first control unit 802 is used to control the power module based on the voltage signal to obtain the power supply status of the memory in the microcontroller MCU chip.

[0097] The second control unit 803 is used to control the reset circuit based on the power supply state to perform a reset operation on the memory.

[0098] Optionally, the first control unit 802 may include: a first determination module, used to determine, in the reset circuit, a first control state of the first transistor, a second control state of the second transistor, and a third control state of the third transistor based on a voltage signal; and a second determination module, used to determine a power supply state of the memory based on the first control state, the second control state, and the third control state.

[0099] Optionally, the second determining module may include: a determining submodule, configured to determine that the power supply state is the powered state in response to the first control state being the on state, the second control state being the on state and the third control state being the off state.

[0100] Optionally, the device also includes: a determination unit, used to determine that the power supply state is a non-power supply state in response to the first control state being a cut-off state, the second control state being a cut-off state and the third control state being a conduction state; a third control unit, used to control the memory to perform a discharge operation based on the non-power supply state.

[0101] In this embodiment, a voltage signal received by a first control pin is acquired by a first acquisition unit; a power supply module is controlled by a first control unit based on the voltage signal to obtain a power supply state of a memory in a microcontroller MCU chip; a reset circuit is controlled by a second control unit based on the power supply state to perform a reset operation on the memory, thereby solving the technical problem of low reset efficiency of the memory in the chip and achieving the technical effect of improving the reset efficiency of the memory in the chip.

[0102] According to an embodiment of the present invention, there is further provided an electronic device, comprising: a memory storing an executable program; and a processor for running the program, wherein the method in each embodiment of the present invention is executed when the program is running.

[0103] Optionally, the electronic device is also used to control the power module based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip, including: based on the voltage signal, in the reset circuit, respectively determining the first control state of the first transistor, the second control state of the second transistor and the third control state of the third transistor; based on the first control state, the second control state and the third control state, determining the power supply state of the memory.

[0104] Optionally, the electronic device is also used to determine the power supply state of the memory based on the first control state, the second control state and the third control state, including: in response to the first control state being the on state, the second control state being the on state and the third control state being the off state, determining that the power supply state is the powered state.

[0105] Optionally, the electronic device is also used to determine that the power supply state is a non-power supply state in response to the first control state being an off state, the second control state being an off state and the third control state being an on state; and to control the memory to perform a discharge operation based on the non-power supply state.

[0106] According to an embodiment of the present invention, a computer-readable storage medium is further provided. The computer-readable storage medium includes a stored executable program. When the executable program is running, the device where the computer-readable storage medium is located is controlled to execute the methods in various embodiments of the present invention.

[0107] Optionally, the storage medium is also used to control the power module based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip, including: based on the voltage signal, in the reset circuit, respectively determining the first control state of the first transistor, the second control state of the second transistor, and the third control state of the third transistor; based on the first control state, the second control state and the third control state, determining the power supply state of the memory.

[0108] Optionally, the storage medium is also used to determine the power supply state of the memory based on the first control state, the second control state and the third control state, including: in response to the first control state being the on state, the second control state being the on state and the third control state being the off state, determining that the power supply state is the powered state.

[0109] Optionally, the storage medium is also used to determine that the power supply state is a non-power supply state in response to the first control state being an off state, the second control state being an off state and the third control state being an on state; and to control the memory to perform a discharge operation based on the non-power supply state.

[0110] According to an embodiment of the present invention, a computer program product is also provided, including a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present invention is implemented.

[0111] According to an embodiment of the present invention, a computer program product is also provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present invention is implemented.

[0112] According to an embodiment of the present invention, a computer program is also provided. When the computer program is executed by a processor, the method in each embodiment of the present invention is implemented.

[0113] According to an embodiment of the present invention, a vehicle is also provided, which implements the method in each embodiment of the present invention when executed.

[0114] Optionally, the vehicle is also used to control the power module based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip, including: based on the voltage signal, in the reset circuit, respectively determining the first control state of the first transistor, the second control state of the second transistor, and the third control state of the third transistor; based on the first control state, the second control state and the third control state, determining the power supply state of the memory.

[0115] Optionally, the vehicle is also used to determine the power supply state of the memory based on the first control state, the second control state and the third control state, including: in response to the first control state being the on state, the second control state being the on state and the third control state being the off state, determining the power supply state to be the powered state.

[0116] Optionally, the vehicle is also used to determine that the power supply state is a non-power supply state in response to the first control state being an off state, the second control state being an off state and the third control state being an on state; and to control the memory to perform a discharge operation based on the non-power supply state.

[0117] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0118] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0119] In the several embodiments provided by the present invention, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of units can be a logical function division, and there can be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0120] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed over multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0121] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0122] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0123] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A control circuit of a memory in a chip, characterized in that: include: A first control pin, integrated in a microcontroller MCU chip, and configured to receive a voltage signal of the first control pin; A power module, connected to the MCU chip and the reset circuit, and used to determine the power supply state of the memory in the MCU chip based on the voltage signal; A reset circuit is connected to the MCU chip and is used to determine that the memory performs a reset operation based on the power supply state.

2. The circuit according to claim 1, characterized in that The reset circuit comprises: A first resistor, one end of which is connected to the first control pin, and the other end of which is connected to the first transistor; A second resistor, one end of which is connected to the first transistor and the other end of which is grounded; One end of the first transistor is connected to the third resistor and is used to control the switching state of the reset circuit.

3. The circuit according to claim 1, characterized in that The reset circuit comprises: a third resistor, one end of which is connected to the first transistor, and the other end of which is connected to the second transistor and the fourth resistor; The fourth resistor has one end connected to the power module and the other end connected to the third resistor; The second transistor has one end connected to the second control pin and is used to control the switching state of the reset circuit.

4. The circuit according to claim 1, characterized in that The reset circuit comprises: A second control pin, one end of which is respectively connected to the second transistor and the fifth resistor, and the other end of which is connected to the memory, for controlling the power supply of the memory; The fifth resistor has one end connected to the third transistor and is connected in parallel with the sixth resistor to form a current limiting resistor; The third transistor has one end connected to the seventh resistor and the other end connected between the second resistor and the first transistor; One end of the seventh resistor is connected between the first transistor and the third resistor.

5. A method for controlling a memory in a chip, characterized in that: include: Acquiring a voltage signal received by the first control pin; The power module is controlled based on the voltage signal to obtain the power supply status of the memory in the microcontroller MCU chip; A reset circuit is controlled based on the power supply state to perform a reset operation on the memory.

6. The method according to claim 5, characterized in that The power module is controlled based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip, including: Based on the voltage signal, in the reset circuit, respectively determine a first control state of the first transistor, a second control state of the second transistor, and a third control state of the third transistor; The power supply state of the memory is determined based on the first control state, the second control state, and the third control state.

7. The method according to claim 6, characterized in that Determining the power supply state of the memory based on the first control state, the second control state, and the third control state includes: In response to the first control state being the on state, the second control state being the on state, and the third control state being the off state, the power supply state is determined to be the powered state.

8. The method according to claim 6, characterized in that Based on the first control state, the second control state and the third control state, determining the power supply state of the memory, the method further comprising: In response to the first control state being an off state, the second control state being an off state, and the third control state being an on state, determining that the power supply state is a non-power supply state; Based on the unpowered state, the memory is controlled to perform a discharge operation.

9. A control device for a memory in a chip, characterized in that: include: A first acquisition unit, used to acquire a voltage signal received by the first control pin; A first control unit is used to control the power module based on the voltage signal to obtain the power supply state of the memory in the microcontroller MCU chip; The second control unit is used to control the reset circuit based on the power supply state to perform a reset operation on the memory.

10. An electronic device, characterized in that: include: A memory storing an executable program; A processor, configured to run the program, wherein the program executes the method according to any one of claims 5 to 8 when running.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored executable program, wherein when the executable program is run, the device where the storage medium is located is controlled to execute the method according to any one of claims 5 to 8.

12. A computer program product, characterized in that It comprises a computer program which, when executed by a processor, implements the method according to any one of claims 5 to 8.

13. A vehicle, characterized in that: The vehicle is used to perform the method according to any one of claims 5 to 8.

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