Controller of storage device and instruction scheduling method

Abstract

The invention discloses a controller of a storage device and an instruction scheduling method. A plurality of CA buses and CA control units in one-to-one correspondence with the CA buses are arranged in each channel of a controller of the storage equipment, and the bandwidth utilization rate of a DQ bus can be improved only by increasing a small number of physical resources by increasing the number of the CA buses in each channel. Moreover, the number of CA buses in each channel can be flexibly configured, and corresponding matching bandwidths are designed according to different performance scenes, so that the chip area and performance are balanced.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a controller of a storage device and an instruction scheduling method. Background Art

[0002] Currently, many storage devices, such as USB flash memory, SD card, CF card, SSD, eMMC embedded storage card, UFS device, etc., use flash storage media (especially NAND storage media) as the main storage media, and it has gradually become the mainstream form. Compared with the traditional magnetic media storage, the performance has made a qualitative leap. The traditional flash interface protocol (ONFi or Toggle) used by such storage devices uses the same bus for command / address and data transmission. As the data transmission rate of the flash interface increases, the command / address transmission rate does not change, resulting in an increase in the proportion of command / address transmission time, which in turn leads to a bottleneck in the improvement of the data transmission bandwidth of the flash interface.

[0003] In order to solve the problem of traditional flash memory interface improvement, the new flash memory interface protocol (for example, Separate Command Address, SCA for short) separates the command / address and data transmission and puts them on two different transmission buses for transmission, that is, CA instructions are placed on the command and address (CA) bus for transmission, and DQ instructions (that is, data to be written to or read from the flash memory storage medium) are placed on the data (DATA, also called DQ) bus for transmission.

[0004] As the transmission rate of the DQ bus increases, the time it takes for storage devices to read a unit of data is also decreasing. However, since the CA bus is a low-speed signal, its operating frequency has a maximum limit, and the time required for CA instructions on the CA bus can no longer be shortened by increasing the frequency. When the time required for transmission on the DQ bus is less than the time required for CA instructions on the CA bus, data transmission on the DQ bus will be idle because it needs to wait for the execution of CA instructions on the CA bus. Figure 1 As shown in the figure, data transmission G needs to wait for command A / B / C / D / G to be executed before it can start to execute; during the execution of command G, the DQ bus is idle, resulting in a waste of DQ bus bandwidth. In this case, the data transmission bandwidth of the flash storage medium bus is limited and no longer increases with the increase of the input and output transmission rate of the flash storage medium. Summary of the invention

[0005] In view of this, the embodiments of the present disclosure provide an instruction scheduling method and device to solve the above problems.

[0006] According to a first aspect of an embodiment of the present disclosure, a controller of a storage device is provided, the controller comprising at least one channel, a first channel of the at least one channel being coupled to a plurality of flash memory particles through a plurality of CA buses and a DQ bus, the first channel comprising: An instruction cache unit, which caches various instructions adapted to the plurality of flash memory particles respectively through a plurality of instruction queues; A plurality of CA control units, corresponding one to one with the plurality of CA buses, each CA control unit being responsible for writing a corresponding CA instruction into its corresponding CA bus; A DQ control unit, corresponding to the DQ bus, for writing data from a data path to a corresponding flash memory particle via the DQ bus according to a received DQ instruction, or reading data from a corresponding flash memory particle to the data path; The arbitration scheduling unit is used to monitor the working status of the multiple CA control units and the DQ control unit, select a CA instruction or a DQ instruction from the multiple instruction queues for a CA control unit or a DQ control unit in an idle state, and send the selected CA instruction or the DQ instruction to the CA control unit or the DQ control unit in an idle state.

[0007] In some embodiments, for the storage device, the transmission time of the DQ bus and the CA bus in multiple scenarios of random reading, random writing, continuous reading and continuous writing are obtained, and the transmission time of the DQ bus and the CA bus are compared and summarized to obtain the preferred number of CA buses in the first channel.

[0008] In some embodiments, the preferred number of CA buses in the first channel is equal to the data transmission time of a single CA bus divided by the data transmission time of a single CA bus rounded up.

[0009] In some embodiments, the selected CA instruction is a CA instruction that can be executed in parallel with the DQ instruction being executed by the DQ control unit and the CA instructions being executed by the multiple CA control units, and the selected DQ instruction is a DQ command that can be executed in parallel with the CA instructions being executed by the multiple CA control units.

[0010] In some embodiments, the selected CA instruction is the first CA instruction in the corresponding instruction queue, and the selected DQ instruction is the first DQ instruction in the corresponding instruction queue.

[0011] In some embodiments, the selected CA instruction is a CA instruction with the highest priority among multiple CA instructions that meet the requirements, and the selected DQ instruction is a DQ instruction with the highest priority among multiple DQ instructions that meet the requirements.

[0012] In some embodiments, the controller further comprises: The command parser is used to parse the received host command, convert it into an instruction adapted to the flash memory particle, and store the instruction in the instruction cache unit.

[0013] According to a second aspect of an embodiment of the present disclosure, there is provided an instruction scheduling method for a controller of a storage device, the controller comprising at least one channel, a first channel of the at least one channel being coupled to a plurality of flash memory particles via a plurality of CA buses and a DQ bus, the first channel further comprising a plurality of CA control units for controlling the plurality of CA buses one-to-one, the first channel further comprising a DQ control unit responsible for controlling the DQ bus, the instruction scheduling method comprising: monitoring states of the plurality of CA control units and the DQ control unit; When a first CA control unit among the multiple CA control units is in an idle state, taking out a CA instruction that can be executed in parallel with the currently executed CA instruction and DQ instruction from the multiple instruction queues, and sending the CA instruction to the first CA control unit for execution, wherein the multiple instruction queues respectively cache various instructions adapted to the multiple flash memory particles; When the DQ control unit is in an idle state, a DQ instruction that can be executed in parallel with the currently executing CA instruction is taken out from multiple instruction queues and sent to the DQ control unit for execution.

[0014] In some embodiments, the method further includes: if there are multiple CA instructions that meet the conditions, selecting the CA instruction with the highest priority and sending it to the first CA control unit for execution; and If there are multiple DQ instructions that meet the conditions, the DQ instruction with the highest priority is selected and sent to the DQ control unit for execution.

[0015] According to a third aspect of an embodiment of the present disclosure, there is provided a storage device, comprising: a coupled controller and a flash memory storage medium, wherein the controller is the controller described above.

[0016] According to the controller of the storage device provided by the embodiment of the present disclosure, multiple CA control units are designed in each channel to correspond to multiple CA buses. By increasing the number of CA buses in the channel, only a small amount of physical resources need to be added to improve the bandwidth utilization of the DQ bus. In addition, the number of CA buses in each channel can be flexibly configured, and the corresponding matching bandwidth design can be made for different performance scenarios to balance the chip area and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 This is an example diagram of CA bus and DQ bus executing in parallel; Figure 2 is a schematic block diagram of an exemplary host system; Figure 3 is a schematic diagram of the structure of an instruction scheduling device provided by an embodiment of the present disclosure; Figure 4 The embodiment of the present disclosure provides an application for Figure 3 A control flow chart of the arbitration scheduling unit in; Figure 5 FIG. 4 is another example of parallel execution on the CA bus and the DQ bus. DETAILED DESCRIPTION

[0018] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0019] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0020] Unless the context clearly requires otherwise, the words "include", "comprising" and the like throughout the specification and claims should be interpreted as inclusive rather than exclusive or exhaustive; that is, as "including but not limited to". In the description of the present invention, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0021] Figure 2 is a schematic block diagram of an exemplary host system 100. The host system 100 is, for example, a personal computer, a notebook computer, or a server.

[0022] The host system 100 includes a host device 110 (e.g., a computer system including a main processor and a memory) and a storage device. The host device 110 may issue a host command to the storage device so that the storage device manages the data stored in the storage device according to the command. For example, the host device 110 may be communicatively connected to the storage device (e.g., through a host interface) and issue various commands (e.g., READ, WRITE, UNMAP, REASSIGNBLOCK, TRIM, etc.) to the storage device. The storage device may store, update, read, and / or otherwise manage host data according to the address range prompted by the command. Once the command is executed, the storage device may transmit a response to the host device 110, indicating that the command has been successfully completed.

[0023] The storage device is composed of a controller 120 and a storage medium 130. The controller 120 parses the host command and converts the host command into an instruction adapted to the storage medium 130, then executes the instruction and feeds back the instruction result to the host device 110. The controller 120 is composed of various hardware and software, such as a (micro)processor, a cache unit such as SRAM and DRAM, and an interface circuit, and the software is a series of software programs that complete management functions, including but not limited to data reading and writing, bad block management, wear leveling, garbage collection, power failure recovery, and write balancing technology.

[0024] The storage medium 130 is used to store data. There are multiple channels (such as CH0 and CH1) between the controller 120 and the storage medium 130, and the controller 120 and the storage medium 130 exchange data through each channel.

[0025] At present, the mainstream storage medium 130 is a flash memory storage medium (especially a NAND storage medium). Usually, each channel (such as CH0 or CH1 in the figure) is coupled to N (N is 2, 4, 8, etc.) flash memory particles, and the controller 120 needs to operate the corresponding flash memory particles through each channel. When the SCA protocol is used as the flash memory interface protocol, each channel includes two buses: a DQ bus and a CA bus. The controller 120 executes a DQ instruction through the DQ bus to write data to or read data from the flash memory particles, and executes a CA instruction through the CA bus to perform command / address operations on the flash memory particles.

[0026] As an optional solution, more channels can be added between the controller 120 and the storage medium 130 to increase the data transmission bandwidth of the flash memory interface and improve the performance of the processor, thereby solving the problem raised in the background technology. However, this solution requires the controller 120 to add a lot of IO resources and logic control resources, which will lead to a sharp increase in the chip area and product cost of the controller 120. To this end, the embodiment of the present disclosure proposes another solution, Figure 3A schematic diagram of the structure of the controller 120 of the storage device proposed in the embodiment of the present disclosure is shown.

[0027] like Figure 3 As shown, the controller 120 includes a host interface 301, a command parser 302, a channel 303 and a physical layer module 304. The channel 303 includes an instruction cache unit 3031, an arbitration scheduling unit 3032, n CA control units 0 to n-1, 1 DQ control unit and a data path 3033. The channel 303 is coupled to n CA buses and 1 DQ bus respectively via the physical layer module 304, and then coupled to m flash memory particles, so that the controller 120 can access the m flash memory particles through the channel 303 and the above-mentioned bus. Here, m and n are both positive integers greater than or equal to 2. It should be understood that the controller 120 usually has multiple channels, but for simplicity, only a single channel 303 is used as an example for description.

[0028] The host interface 301 is used to receive host commands from the host device 110 and to transmit data with the host device 110. The host command is, for example, a write command to write data to the flash storage medium 130, a read command to read data from the flash storage medium, a query command to check the execution status of a write command or a read command, etc. The interface protocol adopted by the host interface 301 determines the various command types and formats. For example, when UPIU (UFS Protocol Information Units) is adopted as the interface protocol, the transmitted UPIU packet is composed of multiple parts such as a header and a data payload. The header provides information such as the interaction type, length, and attributes, and the data payload provides the specific content of the command or data.

[0029] The command parser 302 parses the received host command, converts it into instructions that are compatible with the flash memory particles, and stores the instructions in the instruction cache unit 3031. Flash memory particles of different products support different instruction sets. For example, for "write operation", different flash memory particle products have different instruction formats, so the command parser 302 is required to convert the received host command into the corresponding instruction format. The command parser 302 can convert one host command into multiple instructions that are compatible with the flash memory particles, and can also convert multiple host commands into multiple instructions that are compatible with the flash memory particles. The embodiment of the present disclosure does not specifically limit the correspondence between the host command and the number of instructions that are compatible with the flash memory particles.

[0030] Based on the SCA protocol, the command parser 302 classifies the instructions adapted to the flash memory particles into CA instructions and DQ instructions. CA instructions are generally operation instructions related to the configuration of the flash memory particles, such as instructions for reading the status of the flash memory particles and instructions for modifying the status of the registers on the flash memory particles. DQ instructions are generally instructions related to the data stored on the flash memory particles, such as reading or writing data to the flash memory particles. The command parser 302 can also obtain the priority of each CA instruction, and store the priority and the corresponding CA instruction in the instruction cache unit.

[0031] In some embodiments, the command parser 302 maintains multiple first-in-first-out instruction queues for multiple flash memory particles in the instruction cache unit 3031, which are used to store CA instructions and DQ instructions adapted to each flash memory particle. The figure shows (m+1) instruction queues corresponding to flash memory particles DIE 0 to DIE m respectively.

[0032] CA control units 0 to n-1 correspond to CA buses 0 to CA buses n-1 respectively, and each CA control unit is responsible for writing the corresponding CA instruction into its corresponding CA bus via the physical layer module 304 to execute the CA instruction through the CA bus.

[0033] The DQ control unit 3034 corresponds to the DQ bus 0 and is used to write data from the data path 3033 to the corresponding flash memory particles or read data from the corresponding flash memory particles to the data path 3033 via the DQ bus 0 according to the received DQ instruction. The data path 3033 is, for example, a cache. The data to be written to the flash memory particles is first placed in the data path 3033 and then taken away by the DQ control unit 3034. The data read from the flash memory particles is first placed in the data path 3033 by the DQ control unit 3034 and then transmitted to the host device 110.

[0034] The physical layer module 304 refers to the hardware and software components in the physical layer of the controller 120, which are responsible for managing the transmission and storage of data on the physical medium, including converting internal digital control signals into high-speed analog signals for input and output, and converting high-speed analog signals into internal digital control signals.

[0035] The arbitration scheduling unit 3032 is responsible for monitoring the working status of multiple CA control units and DQ control units. When one of the control units is in an idle state, a CA instruction or DQ instruction is taken out from a certain instruction queue, and the taken out CA instruction or DQ instruction is sent to the idle CA control unit or DQ control unit. Due to the limitation of the SCA protocol, some DQ instructions and / or CA instructions cannot be executed in parallel. Therefore, the arbitration scheduling unit 3032 needs to detect and exclude some instructions that conflict with the currently executed CA instructions and / or DQ instructions in the above process, and ensure that the CA instructions or DQ instructions sent to the idle CA control unit or DQ control unit can be executed in parallel with the currently executed CA instructions and / or DQ instructions. For example, if the CA instruction is a DQ-relate instruction, it conflicts with the DQ data transmission command of the same LUN (Logical Unit Number), and these two commands cannot be executed at the same time.

[0036] Figure 4 It is a control flow chart applied to the arbitration scheduling unit 3032 provided in an embodiment of the present disclosure, which specifically includes the following steps.

[0037] In step S401, the status of the CA and DQ control units are monitored.

[0038] In step S402, if there is an idle DQ control unit, step S404 is executed.

[0039] In step S403, if there is an idle CA control unit, step S405 is executed.

[0040] In step S404, a queue whose first instruction is a DQ instruction is selected.

[0041] In step S405, a queue whose first instruction is a CA instruction is selected.

[0042] In step S406 , a DQ instruction that does not conflict with all the CA instructions being executed is selected.

[0043] In step S407 , a CA instruction that does not conflict with the currently executed DQ instruction is selected.

[0044] In step S408, a DQ instruction with the highest priority is selected.

[0045] In step S409, a CA instruction with the highest priority is selected.

[0046] In step S410, a corresponding DQ instruction is sent to the idle DQ control unit.

[0047] In step S411, a corresponding CA instruction is sent to the idle CA control unit.

[0048] According to this embodiment, the status of all CA control units and DQ control units is continuously monitored. When the DQ control unit is in an idle state, it is necessary to obtain a DQ instruction from multiple instruction queues, and the DQ instruction can be executed in parallel with the currently executing CA instruction, so that the DQ instruction can be sent to the idle DQ control unit. To this end, a queue whose first instruction is a DQ instruction can be found first and the first instruction can be taken out from it to determine whether the instruction can be executed in parallel with the currently executing CA instruction. If so, the instruction is sent to the idle DQ control unit for execution. If there are multiple queues whose first instructions are DQ instructions, these first instructions are taken out from them, and it is determined which instructions among them can be executed in parallel with the currently executing CA instruction. If there are multiple instructions that can be executed in parallel with the currently executing CA instruction, the instruction with the highest priority is sent to the idle DQ control unit for execution.

[0049] When a CA control unit is in an idle state, it is necessary to obtain a CA instruction from multiple instruction queues. The CA instruction can be executed in parallel with the currently executing DQ instruction and the remaining CA instructions, so that the CA instruction can be sent to the idle CA control unit. To this end, a queue whose first instruction is a CA instruction can be found first and the first instruction can be taken out to determine whether the instruction can be executed in parallel with the currently executing DQ instruction and the remaining CA instructions. If so, the instruction is sent to the idle CA control unit. If there are multiple queues whose first instructions are CA instructions, these first instructions are taken out and it is determined which instructions among them can be executed in parallel with the currently executing DQ instruction and the remaining CA instructions. If there are multiple instructions that can be executed in parallel with the currently executing DQ instruction and the remaining CA instructions, the instruction with the highest priority among them is sent to the idle CA control unit for execution. Figure 5 FIG. 4 is another example of parallel execution on the CA bus and the DQ bus.

[0050] refer to Figure 5As shown in the figure, when data transfer X is executed, the arbitration scheduling unit distributes CA instruction B / C / G to CA bus 0 of CA control unit 0 for execution; and distributes CA instruction A / D to CA bus 1 of CA control unit 1 for execution. Since the two CA buses are executed in parallel, the CA instruction obtains twice the bandwidth. Before data transfer X is completed, data transfer G starts to execute. The prerequisite is that the command A / B / C / D / G has been executed. Then, after data transfer X is executed, data transfer G can start to execute immediately. In this way, data transfers are closely connected on the DQ bus, making full use of the bandwidth of the DQ bus.

[0051] According to the above embodiment, a pair of N (N is an integer greater than or equal to 2) DQ buses and CA buses are respectively set in each channel of the controller of the memory, which can avoid the idle state of the DQ bus due to waiting for the execution of the CA instruction on the CA bus to a certain extent. As long as the DQ bus is in a busy state most of the time, the data transmission bandwidth of the DQ bus and the data transmission bandwidth of the flash memory interface can be improved. However, the larger N is, the more the chip area and product cost of the controller increase, so N needs to select an appropriate value. Generally, for a certain storage device, the transmission time of a single DQ bus and a single CA bus in multiple scenarios can be obtained through experiments, and the data transmission time of a single DQ bus and a single CA bus can be compared and summarized to estimate the preferred value of N of the storage device. Multiple scenarios include but are not limited to: random read, random write, continuous read and continuous write. These reads and writes are generally performed in memory pages (4K units) as basic units.

[0052] For a certain storage device, if the data transmission time of a single CA bus is N times the data transmission time of a single DQ bus, then N is preferably equal to the data transmission time of a single CA bus divided by the data transmission time of a single DQ bus and then rounded up. More specifically, for example, m samples in multiple scenarios are obtained through experiments, and the i-th sample is represented by {} , which represents the data transmission time of the CA bus in the i-th sample, and represents the data transmission time of the DQ bus in the i-th sample. Then, the following formula (1) is used to obtain N: N>=Max(ceil( / )) i=1,…,m (1), Among them, ceil() means rounding up, Max means selecting the maximum value, and the preferred value of N is the selected maximum value.

[0053] According to the controller of the storage device provided by the embodiment of the present disclosure, multiple CA buses and CA control units corresponding to the multiple CA buses are set in each channel. By increasing the number of CA buses in the channel, only a small amount of physical resources need to be added to improve the bandwidth utilization of the DQ bus. In addition, the number of CA buses in each channel can be flexibly configured, and the corresponding matching bandwidth design can be made for different performance scenarios to balance the chip area and performance.

[0054] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A controller of a storage device, the controller comprising at least one channel, a first channel of the at least one channel being coupled to a plurality of flash memory particles via a plurality of CA buses and a DQ bus, the first channel comprising: An instruction cache unit, which caches various instructions adapted to the plurality of flash memory particles respectively through a plurality of instruction queues; A plurality of CA control units, corresponding one to one with the plurality of CA buses, each CA control unit being responsible for writing a corresponding CA instruction into its corresponding CA bus; A DQ control unit, corresponding to the DQ bus, for writing data from a data path to a corresponding flash memory particle via the DQ bus according to a received DQ instruction, or reading data from a corresponding flash memory particle to the data path; The arbitration scheduling unit is used to monitor the working status of the multiple CA control units and the DQ control unit, select a CA instruction or a DQ instruction from the multiple instruction queues for a CA control unit or a DQ control unit in an idle state, and send the selected CA instruction or the DQ instruction to the CA control unit or the DQ control unit in an idle state.

2. The controller according to claim 1, wherein: For the storage device, transmission times of a single DQ bus and a single CA bus in multiple scenarios of random reading, random writing, continuous reading, and continuous writing are obtained, and the transmission times of the DQ bus and the CA bus are compared and summarized to obtain a preferred number of CA buses in the first channel.

3. The controller according to claim 2, wherein: The preferred number of CA buses in the first channel is equal to the data transmission time of a single CA bus divided by the data transmission time of a single CA bus, and the result is rounded up.

4. The controller according to claim 1, wherein: The selected CA instruction is a CA instruction that can be executed in parallel with the DQ instruction being executed by the DQ control unit and the CA instruction being executed by the CA control unit. The selected DQ instruction is a DQ command that can be executed in parallel with the CA instruction being executed by the CA control unit.

5. The controller according to claim 4, wherein: The selected CA instruction is the first CA instruction in the corresponding instruction queue, and the selected DQ instruction is the first DQ instruction in the corresponding instruction queue.

6. The controller according to claim 4, wherein: The selected CA instruction is the CA instruction with the highest priority among multiple CA instructions that meet the requirements, and the selected DQ instruction is the DQ instruction with the highest priority among multiple DQ instructions that meet the requirements.

7. The controller according to any one of claims 1 to 6, wherein: The controller further comprises: The command parser is used to parse the received host command, convert it into an instruction adapted to the flash memory particle, and store the instruction in the instruction cache unit.

8. A method for command scheduling, for use in a controller of a storage device, the controller comprising at least one channel, a first channel of the at least one channel being coupled to a plurality of flash memory particles via a plurality of CA buses and a DQ bus, the first channel further comprising a plurality of CA control units for one-to-one control of the plurality of CA buses, the first channel further comprising a DQ control unit responsible for controlling the DQ bus, the method for command scheduling comprising: monitoring states of the plurality of CA control units and the DQ control unit; When a first CA control unit among the multiple CA control units is in an idle state, taking out a CA instruction that can be executed in parallel with the currently executed CA instruction and DQ instruction from the multiple instruction queues, and sending the CA instruction to the first CA control unit for execution, wherein the multiple instruction queues respectively cache various instructions adapted to the multiple flash memory particles; When the DQ control unit is in an idle state, a DQ instruction that can be executed in parallel with the currently executing CA instruction is taken out from multiple instruction queues and sent to the DQ control unit for execution.

9. The instruction scheduling method according to claim 8, further comprising: If there are multiple CA instructions that meet the conditions, select the CA instruction with the highest priority and send it to the first CA control unit for execution; as well as If there are multiple DQ instructions that meet the conditions, the DQ instruction with the highest priority is selected and sent to the DQ control unit for execution.

10. A storage device comprising: A coupled controller and a flash memory storage medium, wherein the controller is a controller as described in any one of claims 1 to 7.

Images