External multi-stage extensible network bypass design system and method

Abstract

The invention discloses an external multi-stage extensible network bypass design system which comprises a network device and a plurality of external network bypass modules in linear cascade connection with the network device, and each external network bypass module adopts two BYPASS interfaces (IN / OUT) as upper and lower connection ports in linear cascade connection. And the downlink port (OUT) of each external network bypass module is interconnected with the uplink port (IN) of the next cascaded external network bypass module. The external network bypass module comprises a power supply conversion module, a serial-to-parallel logic module and a plurality of network bypasses. Correspondingly, the invention further provides a design method of the external multi-stage extensible network bypass. The problems that an existing built-in network bypass occupies a large space of a mainboard and is not flexible in configuration, the number of external network bypass signal lines is too large, the requirements of different users for the number of network bypasses cannot be met, and the network structure of the network bypasses is difficult to expand are solved.

Description

Technical Field

[0001] The invention belongs to the field of network security, and in particular relates to an external multi-stage expandable network bypass design system and method. Background Art

[0002] Network bypass is a very common network application requirement in the field of network security. Network bypass is generally designed directly inside the network device. For network devices with many network ports, the motherboard occupies a large space and the configuration is inflexible. It cannot meet the needs of different users for the number of network bypasses, resulting in a wide variety of motherboards and increased costs. In the external network bypass control circuit, each set of switches uses a BYPASS_EN signal to transmit the bypass state, and another GATE_EN signal to transmit the bypass selection. BYPASS_EN high level indicates that the bypass is turned on, and low level indicates that the bypass is turned off. GATE_EN is a pulse control signal, which is low by default. A high pulse indicates that the control circuit latches the BYPASS_EN signal. According to this design idea, using N network bypasses requires 2N signal lines. For external modules, the number of signal lines is too large to meet the requirements of ease of use and cost. In addition to the signal lines, external expandable modules also require additional power supply, which requires more connections. Therefore, there is an urgent need for an external multi-stage expandable network bypass design system to solve the problems of inflexible network device configuration, too many signal lines, and difficulty in meeting the requirements of ease of use and cost. In addition, the network structure of the built-in network bypass is fixed. If the number of network bypasses needs to be increased or decreased, it may be necessary to redesign the motherboard and modify the structure of the entire machine, which will bring a large workload and design cost. Therefore, there is an urgent need for an external multi-stage expandable network bypass design method to solve the problem that the network structure of the network bypass is difficult to expand.

[0003] The Chinese patent with the publication number "CN106708771A" discloses a network bypass device and a processing method thereof, the network bypass device includes: a controller unit, including a main chip connected to the processing end and exchanging data with the processing end and a plurality of slave chips exchanging data with the main chip; a driver unit connected between the controller unit and the actuator unit, the driver unit is used to connect to the slave chip through a plurality of network bypass channels, and drive the actuator unit to work according to the data sent by the controller unit; the actuator unit is connected to the network end through a differential line, and the actuator unit is used to process the network differential signal interacting with the network end. The beneficial effect of the invention is: through the division of labor of the cascade bypass controller, the number of network bypass channels is increased, the upper software and parameter configuration can be unified controlled. The management of all data and information is the responsibility of the same controller, the data can be centrally acquired and sent, and the operation control and fault location are very simple. However, the network bypass design of the invention is also built into the network device, and multiple slave chips are required to manage the multiple network bypass channels connected to it, which takes up a high space cost. Summary of the invention

[0004] The present invention provides an external multi-stage expandable network bypass design system and method, aiming to solve the problems that the current built-in network bypass occupies a large space on the mainboard, the configuration is inflexible, the number of external network bypass signal lines is too large, the demand scenarios of the number of network bypasses for different users cannot be met, and the network structure of the network bypass is difficult to expand.

[0005] To solve the above technical problems, the present invention proposes an external multi-stage expandable network bypass design system, the system comprising a network device and a plurality of external network bypass modules linearly cascaded with the network device, the external network bypass module using two BYPASS interfaces (IN / OUT) as the upper and lower ports of the linear cascade, the lower port (OUT) of each external network bypass module is interconnected with the upper port (IN) of the next external network bypass module in the cascade.

[0006] The external network bypass module includes a power conversion module, a serial-to-parallel logic module and a plurality of network bypasses.

[0007] The power conversion module is used to perform level matching between the power transmitted by the network device and the power used by the serial-to-parallel logic module. The power conversion module is connected to the serial-to-parallel logic module via a power signal.

[0008] The serial-to-parallel logic module is used to convert the serial signal sent by the network device into a parallel signal. The network bypass includes a GATE_EN signal port and a BYPASS_EN signal port. The serial-to-parallel logic module is connected in parallel with several corresponding network bypasses through a GATE_EN signal. The serial-to-parallel logic module is also connected to several corresponding network bypasses through several BYPASS_EN signals.

[0009] Preferably, the BYPASS interface of the external network bypass module is a USB TYPE-C interface, and the USB TYPE-C interface realizes the connection of five groups of signals +5V / CLK / DATA / GND / LATCH. The BYPASS interface definition is compatible with the existing USB TYPE-C interface definition level.

[0010] Preferably, the network bypass also includes two network port interfaces and two network cable interfaces and corresponding indicator lights, the network port interfaces are used to connect network devices, the network cable interfaces are used to connect user network cables, and the indicator lights are used to indicate the operating status of the corresponding network bypass.

[0011] Preferably, the serial-to-parallel logic module is implemented using a 74HC595 chip, which is used to convert the serial signal sent by the network device into an eight-bit parallel signal, one bit of the eight-bit parallel signal is used as a GATE_EN signal to be connected in parallel with all the corresponding network bypasses, and at least one bit of the remaining signals of the eight-bit parallel signal is used as a BYPASS_EN signal to be connected with a corresponding network bypass.

[0012] Preferably, the number of external network bypass modules using linear cascade in the system is set to four, and the number of network bypasses in the external network bypass module is set to four.

[0013] One of the eight-bit parallel signals converted by the serial-to-parallel logic module in the external network bypass module is used as a GATE_EN signal to be connected in parallel with all four corresponding network bypasses, and four of the remaining eight-bit parallel signals are used as BYPASS_EN1, BYPASS_EN2, BYPASS_EN3, and BYPASS_EN4 signals to be connected with the corresponding four network bypasses.

[0014] Accordingly, the present invention also proposes an external multi-stage scalable network bypass design method, comprising the following steps:

[0015] S1: The network device is linearly cascaded with K (K∈[1, N]) external network bypass modules. The MCU of the network device sends N bytes to the linearly cascaded external network bypass modules in reverse order. Each time a configuration byte is sent, all external network bypass modules automatically move the currently matched byte data to the next network bypass module. If the next network bypass module does not exist, the byte data is automatically discarded.

[0016] S2: After the MCU of the network device sends N configuration bytes, the first external network module matches the first configuration byte, and so on, the Kth external network module matches K configuration bytes, each network module corresponds to a configuration byte, and after the configuration matching is completed, it is latched, and each external network bypass module can output the bytes to the user end of the subordinate network bypass connection.

[0017] Compared with the prior art, the present invention has the following technical effects:

[0018] 1. The network device of the present invention does not need to design a network bypass circuit, but is implemented by an external network bypass module, which saves the motherboard space of the network device and solves the problem of diversified user applications.

[0019] 2. The network device in the external multi-level expandable network bypass design system is connected to the external network bypass module using the USBTYPE-C interface. The signal quantity, level and definition are compatible, it takes up little space, is low cost and is easy to connect.

[0020] 3. The external network bypass module can realize multi-stage linear cascading, and the circuits of each external network bypass module are completely consistent. The MCU of the network device controls the external network bypass module without identifying the number of external network bypass modules. The number of external network bypass modules and the number of network bypasses in each external network bypass module can be set according to the needs of the network device to ensure maximum software compatibility and ease of use.

[0021] 4. The external multi-stage scalable network bypass design method described in the present invention can flexibly and dynamically adjust the number and connection mode of network bypasses, is suitable for an adjustable network bypass network structure, and can dynamically adjust the number of network bypasses in the system according to different user demand scenarios for the number of network bypasses. In addition, the physical connection of this method is simple, and the cables used are common materials, which are easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is an overall structural diagram of an external multi-stage expandable network bypass design system described in the present invention;

[0023] Figure 2 It is an overall structural diagram of the external network bypass module described in the present invention;

[0024] Figure 3 It is the overall structural diagram of the network bypass described in the present invention;

[0025] Figure 4 It is an internal signal transmission diagram of the network bypass when the BYPASS_EN signal of the present invention is at a high level;

[0026] Figure 5 It is an internal signal transmission diagram of the network bypass when the BYPASS_EN signal of the present invention is at a low level;

[0027] Figure 6 It is the logic diagram of the 74HC595 chip of the present invention;

[0028] Figure 7 It is the pin diagram of the 74HC595 chip of the present invention;

[0029] Figure 8 This is the overall structure diagram of an external four-level expandable network bypass design system described in the present invention;

[0030] Fig. 9 It is an overall structural diagram of the external network bypass module including four network bypasses described in the present invention. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in combination with specific embodiments of the present application and with reference to the accompanying drawings.

[0032] Embodiment 1

[0033] The present invention proposes an external multi-level expandable network bypass design system, see Figure 1 As shown, the system includes a network device and several external network bypass modules that are linearly cascaded with the network device. The external network bypass module uses two BYPASS interfaces (IN / OUT) as upper and lower ports of the linear cascade, and the lower port (OUT) of each external network bypass module is interconnected with the upper port (IN) of the next external network bypass module in the cascade.

[0034] See also Figure 2 As shown, the external network bypass module includes a power conversion module, a serial-to-parallel logic module and a plurality of network bypasses.

[0035] The power conversion module is used to level-match the power transmitted by the network device with the power used by the serial-to-parallel logic module, and the power conversion module is connected to the serial-to-parallel logic module through a power signal. In order to ensure that the pin definition of each external network bypass module is compatible with the USB interface, each external network bypass module is only connected to a +5V power supply, and the +5V power supply is mainly used for the network bypass relay circuit. Since the current is relatively large when the relay is working, additional energy storage will be designed, but the power used by the serial-to-parallel logic module is +3.3V, so an additional power conversion module needs to be designed. The power conversion module converts the +5V power supply of the network device into a +3.3V power supply for the serial-to-parallel logic module. At the same time, the power used by the serial-to-parallel logic module is separated from the +5V power supply, which also ensures that the serial-to-parallel logic module will not be affected when the external network bypass module relay is actuated.

[0036] The serial-to-parallel logic module is used to convert the serial signal sent by the network device into a parallel signal. The single network bypass includes a GATE_EN signal port and a BYPASS_EN signal port. The serial-to-parallel logic module is connected in parallel with the corresponding several network bypasses through a GATE_EN signal. More GATE_EN signals are independently controlled, and more software time is required to operate the serial port to convert and send complete data. The GATE_EN signal level is flipped, and each flip requires sending the same number of bytes as the number of network bypasses, which will cause each network bypass to require more serial-to-parallel time to send data. From a design perspective, a GATE_EN signal can share one to improve the efficiency of software operation. The serial-to-parallel logic module is also connected to the corresponding several network bypasses through several BYPASS_EN signals.

[0037] Furthermore, the BYPASS interface of the external network bypass module is a USB TYPE-C interface, and a TYPE-C data cable is used between the network device and several external network bypass modules that are linearly cascaded with the network device, that is, N external network bypass modules can be connected using N TYPE-C data cables. The USB TYPE-C interface realizes the connection of five groups of signals +5V / CLK / DATA / GND / LATCH, ensuring the physical pin compatibility between the network device and the external network bypass module. The +5V power supply of the external network bypass module is the same as the default USB voltage, and the CLK / DATA / LATCH signal level is the same as the USB signal voltage level, thereby ensuring that the network device and the external network bypass module can be interconnected using a standard TYPE-C connection cable, and that user error insertion will not cause malfunctions. The specific definition of the USB TYPE-C interface is shown in Table 1:

[0038] Table 1 USB TYPE-C interface definition table

[0039] TYPE-C Pin A4 / A9 / B4 / B9 A7 / B7 A6 / B6 A1 / A12 / B1 / B12 A5 / B5 USB Definition VBUS D- D+ GND CC1 / CC2 BYPASS Definition +5V CLK DATA GND LATCH

[0040] For further information, see Figure 3 As shown, the network bypass also includes two network ports and two network cable ports and corresponding indicator lights. The network port is used to connect the network device, the network cable port is used to connect the user network cable, and the indicator light is used to indicate the operation status of the corresponding network bypass. The indicator lights respectively indicate the level status of BYPASS_EN corresponding to the network bypass. When the BYPASS_EN signal is at a high level, the indicator light is on to indicate that the network bypass is turned on. When the BYPASS_EN signal is at a low level, the indicator light is off to indicate that the network bypass is turned off. Figure 4 As shown in FIG. 1 , when the BYPASS_EN signal is at a high level, the network port interface is disconnected from the network cable interface, and the two user terminals respectively connected to the network port interface bypass the network device to communicate with each other. Figure 5 As shown, when the BYPASS_EN signal is at a low level, the network port interface is connected to the network cable interface, and the two user terminals respectively connected to the network port interface are interconnected and communicated with the network device respectively.

[0041] Furthermore, the serial-to-parallel logic module is implemented using a 74HC595 chip, see Figure 6 , Figure 7 As shown, the OE pin of the 74HC595 chip of the first external network bypass module is connected to the GND signal, OE is pulled low to enable 8 tri-state gate outputs, the SHCP pin is connected to the CLK signal of the network device, the MR pin is connected to the +5V signal to design an RC power-on reset, which is high level after power-on, so that the tri-state gate outputs are all 0 by default, the DS pin is connected to the DATA signal of the network device, the STCP pin is connected to the LATCH signal of the network device, and the Q7S pin is connected to the DATA signal of the next level external network bypass module. The 74HC595 chip is used to convert the serial signal sent by the network device into an eight-bit parallel signal, one of the eight-bit parallel signals is used as a GATE_EN signal to be connected in parallel with all the corresponding network bypasses, and at least one of the remaining signals of the eight-bit parallel signal is used as a BYPASS_EN signal to be connected with a corresponding network bypass.

[0042] Embodiment 2

[0043] Preferably, the present invention proposes an external multi-level scalable network bypass design system, see Figure 8As shown, the system includes a network device and four external network bypass modules that are linearly cascaded with the network device. The external network bypass modules use two BYPASS interfaces as upper and lower ports of the linear cascade, and the lower port of each external network bypass module is interconnected with the upper port of the next external network bypass module in the cascade.

[0044] For further information, see Fig. 9 As shown, the external network bypass module includes a power conversion module, a serial-to-parallel logic module and four network bypasses.

[0045] The power conversion module is used to level-match the power transmitted by the network device with the power used by the serial-to-parallel logic module, and the power conversion module is connected to the serial-to-parallel logic module through a power signal. In order to ensure that the pin definition of each external network bypass module is compatible with the USB interface, each external network bypass module is only connected to a +5V power supply, and the +5V power supply is mainly used for the network bypass relay circuit. Since the current is relatively large when the relay is working, additional energy storage will be designed, but the power used by the serial-to-parallel logic module is +3.3V, so an additional power conversion module needs to be designed. The power conversion module converts the +5V power supply of the network device into a +3.3V power supply for the serial-to-parallel logic module. At the same time, the power used by the serial-to-parallel logic module is separated from the +5V power supply, which also ensures that the serial-to-parallel logic module will not be affected when the external network bypass module relay is actuated.

[0046] The serial-to-parallel logic module is used to convert the serial signal sent by the network device into a parallel signal. The network bypass includes a GATE_EN signal port and a BYPASS_EN signal port. The serial-to-parallel logic module is connected in parallel with the corresponding four network bypasses through a GATE_EN signal. The serial-to-parallel logic module is also connected to the corresponding four network bypasses through four BYPASS_EN signals. That is, the four groups of network bypasses in the external network bypass module share a GATE_EN signal. The serial-to-parallel logic module converts the serial signal sent by the network device into a five-bit parallel signal.

[0047] Furthermore, the BYPASS interface of the external network bypass module is a USB TYPE-C interface, and a TYPE-C data cable can be used between the network device and the four external network bypass modules that are linearly cascaded with the network device. The USB TYPE-C interface realizes the connection of five groups of signals +5V / CLK / DATA / GND / LATCH, ensuring the physical pin compatibility between the network device and the external network bypass module. The +5V power supply of the external network bypass module is the same as the default USB voltage, and the CLK / DATA / LATCH signal level is the same as the USB signal voltage level, thereby ensuring that the network device and the external network bypass module can be interconnected using a standard TYPE-C connection cable, and that a malfunction will not occur if the user inserts it by mistake.

[0048] For further information, see Figure 3 As shown, the network bypass also includes two network ports and two network cable ports and corresponding indicator lights. The network port is used to connect the network device, the network cable port is used to connect the user network cable, and the indicator lights are used to indicate the operation status of the corresponding network bypass. The indicator lights respectively indicate the level status of BYPASS_EN of the corresponding network bypass. When the BYPASS_EN signal is at a high level, the indicator lights are on to indicate that the network bypass is turned on. When the BYPASS_EN signal is at a low level, the indicator lights are off to indicate that the network bypass is turned off. Figure 4 As shown in FIG. 1 , when the BYPASS_EN signal is at a high level, the network port interface is disconnected from the network cable interface, and the two user terminals respectively connected to the network port interface bypass the network device to communicate with each other. Figure 5 As shown, when the BYPASS_EN signal is at a low level, the network port interface is connected to the network cable interface, and the two user terminals respectively connected to the network port interface are interconnected and communicated with the network device respectively.

[0049] Furthermore, the serial-to-parallel logic module is implemented using a 74HC595 chip, see Figure 6 , Figure 7As shown, the 0E pin of the 74HC595 chip of the first external network bypass module is connected to the GND signal, 0E is pulled low, and the eight tri-state gate outputs are enabled, the SHCP pin is connected to the CLK signal of the network device, the MR pin is connected to the +5V signal, and an RC power-on reset is designed. After power-on, the high level is set, so that the tri-state gate outputs are all 0 by default, the DS pin is connected to the DATA signal of the network device, the STCP pin is connected to the LATCH signal of the network device, and the Q7S pin is connected to the DATA signal of the next level external network bypass module. The 74HC595 chip is used to convert the serial signal sent by the network device into an eight-bit parallel signal, one of the eight-bit parallel signals is used as a GATE_EN signal to be connected in parallel with the corresponding four network bypasses, and the four-bit signals of the remaining eight-bit parallel signals are used as BYPASS_EN1, BYPASS_EN2, BYPASS_EN3, BYPASS_EN4 signals to be connected with the corresponding four network bypasses. Three of the remaining eight-bit parallel signals are not connected.

[0050] Embodiment 3

[0051] Accordingly, the present invention also proposes an external multi-level scalable network bypass design method to achieve self-adaptation of the number of external network bypass modules, comprising the following steps:

[0052] S1: The network device is linearly cascaded with K (K∈[1, N]) external network bypass modules. The MCU of the network device sends N bytes to the linearly cascaded external network bypass modules in reverse order. Every time a configuration byte is sent, all external network bypass modules automatically move the currently matched byte data to the next network bypass module. If the next network bypass module does not exist, the byte data is automatically discarded.

[0053] S2: After the MCU of the network device sends N configuration bytes, the first external network module matches the first configuration byte, and so on, the Kth external network module matches K configuration bytes, each network module corresponds to a configuration byte, and after the configuration matching is completed, it is latched, and each external network bypass module can output the bytes to the user end of the subordinate network bypass connection.

[0054] For example, when the network device is connected to 1-4 external network bypass modules, the MCU of the network device needs to send 4 bytes to the external network bypass module. If the network device is connected to 3 external network bypass modules, after the MCU of the network device sends 3 bytes, the third external network bypass module corresponds to configuration 4, the second external network bypass module corresponds to configuration 3, and the first external network bypass module corresponds to configuration 2. Then the MCU of the network device continues to send bytes representing configuration 1, and the 74HC595 chip continues to shift. The byte representing configuration 4 originally corresponding to the third external network bypass module is shifted out and replaced by the new byte representing configuration 3, and so on. After 4 bytes of data are sent, each external network bypass module completely matches the configuration number.

[0055] The above is only a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several modifications and improvements without departing from the inventive concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. An external multi-level scalable network bypass design system, characterized in that: The system includes a network device and a plurality of external network bypass modules that are linearly cascaded with the network device, wherein the external network bypass modules use two BYPASS interfaces (IN / OUT) as upper and lower ports of the linear cascade, and the lower port (OUT) of each external network bypass module is interconnected with the upper port (IN) of the next external network bypass module in the cascade; The external network bypass module includes a power conversion module, a serial-to-parallel logic module and a plurality of network bypasses; The power conversion module is used to perform level matching between the power transmitted by the network device and the power used by the serial-to-parallel logic module, and the power conversion module is connected to the serial-to-parallel logic module via a power signal; The serial-to-parallel logic module is used to convert the serial signal sent by the network device into a parallel signal. The single network bypass includes a GATE_EN signal port and a BYPASS_EN signal port. The serial-to-parallel logic module is connected in parallel with the corresponding network bypasses through a GATE_EN signal. The serial-to-parallel logic module is also connected to the corresponding network bypasses through several BYPASS_EN signals.

2. According to claim 1, an external multi-level scalable network bypass design system is characterized in that: The BYPASS interface of the external network bypass module is a USB TYPE-C interface, and the USB TYPE-C interface realizes the connection of five groups of signals +5V / CLK / DATA / GND / LATCH. The BYPASS interface definition is compatible with the existing USB TYPE-C interface definition level.

3. The external multi-level scalable network bypass design system according to claim 1, characterized in that: The network bypass also includes two network port interfaces, two network cable interfaces and corresponding indicator lights. The network port interfaces are used to connect to network devices, the network cable interfaces are used to connect to user network cables, and the indicator lights are used to indicate the operating status of the corresponding network bypass.

4. The external multi-level scalable network bypass design system according to claim 2, characterized in that: The serial-to-parallel logic module is implemented using a 74HC595 chip, which is used to convert a serial signal sent by a network device into an eight-bit parallel signal, one of the eight-bit parallel signals is used as a GATE_EN signal to be connected in parallel with all corresponding network bypasses, and at least one of the remaining eight-bit parallel signals is used as a BYPASS_EN signal to be connected with a corresponding network bypass.

5. The external multi-level scalable network bypass design system according to claim 4, characterized in that: The number of linearly cascaded external network bypass modules in the system is set to four, and the number of network bypasses in the external network bypass modules is set to four; One of the eight-bit parallel signals converted by the serial-to-parallel logic module in the external network bypass module is used as a GATE_EN signal to be connected in parallel with all four corresponding network bypasses, and four of the remaining eight-bit parallel signals are used as BYPASS_EN1, BYPASS_EN2, BYPASS_EN3, and BYPASS_EN4 signals to be connected with the corresponding four network bypasses.

6. A method for designing an external multi-level scalable network bypass, characterized in that: The method uses an external multi-stage scalable network bypass design system according to any one of claims 1 to 5, comprising the following steps: S1: The network device is linearly cascaded with K (K∈[1, N]) external network bypass modules. The MCU of the network device sends N bytes to the linearly cascaded external network bypass modules in reverse order. Each time a configuration byte is sent, all external network bypass modules automatically move the currently matched byte data to the next network bypass module. If the next network bypass module does not exist, the byte data is automatically discarded. S2: After the MCU of the network device sends N configuration bytes, the first external network module matches the first configuration byte, and so on, the Kth external network module matches K configuration bytes, each network module corresponds to a configuration byte, and after the configuration matching is completed, it is latched, and each external network bypass module can output the bytes to the user end of the subordinate network bypass connection.

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