Cross-core data synchronization method and device of multi-core chip and electronic equipment

Abstract

The invention provides a cross-core data synchronization method and device of a multi-core chip, electronic equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: detecting data states of a plurality of cores in the multi-core chip; wherein the data state is used for representing whether a data synchronization instruction is valid or not, and the data synchronization instruction comprises data corresponding to the data block identifier; when it is detected that the data state is a valid synchronization core, performing query processing on a data block by using a registry according to a data block identifier corresponding to data in a data synchronization instruction of the synchronization core to obtain a to-be-synchronized core; wherein the data block use registry comprises a corresponding relation between a data block identifier and a core which needs to use the data block; and sending the data synchronization instruction of the synchronization core to the to-be-synchronized core through inter-core communication. According to the invention, the data synchronization efficiency can be improved.

Description

Technical Field

[0001] The present application relates to computer technology, and in particular to a method, device, electronic device, computer-readable storage medium and computer program product for cross-core data synchronization of a multi-core chip. Background Art

[0002] With the development of intelligent vehicle technology, more and more vehicles are adopting the domain controller architecture to reduce the number of electronic control nodes and body wiring harnesses on the vehicle to meet the overall demand for lightweight vehicles. This has resulted in the functions that previously required multiple control nodes to be implemented in one domain controller, and the functions deployed in the domain controller are becoming increasingly large and complex.

[0003] For the new architecture of domain controller, the current mainstream solution is to use multi-core chips, and complete complex functions through the collaborative work of multiple cores in the multi-core chip. Among them, ensuring the data consistency of each core is an important part of the collaborative work. In the solution provided by the relevant technology, it is usually to establish a peer-to-peer communication channel between multiple cores, and transmit data in a specific communication message format to achieve data synchronization. However, before each data transmission, the communicating parties need to establish a communication channel, and the communication initiator needs to wait for the response of the other end before continuing the next data transmission, resulting in low timeliness of data synchronization. Summary of the invention

[0004] The present application provides a cross-core data synchronization method, device, electronic device, computer-readable storage medium and computer program product for a multi-core chip, which can improve data synchronization efficiency.

[0005] The technical solution of this application is implemented as follows:

[0006] The present application provides a cross-core data synchronization method for a multi-core chip, comprising:

[0007] Detecting and processing the data status of multiple cores in a multi-core chip; wherein the data status is used to indicate whether a data synchronization instruction is valid, and the data synchronization instruction includes data corresponding to a data block identifier;

[0008] When a synchronization core with a valid data state is detected, a data block usage registration table is queried and processed according to a data block identifier corresponding to the data in the data synchronization instruction of the synchronization core to obtain a core to be synchronized; wherein the data block usage registration table includes a correspondence between a data block identifier and a core that needs to use the data block;

[0009] The data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication.

[0010] The present application provides a cross-core data synchronization device for a multi-core chip, comprising:

[0011] A detection module is used to detect and process the data status of multiple cores in the multi-core chip; wherein the data status is used to indicate whether the data synchronization instruction is valid, and the data synchronization instruction includes data corresponding to the data block identifier;

[0012] A query module, for, when a synchronization core with a valid data status is detected, querying a data block usage registration table according to a data block identifier corresponding to the data in a data synchronization instruction of the synchronization core, to obtain a core to be synchronized; wherein the data block usage registration table includes a correspondence between a data block identifier and a core that needs to use the data block;

[0013] The sending module is used to send the data synchronization instruction of the synchronization core to the core to be synchronized through inter-core communication.

[0014] The present application provides a multi-core chip, which includes executable instructions. The multi-core chip runs in an electronic device to implement the cross-core data synchronization method of the multi-core chip provided in the present application.

[0015] The present application provides an electronic device, including:

[0016] A memory for storing executable instructions;

[0017] The processor is used to implement the cross-core data synchronization method of the multi-core chip provided in the present application when executing the executable instructions stored in the memory.

[0018] The present application provides a computer-readable storage medium storing executable instructions for causing a processor to execute and implement the cross-core data synchronization method of a multi-core chip provided by the present application.

[0019] The present application provides a computer program product, which includes executable instructions for causing a processor to execute and implement the cross-core data synchronization method of a multi-core chip provided by the present application.

[0020] This application has the following beneficial effects:

[0021] The present application detects and processes the data status of multiple cores in a multi-core chip; wherein the data status is used to characterize whether a data synchronization instruction is valid, and the data synchronization instruction includes data corresponding to a data block identifier; when a synchronization core whose data status is valid is detected, a data block usage registry is queried and processed according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core, to obtain a core to be synchronized; wherein the data block usage registry includes a correspondence between the data block identifier and the core that needs to use the data block; the data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication. The present application locates the synchronization core that needs to perform data synchronization by detecting the data status, and uniformly sends the data synchronization instruction of the synchronization core to the core to be synchronized through inter-core communication, so as to achieve efficient data synchronization on all cores, that is, it can improve the efficiency of data synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a first structural schematic diagram of a vehicle provided in an embodiment of the present application;

[0024] Figure 2 is a second structural schematic diagram of a vehicle provided in an embodiment of the present application;

[0025] Figure 3A This is a first flow chart of a cross-core data synchronization method for a multi-core chip provided in an embodiment of the present application;

[0026] Figure 3B This is a second flow chart of the cross-core data synchronization method of a multi-core chip provided in an embodiment of the present application;

[0027] Figure 3C 3 is a schematic diagram of a third flow chart of a cross-core data synchronization method for a multi-core chip provided in an embodiment of the present application;

[0028] Figure 3D This is a fourth flow chart of the cross-core data synchronization method of a multi-core chip provided in an embodiment of the present application;

[0029] Figure 4 is a schematic diagram of an internal module of an operating system provided in an embodiment of the present application;

[0030] Figure 5 It is a flow chart of the operation process of the centralized management module provided in the embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0032] In the following description, reference is made to "some embodiments", which describes a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. In the following description, reference is made to the term "multiple" to mean at least two.

[0033] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0035] The embodiments of the present application provide a cross-core data synchronization method, device, electronic device, computer-readable storage medium and computer program product of a multi-core chip, which can improve the efficiency of data synchronization. The following describes an exemplary application of the electronic device provided by the embodiments of the present application. The electronic device has a multi-core chip deployed inside. The electronic device can be implemented as various types of terminal devices or as a server.

[0036] See also Figure 1 , Figure 1 1 is a schematic diagram of the architecture of a vehicle 100 provided in an embodiment of the present application, showing a domain controller 100-1 in the vehicle 100. The domain controller 100-1 adopts a multi-core chip. Figure 1 The figure shows core 1, core 2, ..., and core N in a multi-core chip by way of example.

[0037] In some embodiments, a core in a multi-core chip may be used as a main core. Figure 1In the example, the main core is taken as core 1. Based on this, the following processing can be implemented through the main core in the multi-core chip: the data status of multiple cores (including the main core itself) in the multi-core chip is detected and processed; wherein the data status is used to characterize whether the data synchronization instruction is valid, and the data synchronization instruction includes data corresponding to the data block identifier; when a synchronization core with a valid data status is detected, the data block usage registry is queried and processed according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core, and the core to be synchronized is obtained; wherein the data block usage registry includes the corresponding relationship between the data block identifier and the core that needs to use the data block; the data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication.

[0038] In some embodiments, the electronic device can implement the cross-core data synchronization method of the multi-core chip provided in the embodiments of the present application by running a computer program. For example, the computer program can be a native program or software module in the operating system; it can be a native application (APP, Application), that is, a program that needs to be installed in the operating system to run. In short, the above-mentioned computer program can be an application, module or plug-in in any form.

[0039] Take the electronic device provided in the embodiment of the present application as an example of a vehicle, see Figure 2 , Figure 2 is a schematic diagram of the structure of a vehicle 100 provided in an embodiment of the present application, Figure 2 The vehicle 100 shown includes: at least one processor 110, a memory 150, at least one network interface 120 and a user interface 130. The various components in the vehicle 100 are coupled together via a bus system 140. It is understood that the bus system 140 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 140 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, the bus system 140 is not described in detail. Figure 2 Various buses are labeled as bus system 140 .

[0040] The processor 110 can be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., where the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0041] The user interface 130 includes one or more output devices 131 that enable presentation of media content, including one or more speakers and / or one or more visual display screens. The user interface 130 also includes one or more input devices 132, including user interface components that facilitate user input, such as microphones, touch screen displays, other input buttons and controls.

[0042] The memory 150 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memory, hard disk drives, etc. The memory 150 may optionally include one or more storage devices that are physically remote from the processor 110.

[0043] The memory 150 includes a volatile memory or a non-volatile storage medium, and may also include both volatile and non-volatile storage media. The non-volatile storage medium may be a read-only memory (ROM), and the volatile memory may be a random access memory (RAM). The memory 150 described in the embodiments of the present application is intended to include any suitable type of memory.

[0044] In some embodiments, the memory 150 can store data to support various operations, examples of which include programs, modules, and data structures, or a subset or superset thereof, as exemplarily described below.

[0045] Operating system 151, including system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks;

[0046] A network communication module 152, used to reach other electronic devices via one or more (wired or wireless) network interfaces 120, exemplary network interfaces 120 include: Bluetooth, Wireless Compatibility Authentication (WiFi), and Universal Serial Bus (USB), etc.;

[0047] a presentation module 153 for enabling presentation of information via one or more output devices 131 (e.g., display screen, speaker, etc.) associated with the user interface 130 (e.g., a user interface for operating peripherals and displaying content and information);

[0048] The input processing module 154 is configured to detect one or more user inputs or interactions from one of the one or more input devices 132 and to translate the detected inputs or interactions.

[0049] In some embodiments, the cross-core data synchronization device of a multi-core chip provided in the embodiments of the present application can be implemented in a software manner. Figure 2 The cross-core data synchronization device 155 of the multi-core chip stored in the memory 150 is shown, which can be software in the form of a program and a plug-in, including the following software modules: a detection module 1551, a query module 1552, and a sending module 1553. These modules are logical, so they can be arbitrarily combined or further split according to the functions implemented. The functions of each module will be explained below.

[0050] The cross-core data synchronization method of a multi-core chip provided in an embodiment of the present application will be explained in combination with the exemplary application and implementation of the electronic device provided in an embodiment of the present application.

[0051] See also Figure 3A , Figure 3A is a flow chart of a cross-core data synchronization method for a multi-core chip provided in an embodiment of the present application, which will be combined with Figure 3A The steps shown are explained.

[0052] In step 101, the data status of multiple cores in the multi-core chip is detected and processed; wherein the data status is used to indicate whether a data synchronization instruction is valid, and the data synchronization instruction includes data corresponding to a data block identifier.

[0053] For each core in the multi-core chip, when a data synchronization instruction is generated, the data state of the core itself will be set to valid, wherein the data synchronization instruction includes data corresponding to the data block identifier (which is also the data that needs to be synchronized). Therefore, the data states of multiple cores in the multi-core chip can be detected and processed. In some embodiments, considering that data synchronization needs to be frequently performed during the operation of the multi-core chip, the data states of multiple cores in the multi-core chip can be detected and processed periodically.

[0054] It is worth noting that the multi-core chip involved in the embodiments of the present application may refer to a multi-core homogeneous chip or a multi-core heterogeneous chip, without limitation.

[0055] In step 102, when a synchronization core whose data status is valid is detected, the data block usage registration table is queried and processed according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core to obtain the core to be synchronized; wherein the data block usage registration table includes the correspondence between the data block identifier and the core that needs to use the data block.

[0056] When a core with valid data status is detected (for easy distinction, the core with valid data status is named as synchronization core), it proves that there is data in the synchronization core that needs to be synchronized. Therefore, the data synchronization instruction of the synchronization core is obtained, and the data block is queried and processed using the registration table according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core to obtain the core to be synchronized. The core to be synchronized is different from the synchronization core; the number of cores to be synchronized can be one or more, and there is no limit on this.

[0057] It is worth noting that the data block usage registry includes the correspondence between the data block identifier and the core that needs to use the data block, and the data block usage registry can be pre-set according to the specific situation of the multi-core chip. For example, the data block usage registry includes "ID1-core 1, core 2" and "ID2-core 2, core 3". On this basis, assuming that the synchronization core is core 1, and the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core is ID1, then by querying the data block usage registry, it can be obtained that the core to be synchronized is core 2; assuming that the synchronization core is core 2, and the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core is ID2, then by querying the data block usage registry, it can be obtained that the core to be synchronized is core 3.

[0058] In some embodiments, for each core in a multi-core chip, the generated data synchronization instruction may be stored in a local memory buffer of the core so as to be retrieved when needed.

[0059] In step 103, the data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication.

[0060] Here, the data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication, thereby realizing cross-core data synchronization.

[0061] In some embodiments, the above steps 101 to 103 can be implemented by a master core in a multi-core chip, that is, unified management and control by the master core can improve the orderliness of cross-core data synchronization. The master core can be any core in the multi-core chip.

[0062] In some embodiments, each core in a multi-core chip runs an operating system, and the operations involved in the embodiments of the present application can be implemented in the operating system running on the core.

[0063] In some embodiments, the multiple cores include a main core and at least one slave core, each of the multiple cores includes a data management module, and the main core also includes a centralized management module; between any steps, the cross-core data synchronization method of the multi-core chip also includes: responding to a data sending instruction through the data management module in any core, generating a data synchronization instruction based on the data sent through the data sending instruction, and setting the data status of any core to valid; the above-mentioned detection and processing of the data status of multiple cores in the multi-core chip can be achieved in this way: detecting and processing the data status of multiple cores through the centralized management module in the main core.

[0064] Here, the multi-core chip includes a master core and at least one slave core; each core in the multi-core chip includes a data management module, and the master core includes a centralized management module in addition to the data management module.

[0065] For any core in the multi-core chip (named as core 1), the data management module in core 1 responds to the data sending instruction, generates a data synchronization instruction according to the data sent by the data sending instruction, and sets the data status of core 1 to valid, wherein the data sending instruction can be triggered by a preset data sending interface in core 1, and the data sending instruction can be triggered by an application module in core 1; for the main core in the multi-core chip, the above steps 101 to 103 are executed by the centralized management module in the main core.

[0066] In the above method, data management within the core is implemented through the data management module in each core, and cross-core data synchronization is achieved through the centralized management module in the main core, which can achieve clear division of labor and improve processing efficiency and accuracy; at the same time, the data management module and the centralized management module in the main core can run in parallel, so that the cross-core data synchronization process will not have an adverse effect on the data management within the main core.

[0067] In some embodiments, when a synchronization core with a valid data state is detected, the cross-core data synchronization method of a multi-core chip also includes: storing the data synchronization instructions of the synchronization core in a global memory buffer, and storing the data synchronization instructions in the global memory buffer in a non-volatile storage medium; between any steps, the cross-core data synchronization method of a multi-core chip also includes: when the multi-core chip is powered on again after being powered off, restoring the data synchronization instructions in the non-volatile storage medium to the global memory buffer, and restoring the data synchronization instructions in the global memory buffer to multiple cores.

[0068] Here, the data synchronization instructions of the synchronization core can be stored in the global memory buffer, and the data synchronization instructions in the global memory buffer can be stored (for example, stored every fixed period) in a non-volatile storage medium. It is worth noting that the global memory buffer refers to a memory buffer accessible to multiple cores (data management modules of multiple cores).

[0069] The non-volatile storage medium has the characteristic that data is not lost after power failure. When the multi-core chip is powered on again after power failure, the non-volatile storage medium still stores data synchronization instructions. Therefore, the data synchronization instructions in the non-volatile storage medium are restored to the global memory buffer, and the data synchronization instructions in the global memory buffer are restored to multiple cores.

[0070] Through the above method, the problem of data loss after power failure of the multi-core chip can be effectively solved, and the effectiveness and accuracy of the restored data synchronization instructions can also be guaranteed.

[0071] In some embodiments, after the data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication, the cross-core data synchronization method of the multi-core chip further includes: setting the data state of the synchronization core to invalid. Here, since the data synchronization instruction of the synchronization core has completed data synchronization, the data state of the synchronization core is set to invalid, thereby ensuring the accuracy of the data state and avoiding resource waste caused by repeated data synchronization for the same data synchronization instruction.

[0072] like Figure 3A As shown, the embodiment of the present application detects and processes the data status of multiple cores in a multi-core chip; wherein the data status is used to characterize whether the data synchronization instruction is valid, and the data synchronization instruction includes data corresponding to the data block identifier; when a synchronization core whose data status is valid is detected, the data block usage registry is queried and processed according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core, and the core to be synchronized is obtained; wherein the data block usage registry includes the correspondence between the data block identifier and the core that needs to use the data block; the data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication. The embodiment of the present application locates the synchronization core that needs to perform data synchronization by detecting the data status, and uniformly sends the data synchronization instruction of the synchronization core to the core to be synchronized through inter-core communication, which can achieve efficient data synchronization on all cores, that is, it can improve the efficiency of data synchronization.

[0073] In some embodiments, see Figure 3B , Figure 3B is a flow chart of a cross-core data synchronization method for a multi-core chip provided in an embodiment of the present application. Figure 3A Step 102 shown can be implemented through steps 201 to 203 .

[0074] In step 201, when multiple synchronization cores with valid data status are detected, timestamps in data synchronization instructions corresponding to the multiple synchronization cores are compared to obtain the latest timestamp.

[0075] Here, the data synchronization instruction includes not only the data corresponding to the data block identifier, but also a timestamp. Based on this, when multiple synchronization cores with valid data status are detected, and the data synchronization instructions corresponding to the multiple synchronization cores respectively include data corresponding to the same data block identifier, the timestamps in the data synchronization instructions corresponding to the multiple synchronization cores are compared and processed to obtain the latest timestamp.

[0076] In some embodiments, before detecting and processing the data status of multiple cores in a multi-core chip, the cross-core data synchronization method of the multi-core chip also includes: initializing the time management module through the main core; responding to the data sending instruction through any core, obtaining a timestamp from the time management module, and forming a data synchronization instruction for any core with the timestamp obtained from the time management module and the data sent through the data sending instruction, and setting the data status of any core to valid.

[0077] Here, the multi-core chip includes a master core and at least one slave core, and the time management module can be initialized by the master core, wherein the time management module is used to provide timestamp services to all cores. Then, for any core (named as core 1) in the multi-core chip, core 1 responds to the data sending instruction, obtains the timestamp from the time management module, and the timestamp obtained from the time management module and the data sent by the data sending instruction constitute the data synchronization instruction of core 1, and at the same time, the data state of core 1 is set to valid. Among them, core 1 can be a master core or a slave core.

[0078] In the above manner, a unified time management module is used to provide a timestamp service, which can ensure the accuracy of the timestamp in the data synchronization instruction generated by each core.

[0079] In some embodiments, multiple synchronization cores with valid data status can be directly detected through step 101; or, when a synchronization core with valid data status is detected through step 101, the data block is queried using a registration table according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core, and the queried core with valid data status is also determined as a synchronization core. The latter method can locate all synchronization cores more quickly by looking up the table.

[0080] In some embodiments, after comparing the timestamps in the data synchronization instructions corresponding to the multiple synchronization cores and obtaining the latest timestamp, the cross-core data synchronization method of the multi-core chip also includes: storing the latest data synchronization instruction in the global memory buffer, and storing the data synchronization instruction in the global memory buffer in a non-volatile storage medium; between any steps, the cross-core data synchronization method of the multi-core chip also includes: when the multi-core chip is powered on again after power failure, restoring the data synchronization instruction in the non-volatile storage medium to the global memory buffer, and restoring the data synchronization instruction in the global memory buffer to multiple cores. Here, only the latest data synchronization instruction is non-volatilely stored, which can achieve accurate data recovery when power is turned on again on the one hand, and save storage space on the other hand, avoiding unnecessary waste of storage resources.

[0081] In step 202, the synchronization core corresponding to the data synchronization instruction including the latest timestamp is determined as the target synchronization core.

[0082] That is, the timestamp in the data synchronization instruction of the target synchronization core is the latest timestamp, and the data synchronization instruction of the target synchronization core is also the latest data synchronization instruction.

[0083] In some embodiments, for other synchronization cores different from the target synchronization core, data synchronization instructions of other synchronization cores do not need to perform data synchronization, so the data status of other synchronization cores can be set to invalid.

[0084] In step 203, a data block usage registration table is queried according to the data block identifier corresponding to the data in the data synchronization instruction of the target synchronization core to obtain the core to be synchronized.

[0085] Here, the core to be synchronized is different from the target synchronization core, and the number of the cores to be synchronized is not limited.

[0086] exist Figure 3B middle, Figure 3A The illustrated step 103 may be updated to step 204. In step 204, the data synchronization instruction of the target synchronization core is sent to the to-be-synchronized core through inter-core communication.

[0087] Here, the data synchronization instruction of the target synchronization core is sent to the core to be synchronized through inter-core communication, thereby achieving data synchronization of the data synchronization instruction of the target synchronization core.

[0088] like Figure 3BAs shown, when there are multiple synchronization cores that need to synchronize data, the embodiment of the present application determines the target synchronization core by comparing the timestamps, and uses the registration table to query the data block according to the data block identifier corresponding to the data in the data synchronization instruction of the target synchronization core, to obtain the core to be synchronized, and finally sends the data synchronization instruction of the target synchronization core to the core to be synchronized through inter-core communication. The embodiment of the present application can support multiple cores to rewrite the same data block, and can ensure the real-time performance of the data synchronization instruction that finally reaches the core to be synchronized.

[0089] In some embodiments, see Figure 3C , Figure 3C is a flow chart of a cross-core data synchronization method for a multi-core chip provided in an embodiment of the present application. Figure 3A After step 103 shown, steps 301 to 303 may also be performed.

[0090] In step 301, the core to be synchronized compares the timestamp in the data synchronization instruction of the synchronization core with the timestamp in the data synchronization instruction of the core to be synchronized to obtain the latest timestamp.

[0091] Here, when the core to be synchronized receives the data synchronization instruction of the synchronization core, and the data synchronization instruction of the synchronization core and the data synchronization instruction of the core to be synchronized both include data corresponding to the same data block identifier, the timestamp in the data synchronization instruction of the synchronization core and the timestamp in the data synchronization instruction of the core to be synchronized are compared to obtain the latest timestamp.

[0092] In step 302, when the data synchronization instruction of the synchronization core includes the latest timestamp, the data synchronization instruction of the core to be synchronized is discarded by the core to be synchronized.

[0093] Here, when the data synchronization instruction of the synchronization core includes the latest timestamp, it is proved that the data synchronization instruction of the core to be synchronized is outdated, and thus the data synchronization instruction of the core to be synchronized is discarded by the core to be synchronized.

[0094] In some embodiments, the data synchronization instructions of the core to be synchronized are stored in the local memory buffer of the core to be synchronized; the above-mentioned discarding of the data synchronization instructions of the core to be synchronized by the core to be synchronized can be achieved in the following manner: the core to be synchronized updates the local memory buffer of the core to be synchronized according to the data synchronization instructions of the synchronization core. That is, the local memory buffer of the core to be synchronized originally stores the data synchronization instructions of the core to be synchronized, and after the update, the local memory buffer of the core to be synchronized stores the data synchronization instructions of the synchronization core, thereby discarding the data synchronization instructions of the core to be synchronized.

[0095] In step 303, when the data synchronization instruction of the to-be-synchronized core includes the latest timestamp, the to-be-synchronized core discards the data synchronization instruction of the synchronization core.

[0096] When the data synchronization instruction of the core to be synchronized includes the latest timestamp, it is proved that the data synchronization instruction of the synchronization core is outdated, and thus the data synchronization instruction of the synchronization core is discarded by the core to be synchronized.

[0097] In some embodiments, when the data synchronization instruction of the core to be synchronized includes the latest timestamp, the cross-core data synchronization method of the multi-core chip further includes: setting the data status of the core to be synchronized to valid by the core to be synchronized.

[0098] Here, when the data synchronization instruction of the core to be synchronized includes the latest timestamp, it proves that the data synchronization instruction of the core to be synchronized needs to be synchronized, and therefore, the data status of the core to be synchronized is set to valid through the core to be synchronized; when the latest data synchronization instruction is the data synchronization instruction of the synchronization core, it proves that the data synchronization instruction of the core to be synchronized is outdated and does not need to be synchronized, and therefore, there is no need to set the data status of the core to be synchronized to valid.

[0099] like Figure 3C As shown, the embodiment of the present application takes into account that each core may generate data synchronization instructions at any time, and the data synchronization instructions of the synchronization core received by the core to be synchronized are not necessarily the latest data synchronization instructions. Therefore, the core to be synchronized compares the timestamps in the data synchronization instructions of the synchronization core and the timestamps in the data synchronization instructions of the core to be synchronized to obtain the latest timestamp, and discards the data synchronization instructions except the latest data synchronization instructions. This can ensure the real-time performance of the data synchronization instructions stored locally in the core to be synchronized, and also avoid unnecessary data occupying storage space.

[0100] In some embodiments, see Figure 3D , Figure 3D is a flow chart of a cross-core data synchronization method for a multi-core chip provided in an embodiment of the present application. Figure 3A After step 103 shown, steps 401 to 402 may also be performed.

[0101] In step 401, the data synchronization instruction of the synchronization core is stored in the local memory buffer through the data management module in the core to be synchronized.

[0102] Here, each core in the multi-core chip includes a data management module and an application module, wherein the application module is used to produce / consume data. Based on this, when the to-be-synchronized core receives the data synchronization instruction of the synchronization core, the data management module in the to-be-synchronized core stores the data synchronization instruction of the synchronization core in the local memory buffer (referring to the local memory buffer of the to-be-synchronized core).

[0103] In step 402, the application module in the core to be synchronized executes the expected action on the data synchronization instruction in the local memory buffer.

[0104] Here, the data synchronization instructions in the local memory buffer are consumed by the application module in the core to be synchronized, that is, the expected actions are executed, such as parsing the data in the data synchronization instructions, or copying the data in the data synchronization instructions to the inside of the application.

[0105] In some embodiments, the above-mentioned execution of the expected action on the data synchronization instruction in the local memory buffer by the application module in the core to be synchronized can be achieved in the following manner: performing any one of the following processing: querying and processing the local memory buffer by the application module in the core to be synchronized, and executing the expected action on the queried data synchronization instruction; calling back the function registered by the application module in the core to be synchronized by the data management module in the core to be synchronized, so as to execute the expected action on the data synchronization instruction in the local memory buffer.

[0106] Here, the local memory buffer can be queried and processed by the application module in the core to be synchronized, and the expected action can be performed on the queried data synchronization instruction. This method is actively queried by the application module, and it independently decides whether to perform the expected action, which is suitable for scenarios where the application module is more proactive. Among them, the buffer status of the local memory buffer can be used to reflect whether the local memory buffer stores valid data synchronization instructions. The buffer status of the local memory buffer includes two types: waiting for data synchronization and data synchronization completed. For example, for the data management module in the core to be synchronized, when the data synchronization instruction of the synchronization core is stored in the local memory buffer, the buffer status of the local memory buffer is set from waiting for data synchronization to data synchronization completed; for the application module in the core to be synchronized, the buffer status of the local memory buffer is first queried, and when the buffer status of the local memory buffer is data synchronization completed, the data synchronization instruction in the local memory buffer is queried. In this way, the validity of the data synchronization instruction queried by the application module can be guaranteed.

[0107] Alternatively, the data management module in the core to be synchronized calls back the function registered by the application module in the core to be synchronized to execute the expected action on the data synchronization instruction in the local memory buffer. This method automatically triggers the execution of the expected action through the callback function, has a high degree of automation and a fast response speed.

[0108] In actual application scenarios, you can choose any of the above two methods according to actual needs.

[0109] like Figure 3DAs shown, in the embodiment of the present application, the data management module in the core to be synchronized stores the data synchronization instructions of the synchronization core in the local memory buffer, thereby realizing temporary storage of the data synchronization instructions so that the application module in the core to be synchronized can use them; and then the application module in the core to be synchronized executes the expected action on the data synchronization instructions in the local memory buffer to realize data consumption, so that the application function can be realized normally.

[0110] The following will describe an exemplary application of the embodiment of the present application in a practical application scenario. The operations involved in the embodiment of the present application may be implemented in an operating system (OS) running on a core. Figure 4 The schematic diagram of the internal modules of the operating system is shown, and an example is provided through the following steps.

[0111] Step 1) Generate a data block usage registration table according to functional requirements, and generate interfaces for accessing data in each OS, such as a data sending interface, a data receiving interface, and a data status query interface. Each OS runs in one core of a multi-core chip.

[0112] Step 2) Generate a callback function interface in each OS.

[0113] Step 3) Select one OS as the master OS (corresponding to the master core above), and other OSs as slave OSs (corresponding to the slave cores above). In the embodiment of the present application, OS1 is used as the master OS, and OS2 is used as the slave OS for illustration.

[0114] Step 4) When OS1 is initialized, it creates a global buff (corresponding to the global memory buffer mentioned above) according to the data block usage registry. The global buff includes a data segment and a timestamp segment. The data segment is used to store data corresponding to the data block identifier in the data block usage registry.

[0115] Step 5) When each OS is initialized, it uses the registry to create a local buff (corresponding to the local memory buffer above) according to the data block, such as local buff1 in OS1 and local buff2 in OS2.

[0116] Step 6) Each OS establishes inter-core communication during initialization.

[0117] Step 7) Initialize the time management module in OS1 and provide a timestamp acquisition function to all OSs. It is worth noting that the time management module is located inside OS1. Figure 4 The time management module is shown separately only for the convenience of explanation.

[0118] Step 8) When the application module 1 in OS1 sends data 1 by calling the data sending interface, the data management module 1 in OS1 obtains the timestamp 1 from the time management module, combines the data 1 and the timestamp 1 into a data synchronization instruction 1, fills it into the local buff1 in OS1, and sets the data status to valid.

[0119] Step 9) When the application module 2 in OS2 sends data 2 by calling the data sending interface, the data management module 2 in OS2 obtains the timestamp 2 from the time management module, combines the data 2 and the timestamp 2 into a data synchronization instruction 2, fills it into the local buff2 in OS2, and sets the data status to valid.

[0120] Step 10) The centralized management module in OS1 runs periodically, and detects the data status of each OS during each run. If the data status of a certain OS is detected to be valid, the data block usage registry is queried according to the data block identifier corresponding to the data in the data synchronization instruction of the OS, and the OS information to which the data block identifier belongs is obtained (in the example, OS1 and OS2 are both belonging OSs), and the timestamps of the data synchronization instructions in multiple belonging OSs with valid data status are compared, and the OS corresponding to the data synchronization instruction including the latest timestamp is determined as the target OS, and finally the data synchronization instruction of the target OS is sent to other belonging OSs (data management modules of other belonging OSs) through inter-core communication. As an example, the embodiment of the present application provides the following Figure 5 The flowchart of the centralized management module operation process is shown.

[0121] In the embodiment of the present application, assuming that the data state of OS1 and the data state of OS2 are both valid, and the data synchronization instruction 1 of OS1 and the data synchronization instruction 2 of OS2 both include data corresponding to the same data block identifier, the centralized management module in OS1 compares the timestamps in the two data synchronization instructions, determines the OS corresponding to the data synchronization instruction including the latest timestamp as the target OS, and sends the data synchronization instruction of the target OS to another OS through inter-core communication. For example, if the timestamp 1 in the data synchronization instruction 1 is newer than the timestamp 2 in the data synchronization instruction 2, OS1 is determined as the target OS, and the data synchronization instruction of the target OS (i.e., the data synchronization instruction 1 of OS1) is sent to another OS (i.e., OS2) through inter-core communication.

[0122] Step 11) The centralized management module in OS1 writes the data synchronization instruction of the target OS into the global buff.

[0123] Step 12) When the data management module 1 in OS1 receives the data synchronization instruction, it writes the received data synchronization instruction into the local buff1 and sets the buffer status from waiting for data synchronization to data synchronization completed so that the application module 1 in OS1 can query.

[0124] Step 13) When the data management module 2 in OS2 receives the data synchronization instruction, it writes the received data synchronization instruction into the local buff2, and sets the buffer status from waiting for data synchronization to data synchronization completed, so that the application module 2 in OS2 can query.

[0125] Step 14) The application module 1 in OS1 can determine whether to execute the expected action of the application by querying the buffer status of the local buff1. For example, when the application module 1 in OS1 queries that the buffer status of the local buff1 is data synchronization completed, it further queries the data synchronization instruction in the local buff1 and executes the expected action of the application; or, the data management module 1 in OS1 executes the expected action of the application by calling back the function registered by the application module 1 (the callback can be implemented through the callback function interface in step 2)), which can further improve the timeliness of data synchronization.

[0126] Step 15) The application module 2 in OS2 can determine whether to execute the expected action of the application by querying the buffer status of the local buff2. For example, when the application module 2 in OS2 queries that the buffer status of the local buff2 is data synchronization completed, it further queries the data synchronization instruction in the local buff2 and executes the expected action of the application; or, the data management module 2 in OS2 executes the expected action of the application by calling back the function registered by the application module 2 (the callback can be implemented through the callback function interface in step 2)), which can further improve the timeliness of data synchronization.

[0127] Step 16) The data synchronization instructions in the global buff can be written to the non-volatile storage medium at an appropriate time (e.g., every fixed period). In this way, the data synchronization instructions can be saved when the power is off, and when the next power-on cycle arrives, the data synchronization instructions in the non-volatile storage medium can be restored to the global buff, and then the data synchronization instructions in the global buff can be restored to all OSes.

[0128] In some embodiments, for an OS that receives a data synchronization instruction, a comparison can be performed between the timestamp in the received data synchronization instruction and the timestamp in the data synchronization instruction generated by the OS to obtain the latest timestamp; when the received data synchronization instruction includes the latest timestamp, the local buff is updated according to the received data synchronization instruction, i.e., the data synchronization instruction originally stored in the local buff (i.e., the data synchronization instruction generated by the OS) is replaced; when the data synchronization instruction generated by the OS includes the latest timestamp, since the data synchronization instruction generated by the OS has been stored in the local buff, the received data synchronization instruction can be directly discarded, and at the same time, the data status of the OS is set to valid.

[0129] The embodiments of the present application can at least achieve the following technical effects:

[0130] 1) By using the centralized management module in conjunction with the data block registry, data status can be quickly obtained and data synchronization can be achieved in a timely manner. Multiple OSs are supported to rewrite the same data block, and the latest rewritten data can be quickly synchronized to all OSes.

[0131] 2) Application functions can be easily ported from a single OS platform to a cross-OS platform with minimal changes, saving time for secondary development and porting verification.

[0132] 3) The realization of cross-OS multi-application collaboration no longer requires consideration of data synchronization strategies, thus simplifying the complexity of application development and design.

[0133] 4) The inter-core communication hardware resources of a multi-core chip are precious. If multiple applications have the need to synchronize data across OSs, only one set of inter-core communication resources is needed in the embodiment of the present application to support both applications at the same time, which results in a relatively low implementation cost.

[0134] 5) In the embodiment of the present application, if there is a need for data storage, it is only necessary to set up a storage medium (such as a non-volatile storage medium) on the hardware, without setting up an independent storage medium for each OS.

[0135] The following is a description of an exemplary structure of a multi-core chip cross-core data synchronization device 155 provided in an embodiment of the present application implemented as a software module. In some embodiments, Figure 2 As shown, the software modules in the cross-core data synchronization device 155 of the multi-core chip stored in the memory 150 may include: a detection module 1551, which is used to detect and process the data status of multiple cores in the multi-core chip; wherein the data status is used to characterize whether the data synchronization instruction is valid, and the data synchronization instruction includes data corresponding to the data block identifier; a query module 1552, which is used to query and process the data block usage registry according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core when a synchronization core with a valid data status is detected, so as to obtain the core to be synchronized; wherein the data block usage registry includes the correspondence between the data block identifier and the core that needs to use the data block; a sending module 1553, which is used to send the data synchronization instruction of the synchronization core to the core to be synchronized through inter-core communication.

[0136] In some embodiments, the data synchronization instruction also includes a timestamp, the number of synchronization cores includes multiple, and the data synchronization instructions corresponding to the multiple synchronization cores respectively include data corresponding to the same data block identifier; the cross-core data synchronization device 155 of the multi-core chip also includes a first comparison module, which is used to: compare the timestamps in the data synchronization instructions corresponding to the multiple synchronization cores respectively to obtain the latest timestamp; determine the synchronization core corresponding to the data synchronization instruction including the latest timestamp as the target synchronization core; the query module 1552 is also used to: query the data block using a registration table according to the data block identifier corresponding to the data in the data synchronization instruction of the target synchronization core to obtain the core to be synchronized; the sending module 1553 is also used to: send the data synchronization instruction of the target synchronization core to the core to be synchronized through inter-core communication.

[0137] In some embodiments, the multiple cores include a master core and at least one slave core; the cross-core data synchronization device 155 of the multi-core chip also includes a timestamp acquisition module, which is used to: initialize the time management module through the master core; obtain a timestamp from the time management module in response to a data sending instruction through any core, and form a data synchronization instruction of any core with the timestamp obtained from the time management module and the data sent through the data sending instruction, and set the data status of any core to valid.

[0138] In some embodiments, the cross-core data synchronization device 155 of the multi-core chip also includes a positioning module, which is used to: when a synchronization core with a valid data status is detected, query and process the data block using a registration table according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core, and determine the queried core with a valid data status as a new synchronization core.

[0139] In some embodiments, the data synchronization instruction also includes a timestamp; the data synchronization instruction of the synchronization core and the data synchronization instruction of the core to be synchronized both include data corresponding to the same data block identifier; the cross-core data synchronization device 155 of the multi-core chip also includes a second comparison module, which is used to: compare the timestamp in the data synchronization instruction of the synchronization core and the timestamp in the data synchronization instruction of the core to be synchronized through the core to be synchronized to obtain the latest timestamp; the cross-core data synchronization device 155 of the multi-core chip also includes a discard module, which is used to: when the data synchronization instruction of the synchronization core includes the latest timestamp, discard the data synchronization instruction of the core to be synchronized; when the data synchronization instruction of the core to be synchronized includes the latest timestamp, discard the data synchronization instruction of the synchronization core.

[0140] In some embodiments, the cross-core data synchronization device 155 of the multi-core chip also includes a setting module for: when the data synchronization instruction of the core to be synchronized includes the latest timestamp, setting the data status of the core to be synchronized to valid through the core to be synchronized.

[0141] In some embodiments, the core to be synchronized includes a data management module and an application module; the cross-core data synchronization device 155 of the multi-core chip also includes a first storage module, which is used to: store the data synchronization instructions of the synchronization core into the local memory buffer through the data management module in the core to be synchronized; the cross-core data synchronization device 155 of the multi-core chip also includes an application execution module, which is used to: execute the expected action on the data synchronization instructions in the local memory buffer through the application module in the core to be synchronized.

[0142] In some embodiments, the application execution module is also used to perform any of the following processing: querying and processing the local memory buffer through the application module in the core to be synchronized, and executing the expected action on the queried data synchronization instruction; calling back the function registered by the application module in the core to be synchronized through the data management module in the core to be synchronized, so as to execute the expected action on the data synchronization instruction in the local memory buffer.

[0143] In some embodiments, the multiple cores include a main core and at least one slave core, each of the multiple cores includes a data management module, and the main core also includes a centralized management module; the cross-core data synchronization device 155 of the multi-core chip also includes a data sending module, which is used to: respond to a data sending instruction through the data management module in any core, generate a data synchronization instruction according to the data sent through the data sending instruction, and set the data status of any core to valid; the detection module 1551 is also used to: detect and process the data status of multiple cores through the centralized management module in the main core.

[0144] In some embodiments, the cross-core data synchronization device 155 of the multi-core chip also includes a second storage module, which is used to: store the data synchronization instructions of the synchronization core into the global memory buffer, and store the data synchronization instructions in the global memory buffer into a non-volatile storage medium; the cross-core data synchronization device 155 of the multi-core chip also includes a data recovery module, which is used to: when the multi-core chip is powered on again after power failure, restore the data synchronization instructions in the non-volatile storage medium to the global memory buffer, and restore the data synchronization instructions in the global memory buffer to multiple cores.

[0145] The embodiment of the present application provides a computer program product or a computer program, which includes executable instructions, and the executable instructions are stored in a computer-readable storage medium. The processor of the electronic device reads the executable instructions from the computer-readable storage medium, and the processor executes the executable instructions, so that the electronic device implements the cross-core data synchronization method of the multi-core chip described in the embodiment of the present application.

[0146] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, wherein executable instructions are stored. When the executable instructions are executed by a processor, the processor will implement the cross-core data synchronization method of a multi-core chip provided in an embodiment of the present application.

[0147] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface storage, optical disk, or CD-ROM; or it may be various devices including one or any combination of the above memories.

[0148] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0149] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0150] As an example, the executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed at multiple sites and interconnected by a communication network.

[0151] The above are only embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A cross-core data synchronization method for a multi-core chip, characterized in that: include: Detecting and processing the data status of multiple cores in a multi-core chip; wherein the data status is used to indicate whether a data synchronization instruction is valid, and the data synchronization instruction includes data corresponding to a data block identifier; When a synchronization core with a valid data state is detected, a data block usage registration table is queried and processed according to a data block identifier corresponding to the data in the data synchronization instruction of the synchronization core to obtain a core to be synchronized; wherein the data block usage registration table includes a correspondence between a data block identifier and a core that needs to use the data block; The data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication.

2. The method according to claim 1, characterized in that: The data synchronization instruction also includes a timestamp, the number of the synchronization cores includes multiple, and the data synchronization instructions corresponding to the multiple synchronization cores respectively include data corresponding to the same data block identifier; before querying the data block using a registration table according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core, the method also includes: Comparing the timestamps in the data synchronization instructions respectively corresponding to the multiple synchronization cores to obtain the latest timestamp; Determine the synchronization core corresponding to the data synchronization instruction including the latest timestamp as the target synchronization core; The querying and processing of the data block usage registration table according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core to obtain the core to be synchronized includes: According to the data block identifier corresponding to the data in the data synchronization instruction of the target synchronization core, the data block usage registration table is queried and processed to obtain the core to be synchronized; The step of sending the data synchronization instruction of the synchronization core to the core to be synchronized through inter-core communication includes: The data synchronization instruction of the target synchronization core is sent to the core to be synchronized through inter-core communication.

3. The method according to claim 2, characterized in that The plurality of cores include a master core and at least one slave core; the method further includes: Initialize a time management module through the main core; In response to a data sending instruction, any core obtains a timestamp from the time management module, and the timestamp obtained from the time management module and the data sent by the data sending instruction form a data synchronization instruction for the any core, and the data status of the any core is set to valid.

4. The method according to claim 2, characterized in that When the data state is detected as a valid synchronization core, the method further includes: The data block usage registration table is queried and processed according to the data block identifier corresponding to the data in the data synchronization instruction of the synchronization core, and the queried core with valid data status is determined as the synchronization core.

5. The method according to claim 1, characterized in that: The data synchronization instruction also includes a timestamp; the data synchronization instruction of the synchronization core and the data synchronization instruction of the core to be synchronized both include data corresponding to the same data block identifier; after the data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication, the method also includes: The following processing is performed by the core to be synchronized: Comparing the timestamp in the data synchronization instruction of the synchronization core and the timestamp in the data synchronization instruction of the core to be synchronized to obtain the latest timestamp; When the data synchronization instruction of the synchronization core includes the latest timestamp, discarding the data synchronization instruction of the core to be synchronized; When the data synchronization instruction of the core to be synchronized includes the latest timestamp, the data synchronization instruction of the synchronization core is discarded.

6. The method according to claim 5, characterized in that When the data synchronization instruction of the core to be synchronized includes the latest timestamp, the method further includes: The data state of the core to be synchronized is set to be valid through the core to be synchronized.

7. The method according to claim 1, characterized in that The core to be synchronized includes a data management module and an application module; after the data synchronization instruction of the synchronization core is sent to the core to be synchronized through inter-core communication, the method further includes: The data management module in the core to be synchronized stores the data synchronization instruction of the synchronization core into the local memory buffer; The expected action is executed on the data synchronization instruction in the local memory buffer by the application module in the core to be synchronized.

8. The method according to claim 7, characterized in that The executing of the expected action on the data synchronization instruction in the local memory buffer by the application module in the core to be synchronized includes: Perform any of the following: Perform query processing on the local memory buffer through the application module in the core to be synchronized, and execute expected actions on the queried data synchronization instructions; The function registered by the application module in the core to be synchronized is called back by the data management module in the core to be synchronized, so as to execute the expected action on the data synchronization instruction in the local memory buffer.

9. The method according to claim 1, characterized in that: The multiple cores include a master core and at least one slave core, each of the multiple cores includes a data management module, and the master core also includes a centralized management module; the method further includes: In response to the data sending instruction, a data management module in any core generates a data synchronization instruction according to the data sent by the data sending instruction, and sets the data state of the any core to be valid; The detecting and processing of the data states of multiple cores in the multi-core chip includes: The data status of the multiple cores is detected and processed through the centralized management module in the main core.

10. The method according to claim 1, characterized in that When the data state is detected as a valid synchronization core, the method further includes: Storing the data synchronization instructions of the synchronization core in a global memory buffer, and storing the data synchronization instructions in the global memory buffer in a non-volatile storage medium; The method further comprises: When the multi-core chip is powered on again after being powered off, the data synchronization instructions in the non-volatile storage medium are restored to the global memory buffer, and the data synchronization instructions in the global memory buffer are restored to the multiple cores.

11. A cross-core data synchronization device for a multi-core chip, characterized in that: include: A detection module is used to detect and process the data status of multiple cores in the multi-core chip; wherein the data status is used to indicate whether the data synchronization instruction is valid, and the data synchronization instruction includes data corresponding to the data block identifier; A query module, for, when a synchronization core with a valid data status is detected, querying a data block usage registration table according to a data block identifier corresponding to the data in a data synchronization instruction of the synchronization core, to obtain a core to be synchronized; wherein the data block usage registration table includes a correspondence between a data block identifier and a core that needs to use the data block; The sending module is used to send the data synchronization instruction of the synchronization core to the core to be synchronized through inter-core communication.

12. A multi-core chip, characterized in that: The multi-core chip includes executable instructions, and the multi-core chip runs in an electronic device to implement the method according to any one of claims 1 to 10.

13. An electronic device, characterized in that: include: A memory for storing executable instructions; A processor, configured to implement the method according to any one of claims 1 to 10 when executing the executable instructions stored in the memory.

14. A computer-readable storage medium, characterized in that: Executable instructions are stored, and when executed by a processor, the method described in any one of claims 1 to 10 is implemented.

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