A signal retrieval method based on FPGA

Abstract

The present invention discloses a signal retrieval method based on FPGA, including: channelizing the signal after N pulse signals are superimposed, using the advantage of FPGA parallel processing, performing signal detection on the multi-channel parallel frequency domain complex signals output by the channelization, and using N registers in the signal retrieval module circuit to respectively record the starting channel, starting frequency, starting time, ending channel, ending frequency and ending time of each existing signal according to the detection result; if a certain signal disappears, the starting data and ending data in the corresponding register are read out and cleared, and the empty register waits for the next valid signal starting data and ending data to be stored, and the register write and read data operations are repeatedly executed to realize the signal retrieval function. The signal retrieval module circuit of multi-channel parallel signals designed by the present invention realizes real-time retrieval of pulse signals, so as to effectively solve the problem of long time consumption in extracting parameters of pulse signals.

Description

Technical Field

[0001] The present invention relates to the field of electronic countermeasures, and more specifically, to a signal retrieval method based on FPGA. Background Art

[0002] The development of radar technology has made various test signals complex and changeable, with wide frequency band, large dynamic range and instantaneous and changeable characteristics. In addition, the superposition of various signals (such as linear frequency modulation signals, phase coded signals, single carrier frequency signals, repetition frequency difference signals, etc.) has become endless, making the electromagnetic environment more complicated, resulting in the inability to analyze the superimposed signals well, which may lead to misjudgment or missed judgment during analysis, or interference from other signals, resulting in erroneous results.

[0003] Therefore, in order to efficiently analyze multi-path parallel multi-system signals within the instantaneous bandwidth, a new method is used to realize parallel signal processing and analysis, which is of great significance in electronic warfare receivers. Summary of the invention

[0004] In view of the above shortcomings of the prior art, the present invention aims to propose a signal retrieval method based on FPGA. By taking advantage of the parallel computing of FPGA, signal retrieval is performed on the multi-channel parallel signal obtained by superimposing N pulse signals to obtain the starting frequency, starting time, ending frequency and ending time and other parameters of the signal, thereby laying a foundation for the subsequent acquisition of pulse signal parameters and better analysis of pulse signals.

[0005] To achieve the above object, the implementation scheme of the present invention includes the following:

[0006] A signal retrieval method based on FPGA is implemented by the following steps:

[0007] Step 1: Channelize the signal after N pulse signals are superimposed to obtain a frequency domain complex signal , the formula is as follows:

[0008]

[0009] Where: n is the time point; k is the channel number; j is the imaginary unit; is the frequency domain complex signal of the kth channel at time n, is the window function, whose width is N;

[0010] Step 2: Channelize the output of multiple parallel frequency domain complex signals Perform signal detection based on the set detection threshold , With detection threshold Compare to detect whether there is a signal in each channel, where n is the time point and k is the channel number;

[0011] Step 3: If the mth road Greater than or equal to the detection threshold , the corresponding sig_valid_m will be set to a high level, marking the location of the signal in the m-th parallel signal, where m=0,1······N-1, and sig_valid_0~sig_valid_N-1 are ORed to obtain sig_valid; the number of channels, frequency, and time of each frequency-domain complex signal are integrated into a 75-bit frame, and there are N such frames; the state machine is used to perform logical control on signal retrieval. Under the condition that sig_valid is a high level, according to the judgment conditions of the same signal, the signals stored in the N registers are searched. If the number of channels of the currently detected signal differs from the number of starting channels or the number of ending channels stored in the a-th register by no more than 2 , then it is determined to be the same signal, or the frequency of the currently detected signal is between the starting frequency and the ending frequency stored in the ath register, it is also determined to be the same signal. One of the above two conditions can be met, where a=0, 1...N-1; and the channel number, frequency and time of the currently detected signal are used to update the register; until the stored signal in the N registers disappears, the register data corresponding to the disappeared signal is read out and cleared, waiting for the next valid signal parameter to be stored in the empty register. The signals in other registers have not disappeared, and the register data is not read out and cleared; the above signal judgment operation is repeatedly performed, and the signal retrieval operation can be performed in real time to realize the storage of the starting data and the ending data of the pulse signal.

[0012] Further, in step 3, the state machine of the signal retrieval module circuit has three states: Idle state, Sig_valid state, and Sig_disappear state; wherein: the Idle state is an idle state, and no specific task is executed. When the logic in the Idle state is executed, it jumps to the Sig_valid state; in the Sig_valid state, the signal judgment and the update of the signal parameters in the N registers are performed to realize the signal retrieval function:

[0013] (1) If the number of channels of the signal detected under the current clock does not differ from the number of channels stored in the a-th register by more than 2, the currently detected signal is the same as the signal in the register. The parameters of the signal in the a-th register are updated with the parameters of the currently detected signal, and sig_valid_flag[a] and memory_valid[a] are set to high, where a=0,1······N-1;

[0014] (2) If the frequency of the signal detected under the current clock is within the range of the start frequency and the end frequency stored in the a-th register, the currently detected signal and the signal stored in the a-th register are the same signal. The parameters of the signal in the a-th register are updated with the parameters of the currently detected signal, and sig_valid_flag[a] and memory_valid[a] are set to high level, where a=0,1······N-1;

[0015] (3) If either of the above two conditions is met, the signal parameters in the corresponding register can be updated. If neither of the above conditions is met, it can be determined that the currently detected signal is a new signal, and an empty register is searched among the 10 registers, and the channel number, frequency, and time of the currently detected signal are stored in the empty register.

[0016] Furthermore, in step three, in the Sig_valid state, at the end of a frame where FFT ends, if the condition sig_valid_flag[a]=0&memory_valid[a]=1 is satisfied, it means that the signal in the ath register disappears, and the value of a is assigned to index, and the process jumps to the Sig_disappear state, where a=0,1······N-1; otherwise, the logic in the Sig_valid state continues to be executed until the jump condition is met.

[0017] Furthermore, in step three, after the Sig_valid state jumps to the Sig_disappear state, the signal parameters stored in memory[index] are read out, and the register memory[index] data is cleared, sig_valid_flag[index] and memory_valid[index] are set to a low level, and the state is jumped to the Idle state to complete the retrieval of a complete signal; the above signal judgment operation is repeated, and the state machine jumps back and forth until all signals are retrieved.

[0018] Technical effects and advantages of the present invention:

[0019] 1. The signal retrieval method based on FPGA provided by the present invention realizes multi-channel signal separation by performing multi-channel real-time parallel signal detection on the time-frequency domain complex signal output by digital channelization, accurately and quickly marks the time-frequency domain position of the target signal and the occupied time-frequency domain interval, so as to facilitate the subsequent completion of pulse parameter measurement and further processing; the retrieved signal can filter out the out-of-band component to reduce the sampling rate, save computing and storage resources, and improve the efficiency and performance of the system.

[0020] 2. According to the signal detection results and signal judgment conditions, the start data and end data of the signal in the pulse parameter register are updated in real time until a certain signal disappears, completing a complete signal retrieval operation; effectively performing real-time retrieval of multiple parallel signals to avoid the loss of signal information, and being able to retrieve N signals in real time and store effective signal information, with a high module reuse rate, solving the problems of long time consumption and high resource consumption in real-time retrieval of multiple parallel signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of a signal retrieval method based on FPGA of the present invention;

[0022] Figure 2 It is a state machine jump flow chart of a signal retrieval method implemented based on FPGA of the present invention;

[0023] Figure 3 It is a flow chart of signal retrieval of a signal retrieval method based on FPGA implementation of the present invention;

[0024] Figure 4 The present invention discloses a flow chart of signal criteria and parameter updating of a signal retrieval method based on FPGA. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The number of registers involved in the present invention may be N, that is, an infinite number. For ease of understanding, the embodiment of the present invention only lists 10 register numbers a=0, 1...9, 16 parallel signal paths m=0, 1...15, and 10 register numbers b=0, 1...9, which are described in detail as follows:

[0027] See also Figure 1As shown, the present invention is a signal retrieval method based on FPGA. The signal used for testing is a signal formed by superimposing ten pulse signals. After the superimposed signal is processed by channelization reception, signal detection, etc., according to the result of signal detection, the start data and end data of the valid signal are stored in registers 0 to 9 respectively, and the data in the register is continuously updated until a signal disappears. The data in the register where the disappeared signal is located is read out and cleared to realize the retrieval of a complete signal. The empty register waits for the next valid signal data to be stored, and this signal retrieval operation is performed repeatedly;

[0028] The specific implementation includes the following steps:

[0029] Step 1: Digital channelization processing

[0030] The broadband pulse signal is digitally channelized by using a 256-point windowed, 50% overlapped fast Fourier transform to divide the signal sampling frequency Fs into 256 subchannels. The bandwidth of each subchannel is Fs / 256, and the frequency of the kth channel is k* Fs / 256.

[0031] The signal after N pulse signals are superimposed is channelized to obtain a frequency domain complex signal , the formula is as follows:

[0032]

[0033] Where: n is the time point; k is the channel number; j is the imaginary unit; is the frequency domain complex signal of the kth channel at time n, is the window function, whose width is N;

[0034] Step 2: Signal detection and processing

[0035] Channelized output of multiple parallel frequency domain complex signals Perform signal detection based on the set detection threshold , With detection threshold Compare to detect whether there is a signal in each channel, where n is the time point and k is the channel number;

[0036] After digital channelization processing, 16 parallel frequency domain complex signals are obtained. , perform modulus processing in FPGA to obtain 16 parallel amplitudes ; Compare the amplitude value of each channel with the set detection threshold For comparison, if the mth road Greater than or equal to the detection threshold, in the Moment At the subchannel, sig_valid_m is set to 1 to mark the location where the signal exists in the mth channel; otherwise, sig_valid_m is set to 0, where m=0, 1······15, =1, 2······256; perform OR operation on sig_valid_0~sig_valid_15 to obtain sig_valid, and concatenate sig_valid_0~sig_valid_15 to obtain 16-bit detection_data; integrate the channel number, frequency and time of each frequency domain complex signal into 75-bit framing data, and there are 16 such framings.

[0037] Step 3: Signal retrieval

[0038] See the signal retrieval flowchart for Figure 3 As shown, the state machine is used to store 16 frame data to realize the storage of effective signal data. The jump flow chart of the state machine is shown in FIG. Figure 2 As shown;

[0039] The signal retrieval module circuit comprises:

[0040] Perform signal detection on each of the multiple parallel frequency domain complex signals. If the mth channel Greater than or equal to the detection threshold , the corresponding sig_valid_m will be set to a high level, marking the location of the signal in the mth parallel signal, where m=0,1······15, and sig_valid_0~sig_valid_15 are calculated to obtain sig_valid; the number of channels, frequency, and time of each frequency-domain complex signal are integrated into a 75-bit frame, and there are 16 such frames; the state machine is used to perform logical control on the signal retrieval, and under the condition that sig_valid is a high level, according to the judgment conditions of the same signal, the signals stored in the 10 registers are searched. If the number of channels of the currently detected signal differs from the starting channel number or the ending channel number stored in the ath register by no more than 2, it is determined to be the same signal, or the frequency of the currently detected signal is the starting frequency stored in the ath register. and the ending frequency, it is also determined to be the same signal, and one of the above two conditions can be met, where a=0, 1...9; according to the result of signal detection, 10 registers are used in the signal retrieval module circuit to store the signal parameters of 10 signals respectively (starting channel number, starting frequency, starting time, ending channel number, ending frequency, ending time), and the signal parameters of subsequent existing signals are continuously used to update the signal parameters in the corresponding registers; until the stored signal in the 10 registers disappears, the register data corresponding to the disappeared signal is read out and cleared, waiting for the next valid signal parameter to be stored in the empty register, the signals in other registers have not disappeared, and the register data is not read out and cleared; the above signal judgment operation is repeatedly performed, and the signal retrieval operation can be performed in real time to realize the storage of the starting data and ending data of the pulse signal.

[0041] The decision conditions of the same signal include:

[0042] If the number of channels of the signal detected under the current clock differs from the number of channels stored in the a-th register by no more than 2, the currently detected signal and the signal in the register are the same signal, and the parameters of the signal in the a-th register are updated with the parameters of the currently detected signal, where a=0,1······9; if the current judgment condition is not met, the next judgment condition is executed;

[0043] If the frequency of the signal detected under the current clock is within the range of the start frequency and the end frequency stored in the a-th register, the currently detected signal and the signal stored in the a-th register are the same signal, and the parameters of the signal in the a-th register are updated with the parameters of the currently detected signal, where a=0, 1······9;

[0044] If either of the above two conditions is met, the signal parameters in the corresponding register can be updated; if neither of the above two conditions is met, the currently detected signal is judged to be a newly appeared signal, an empty register is searched among the 10 registers, and the channel number, frequency and time of the currently detected signal are stored in the empty register.

[0045] The state machine of the signal retrieval module circuit includes:

[0046] The state machine in the signal retrieval module circuit has three states, namely, Idle state, Sig_valid state, and Sig_disappear state;

[0047] The Idle state is an idle state, and no specific task is executed. When the logic in the Idle state is executed, it jumps to the Sig_valid state; in the Sig_valid state, when sig_valid is high, the signal is judged, refer to Figure 4 As shown, there are three situations:

[0048] (1) If the number of channels of the signal detected under the current clock does not differ from the starting channel number or the ending channel number in the a-th register by more than 2, the currently detected signal is the same as the signal in the register, and sig_valid_flag[a] and memory_valid[a] are set to high level; if the frequency of the currently detected signal is smaller than the starting frequency in the a-th register, the frequency and number of channels of the currently detected signal are used to update the starting frequency and the starting channel number of the signal in the a-th register; if the frequency of the currently detected signal is larger than the ending frequency in the a-th register, the current frequency and number of channels of the signal are used to update the starting frequency and the starting channel number of the signal in the a-th register. The frequency and channel number of the previously detected signal are used to update the end frequency and end channel number of the signal in the ath register; otherwise, if the above two conditions are not met, the start channel number, start time, start frequency, end channel number and end frequency in the ath register remain unchanged; search for the number of bits with high level in the 16-bit detection_data data, and find the largest number of bits m. If the time of the mth signal is greater than the end time in the ath register, use the time of the mth signal to update the end time in the ath register; where a=0, 1······9, m=0, 1······15;

[0049] (2) If the frequency of the signal detected under the current clock is between the start frequency and the end frequency in the ath register, the currently detected signal is the same as the signal in the register, sig_valid_flag[a] and memory_valid[a] are set to high level, and the values ​​of the start channel number, start frequency, start time, end channel number and end frequency in the ath register remain unchanged; search for the number of bits with high level in the 16-bit detection_data data, and find the largest number of bits m. If the time of the mth signal is greater than the end time in the ath register, use the time of the mth signal to update the end time in the ath register; where a=0, 1······9, m=0, 1······15;

[0050] (3) If the currently detected signal does not meet the above two conditions, and the same signal cannot be found in the ten registers, the currently detected signal is judged as a newly appeared signal; search for the number of high-level bits in the 16-bit detection_data data, find the maximum number of bits max and the minimum number of bits min, and store the channel number, frequency, time of the min-th channel and the channel number, frequency, time of the max-th channel in the empty register b; where min = 0, 1······15, max = 0, 1······15, b = 0, 1······9;

[0051] Among them, the jump of the state machine adopts the following method:

[0052] After the Idle state instruction is executed, it jumps to the Sig_valid state; in the Sig_valid state, when the end of a frame of FFT is detected, if the condition of sig_valid_flag[a]=0&memory_valid[a]=1 is met, it means that the signal in the ath register disappears, and the value of a is assigned to index, and it jumps to the Sig_disappear state, where a=0,1······9; otherwise, the signal decision logic in the Sig_valid state continues to be executed until the jump condition is met;

[0053] After the Sig_valid state jumps to the Sig_disappear state, the data stored in the register memory[index] is read out to provide parameters for the subsequent signal analysis. The register memory[index] data is cleared, sig_valid_flag[index] and memory_valid[index] are set to low level, and the state machine jumps to the Idle state. When the state machine jumps to the Idle state again, it means that the retrieval of a signal has been completed;

[0054] By repeatedly executing the logic in the above state machine, multiple parallel signals can be retrieved in real time to complete the recording of signal start data and end data.

[0055] The present invention creatively uses a signal retrieval method for multi-channel parallel signals obtained by superimposing multiple pulse signals, completes the storage of start data and end data of each valid signal and implements it in FPGA, and efficiently analyzes multi-channel parallel multi-system signals within the instantaneous bandwidth.

[0056] For those skilled in the art, after understanding the principle of the present invention, it can be reproduced in FPGA.

[0057] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technical users in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A signal retrieval method based on FPGA, characterized in that: The specific implementation includes the following steps: Step 1: Channelize the signal after N pulse signals are superimposed to obtain a frequency domain complex signal , the formula is as follows: Where: n is the time point; k is the channel number; j is the imaginary unit; is the frequency domain complex signal of the kth channel at time n, is the window function, whose width is N; Step 2: Channelize the output of multiple parallel frequency domain complex signals Perform signal detection, where n is the time point and k is the channel number; based on the set detection threshold , With detection threshold Compare and thus detect whether there is a signal in each channel; Step 3: According to the signal detection result, N registers are used in the signal retrieval module circuit to store the signal parameters of N signals respectively, including the starting channel number, starting frequency, starting time, ending channel number, ending frequency, and ending time, and the signal parameters of subsequent existing signals are continuously used to update the signal parameters in the corresponding registers; if a signal disappears, the data in the register corresponding to the disappeared signal is taken out and the register is cleared, and the cleared register waits for the next valid signal data to be stored, and the register write or read data operation is repeatedly executed to realize the signal retrieval function; The signal retrieval module circuit comprises: Perform signal detection on each of the multiple parallel frequency domain complex signals. If the mth channel Greater than or equal to the detection threshold , the corresponding sig_valid_m will be set to a high level, marking the location of the signal in the mth parallel signal, where m=0,1······N-1, N is the number of parallel signals, sig_valid_0~sig_valid_N-1 are ORed to obtain sig_valid; the number of channels, frequency, and time of each frequency-domain complex signal are integrated into a 75-bit frame, and there are N such frames; the state machine is used to perform logical control on signal retrieval. Under the condition that sig_valid is a high level, the signals stored in the N registers are searched according to the judgment conditions of the same signal. If the number of channels of the currently detected signal is the same as the starting channel number or the ending channel number stored in the ath register, the search is performed. If the difference does not exceed 2, it is determined to be the same signal, or the frequency of the currently detected signal is between the start frequency and the end frequency stored in the ath register, it is also determined to be the same signal. One of the above two conditions can be met, where a=0, 1...N-1; and the channel number, frequency and time of the currently detected signal are used to update the register; until the stored signal in the N registers disappears, the register data corresponding to the disappeared signal is read out and cleared, waiting for the next valid signal parameter to be stored in the empty register, the signals in other registers have not disappeared, and the register data is not read out and cleared; the above signal judgment operation is repeatedly performed, and the signal retrieval operation can be performed in real time to realize the storage of the start data and end data of the pulse signal.

2. The signal retrieval method based on FPGA according to claim 1, characterized in that: The decision conditions of the same signal include: If the number of channels of the signal detected under the current clock does not differ from the number of channels stored in the a-th register by more than 2, the currently detected signal and the signal in the register are the same signal, and the parameters of the signal in the a-th register are updated with the parameters of the currently detected signal, where a=0,1······N-1; if the current judgment condition is not met, the next judgment condition is executed; If the frequency of the signal detected under the current clock is within the range of the start frequency and the end frequency stored in the a-th register, the currently detected signal and the signal stored in the a-th register are the same signal, and the parameters of the signal in the a-th register are updated with the parameters of the currently detected signal, where a=0, 1······N-1; If either of the above two conditions is met, the signal parameters in the corresponding register can be updated; if neither of the above two conditions is met, the currently detected signal is judged to be a newly appeared signal, an empty register is searched among the N registers, and the channel number, frequency and time of the currently detected signal are stored in the empty register.

3. The signal retrieval method based on FPGA according to claim 1, characterized in that: The state machine of the signal retrieval module circuit includes: The state machine in the signal retrieval module circuit has three states, namely, Idle state, Sig_valid state, and Sig_disappear state; The idle state is the idle state; the Sig_valid state determines the signal and updates the signal parameters in each register. If the currently detected signal can find the same signal in N registers, or is stored in an empty register as a newly appeared signal, then sig_valid_flag[a] and memory_valid[a] are set to high level at the same time, where a=0, 1...N-1; the Sig_disappear state reads out and clears the register data of the disappeared signal; Among them, the jump of the state machine adopts the following method: After the Idle state instruction is executed, it jumps to the Sig_valid state; in the Sig_valid state, at the end of a frame where FFT ends, if the condition sig_valid_flag[a]=0 & memory_valid[a]=1 is met, it means that the signal in the ath register disappears, and the value of m is assigned to index, and it jumps to the Sig_disappear state, where a=0,1······N-1; otherwise, it continues to execute the logic in the Sig_valid state until the jump condition is met; In the Sig_disappear state, the signal parameters stored in the register memory[index] are read and cleared, sig_valid_flag[index] and memory_valid[index] are set to low level, and the state is jumped to the Idle state to complete the retrieval of a valid signal and the recording of the start data and the end data. The logic in the state machine is repeatedly executed until all signals are retrieved.

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