Modeling method of metal interconnection capacitor SPICE model

Abstract

The invention discloses a modeling method of a metal interconnection capacitor SPICE model. The modeling method comprises the following steps: step 1, providing a capacitance value query table of a metal interconnection capacitor; and 2, providing a normal-temperature SPICE model formula of the metal interconnection capacitor, and fitting fitting parameters of the normal-temperature SPICE model formula by taking the capacitance value at the normal temperature in the capacitance value query table as a data point to obtain a normal-temperature SPICE model. 3, providing a temperature effect SPICE model formula of the metal interconnection capacitor, wherein the temperature effect SPICE model formula is obtained by multiplying a normal temperature SPICE model by a temperature effect item; and fitting the fitting parameter of the temperature effect item in the temperature effect SPICE model formula by taking the capacitance value at each temperature in the capacitance value query table as a data point to obtain the temperature effect SPICE model. According to the invention, accurate modeling of metal interconnection capacitors of different sizes and types at different temperatures can be realized.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit manufacturing method, and in particular to a modeling method of a metal interconnect capacitor SPICE model. Background Art

[0002] SPICE is a circuit simulator that is used to test and simulate the SPICE model. The success or failure of circuit design depends largely on the accuracy of the SPICE model and data.

[0003] The metal interconnection process refers to the process of depositing metal film on an integrated circuit and forming wiring through photolithography technology, interconnecting mutually isolated components into the required circuit according to certain requirements.

[0004] In order to better describe the fluctuations of the actual process under different temperature conditions, a temperature effect model needs to be added to the SPICE model for customers to perform simulations within the extreme temperature range.

[0005] We usually provide two types of interconnect capacitance query tables: Conductive lines above an infinite ground plane and Conductive lines between two infinite ground planes. In the SPICE model development process, the interconnect capacitance table is usually some discrete capacitance values ​​obtained by Raphael (Synopsys) simulation. Customers can only query the capacitance value under specific conditions in this table, but cannot obtain the interconnect capacitance value under other sizes or temperature conditions.

[0006] Therefore, it is necessary to develop a SPICE modeling method for the temperature effect of interconnect capacitance. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a modeling method for a metal interconnect capacitor SPICE model, which can obtain an accurate SPICE model of the metal interconnect capacitor at different temperatures.

[0008] In order to solve the above technical problems, the modeling method of the metal interconnect capacitance SPICE model provided by the present invention comprises the following steps:

[0009] Step 1: Provide a capacitance value query table for metal interconnect capacitors.

[0010] Step 2: providing a normal temperature SPICE model formula of the metal interconnect capacitor, and then fitting the fitting parameters of the normal temperature SPICE model formula using the capacitance values ​​at normal temperature in the capacitance value query table as data points to obtain a normal temperature SPICE model.

[0011] Step three, providing a temperature effect SPICE model formula of the metal interconnect capacitor, wherein the temperature effect SPICE model formula is obtained by multiplying the normal temperature SPICE model by the temperature effect term; then, fitting the fitting parameters of the temperature effect term in the temperature effect SPICE model formula using the capacitance values ​​at each temperature in the capacitance value query table as data points to obtain a temperature effect SPICE model.

[0012] A further improvement is that the expression of the temperature effect term in the temperature effect SPICE model formula is: 1+TC1*(temper-T0).

[0013] Among them, TC1 is the fitting parameter, temper represents temperature, and T0 represents room temperature.

[0014] A further improvement is that the normal temperature is 25°C.

[0015] A further improvement is that in step 2, the expression of the normal temperature SPICE model formula is:

[0016] Cap0={A+AP*wr+(B+BP*wr) / sps+(C+CP*wr) / exp(sps / E)+(D+DP*wr) / exp[pow(sps,2) / F]}.

[0017] Wherein, Cap0 represents the total simulated capacitance of the metal interconnect capacitor at room temperature, wr represents the width of the metal line in the metal interconnect capacitor, and sps represents the spacing between the metal lines in the metal interconnect capacitor.

[0018] A, AP, B, BP, C, CP, D, DP, E and F are fitting parameters.

[0019] The values ​​of A, AP, B, BP, C, CP, D, DP, E and F in the room-temperature SPICE model obtained after fitting are A1, AP1, B1, BP1, C1, CP1, D1, DP1, E1 and F1, respectively.

[0020] A further improvement is that in step 3, the temperature effect SPICE model formula is expressed as:

[0021] Cap1={A1+AP1*wr+(B1+BP1*wr) / sps+(C1+CP1*wr) / exp(sps / E1)+(D1+DP1*wr) / exp[pow(sps,2) / F1]}*[1+TC1*(temper-T0)].

[0022] Wherein, Cap1 represents the total simulated capacitance of the metal interconnect capacitance at the temperature corresponding to temper.

[0023] A further improvement is that, in step 1, each capacitance value in the capacitance value lookup table is based on the structure of the metal interconnect capacitor and is obtained through Raphael simulation.

[0024] A further improvement is that the structure of the metal interconnect capacitor includes a first capacitor structure and a second capacitor structure.

[0025] The first capacitor structure is that the metal wires in the metal interconnect capacitor are on an infinite ground plane.

[0026] The second capacitor structure is that the metal line in the metal interconnect capacitor is between two infinite ground planes.

[0027] A further improvement is that the capacitance expression of the first capacitor structure is:

[0028] Ctotal = Cbottom + 2 × Ccoup;

[0029] Cbottom = Ca + 2 × Cf;

[0030] Where Ctotal represents the total capacitance;

[0031] Ccoup represents the coupling capacitance between the two metal lines;

[0032] Cbottom represents the bottom capacitance of the metal line;

[0033] Ca represents the area capacitance between the metal line and the bottom surface;

[0034] Cf represents the fringe capacitance between the metal line and the bottom surface.

[0035] A further improvement is that the capacitance expression of the second capacitor structure is:

[0036] Ctotal=Cbottom+Ctop+2×Ccoup;

[0037] Cbottom=Cb_area+2×Csd;

[0038] Ctop=Ct_area+2×Csu;

[0039] Where Ctotal represents the total capacitance;

[0040] Ccoup represents the coupling capacitance between the two metal lines;

[0041] Cbottom represents the bottom capacitance of the metal line;

[0042] Ctop represents the top surface capacitance of the metal line;

[0043] Cb_area represents the area capacitance between the metal line and the bottom surface;

[0044] Ct_area represents the area capacitance between the metal line and the top surface;

[0045] Csd represents the edge capacitance between the metal line and the bottom surface;

[0046] Csu represents the fringe capacitance of the metal line and the top surface.

[0047] The present invention can first fit the values ​​of each fitting parameter in the normal temperature SPICE model formula based on the capacitance value provided by the capacitance value query table of the metal interconnect capacitor and thereby obtain the normal temperature SPICE model; then, the normal temperature SPICE model is multiplied by the temperature effect term to obtain the temperature effect SPICE model formula, and then, in combination with the capacitance value provided by the capacitance value query table, the values ​​of the fitting parameters of the temperature effect term can be fitted to obtain the temperature effect SPICE model. Since the temperature effect SPICE model can reflect the influence of the temperature effect on the metal interconnect capacitor, accurate simulation values ​​of the metal interconnect capacitor at different temperatures can be obtained by simulating with the temperature effect SPICE model. Therefore, the present invention can obtain accurate SPICE models of metal interconnect capacitors at different temperatures, that is, can realize accurate modeling of metal interconnect capacitors at different temperatures; since the temperature effect SPICE model includes the normal temperature SPICE model, the present invention can realize accurate modeling of metal interconnect capacitors of different sizes and types at different temperatures. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0049] Figure 1 is a flow chart of a modeling method of a metal interconnect capacitance SPICE model according to an embodiment of the present invention;

[0050] Figure 2A is a schematic diagram of a first capacitor structure in a modeling method of a metal interconnect capacitor SPICE model according to an embodiment of the present invention;

[0051] Figure 2B is a schematic diagram of a second capacitor structure in a modeling method of a metal interconnect capacitor SPICE model according to an embodiment of the present invention;

[0052] Figure 3 is a result curve of fitting a normal temperature SPICE model using a modeling method for a metal interconnect capacitance SPICE model according to an embodiment of the present invention;

[0053] Figure 4 It is a result curve of fitting the temperature effect SPICE model using the modeling method of the metal interconnect capacitance SPICE model according to the embodiment of the present invention. DETAILED DESCRIPTION

[0054] like Figure 1 FIG. 1 is a flow chart of a method for modeling a metal interconnect capacitor SPICE model according to an embodiment of the present invention. The method for modeling a metal interconnect capacitor SPICE model according to an embodiment of the present invention comprises the following steps:

[0055] Step 1: Provide a capacitance value query table for metal interconnect capacitors.

[0056] In the embodiment of the present invention, each capacitance value in the capacitance value query table is based on the structure of the metal interconnect capacitor and is obtained through Raphael simulation. In other embodiments, it can also be: each capacitance value in the capacitance value query table is based on the structure of the metal interconnect capacitor and is obtained through simulation by other different Raphael simulation software or directly tested.

[0057] The capacitance value query table is mainly used to provide the data points required for fitting the SPICE model.

[0058] In the embodiment of the present invention, the structure of the metal interconnect capacitor includes a first capacitor structure and a second capacitor structure.

[0059] like Figure 2A FIG. 1 is a schematic diagram of a first capacitor structure in a modeling method of a metal interconnect capacitor SPICE model according to an embodiment of the present invention; the first capacitor structure is: a metal line 102 in a metal interconnect capacitor is on an infinite ground plane, Figure 2A The infinite ground plane in the figure is the bottom ground plane 101, and the bottom ground plane 101 is also represented by Bottom. Figure 2A Also shown in FIG. 1 are the width W of the metal lines 102 , the spacing S between the metal lines 102 , and the spacing H between the metal lines 102 and the bottom ground plane 101 .

[0060] The capacitance expression of the first capacitor structure is:

[0061] Ctotal = Cbottom + 2 × Ccoup;

[0062] Cbottom = Ca + 2 × Cf;

[0063] Where Ctotal represents the total capacitance;

[0064] Ccoup represents the coupling capacitance between two metal lines 102;

[0065] Cbottom represents the bottom capacitance of the metal line 102;

[0066] Ca represents the area capacitance between the metal line 102 and the bottom surface;

[0067] Cf represents the fringe capacitance between the metal line 102 and the bottom surface.

[0068] Figure 2A The parasitic capacitances Ccoup, Ca and Cf are also shown in FIG. By changing the structural parameters of the first capacitor structure, i.e., the size such as W, S or H, the corresponding parasitic capacitance can be changed. Through Raphael simulation, the parasitic capacitances of the first capacitor structure under multiple different sizes can be obtained, thereby obtaining a capacitance value query table of the metal interconnect capacitor of the first capacitor structure.

[0069] like Figure 2B , which is a schematic diagram of a second capacitor structure in a modeling method of a metal interconnect capacitor SPICE model according to an embodiment of the present invention; the second capacitor structure is: a metal line 102 in the metal interconnect capacitor is between two infinite ground planes; Figure 2B The two infinite ground planes are respectively a bottom ground plane 101 and a top ground plane 103. The bottom ground plane 101 is also represented by Bottom plate, and the top ground plane 103 is also represented by Top plate.

[0070] The capacitance expression of the second capacitor structure is:

[0071] Ctotal=Cbottom+Ctop+2×Ccoup;

[0072] Cbottom=Cb_area+2×Csd;

[0073] Ctop=Ct_area+2×Csu;

[0074] Where Ctotal represents the total capacitance;

[0075] Ccoup represents the coupling capacitance between two metal lines 102;

[0076] Cbottom represents the bottom capacitance of the metal line 102;

[0077] Ctop represents the top surface capacitance of the metal line 102;

[0078] Cb_area represents the area capacitance between the metal line 102 and the bottom surface;

[0079] Ct_area represents the area capacitance between the metal line 102 and the top surface;

[0080] Csd represents the fringe capacitance between the metal line 102 and the bottom surface;

[0081] Csu represents the fringe capacitance between the metal line 102 and the top surface.

[0082] Figure 2B The parasitic capacitances Cb_area, Ct_area, Csd and Csu are also shown in FIG. By changing the structural parameters of the second capacitor structure, i.e., the size, the corresponding parasitic capacitance can be changed. By Raphael simulation, the parasitic capacitances of the second capacitor structure under multiple different sizes can be obtained, thereby obtaining a capacitance value query table of the metal interconnect capacitor of the second capacitor structure.

[0083] Step 2: Provide a normal temperature SPICE model formula of the metal interconnect capacitance, and then use the capacitance values ​​at normal temperature in the capacitance value query table as data points to fit the fitting parameters of the normal temperature SPICE model formula to obtain a normal temperature SPICE model.

[0084] In the embodiment of the present invention, the expression of the normal temperature SPICE model formula is:

[0085] Cap0={A+AP*wr+(B+BP*wr) / sps+(C+CP*wr) / exp(sps / E)+(D+DP*wr) / exp[pow(sps,2) / F]}.

[0086] Wherein, Cap0 represents the total simulated capacitance of the metal interconnect capacitor at room temperature, wr represents the width of the metal line 102 in the metal interconnect capacitor, and sps represents the spacing between the metal lines 102 in the metal interconnect capacitor.

[0087] A, AP, B, BP, C, CP, D, DP, E and F are all fitting parameters.

[0088] The values ​​of A, AP, B, BP, C, CP, D, DP, E and F in the room-temperature SPICE model obtained after fitting are A1, AP1, B1, BP1, C1, CP1, D1, DP1, E1 and F1 respectively.

[0089] like Figure 3 , which is a result curve of fitting the normal temperature SPICE model using the modeling method of the metal interconnect capacitance SPICE model according to the embodiment of the present invention; Figure 3Spacing represents the spacing between metal lines 102, i.e., sps in Cap0. Each point corresponding to the multiple marks 201a represents the capacitance value at room temperature in the capacitance value query table. Figure 3 Data_tt is also used in the representation. Curve 202a is the final fitting curve, that is, the curve corresponding to the normal temperature SPICE model. Figure 3 Model_tt is also used in the figure. It can be seen that the points corresponding to the corresponding marks 201a at different spacings are all located on the curve 202a. The curve 202a is determined by the final fitting values ​​A1, AP1, B1, BP1, C1, CP1, D1, DP1, E1 and F1. During the fitting process, the values ​​of the fitting parameters, i.e., A, AP, B, BP, C, CP, D, DP, E and F, are constantly changed until the final values, i.e., A1, AP1, B1, BP1, C1, CP1, D1, DP1, E1 and F1, are reached.

[0090] Step 3: Provide a temperature effect SPICE model formula for the metal interconnect capacitor. The temperature effect SPICE model formula is obtained by multiplying the normal temperature SPICE model by the temperature effect term. Then, the capacitance values ​​at each temperature in the capacitance value query table are used as data points to fit the fitting parameters of the temperature effect term in the temperature effect SPICE model formula to obtain the temperature effect SPICE model.

[0091] In the embodiment of the present invention, the expression of the temperature effect term in the temperature effect SPICE model formula is: 1+TC1*(temper-T0).

[0092] Wherein, TC1 is a fitting parameter, temper represents temperature, and T0 represents normal temperature. In some preferred embodiments, the normal temperature is 25°C.

[0093] In the embodiment of the present invention, the expression of the temperature effect SPICE model formula is:

[0094] Cap1={A1+AP1*wr+(B1+BP1*wr) / sps+(C1+CP1*wr) / exp(sps / E1)+(D1+DP1*wr) / exp[pow(sps,2) / F1]}*[1+TC1*(temper-T0)].

[0095] Wherein, Cap1 represents the total simulated capacitance of the metal interconnect capacitance at the temperature corresponding to temper.

[0096] like Figure 4 , which is a result curve of fitting the temperature effect SPICE model using the modeling method of the metal interconnect capacitance SPICE model according to an embodiment of the present invention. Figure 4In FIG. 1 , Temperature represents temperature, and the ordinate represents the normalized value of the total capacitance of the metal interconnect capacitance based on the capacitance value of 25 degrees Celsius, namely, Ctotal normalize to25C.

[0097] Figure 4 In FIG. 1 , each point corresponding to the dotted circle 201 b represents the capacitance values ​​of different sizes at different temperatures provided by the capacitance value query table. Figure 4 The right area in shows multiple different sizes and multiple specific values ​​corresponding to W / Spacing, where W represents the width of the metal line 102 and Spacing represents the spacing between the metal lines 102 .

[0098] Curve 202b is the final fitting curve, i.e., the curve corresponding to the temperature effect SPICE model. Figure 4 Model is also used in the figure, and curve 202b only shows the fitting curve under one size. Figure 3 and Figure 4 As shown, the embodiments of the present invention can achieve accurate modeling of metal interconnect capacitors of different sizes and types at different temperatures.

[0099] In the embodiment of the present invention, based on the capacitance value provided by the capacitance value query table of the metal interconnect capacitor, the values ​​of the fitting parameters in the normal temperature SPICE model formula can be fitted first, and the normal temperature SPICE model can be obtained; then, the normal temperature SPICE model is multiplied by the temperature effect term to obtain the temperature effect SPICE model formula, and then the capacitance value provided by the capacitance value query table can be fitted to the values ​​of the fitting parameters of the temperature effect term to obtain the temperature effect SPICE model. Since the temperature effect SPICE model can reflect the influence of the temperature effect on the metal interconnect capacitor, the accurate simulation value of the metal interconnect capacitor at different temperatures can be obtained by simulating with the temperature effect SPICE model. Therefore, the embodiment of the present invention can obtain the accurate SPICE model of the metal interconnect capacitor at different temperatures, that is, it can realize the accurate modeling of the metal interconnect capacitor at different temperatures; since the temperature effect SPICE model includes the normal temperature SPICE model, the embodiment of the present invention can realize the accurate modeling of metal interconnect capacitors of different sizes and types at different temperatures.

[0100] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A modeling method for a metal interconnect capacitance SPICE model, characterized in that: The steps include: Step 1, providing a capacitance value query table of metal interconnect capacitors; Step 2: providing a normal temperature SPICE model formula of the metal interconnect capacitance, and then fitting the fitting parameters of the normal temperature SPICE model formula using the capacitance values ​​at normal temperature in the capacitance value query table as data points to obtain a normal temperature SPICE model; Step three, providing a temperature effect SPICE model formula of the metal interconnect capacitor, wherein the temperature effect SPICE model formula is obtained by multiplying the normal temperature SPICE model by the temperature effect term; then, fitting the fitting parameters of the temperature effect term in the temperature effect SPICE model formula using the capacitance values ​​at each temperature in the capacitance value query table as data points to obtain a temperature effect SPICE model.

2. The modeling method of the metal interconnect capacitance SPICE model according to claim 1, characterized in that: The expression of the temperature effect term in the temperature effect SPICE model formula is: 1+TC1*(temper-T0); Among them, TC1 is the fitting parameter, temper represents temperature, and T0 represents room temperature.

3. The modeling method of the metal interconnect capacitance SPICE model according to claim 2, characterized in that: Normal temperature is 25℃.

4. The modeling method of the metal interconnect capacitance SPICE model according to claim 2, characterized in that: In step 2, the expression of the normal temperature SPICE model formula is: Cap0={A+AP*wr+(B+BP*wr) / sps+(C+CP*wr) / exp(sps / E)+(D+DP*wr) / exp[pow(sps,2) / F]}; Wherein, Cap0 represents the total simulated capacitance of the metal interconnect capacitor at room temperature, wr represents the width of the metal line in the metal interconnect capacitor, and sps represents the spacing between the metal lines in the metal interconnect capacitor; A, AP, B, BP, C, CP, D, DP, E and F are fitting parameters; The values ​​of A, AP, B, BP, C, CP, D, DP, E and F in the room-temperature SPICE model obtained after fitting are A1, AP1, B1, BP1, C1, CP1, D1, DP1, E1 and F1, respectively.

5. The modeling method of the metal interconnect capacitance SPICE model according to claim 4, characterized in that: In step 3, the temperature effect SPICE model formula is expressed as: Cap1={A1+AP1*wr+(B1+BP1*wr) / sps+(C1+CP1*wr) / exp(sps / E1)+(D1+DP1*wr) / exp[pow(sps,2) / F1]}*[1+TC1*(temper-T0)]; Wherein, Cap1 represents the total simulated capacitance of the metal interconnect capacitance at the temperature corresponding to temper.

6. The modeling method of the metal interconnect capacitance SPICE model according to claim 1, characterized in that: In step 1, each capacitance value in the capacitance value query table is based on the structure of the metal interconnect capacitor and is obtained through Raphael simulation.

7. The modeling method of the metal interconnect capacitance SPICE model according to claim 6, characterized in that: The structure of the metal interconnect capacitor includes a first capacitor structure and a second capacitor structure; The first capacitor structure is: the metal wires in the metal interconnect capacitor are on an infinite ground plane; The second capacitor structure is that the metal line in the metal interconnect capacitor is between two infinite ground planes.

8. The modeling method of the metal interconnect capacitance SPICE model according to claim 7, characterized in that: The capacitance expression of the first capacitor structure is: Ctotal = Cbottom + 2 × Ccoup; Cbottom = Ca + 2 × Cf; Where Ctotal represents the total capacitance; Ccoup represents the coupling capacitance between the two metal lines; Cbottom represents the bottom capacitance of the metal line; Ca represents the area capacitance between the metal line and the bottom surface; Cf represents the fringe capacitance between the metal line and the bottom surface.

9. The modeling method of the metal interconnect capacitance SPICE model according to claim 7, characterized in that: The capacitance expression of the second capacitor structure is: Ctotal=Cbottom+Ctop+2×Ccoup; Cbottom=Cb_area+2×Csd; Ctop=Ct_area+2×Csu; Where Ctotal represents the total capacitance; Ccoup represents the coupling capacitance between the two metal lines; Cbottom represents the bottom capacitance of the metal line; Ctop represents the top surface capacitance of the metal line; Cb_area represents the area capacitance between the metal line and the bottom surface; Ct_area represents the area capacitance between the metal line and the top surface; Csd represents the edge capacitance between the metal line and the bottom surface; Csu represents the fringe capacitance of the metal line and the top surface.

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