Memristor array circuit simulation method, device, computer equipment and storage medium

Abstract

The present application relates to a memristor array circuit simulation method, apparatus, computer equipment, and storage medium. The method comprises: decomposing a single network layer input of a convolutional neural network based on a memristor array circuit into multiple binary input vectors and assigning simulation tasks; executing the simulation tasks in parallel based on a distributed, multi-process approach, mapping weight bits to multiple device conductances of the memristor array in the simulation tasks, mapping input bits to multiple voltage signals, and compiling a circuit netlist for each memristor array circuit; parsing the circuit netlist and running a simulation, calculating the output current based on the voltage values ​​and the device conductance values ​​based on Kirchhoff's law; converting the current output by each memristor array circuit simulation task into a digital signal, performing shifting, addition, and combination to obtain an integer, then dequantizing the integer to a floating-point number and adding a bias term, and requantizing to obtain the network layer output.

Description

Technical Field

[0001] The present application relates to the technical field of code snippet adaptation, and in particular to a memristor array circuit simulation method, apparatus, computer equipment, and storage medium. Background Art

[0002] A memristor is a nonlinear resistor with a memory function whose resistance changes with the amount of charge flowing through it and maintains this changed state after power is removed. A memristor crossbar array, also known as a memristor array, is a memristor unit integration process in which the memristor units are located at the intersection of mutually perpendicular word lines and bit lines. The so-called 1T1R (one-transistor-one-resistor) refers to a structure in which a transistor is connected in series with a memristor or resistive switching unit. Transistors are used to enable the memristor unit to avoid crosstalk caused by leakage current. In a traditional 1T1R array, the wire connecting the gates of transistors in the same row is the word line, and the wire connecting the memristor units in the same column is the bit line. To perform multiplication and accumulation operations based on the traditional 1T1R array, an input signal must be applied to the word line to control the switching state of the transistor, and a fixed read voltage must be applied to the bit line. This method is suitable for binary signals. The bit lines in a traditional 1T1R array are rotated perpendicular to the source lines, resulting in a pseudo-crossbar array structure. In this architecture, word lines connect memristor cells in the same row, and bit lines connect transistor gates in the same column. Multiplication and accumulation operations performed using a pseudo-crossbar array can be performed in two ways, corresponding to two structures: bitline-signal 1T1R and gate-signal 1T1R. Bitline-signal 1T1R applies an input signal to the word line and a transistor-on voltage to each bit line, turning all transistors on. Gate-signal 1T1R applies a fixed read voltage to each word line and an input signal to the bit line to control the transistor's on / off state. Similar to the traditional 1T1R array, it is suitable for binary signals. 1R is a transistor-free crossbar array structure. In a 2T2R (two-transistor-two-resistor) array structure, the crossbar cells consist of two transistors and two memristors.

[0003] The primary computation in a convolutional neural network (CNN) is matrix-vector multiplication (MVM), and the fundamental operation of MVM is the multiply-accumulate (MAC) operation. The MAC method implemented with a memristor array assumes that the convolution kernel weights are mapped to memristor conductances by column. Voltage pulses are applied row by row. Kirchhoff's law shows that the current collected at the end of a column is the product of the multiplication and accumulation of the input (voltage) and the weight (conductance).

[0004] Array parasitic resistance. In actual memristor crossbar arrays, there are wire resistance, input / output resistance, and transistor resistance. These parasitic resistances can cause signal attenuation, thus affecting the results of multiplication and accumulation operations.

[0005] In terms of computing architecture, traditional in-memory computing architectures follow the same paradigm as digital circuits and lack fault tolerance. In digital circuit design, each number is represented by multiple bits. During multiplication, each bit in the multiplier is multiplied by each bit in the multiplicand, resulting in many partial products. Therefore, the multiplier circuit has a set of shifters and adders to sum the partial products. Traditional in-memory computing architectures inherit this approach and extend it to arrays, forming the so-called bit-slicing approach. In this approach, the memristors are confined to a finite, predetermined state space (typically binary), and the weight matrix and input vector are decomposed into multiple bit planes. MVM is performed on these bit planes to obtain partial products. These partial products are then quantized and combined using digital circuits such as analog-to-digital converters (ADCs), shifters, and adders to produce the complete MVM result.

[0006] Open-source crossbar array simulators include PytorX, MLP+NeuroSim V3.0, and CrossSim. PytorX equates the transistors in a bitline-signal 1T1R array structure to on-resistors, uses a simplified modified nodal analysis method to establish circuit equations, and solves linear equations on a GPU. Although this simulator does not use Spice simulation, the principle of establishing circuit equations is similar to Spice. In MLP+NeuroSim V3.0, the transistors in the bitline-signal 1T1R structure are equated to on-resistors. The simulation method for wire resistance considers a single voltage transmission path from the input through the bit line to the target memristor, then through the transistor, and finally through the source line to the output. This is the direct path through the memristor. The memristor current = read voltage / (wire resistance of the path + transistor on-resistance). In CrossSim, approximate analysis of three 1T1R circuit array structures is performed. Based on the approximate array structure, approximate calculation and iterative solution methods are used for simulation. The array parasitic resistance simulation methods of both MLP+NeuroSim and CrossSim simulators are approximate calculations, with low accuracy and low reliability. In addition, it is difficult to add new array structures to both, and modifications need to be made to the simulation code logic, which makes them less scalable. In PytorX, the transistors of the Bitline-signal 1T1R array structure are also equivalent to on-resistances. A simplified improved node analysis method is used to establish circuit equations, and linear equations are solved based on the GPU. Similarly, this simulator has the problem of difficulty in adding new array structures, and for some array structures (such as Gate-signal 1T1R), even small-scale array simulations are very time-consuming. Summary of the Invention

[0007] Based on this, it is necessary to provide a memristor array circuit simulation method, device, computer equipment and storage medium to address the above technical problems.

[0008] A memristor array circuit simulation method, the method comprising:

[0009] Decompose the single-layer input of a convolutional neural network based on a memristor array circuit into multiple binary input vectors and assign simulation tasks;

[0010] Executing the simulation task in parallel based on distributed multi-processing, mapping weight bits to multiple device conductances of the memristor array, mapping input bits to multiple voltage signals, and compiling a circuit netlist for each memristor array circuit in the simulation task;

[0011] Parsing the circuit netlist and running a simulation, and calculating the output current based on Kirchhoff's law according to the voltage signal and the device conductance value;

[0012] The current output by each memristor array circuit simulation task is converted into a digital signal, which is then shifted, added, and combined to obtain an integer. The integer is then dequantized to a floating-point number and a bias term is added. The network layer output is then quantized again.

[0013] In one embodiment, the memristor array circuit includes traditional 1T1R, gate-signal 1T1R, bitline-signal 1T1R, 1R, and 2T2R. Simply by compiling a circuit netlist, circuit simulation of various array structures can be supported. The following method uses traditional 1T1R as an example.

[0014] In one embodiment, the method further includes: modeling the conduction state of transistors in the memristor array circuit, and modifying the circuit netlist according to the modeled memristor array circuit.

[0015] In one embodiment, the method further includes: for each row of word lines, connecting the gates of the transistors in the row, wherein the unit resistance of each segment on the word line is R_wl_wire, the word line driving signal source Vgate is a DC voltage source, and the signal enters the array through the input resistor Rload_1;

[0016] For each column of bit lines, the memristors R in that column are connected. The unit resistance of each section on the bit line is R_bl_wire. The bit line driving signal source Vread is a DC voltage source. The signal enters the array through the input resistor Rload_2.

[0017] The source line of each column connects the sources of the transistors in the column. The unit resistance of each section of the source line is R_sl_wire. The current passing through each memristor is collected from the source line and flows through the output resistor Rload_3.

[0018] In one embodiment, the method further includes: when the input signal is 1, converting the cross cell Rcell into a combination of a memristor and a transistor on-resistance;

[0019] When the input signal is 0, the cross cell Rcell is equivalent to a combination of a memristor and a transistor off resistor;

[0020] Applying a read voltage using the bit line maintains the bit line structure;

[0021] Use the source line to sink the current and output the current through the output resistor.

[0022] In one embodiment, the method further includes: allocating each input vector to a corresponding memristor array circuit simulation task, performing multi-node distributed computing based on a message passing interface, and using multiple processes in each node to run the Ngspice simulation task in parallel.

[0023] In one embodiment, the method further includes: in each memristor array, calling the Ngspice API through the FFI interface to parse the circuit netlist and perform circuit simulation to obtain the sum of the column currents of each part; using regular expressions to process the Ngspice simulation callback results, extracting the sum of the column currents output by each memristor array circuit simulation task, and quantizing the currents into digital signals.

[0024] A memristor array circuit simulation device, comprising:

[0025] The task decomposition module decomposes the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assigns simulation tasks;

[0026] A netlist writing module is used to execute the simulation task in parallel based on a distributed, multi-process approach, map weight bits to multiple device conductances of the memristor array, map input bits to multiple voltage signals, and write a circuit netlist for each memristor array circuit in the simulation task;

[0027] A simulation output module parses the circuit netlist and runs a simulation, and calculates the output current based on Kirchhoff's law according to the voltage signal and the device conductance value;

[0028] The output processing module is used to convert the current output by each memristor array circuit simulation task into a digital signal, shift, add, and combine it to obtain an integer number, then dequantize the integer number into a floating-point number and add a bias term, and quantize it again to obtain the network layer output.

[0029] A computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0030] Decompose the single-layer input of a convolutional neural network based on a memristor array circuit into multiple binary input vectors and assign simulation tasks;

[0031] Executing the simulation task in parallel based on distributed multi-processing, mapping weight bits to multiple device conductances of the memristor array, mapping input bits to multiple voltage signals, and compiling a circuit netlist for each memristor array circuit in the simulation task;

[0032] Parsing the circuit netlist and running a simulation, and calculating the output current based on Kirchhoff's law according to the voltage signal and the device conductance value;

[0033] The current output by each memristor array circuit simulation task is converted into a digital signal, which is then shifted, added, and combined to obtain an integer. The integer is then dequantized to a floating-point number and a bias term is added. The network layer output is then quantized again.

[0034] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps:

[0035] Decompose the single-layer input of a convolutional neural network based on a memristor array circuit into multiple binary input vectors and assign simulation tasks;

[0036] Executing the simulation task in parallel based on distributed multi-processing, mapping weight bits to multiple device conductances of the memristor array, mapping input bits to multiple voltage signals, and compiling a circuit netlist for each memristor array circuit in the simulation task;

[0037] Parsing the circuit netlist and running a simulation, and calculating the output current based on Kirchhoff's law according to the voltage signal and the device conductance value;

[0038] The current output by each memristor array circuit simulation task is converted into a digital signal, which is then shifted, added, and combined to obtain an integer. The integer is then dequantized to a floating-point number and a bias term is added. The network layer output is then quantized again.

[0039] The above-mentioned memristor array circuit simulation method, device, computer equipment and storage medium first decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors, assign a simulation task to each input vector, and improve the simulation efficiency based on distributed, multi-process parallel processing tasks; secondly, in the simulation task, the weight bit is mapped to the multiple device conductances of the memristor array, the input bit is mapped to multiple voltage signals, and the circuit netlist of each memristor array circuit is compiled. For different memristor array architectures, only the circuit netlist needs to be changed without modifying the simulation framework; then the circuit netlist is parsed and the simulation is run, and the output current is calculated based on the voltage value and the device conductance value based on Kirchhoff's law; finally, the current output by each memristor array circuit simulation task is converted into a digital signal, shifted, added and combined to obtain an integer, the integer is dequantized into a floating point number and a bias term is added, and the network layer output is obtained after requantization. The method of the present invention can significantly improve the efficiency of memristor array circuit simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 11 is a flow chart of a memristor array circuit simulation method according to an embodiment;

[0041] Figure 2 A schematic diagram of a memristor array circuit simulation framework in one embodiment;

[0042] Figure 3 FIG1 is a schematic diagram of a 1T1R equivalent circuit in which a transistor is added in one embodiment;

[0043] Figure 4 FIG1 is a schematic diagram of a 1T1R equivalent circuit without transistors in one embodiment;

[0044] Figure 5 is a structural block diagram of a memristor array circuit simulation device in one embodiment;

[0045] Figure 6 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0047] The simulation program of the present invention can adopt multi-node distributed computing based on MPI communication to divide the test data set equally into each computing node, thereby accelerating the test speed without using a GPU.

[0048] In one embodiment, Figure 1 As shown, a circuit simulation method based on a memristor array is provided, comprising:

[0049] Step 102: Decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assign simulation tasks.

[0050] In this step, the main process asynchronously creates multiple processes based on CPU resources to handle simulation tasks of multiple binary input vectors, and each binary input vector corresponds to each task.

[0051] Step 104 , executing the simulation task in parallel based on distributed multi-processing, mapping the weight bits to multiple device conductances of the memristor array, mapping the input bits to multiple voltage signals, and compiling a circuit netlist for each memristor array circuit in the simulation task.

[0052] Step 106 : parsing the circuit netlist and running a simulation, and calculating the output current based on Kirchhoff's law according to the voltage signal and the device conductance.

[0053] Step 108: Convert the current output by each memristor array circuit simulation task into a digital signal, perform shifting, addition, and combination to obtain an integer, then dequantize the integer into a floating point number and add a bias term, and quantize again to obtain the network layer output.

[0054] The above-mentioned memristor array circuit simulation method first decomposes the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors, assigns a simulation task to each input vector, and improves the simulation efficiency based on distributed, multi-process parallel processing tasks; secondly, in the simulation task, the weight bit is mapped to the multiple device conductances of the memristor array, and the input bit is mapped to multiple voltage signals. The circuit netlist of each memristor array circuit is compiled. For different memristor array architectures, only the circuit netlist needs to be changed without modifying the simulation framework; then the circuit netlist is parsed and the simulation is run, and the output current is calculated based on Kirchhoff's law according to the voltage value and the device conductance value; finally, the current output by each memristor array circuit simulation task is converted into a digital signal, shifted, added and combined to obtain an integer, the integer is dequantized into a floating point number and a bias term is added, and the network layer output is obtained after requantization. The method of the present invention can significantly improve the efficiency of memristor array circuit simulation.

[0055] The framework of this method is Figure 2 As shown, first, for the calculation of a certain network layer, the main process asynchronously creates multiple processes based on CPU resources to handle the simulation tasks of multiple input vectors, and determines whether the processing of all tasks is completed. If not, a single array simulation is performed on each task in turn. If all arrays are simulated, if not, a circuit netlist is written to determine whether word lines and transistors are added. If so, the BSIMBULK107 transistor model, word line resistance and input signal are added. If not, the approximate resistance of the transistor being turned on or off is added to the unit resistance according to the input signal. The simulation is defined to only save the current data of the output resistance. The Shared Ngspice API is called based on the FFI interface to run the simulation. Regular expressions are used to match and process the simulation output data until all array simulations are completed. The output data of all arrays are combined. The results of all tasks are processed and combined to obtain the current output of the network layer. The output is converted, dequantized, biased and requantized to obtain the output of a certain network layer, and the calculation of the network layer is completed.

[0056] Specifically, the main process asynchronously creates multiple processes based on CPU resources to handle simulation tasks for multiple binary input vectors. Each input vector corresponds to a task, and each input vector contains multiple arrays. Within each task, a single array is simulated sequentially. First, based on the two structures obtained by the aforementioned analysis, whether or not to include transistors, Ngspice circuit netlists are compiled. Within the netlists, it is defined that only the output resistor current data will be saved for simulation. Then, Python uses the FFI interface to call the Shared Ngspice API to run the simulation. The simulated data is matched and processed using regular expressions, completing the multiplication and accumulation simulation of a single array. Each task simulates all arrays associated with the input vector and combines the output data from all arrays. The main process blocks to obtain the results of each task, processes and combines them to obtain the raw output current data of the network layer's array operations. The raw output current is converted to an integer through analog-to-digital conversion, dequantized to a floating-point number, and then biased and quantized again to obtain the output of the network layer.

[0057] In one embodiment, memristor array circuits include traditional 1T1R, gate-signal 1T1R, bitline-signal 1T1R, 1R, and 2T2R. Simply by creating a circuit netlist, circuit simulations for various array structures can be supported. The following method uses the traditional 1T1R as an example.

[0058] In one embodiment, the conduction states of transistors in the memristor array circuit are modeled, and the circuit netlist is modified based on the modeled memristor array circuit.

[0059] Specifically, take the traditional 1T1R as an example. Figure 3 As shown, each row's wordline (WL) connects the gates of each transistor in that row. Each segment of the wordline has a unit resistance R_wl_wire. The wordline drive signal source Vgate is a DC voltage source, and the signal enters the array through input resistor Rload_1. Each column's bitline (BL) connects the memristors R in that column. Each segment of the bitline has a unit resistance R_bl_wire. The bitline drive signal source Vread is a DC voltage source, and the signal enters the array through input resistor Rload_2. Each column's sourceline (SL) connects the sources of each transistor in that column. Each segment of the sourceline has a unit resistance R_sl_wire. The current flowing through each memristor is collected from the source line and flows through output resistor Rload_3 to the analog-to-digital converter. The analog-to-digital conversion here is handled in the program, so output resistor Rload_3 is grounded.

[0060] In another embodiment, in order to improve the simulation speed, transistors may not be added, but approximate processing may be performed, specifically as follows: Figure 4 As shown, when the input signal is 1, the cross unit Rcell is equivalent to a combination of a memristor and a transistor on-resistance; when the input signal is 0, the cross unit Rcell is equivalent to a combination of a memristor and a transistor off-resistance; a read voltage is applied using the bit line to maintain the bit line structure; a source line is used to collect current and output the current through the output resistor.

[0061] Specifically, the program calculates the cross-cell Rcell resistance based on the input data bit. If it is 1 (0), then the resistance of the cross-cell Rcell = the resistance of the memristor + the on (off) resistance of the transistor. This structure is similar to the structure with added transistors in that the bit line applies the read voltage and the source line collects the current. The difference is that this structure does not require the addition of transistors or word lines, and the number of circuit nodes is reduced by two times. Furthermore, each set of inputs in this structure causes a change in the cross-cell resistance, while the structure with added transistors has a constant cross-cell resistance and a change in input. Approximating the process without adding transistors increases simulation speed but affects simulation accuracy, albeit to a small degree.

[0062] In one embodiment, each input vector is assigned to a corresponding memristor array circuit simulation task, multi-node distributed computing is performed based on a message passing interface, and Ngspice simulation tasks are run in parallel using multiple processes in each node.

[0063] In one embodiment, in each memristor array, the Ngspice API is called through the FFI interface to parse the circuit netlist and perform circuit simulation to obtain the sum of the column currents of each part; the Ngspice simulation callback results are processed using regular expressions to extract the sum of the column currents output by each memristor array circuit simulation task, and the currents are quantized and converted into digital signals.

[0064] In one embodiment, Figure 5 As shown, a memristor array circuit simulation device is provided, including: a task decomposition module 502, a netlist writing module 504, a simulation output module 506 and an output processing module 508, wherein:

[0065] A task decomposition module 502 is used to decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assign simulation tasks;

[0066] A netlist writing module 504 is configured to execute the simulation task in a distributed, multi-process parallel manner, map weight bits to multiple device conductances of the memristor array, map input bits to multiple voltage signals, and write a circuit netlist for each memristor array circuit in the simulation task;

[0067] A simulation output module 506 parses the circuit netlist and runs a simulation, and calculates the output current based on the voltage signal and the device conductance value according to Kirchhoff's law;

[0068] The output processing module 508 is used to convert the current output by each memristor array circuit simulation task into a digital signal, perform shifting, addition, and combination to obtain an integer number, then dequantize the integer number into a floating point number and add a bias term, and quantize it again to obtain the network layer output.

[0069] In one embodiment, the memristor array circuit includes traditional 1T1R, gate-signal 1T1R, bitline-signal 1T1R, 1R, and 2T2R. Simply by compiling a circuit netlist, circuit simulation of various array structures can be supported. The following method uses traditional 1T1R as an example.

[0070] In one embodiment, the netlist writing module 504 is further configured to model the conduction states of transistors in the memristor array circuit, and modify the circuit netlist according to the modeled memristor array circuit.

[0071] In one embodiment, the netlist writing module 504 is further configured to connect the gates of each transistor in each row of word lines, wherein the unit resistance of each segment on the word line is R_wl_wire, the word line driving signal source Vgate is a DC voltage source, and the signal enters the array through the input resistor Rload_1; connect the memristors R in each column of bit lines, wherein the unit resistance of each segment on the bit line is R_bl_wire, the bit line driving signal source Vread is a DC voltage source, and the signal enters the array through the input resistor Rload_2; and connect the sources of each transistor in each column of source lines, wherein the unit resistance of each segment on the source line is R_sl_wire, and the current passing through each memristor is collected from the source line and flows through the output resistor Rload_3.

[0072] In one embodiment, the netlist writing module 504 is further used to, when the input signal is 1, equate the cross cell Rcell to a combination of a memristor and a transistor on-resistance; when the input signal is 0, equate the cross cell Rcell to a combination of a memristor and a transistor off-resistance; use the bit line to apply a read voltage to maintain the bit line structure; use the source line to collect current and output the current through the output resistor.

[0073] In one embodiment, the task decomposition module 502 is further configured to assign each input vector to a corresponding memristor array circuit simulation task, perform multi-node distributed computing based on a message passing interface, and use multiple processes in each node to run Ngspice simulation tasks in parallel.

[0074] In one embodiment, the simulation output module 506 is further configured to call the Ngspice API through the FFI interface to parse the circuit netlist and perform circuit simulation in each memristor array to obtain the sum of the column currents of each part; the output processing module is further configured to process the Ngspice simulation callback results using a regular expression, extract the sum of the column currents output by each memristor array circuit simulation task, and quantize the currents into digital signals.

[0075] For the specific definition of the memristor array circuit simulation device, please refer to the definition of the memristor array circuit simulation method above, which will not be repeated here. The various modules in the above-mentioned memristor array circuit simulation device can be implemented in whole or in part by software, hardware, or a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0076] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a memristor array circuit simulation method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a key, trackball or touchpad provided on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0077] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0078] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps of the method in the above embodiment when executing the computer program.

[0079] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method in the above embodiment are implemented.

[0080] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0081] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A memristor array circuit simulation method, characterized in that: The method comprises: Decompose the single-layer input of a convolutional neural network based on a memristor array circuit into multiple binary input vectors and assign simulation tasks; Executing the simulation task in parallel based on distributed multi-processing, mapping weight bits to multiple device conductances of the memristor array, mapping input bits to multiple voltage signals, and compiling a circuit netlist for each memristor array circuit in the simulation task; Parsing the circuit netlist and running a simulation, and calculating the output current based on Kirchhoff's law according to the voltage signal and the device conductance value; The current output by each memristor array circuit simulation task is converted into a digital signal, which is then shifted, added, and combined to obtain an integer. The integer is then dequantized to a floating-point number and a bias term is added. The network layer output is then quantized again.

2. The method according to claim 1, wherein The memristor array circuit includes: traditional 1T1R, Gate-signal 1T1R, Bitline-signal 1T1R, 1R and 2T2R.

3. The method according to claim 1, characterized in that The method further comprises: The conduction states of transistors in the memristor array circuit are modeled, and the circuit netlist is modified according to the modeled memristor array circuit.

4. The method according to claim 3, characterized in that The step of modeling the conduction state of the transistors in the memristor array circuit comprises: For each row of word lines, the gates of the transistors in that row are connected. The unit resistance of each segment on the word line is R_wl_wire. The word line drive signal source Vgate is a DC voltage source. The signal enters the array through the input resistor Rload_1. For each column of bit lines, the memristors R in that column are connected. The unit resistance of each section on the bit line is R_bl_wire. The bit line driving signal source Vread is a DC voltage source. The signal enters the array through the input resistor Rload_2. The source line of each column connects the sources of the transistors in the column. The unit resistance of each section of the source line is R_sl_wire. The current passing through each memristor is collected from the source line and flows through the output resistor Rload_3.

5. The method according to claim 3, characterized in that The step of modeling the conduction state of the transistors in the memristor array circuit comprises: When the input signal is 1, the cross unit Rcell is equivalent to a combination of a memristor and a transistor on-resistance; When the input signal is 0, the cross cell Rcell is equivalent to a combination of a memristor and a transistor off resistor; Applying a read voltage using the bit line maintains the bit line structure; Use the source line to sink the current and output the current through the output resistor.

6. The method according to claim 1, characterized in that Decompose the input of a single network layer of a convolutional neural network based on a memristor array circuit into multiple binary input vectors and assign simulation tasks, including: Each input vector is assigned to the corresponding memristor array circuit simulation task, and multi-node distributed computing is performed based on the message passing interface. Multiple processes are used in each node to run the Ngspice simulation task in parallel.

7. The method according to claim 6, characterized in that The circuit netlist is parsed and a simulation is run to calculate the output current based on the voltage signal and the device conductance value according to Kirchhoff's law, including: In each memristor array, the Ngspice API is called through the FFI interface to parse the circuit netlist and perform circuit simulation to obtain the sum of the column currents in each part; The step of converting the current output by each memristor array circuit simulation task into a digital signal includes: Regular expressions are used to process the Ngspice simulation callback results, extract the sum of the currents in each column output by each memristor array circuit simulation task, and quantize the currents into digital signals.

8. A memristor array circuit simulation device, characterized in that: The device comprises: A task decomposition module is used to decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assign simulation tasks; A netlist writing module is used to execute the simulation task in parallel based on a distributed, multi-process approach, map weight bits to multiple device conductances of the memristor array, map input bits to multiple voltage signals, and write a circuit netlist for each memristor array circuit in the simulation task; A simulation output module parses the circuit netlist and runs a simulation, and calculates the output current based on Kirchhoff's law according to the voltage signal and the device conductance value; The output processing module is used to convert the current output by each memristor array circuit simulation task into a digital signal, shift, add, and combine it to obtain an integer number, then dequantize the integer number into a floating-point number and add a bias term, and quantize it again to obtain the network layer output.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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