A standard cell layout optimization method and related equipment for FinFET process

Abstract

The present application discloses a standard cell layout optimization method and related equipment for FinFET process, including: constructing an initial layout optimization model according to initial layout information of standard cells, design cell information, physical constraint information and multi-objective requirements, wherein the initial layout optimization model includes decision variables, objective functions and constraints; performing a model mapping optimization operation on the initial layout optimization model to obtain multiple decision variable sub-problems and constraints of the sub-problems; performing quantum mapping on each decision variable sub-problem to obtain an equivalent Hamiltonian corresponding to each decision variable sub-problem; reducing the expected energy corresponding to each decision variable sub-problem through a quantum approximate optimization algorithm according to all decision variable sub-problems and their corresponding equivalent Hamiltonians, and obtaining a binary variable solution for each decision variable sub-problem; mapping the binary variable solution to the layout information of the standard cell to obtain the optimized layout information of the standard cell.

Description

Technical Field

[0001] The present specification relates to the field of electronic design automation, and more specifically, the present application relates to a standard cell layout optimization method and related equipment for FinFET process. Background Art

[0002] As integrated circuit design enters the FinFET (Fin Field-Effect Transistor) process node, the three-dimensional structure and complexity of transistors increase, making the placement algorithm of mature processes face huge challenges in dealing with massive DRC (Design Rule Check) rules, variable 3D track grids, routing resource allocation below the M3 metal level, three-dimensional routing congestion and DRC compliance.

[0003] In related technologies, methods such as simulated annealing are usually used for placement optimization. No matter how the objective function is set, parameters such as HPWL (Half Perimeter Wire Length), routing congestion, and pin density are used in advance as heuristic information to guide the placement optimization method from back to front. The limitations of the algorithm itself often lead to falling into the local optimal solution of placement, and ultimately it is difficult to obtain a good routing result, especially when exploring multiple goals such as the smallest chip design area, the lowest power consumption, and the highest main frequency. Once it falls into the local optimum, the optimal final result cannot be obtained, resulting in the GDS (Graphic Database System File) generated by the routing result being unmanufacturable or having no cost advantage, which brings irreparable losses to chip design.

[0004] Therefore, it is necessary to propose a standard cell layout optimization method and related equipment for FinFET process to at least solve some of the above problems. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In a first aspect, the present application proposes a standard cell layout optimization method for a FinFET process, comprising:

[0007] Constructing an initial layout optimization model according to initial layout information of standard cells, design cell information, physical constraint information and multi-objective requirements, wherein the initial layout optimization model includes decision variables, objective functions and constraint conditions;

[0008] The above layout optimization initial model is subjected to a model mapping optimization operation to obtain multiple decision variable sub-problems and constraint conditions of the sub-problems;

[0009] Perform quantum mapping according to each of the above decision variable sub-problems to obtain an equivalent Hamiltonian corresponding to each of the above decision variable sub-problems;

[0010] According to all decision variable subproblems and their corresponding equivalent Hamiltonians, the expected energy corresponding to each of the above decision variable subproblems is reduced through a quantum approximate optimization algorithm, and a binary variable solution for each of the above decision variable subproblems is obtained;

[0011] The above binary variables are demapped into the layout information of the standard cell to obtain the optimized layout information of the standard cell.

[0012] In a feasible implementation manner, the decision variable is whether the i-th standard unit is placed at position j; and / or,

[0013] The above objective function is based on the half-circle length sub-problem, the routing DRC estimation sub-function and the congestion sub-function; and / or,

[0014] The above constraints include placement position constraints and physical constraints. The above placement position constraints include that the placement position of each standard cell is unique, only one standard cell is placed at each position, and the position of the fixed standard cell is fixed. The above physical constraints include that each standard cell is placed on the wiring grid track and the standard cell is within the design area.

[0015] In a feasible implementation, the above-mentioned layout optimization initial model is subjected to a model mapping optimization operation to obtain multiple decision variable sub-problems and constraint conditions of the sub-problems, including:

[0016] The large-scale problem of the above layout optimization initial model is split into multiple small-scale decision variable sub-problems through a distributed quadratic unconstrained binary optimization algorithm;

[0017] According to the above objective function, the above decision variable sub-problem is added through the Lagrange multiplier method and converted into a penalty term;

[0018] According to the penalty coefficient of the above penalty item, the constraint conditions of the above sub-problem are obtained.

[0019] In a feasible implementation, the quantum mapping is performed according to each of the above decision variable sub-problems to obtain the equivalent Hamiltonian corresponding to each of the above decision variable sub-problems, including

[0020] Allocating quantum bits to each of the above decision variable subproblems to obtain independent mappings for each of the above decision variable subproblems;

[0021] The coupling coefficient of the decision variable sub-problem is defined in the quadratic unconstrained binary optimization matrix Q of the decision variable sub-problem, wherein the coupling coefficient is used to splice the independent mappings of the decision variable sub-problem, and the coupling coefficient is also used to characterize the objective function and constraint conditions of the decision variable sub-problem;

[0022] The quadratic unconstrained binary problem corresponding to the above decision variable subproblems is equivalent to the Ising model, and the equivalent Hamiltonian corresponding to each of the above decision variable subproblems is obtained.

[0023] In a feasible implementation, the above-mentioned method reduces the expected energy corresponding to each of the above-mentioned decision variable subproblems and their corresponding equivalent Hamiltonians through a quantum approximate optimization algorithm, and obtains a binary variable solution for each of the above-mentioned decision variable subproblems, including:

[0024] Using a distributed parallel approach, an independent initial state variable is set for each of the above decision variable sub-problems to obtain multiple initial quantum states;

[0025] For each of the above initial quantum states, an evolution operator is applied to the above equivalent Hamiltonian at the problem layer, a Pauli matrix operator is applied to the above equivalent Hamiltonian at the mixing layer, and iterative calculation is performed through multiple of the above problem layers and multiple of the above mixing layers to obtain the evolved quantum state;

[0026] Measuring the evolved quantum state to obtain a measurement result;

[0027] Calculate the expected energy for the above measurement results and the equivalent Hamiltonian;

[0028] The target optimizer is used to perform parameter tuning on the expected energy to reduce the expected energy corresponding to each of the decision variable sub-problems, and a binary variable solution for each of the decision variable sub-problems is obtained.

[0029] In a feasible implementation, it also includes:

[0030] Obtaining workload information in the process of reducing the expected energy corresponding to each of the above decision variable subproblems through quantum approximate optimization algorithms,

[0031] When the workload information exceeds a preset threshold, the remote platform is called to perform accelerated solution, and the solution result is sent to the local end so that the local end can continue to perform optimization operations based on the solution result.

[0032] In a feasible implementation, it also includes:

[0033] Performance evaluation of all binary variable solutions;

[0034] If the performance evaluation result does not meet the preset requirements, adjusting the weight coefficient corresponding to the objective function and / or the iteration depth of the quantum approximate optimization algorithm;

[0035] The binary variable solution is repeatedly solved based on the adjusted objective function and / or the adjusted quantum approximate optimization algorithm, so that the evaluation result of the binary variable solution meets the preset requirements or the number of repeated solutions reaches a preset number.

[0036] In a second aspect, the present application proposes a standard cell layout optimization device for FinFET process, comprising:

[0037] A construction unit is used to construct an initial layout optimization model according to the initial layout information of the standard unit, the design unit information, the physical constraint information and the multi-objective requirements, wherein the initial layout optimization model includes decision variables, objective functions and constraint conditions;

[0038] A first acquisition unit is used to perform a model mapping optimization operation on the above-mentioned layout optimization initial model to obtain multiple decision variable sub-problems and constraint conditions of the sub-problems;

[0039] A second acquisition unit is used to perform quantum mapping according to each of the above decision variable sub-problems to obtain an equivalent Hamiltonian corresponding to each of the above decision variable sub-problems;

[0040] A third acquisition unit is used to reduce the expected energy corresponding to each of the decision variable subproblems and their corresponding equivalent Hamiltonians through a quantum approximate optimization algorithm, and obtain a binary variable solution for each of the decision variable subproblems;

[0041] The fourth acquisition unit is used to demap the binary variable into the layout information of the standard cell to obtain the optimized layout information of the standard cell.

[0042] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is used to implement the steps of the standard cell layout optimization method of the FinFET process as described in any one of the first aspects above when executing the computer program stored in the memory.

[0043] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the standard cell layout optimization method of the FinFET process of any one of the first aspects is implemented.

[0044] In summary, the present application proposes a standard cell layout optimization method for FinFET process, including: constructing a layout optimization initial model according to the initial layout information of the standard cell, the design cell information, the physical constraint information and the multi-objective requirements, wherein the above-mentioned layout optimization initial model includes decision variables, objective functions and constraints; performing model mapping optimization operation on the above-mentioned layout optimization initial model to obtain multiple decision variable sub-problems and constraints of the sub-problems; performing quantum mapping according to each of the above-mentioned decision variable sub-problems to obtain the equivalent Hamiltonian corresponding to each of the above-mentioned decision variable sub-problems; according to all the decision variable sub-problems and their corresponding equivalent Hamiltonian, using the quantum approximate optimization algorithm, reducing the expected energy corresponding to each of the above-mentioned decision variable sub-problems, and obtaining the binary variable solution of each of the above-mentioned decision variable sub-problems; mapping the above-mentioned binary variable solution to the layout information of the standard cell to obtain the standard cell optimization layout information. Compared with the traditional simulated annealing method, the method proposed in the embodiment of the present application significantly reduces the running time by using parallel computing and tunneling effect. Even in the face of design problems of hundreds of millions of cells, it can converge quickly. Avoid falling into the local optimal solution through quantum tunneling to ensure that the optimization result is closer to the global optimal solution. The generated optimized layout information meets the DRC rules and significantly improves the manufacturability of the chip. The layout scheme can be directly applied to FinFET process design to support high-performance and low-power chip requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0046] Figure 1 A schematic diagram of a standard cell layout optimization method for a FinFET process provided in an embodiment of the present application;

[0047] Figure 2 A schematic diagram of the structure of a standard cell layout optimization device for a FinFET process provided in an embodiment of the present application;

[0048] Figure 3 A schematic diagram of an electronic device structure for optimizing the standard cell layout of a FinFET process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0050] See also Figure 1 , is a schematic flow chart of a standard cell layout optimization method for a FinFET process provided in an embodiment of the present application, and the method may specifically include:

[0051] S110, constructing an initial layout optimization model according to the initial layout information of the standard cells, the design cell information, the physical constraint information and the multi-objective requirements, wherein the initial layout optimization model includes decision variables, objective functions and constraint conditions;

[0052] Exemplarily, the initial layout information of standard cells includes the initial coordinates and layout status of each cell. Design cell information includes cell type (STDCell or Macro Cell), size, functional attributes, etc. Physical constraint information includes constraints such as design cells cannot exceed the chip design area, cells need to maintain a certain distance, wiring grid alignment, etc. Multi-objective requirements include optimization goals (such as half-perimeter wire length HPWL, wiring congestion, power consumption, etc.), which need to be balanced according to design requirements.

[0053] Building the initial model specifically includes:

[0054] 1. Define decision variables: such as q i,j Indicates standard unit S i Whether it is placed at position j.

[0055] 2. Define the objective function: Integrate multiple objectives and express them in functional form to minimize the multi-objective optimization function F2.

[0056] 3. Define constraints: Each cell must be uniquely placed (∑ j q i,j =1). Each position can only accommodate one unit (∑i q i,j =1). Physical constraints are met (such as boundary restrictions, routing track rules, etc.).

[0057] S120, performing a model mapping optimization operation on the above-mentioned layout optimization initial model to obtain multiple decision variable sub-problems and constraint conditions of the sub-problems;

[0058] For example, the initial layout optimization model may be too complex and computationally intensive. Through model mapping, the entire layout problem is decomposed into multiple independent or coupled small-scale sub-problems. Constraints need to be divided into each sub-problem, such as: cell position constraints are within a local range, and the sub-problems influence each other through coupling coefficients.

[0059] S130, performing quantum mapping according to each of the above decision variable sub-problems to obtain an equivalent Hamiltonian corresponding to each of the above decision variable sub-problems;

[0060] Exemplarily, each subproblem is mapped to an equivalent quantum model, such as the QUBO (Quadratic Unconstrained Binary Optimization) model.

[0061] The expression of QUBO is:

[0062] ,

[0063] Where Q is the weight matrix and c is a constant.

[0064] The QUBO problem can be further transformed into the Ising model:

[0065] ,

[0066] Where: Z i and Z j is the Pauli Z matrix of the qubit, representing the spin states of qubits i and j. i and J ij are the linear and quadratic coupling coefficients in the Hamiltonian.

[0067] According to the optimization goal, the various parts of the multi-objective function F2 are decomposed and quantized. The constraints are added to the quantum Hamiltonian through penalty terms.

[0068] S140, according to all decision variable subproblems and their corresponding equivalent Hamiltonians, reducing the expected energy corresponding to each of the above decision variable subproblems through a quantum approximate optimization algorithm, and obtaining a binary variable solution for each of the above decision variable subproblems;

[0069] For example, QAOA (Quantum Approximate Optimization Algorithm) is run on a quantum computing platform. The expected energy is optimized through quantum tunneling and quantum superposition to jump out of the local optimal solution. The state of the quantum bit corresponding to each sub-problem is initialized. Using QAOA loop optimization, the problem layer (Problem Layer) and the mixing layer (Mixing Layer) are alternately applied to the quantum state. Parameters (such as rotation angle) are adjusted to minimize the expected energy, and finally a binary solution is obtained.

[0070] S150 , demap the above binary variables into layout information of the standard cell to obtain optimized layout information of the standard cell.

[0071] For example, the binary variable solution (sub-problem result) obtained by quantum computing is mapped back to the layout information of the design unit. The position S of each design unit i (x i , y i ) is re-optimized. The optimized placement information takes into account global goals (such as minimizing HPWL, reducing routing congestion, etc.) to ensure that physical constraints are met. The optimized placement information can be directly used as input for subsequent routing stages, significantly improving DRC compliance and routing efficiency.

[0072] In summary, the method proposed in the embodiment of the present application significantly reduces the running time by utilizing parallel computing and tunneling effect compared to the traditional simulated annealing method. Even in the face of design problems with hundreds of millions of units, it can converge quickly. Quantum tunneling is used to avoid falling into the local optimal solution and ensure that the optimization result is closer to the global optimal solution. The generated optimized layout information meets the DRC rules and significantly improves the manufacturability of the chip. The layout scheme can be directly applied to FinFET process design to support high-performance and low-power chip requirements.

[0073] In some examples, the decision variable is whether the i-th standard unit is placed at position j; and / or,

[0074] The above objective function is based on the half-circle length sub-problem, the routing DRC estimation sub-function and the congestion sub-function; and / or,

[0075] The above constraints include placement position constraints and physical constraints. The above placement position constraints include that the placement position of each standard cell is unique, only one standard cell is placed at each position, and the position of the fixed standard cell is fixed. The above physical constraints include that each standard cell is placed on the wiring grid track and the standard cell is within the design area.

[0076] Exemplarily, the position of each standard cell is represented by a binary variable. For example, the variable q i,jIndicates whether the i-th standard cell is placed at position j: if q i,j = 1, then standard cell i is placed at position j. If q i,j =0, then standard cell i is not at position j.

[0077] The objective function combines key optimization goals in chip design, including the half-perimeter wire length sub-problem (HPWL), the routing DRC estimation sub-function, and the congestion sub-function

[0078] The goal of the half-perimeter wire length subproblem (HPWL) is to minimize the total wire length of the chip: Half-perimeter wire length is a classic way to measure the cost of wiring, which estimates the wire length by calculating the perimeter of the network bounding box.

[0079] The formula means:

[0080]

[0081] In the quantum model, HPWL is quantized as part of the energy objective function, max x is the maximum value of the x-coordinate of all connection points in the network, min x is the minimum x-coordinate value of all connection points in the network, max y is the maximum value of the y coordinates of all connection points in the network, min y is the minimum value of the y coordinates of all connection points in the network.

[0082] The routing DRC estimation sub-function estimates potential routing conflicts based on the constraints of the design rule check (DRC). The sub-function generates estimates by evaluating the distribution of routing resources and possible violations and incorporates them into the objective function optimization.

[0083] Local congestion in chip layout will increase routing difficulty and even lead to routing failure. The congestion subfunction analyzes local cell density and routing resource utilization and marks high-density areas as high-cost areas.

[0084] The objective function combined with the above sub-problems can be optimized by linear weighting

[0085]

[0086] in, , and It can be adjusted according to specific design requirements.

[0087] The method proposed in the embodiment of the present application obtains the optimal layout solution by comprehensively considering the semi-circumference line length, wiring rules and congestion. The parallelism and tunneling effect of quantum computing are used to break through the limitation of local optimal solution. The design constraints are strictly observed to ensure that the generated layout solution meets the manufacturing requirements.

[0088] In some examples, the above-mentioned layout optimization initial model is subjected to a model mapping optimization operation to obtain multiple decision variable sub-problems and constraint conditions of the sub-problems, including:

[0089] The large-scale problem of the above layout optimization initial model is split into multiple small-scale decision variable sub-problems through a distributed quadratic unconstrained binary optimization algorithm;

[0090] According to the above objective function, the above decision variable sub-problem is added through the Lagrange multiplier method and converted into a penalty term;

[0091] According to the penalty coefficient of the above penalty item, the constraint conditions of the above sub-problem are obtained.

[0092] For example, in standard cell layout optimization, large-scale problems usually contain tens of thousands of standard cells and possible placement locations. Directly solving these problems will result in excessive computation and difficulty in fast convergence. Decompose the initial model of layout optimization into multiple small-scale sub-problems to reduce the complexity of a single calculation. Based on the design area, the standard cells can be divided into multiple local areas, and the cells in the local area are regarded as a sub-problem. In a distributed system, each sub-problem is optimized independently, and the consistency of the overall layout is maintained between multiple sub-problems through coupling coefficients. For example: suppose a design area contains 1,000 standard cells, divided into 10 local areas, each area contains 100 cells. The optimization of each area is treated as an independent sub-problem and handled separately.

[0093] The sub-problem needs to optimize the objective function and satisfy the constraints at the same time. Through the Lagrange multiplier method, the constraints are transformed into penalty terms in the objective function. The penalty terms of the constraints are introduced into the objective function, for example:

[0094]

[0095] The first term enforces that each cell can only be placed in one position. The second term ensures that each position can only hold one cell. is the penalty coefficient, which is used to control the importance of the constraint. The sub-problem optimization is transformed into a single objective function optimization, and the constraint is indirectly reflected through the penalty term. A binary variable indicating whether the i-th standard cell is placed at the j-th position.

[0096] The value of determines the weight of the constraints in the optimization process. A larger λ value will make the constraints stricter, but may reduce the optimization effect of the objective function. A smaller λ value will tend to optimize the objective function more, but may violate the constraints.

[0097] Constraints expressed through penalty terms are automatically satisfied during optimization. For example: Uniqueness constraint: Each unit can only be placed in a unique location. Location conflict constraint: A location can only accommodate one unit. Physical restriction: The unit must be within the design area. During the optimization process, the penalty coefficient can be dynamically adjusted according to the conflict between the objective function and the constraints to ensure a balance between the two.

[0098] Through a distributed method, large-scale problems are decomposed into multiple sub-problems that can be solved in parallel, greatly reducing the calculation time. Constraints are introduced through penalty terms to ensure that the layout results meet physical limitations and design rules. The sub-problems maintain global consistency through coupling coefficients, and the final optimized layout meets both global goals and local constraints. The penalty coefficient is dynamically adjusted according to design requirements to flexibly handle the balance between the objective function and the constraints. The method proposed in this embodiment is particularly suitable for ultra-large-scale standard cell layout optimization problems. Through distributed quantum optimization methods, the efficiency and accuracy bottlenecks of traditional methods in large-scale problems are solved, providing an efficient solution for modern FinFET process chip design.

[0099] In some examples, the quantum mapping is performed according to each of the above decision variable subproblems to obtain an equivalent Hamiltonian corresponding to each of the above decision variable subproblems, including

[0100] Allocating quantum bits to each of the above decision variable subproblems to obtain independent mappings for each of the above decision variable subproblems;

[0101] The coupling coefficient of the decision variable sub-problem is defined in the quadratic unconstrained binary optimization matrix Q of the decision variable sub-problem, wherein the coupling coefficient is used to splice the independent mappings of the decision variable sub-problem, and the coupling coefficient is also used to characterize the objective function and constraint conditions of the decision variable sub-problem;

[0102] The quadratic unconstrained binary problem corresponding to the above decision variable subproblems is equivalent to the Ising model, and the equivalent Hamiltonian corresponding to each of the above decision variable subproblems is obtained.

[0103] For example, map the variables in each decision variable subproblem to qubits. Ensure that each subproblem has an independent qubit allocation. Assume that the decision variable subproblem contains n decision variables (q i,j Indicates whether unit i is placed at position j), then n qubits are allocated to this subproblem. Each qubit corresponds to a binary variable with a value of 0 or 1. For a subproblem q1,1 ,q 1,2 ,q 1,3 , assigning three quantum bits Q 1 ,Q 2 ,Q 3 .Q k =1 indicates a specific state of the decision variable.

[0104] The core of the QUBO problem is the matrix form of the objective function:

[0105]

[0106] is the decision variable vector. is a weight matrix, where each element Represents decision variables and The integration coefficient of . is a constant.

[0107] Within the subproblem, the coupling coefficients between variables are defined to express the objective function and constraints. For example: for the uniqueness constraint , by adding a penalty term:

[0108]

[0109] The constraints are decomposed into the diagonal and off-diagonal elements of the QUBO matrix.

[0110] If there are interactions between subproblems, define the combination coefficients across the subproblems to express the overall objective function. For example, if the placement of subproblem A affects the congestion of subproblem B, define additional coupling coefficients express this relationship.

[0111] Assume that the subproblem contains three variables , whose goal is to minimize:

[0112]

[0113] The corresponding QUBO matrix for:

[0114]

[0115] The Ising model is used for quantum computing optimization problems and its form is:

[0116]

[0117] and Pauli A matrix representing the state of a quantum bit. is a linear term, representing the weight of a single variable. is a quadratic coupling term, which represents the interaction between variables.

[0118] Conversion from QUBO to Ising model, variables in QUBO Transformed into the quantum bit state in the Ising model:

[0119]

[0120] Replace the matrix form in the QUBO objective function with the Hamiltonian form of the Ising model:

[0121] Linear term Convert to The quadratic coupling term Convert to The converted Ising model Hamiltonian is used in the quantum optimization process. For the above QUBO matrix , the corresponding Ising model after conversion is:

[0122]

[0123] In summary, in the method provided in this embodiment, qubits are independently assigned to each sub-problem to reduce interference between qubits and improve parallel optimization efficiency. The objective function and constraints are expressed by the coupling coefficient of the QUBO matrix to support accurate modeling of complex problems. The QUBO problem is converted into an Ising model to provide the equivalent Hamiltonian required for optimization for quantum computing platforms (such as D-WAVE). Distributed quantum mapping and coupled splicing make the layout optimization problem of ultra-large-scale standard cells feasible on quantum computing platforms.

[0124] In some examples, the above-mentioned method reduces the expected energy corresponding to each of the above-mentioned decision variable subproblems and their corresponding equivalent Hamiltonians through a quantum approximate optimization algorithm, and obtains a binary variable solution for each of the above-mentioned decision variable subproblems, including:

[0125] Using a distributed parallel approach, an independent initial state variable is set for each of the above decision variable sub-problems to obtain multiple initial quantum states;

[0126] For each of the above initial quantum states, an evolution operator is applied to the above equivalent Hamiltonian at the problem layer, a Pauli matrix operator is applied to the above equivalent Hamiltonian at the mixing layer, and iterative calculation is performed through multiple of the above problem layers and multiple of the above mixing layers to obtain the evolved quantum state;

[0127] Measuring the evolved quantum state to obtain a measurement result;

[0128] Calculate the expected energy for the above measurement results and the equivalent Hamiltonian;

[0129] The target optimizer is used to perform parameter tuning on the expected energy to reduce the expected energy corresponding to each of the decision variable sub-problems, and a binary variable solution for each of the decision variable sub-problems is obtained.

[0130] Exemplarily, each subproblem initializes its quantum state independently to support distributed parallel computing.

[0131] The initial state is usually a uniform superposition state. :

[0132]

[0133] is the number of qubits in the subproblem. The uniform superposition state ensures that the initial probability of the qubit in all possible states is equal. Each subproblem sets the initial state variable independently to ensure that there is no interference between the subproblems, which is convenient for parallel optimization. Represents the basis vectors of the quantum state x.

[0134] QAOA consists of a problem layer and a mixing layer that act alternately, and optimizes the objective function through multiple iterations.

[0135] At the problem level, the equivalent Hamiltonian of the subproblem Apply evolution operations:

[0136]

[0137] As the Hamiltonian of the subproblem, define the objective function, Represents the evolution operation of the problem layer. is the parameter of the problem layer, which is adjusted by the optimizer. After the action, the quantum state becomes:

[0138]

[0139] In the mixed layer, the Pauli Matrix evolution operations:

[0140]

[0141] Represents the evolution operation of the mixing layer. For the Pauli Operator. are the parameters of the mixing layer, adjusted by the optimizer.

[0142] After the action, the quantum state is further updated to:

[0143]

[0144] Problem layer and mixed layer act alternately times, generating the final evolution state:

[0145]

[0146] and is an adjustable parameter of the j-th problem layer and the mixing layer.

[0147] The final evolutionary state Perform measurements and obtain the measurement results represented by classical bits. Each measurement will produce a binary result. To improve accuracy, it is necessary to measure the evolving state multiple times and record all the measurement results. The frequency distribution of each measurement result is statistically analyzed for the calculation of the expected energy.

[0148] Calculate the expectation value of the Hamiltonian for the measurement results:

[0149]

[0150] Through statistical measurement results The corresponding energy , calculate the expected value:

[0151]

[0152] Status The probability distribution of . Status The corresponding Hamiltonian value.

[0153] Parameter tuning to reduce expected energy, adjust problem layer parameters and mixing layer parameters , to minimize the expected energy . Use classic optimizers (such as gradient descent, Nelder-Mead algorithm, etc.) to tune parameters.

[0154] Iterative update through optimization algorithm :

[0155]

[0156] When the expected energy converges to the minimum value, the binary solution corresponding to the optimal measurement result is selected as the final solution of the subproblem.

[0157] The method proposed in this embodiment adopts a distributed parallel approach, and each sub-problem is optimized independently, which significantly speeds up the overall calculation speed. By alternating between the problem layer and the mixed layer, it is ensured that the optimization process fully explores the state space and avoids local optimal solutions. Through the collaboration of the quantum tunneling effect and the optimizer, the expected energy is greatly reduced and converges quickly to the optimal solution. The optimal binary solution reflects the global optimal placement result of the sub-problem, providing key support for the layout optimization of the standard cell.

[0158] In some examples, this also includes:

[0159] Obtaining workload information in the process of reducing the expected energy corresponding to each of the above decision variable subproblems through quantum approximate optimization algorithms,

[0160] When the workload information exceeds a preset threshold, the remote platform is called to perform accelerated solution, and the solution result is sent to the local end so that the local end can continue to perform optimization operations based on the solution result.

[0161] For example, during the optimization process, the usage of computing resources and the complexity of tasks are dynamically monitored. The workload information includes, but is not limited to, the number of qubits n of the subproblem, the number of layers p of the substate evolution, the number of optimization iterations and the convergence speed, and the occupancy of local computing resources (such as CPU, memory, GPU utilization), etc.

[0162] In each QAOA parameter optimization iteration, the above workload information is collected and compared with the preset threshold. The threshold is set according to the hardware performance and task requirements. For example: the number of quantum bits n>100, the number of evolution layers p>10, and the single iteration time t>10 seconds.

[0163] When the workload information is monitored to exceed the preset threshold (such as the sub-problem is too complex or the local computing resources are insufficient), remote solving is started. Choice of remote platform: Common quantum computing hardware platforms (such as D-WAVE, IBM Quantum). High-performance distributed computing platforms (such as AWS Braket, Google Quantum AI).

[0164] Package the quantum model of the subproblem (such as QUBO matrix or equivalent Hamiltonian) and send it to the remote platform. Perform QAOA optimization operations on the remote platform: set initial parameters (γ, β). Call remote hardware resources for quantum state evolution, measurement, and expected energy calculation. Return remote solution results (such as optimal binary solution and optimization parameters).

[0165] The remote results include the optimal parameters , optimal binary solutions to the subproblems, and workload feedback (e.g., total solution time, resource usage) on the remote platform.

[0166] Based on the optimal parameters and solutions returned by the remote server, continue the local optimization: adjust the optimization strategies of other sub-problems, new global objective functions and constraints. Integrate the remote and local solution results to generate a complete optimization layout.

[0167] The method provided in this embodiment monitors the workload in real time and dynamically determines whether remote resources need to be called to avoid local performance bottlenecks caused by excessive computing. Combined with the powerful computing power of the remote quantum computing platform, the solution of complex sub-problems is accelerated, while other optimization tasks continue to be performed locally to improve overall efficiency. The remote solution results are combined with the local optimization results to achieve seamless collaboration between sub-problems and ensure the global consistency of the final layout optimization results. In the face of ultra-large-scale standard unit optimization problems, remote resources can be flexibly scheduled, which expands the scope of application of the algorithm.

[0168] In some examples, this also includes:

[0169] Performance evaluation of all binary variable solutions;

[0170] If the performance evaluation result does not meet the preset requirements, adjusting the weight coefficient corresponding to the objective function and / or the iteration depth of the quantum approximate optimization algorithm;

[0171] The binary variable solution is repeatedly solved based on the adjusted objective function and / or the adjusted quantum approximate optimization algorithm, so that the evaluation result of the binary variable solution meets the preset requirements or the number of repeated solutions reaches a preset number.

[0172] Exemplarily, it is checked whether the binary variable solution obtained by QAOA meets the design requirements and constraints of the problem. Performance evaluation includes objective function value verification, constraint condition checking and design performance verification.

[0173] Compute how all binary solutions perform on the objective function, for example:

[0174]

[0175] Ensure that the objective function value is close to the theoretical optimal value.

[0176] Constraint checking verifies that the solution meets design rules and physical constraints, such as whether each cell is placed in a unique location, whether it exceeds the design area, etc.

[0177] Design performance verification includes evaluating the design performance (such as power consumption, delay, area, etc.) corresponding to the solution.

[0178] If the evaluation result meets the preset requirements, the solution is accepted as the final result. If it does not meet the requirements, the next step is to adjust the optimization parameters. According to the performance evaluation results, the weight coefficients in the multi-objective optimization are adjusted to rebalance the optimization direction.

[0179] For example: If the congestion problem of the solution is found to be serious, increase λ 3 (Congestion assessment weight). If the connection length (HPWL) is too long, increase λ 1 Adjust the number of iterations p of the problem layer and the mixed layer in QAOA to improve the solution accuracy. Increasing p allows the quantum state to explore the solution space more fully, but it will increase the computational complexity. For example: Initial parameter: λ 1 =1,λ 2 =1,λ 3 =1, iteration depth p=5. If the evaluation finds that the objective function value does not meet expectations: New parameter: λ 1 =2,λ 2 =1,λ 3 , p=8.

[0180] Using the adjusted objective function weight coefficient and iteration depth, QAOA is re-executed to obtain a new binary variable solution. If the new binary solution passes the performance evaluation, the optimization process is stopped and the solution is accepted as the final result. Alternatively, if the optimization is repeated for a preset number of times (such as 10 times), the optimization is stopped and the best solution is returned even if the performance evaluation does not fully meet the requirements.

[0181] The method proposed in this embodiment ensures that the optimization process focuses on the main problem by adjusting the objective function weight coefficient and dynamically responding to the feedback of the performance evaluation results. The iteration depth of QAOA can be adjusted to balance the quality of the solution and the computational complexity to adapt to problems of different scales and complexities. Through multiple solutions and evaluations, it is ensured that the final solution meets the design performance requirements to avoid suboptimal results caused by insufficient single optimization. Stop the optimization after the performance evaluation meets the requirements or reaches the preset number of times to ensure the convergence and execution efficiency of the algorithm.

[0182] like Figure 2 As shown, the present application proposes a standard cell layout optimization device for FinFET process, including:

[0183] A construction unit 21 is used to construct an initial layout optimization model according to the initial layout information of the standard cells, the design cell information, the physical constraint information and the multi-objective requirements, wherein the initial layout optimization model includes decision variables, objective functions and constraint conditions;

[0184] A first acquisition unit 22 is used to perform a model mapping optimization operation on the above-mentioned layout optimization initial model to obtain a plurality of decision variable sub-problems and constraint conditions of the sub-problems;

[0185] A second acquisition unit 23 is used to perform quantum mapping according to each of the above decision variable sub-problems to obtain an equivalent Hamiltonian corresponding to each of the above decision variable sub-problems;

[0186] A third acquisition unit 24 is used to reduce the expected energy corresponding to each of the decision variable subproblems and their corresponding equivalent Hamiltonians through a quantum approximate optimization algorithm, and obtain a binary variable solution for each of the decision variable subproblems;

[0187] The fourth acquisition unit 25 is used to demap the above binary variables into the layout information of the standard cells to obtain the optimized layout information of the standard cells.

[0188] The standard cell layout optimization device of the FinFET process may further perform the following steps:

[0189] In some examples, the decision variable is whether the i-th standard unit is placed at position j; and / or,

[0190] The above objective function is based on the half-circle length sub-problem, the routing DRC estimation sub-function and the congestion sub-function; and / or,

[0191] The above constraints include placement position constraints and physical constraints. The above placement position constraints include that the placement position of each standard cell is unique, only one standard cell is placed at each position, and the position of the fixed standard cell is fixed. The above physical constraints include that each standard cell is placed on the wiring grid track and the standard cell is within the design area.

[0192] In some examples, the above-mentioned layout optimization initial model is subjected to a model mapping optimization operation to obtain multiple decision variable sub-problems and constraint conditions of the sub-problems, including:

[0193] The large-scale problem of the above layout optimization initial model is split into multiple small-scale decision variable sub-problems through a distributed quadratic unconstrained binary optimization algorithm;

[0194] According to the above objective function, the above decision variable sub-problem is added through the Lagrange multiplier method and converted into a penalty term;

[0195] According to the penalty coefficient of the above penalty item, the constraint conditions of the above sub-problem are obtained.

[0196] In some examples, the quantum mapping is performed according to each of the above decision variable subproblems to obtain an equivalent Hamiltonian corresponding to each of the above decision variable subproblems, including

[0197] Allocating quantum bits to each of the above decision variable subproblems to obtain independent mappings for each of the above decision variable subproblems;

[0198] The coupling coefficient of the decision variable sub-problem is defined in the quadratic unconstrained binary optimization matrix Q of the decision variable sub-problem, wherein the coupling coefficient is used to splice the independent mappings of the decision variable sub-problem, and the coupling coefficient is also used to characterize the objective function and constraint conditions of the decision variable sub-problem;

[0199] The quadratic unconstrained binary problem corresponding to the above decision variable subproblems is equivalent to the Ising model, and the equivalent Hamiltonian corresponding to each of the above decision variable subproblems is obtained.

[0200] In some examples, the above-mentioned method reduces the expected energy corresponding to each of the above-mentioned decision variable subproblems and their corresponding equivalent Hamiltonians through a quantum approximate optimization algorithm, and obtains a binary variable solution for each of the above-mentioned decision variable subproblems, including:

[0201] Using a distributed parallel approach, an independent initial state variable is set for each of the above decision variable sub-problems to obtain multiple initial quantum states;

[0202] For each of the above initial quantum states, an evolution operator is applied to the above equivalent Hamiltonian at the problem layer, a Pauli matrix operator is applied to the above equivalent Hamiltonian at the mixing layer, and iterative calculation is performed through multiple of the above problem layers and multiple of the above mixing layers to obtain the evolved quantum state;

[0203] Measuring the evolved quantum state to obtain a measurement result;

[0204] Calculate the expected energy for the above measurement results and the equivalent Hamiltonian;

[0205] The target optimizer is used to perform parameter tuning on the expected energy to reduce the expected energy corresponding to each of the decision variable sub-problems, and a binary variable solution for each of the decision variable sub-problems is obtained.

[0206] In some examples, this also includes:

[0207] Obtaining workload information in the process of reducing the expected energy corresponding to each of the above decision variable subproblems through quantum approximate optimization algorithms,

[0208] When the workload information exceeds a preset threshold, the remote platform is called to perform accelerated solution, and the solution result is sent to the local end so that the local end can continue to perform optimization operations based on the solution result.

[0209] In some examples, this also includes:

[0210] Performance evaluation of all binary variable solutions;

[0211] If the performance evaluation result does not meet the preset requirements, adjusting the weight coefficient corresponding to the objective function and / or the iteration depth of the quantum approximate optimization algorithm;

[0212] The binary variable solution is repeatedly solved based on the adjusted objective function and / or the adjusted quantum approximate optimization algorithm, so that the evaluation result of the binary variable solution meets the preset requirements or the number of repeated solutions reaches a preset number.

[0213] like Figure 3 As shown, an embodiment of the present application also provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor, and when the processor 320 executes the computer program 311, the steps of any method of optimizing the standard cell layout of the above-mentioned FinFET process are implemented.

[0214] Since the electronic device introduced in this embodiment is a device used to implement a standard cell layout optimization device of a FinFET process in the embodiment of the present application, based on the method introduced in the embodiment of the present application, the technical personnel in this field can understand the specific implementation of the electronic device of the present embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by the technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0215] In the specific implementation process, when the computer program 311 is executed by the processor, it can achieve Figure 1 Any implementation manner in the corresponding embodiments.

[0216] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0217] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0218] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0219] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0220] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0221] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes a standard cell layout optimization process of the FinFET process in the corresponding embodiment.

[0222] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)), etc.

[0223] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0224] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0225] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0226] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0227] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0228] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A standard cell layout optimization method for FinFET process, characterized in that: include: Constructing an initial layout optimization model according to initial layout information of standard cells, design cell information, physical constraint information and multi-objective requirements, wherein the initial layout optimization model includes decision variables, objective functions and constraint conditions; Performing a model mapping optimization operation on the layout optimization initial model to obtain multiple decision variable sub-problems and constraint conditions of the sub-problems; Perform quantum mapping according to each of the decision variable sub-problems to obtain an equivalent Hamiltonian corresponding to each of the decision variable sub-problems; According to all decision variable subproblems and their corresponding equivalent Hamiltonians, the expected energy corresponding to each decision variable subproblem is reduced by a quantum approximate optimization algorithm, and a binary variable solution for each decision variable subproblem is obtained; The binary variable is demapped into the layout information of the standard cell to obtain the standard cell optimized layout information.

2. The standard cell layout optimization method of FinFET process according to claim 1, characterized in that: The decision variable is whether the i-th standard unit is placed at position j; and / or, The objective function is based on the half-perimeter line length sub-problem, the routing DRC estimation sub-function and the congestion sub-function; and / or, The constraints include placement position constraints and physical constraints. The placement position constraints include that the placement position of each standard cell is unique, only one standard cell is placed at each position, and the position of the fixed standard cell is fixed. The physical constraints include that each standard cell is placed on a routing grid track and the standard cell is within the design area.

3. The standard cell layout optimization method of FinFET process according to claim 1, characterized in that: The initial layout optimization model is subjected to a model mapping optimization operation to obtain a plurality of decision variable sub-problems and constraint conditions of the sub-problems, including: The large-scale problem of the layout optimization initial model is split into multiple small-scale decision variable sub-problems by using a distributed quadratic unconstrained binary optimization algorithm; According to the objective function, the decision variable sub-problem is added by Lagrange multiplier method and converted into a penalty term; According to the penalty coefficient of the penalty item, the constraint condition of the sub-problem is obtained.

4. The standard cell layout optimization method of FinFET process according to claim 1, characterized in that: The quantum mapping is performed according to each of the decision variable sub-problems to obtain an equivalent Hamiltonian corresponding to each of the decision variable sub-problems, including Allocating a quantum bit to each of the decision variable subproblems to obtain an independent mapping of each of the decision variable subproblems; The coupling coefficient of the decision variable subproblem is defined in the quadratic unconstrained binary optimization matrix Q of the decision variable subproblem, wherein the coupling coefficient is used to splice the independent mappings of the decision variable subproblem, and the coupling coefficient is also used to characterize the objective function and constraint conditions of the decision variable subproblem; The quadratic unconstrained binary problem corresponding to the decision variable subproblem is equivalent to an Ising model, and an equivalent Hamiltonian corresponding to each decision variable subproblem is obtained.

5. The standard cell layout optimization method of FinFET process according to claim 1, characterized in that: The method of reducing the expected energy corresponding to each decision variable subproblem and obtaining a binary variable solution for each decision variable subproblem by using a quantum approximate optimization algorithm according to all decision variable subproblems and their corresponding equivalent Hamiltonians includes: Using a distributed parallel approach to set an independent initial state variable for each of the decision variable sub-problems to obtain multiple initial quantum states; For each of the initial quantum states, an evolution operator is applied to the equivalent Hamiltonian at the problem layer, a Pauli matrix operator is applied to the equivalent Hamiltonian at the mixing layer, and iterative calculation is performed through a plurality of the problem layers and a plurality of the mixing layers to obtain an evolved quantum state; Measuring the evolved quantum state to obtain a measurement result; Calculating expected energy for the measurement results and the equivalent Hamiltonian; The expected energy is parameter-tuned using a target optimizer to reduce the expected energy corresponding to each of the decision variable sub-problems, and a binary variable solution for each of the decision variable sub-problems is obtained.

6. The standard cell layout optimization method of FinFET process according to claim 5, characterized in that: Also includes: Obtaining workload information in the process of reducing the expected energy corresponding to each of the decision variable subproblems through a quantum approximate optimization algorithm, When the workload information exceeds a preset threshold, the remote platform is called to perform accelerated solution, and the solution result is sent to the local end so that the local end can continue to perform optimization operations based on the solution result.

7. The standard cell layout optimization method of FinFET process according to any one of claims 1 to 6, characterized in that: Also includes: Performance evaluation of all binary variable solutions; When the performance evaluation result does not meet the preset requirements, adjusting the weight coefficient corresponding to the objective function and / or the iteration depth of the quantum approximate optimization algorithm; The binary variable solution is repeatedly solved based on the adjusted objective function and / or the adjusted quantum approximate optimization algorithm, so that the evaluation result of the binary variable solution meets the preset requirement or the number of repeated solutions reaches a preset number.

8. A standard cell layout optimization device for FinFET process, characterized in that: include: A construction unit, used to construct an initial layout optimization model according to the initial layout information of the standard unit, the design unit information, the physical constraint information and the multi-objective requirements, wherein the initial layout optimization model includes decision variables, objective functions and constraint conditions; A first acquisition unit is used to perform a model mapping optimization operation on the layout optimization initial model to obtain a plurality of decision variable sub-problems and constraint conditions of the sub-problems; A second acquisition unit is used to perform quantum mapping according to each of the decision variable sub-problems to obtain an equivalent Hamiltonian corresponding to each of the decision variable sub-problems; A third acquisition unit is used to reduce the expected energy corresponding to each decision variable subproblem through a quantum approximate optimization algorithm according to all decision variable subproblems and their corresponding equivalent Hamiltonians, and to obtain a binary variable solution for each decision variable subproblem; The fourth acquisition unit is used to demap the binary variable into the layout information of the standard cell to obtain the standard cell optimized layout information.

9. An electronic device, comprising: A memory and a processor, wherein the processor is used to implement the steps of the standard cell layout optimization method of the FinFET process as described in any one of claims 1 to 7 when executing the computer program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the standard cell layout optimization method of the FinFET process according to any one of claims 1 to 7 are implemented.

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