Method, device and equipment for displaying register address in programmable logic controller

Abstract

The invention discloses a method, a device and equipment for displaying a register address in a programmable logic controller, and relates to the technical field of computers, the method comprises the following steps: in response to a received register address display request, executing a reading operation on a register address storage area of the programmable logic controller to obtain read data, the read data comprises a plurality of byte data arranged continuously, and a part of byte data is used for identifying a starting point position of a register address; executing analysis operation according to different analysis data lengths from a starting point position of a register address in the read data to obtain a plurality of pieces of analysis data; one of the multiple pieces of analysis data corresponding to each starting point position is a register address; and performing distinguished display on the analysis data.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device and apparatus for displaying register addresses in a programmable logic controller. Background Art

[0002] In industrial automation systems, PLC (Programmable Logic Controller) is widely used in the control and monitoring of various production processes. PLC stores control data, status information and sensor readings through registers. HMI (Human Machine Interface) provides an interface for interaction with operators to display the operating status and data of PLC controllers.

[0003] In the prior art, such as Figure 1 As shown, the register address in the PLC displays the byte data directly to the user in the form of a continuous string. The user needs to distinguish the register address one by one from the displayed continuous string based on his own experience and relevant knowledge, and then compare it with the register address displayed in the HMI device to verify the register address. In addition, due to the large amount of byte data, errors may occur due to human errors such as dazzle. Summary of the invention

[0004] The purpose of the present application is to provide a method, device and equipment for displaying register addresses in a programmable logic controller, so as to solve the technical problem that the register addresses in the PLC are displayed in a cumbersome form of a continuous string in the prior art, which requires the user to master relevant knowledge to identify the required register address from the continuous string, and is prone to human errors.

[0005] To achieve the above objectives, this application provides the following solutions:

[0006] In a first aspect, the present application provides a method for displaying a register address in a programmable logic controller, comprising:

[0007] Performing a read operation on a register address storage area of ​​a programmable logic controller to obtain read data, the read data comprising: a plurality of consecutively arranged byte data, wherein part of the byte data is used to identify a starting position of the register address;

[0008] From the starting position of the register address in the read data, a parsing operation is performed according to different parsing data lengths to obtain a plurality of parsing data; one of the plurality of parsing data corresponding to each starting position is a register address;

[0009] The analyzed data are displayed in a differentiated manner.

[0010] Optionally, the step of performing a read operation on a register address storage area of ​​the programmable logic controller to obtain read data includes:

[0011] A read operation is performed on the register address storage area of ​​the programmable logic controller according to a preset read length to obtain read data, wherein the preset read length is less than the data length of the register address storage area and greater than or equal to the maximum length of the register address.

[0012] Optionally, the step of performing a read operation on the register address storage area of ​​the programmable logic controller according to a preset read length to obtain read data includes:

[0013] Performing a read operation according to the preset read length from a target position of a register address storage area of ​​a programmable logic controller to obtain read data;

[0014] Among them, when the end position of the previous read operation does not exist, the target position is the beginning position of the register address storage area; when the end position of the previous read operation is not at the end position of the register address storage area, the target position is the next byte of the end position; when the end position of the previous read operation is at the end position of the register address storage area, the target position is the beginning position of the register address storage area.

[0015] Optionally, before the step of performing a parsing operation according to different parsed data lengths from the starting position of the register address in the read data to obtain a plurality of parsed data, the step further includes:

[0016] The register address configuration length of the programmable logic controller is multiplied according to a plurality of different multiples to obtain a plurality of different parsed data lengths.

[0017] Optionally, the step of multiplying the register address configuration length of the programmable logic controller according to a plurality of different multiples to obtain a plurality of different parsed data lengths comprises:

[0018] The register address configuration length of the programmable logic controller is multiplied by 1, 2, and 4 respectively to obtain three different parsed data lengths.

[0019] Optionally, after the step of performing a parsing operation according to different parsed data lengths from the starting position of the register address in the read data to obtain a plurality of parsed data, the method further includes:

[0020] Using the parsed data to update the parsed record of the starting point in the cache;

[0021] The step of distinguishing and displaying the parsed data comprises:

[0022] Querying the cache for a parsing record of the parsed data;

[0023] When the updated parsing record meets the highlighting condition, the parsing data is displayed in a highlighting manner.

[0024] Optionally, the highlighting condition includes at least one of the following:

[0025] The parsing data obtained in the current parsing operation in the updated parsing record has changed compared to the parsing data obtained in the previous parsing operation;

[0026] The change frequency of the parsed data in the updated parsed record is greater than or not less than a frequency threshold.

[0027] Optionally, the step of displaying the parsed data in a highlighted manner includes:

[0028] The parsed data is placed in a priority display position for display.

[0029] Optionally, the step of placing the parsed data in a priority display position for display includes:

[0030] Counting the change frequency of the parsed data satisfying the highlighting condition;

[0031] Assigning display priorities to corresponding parsed data according to the change frequency; wherein the display priority of parsed data that meets the highlighting condition is higher than the display priority of parsed data that does not meet the highlighting condition;

[0032] The parsed data are displayed in a differentiated manner according to the order of the display priorities from high to low.

[0033] In a second aspect, the present application provides a display device for register addresses in a programmable logic controller, the display device for register addresses in the programmable logic controller comprising:

[0034] A reading module is used to perform a reading operation on a register address storage area of ​​a programmable logic controller in response to a received register address display request to obtain read data, wherein the read data includes: a plurality of consecutively arranged byte data, wherein part of the byte data is used to identify a starting position of the register address;

[0035] A parsing module, used for performing a parsing operation from a starting point of a register address in the read data according to different parsing data lengths to obtain a plurality of parsing data; one of the plurality of parsing data corresponding to each starting point is a register address;

[0036] The display module is used to differentiate and display the parsed data.

[0037] Optionally, the reading module is further configured to:

[0038] For the register address storage area of ​​the programmable logic controller, a read operation is performed according to a preset read length to obtain read data, wherein the preset read length is less than the data length of the register address storage area and greater than or equal to the maximum length of the register address.

[0039] Optionally, in the aspect of performing a read operation on a register address storage area of ​​a programmable logic controller according to a preset read length to obtain read data, the reading module is specifically used for:

[0040] Performing a read operation according to the preset read length from a target position of a register address storage area of ​​a programmable logic controller to obtain read data;

[0041] Among them, when the end position of the previous read operation does not exist, the target position is the beginning position of the register address storage area; when the end position of the previous read operation is not at the end position of the register address storage area, the target position is the next byte of the end position; when the end position of the previous read operation is at the end position of the register address storage area, the target position is the beginning position of the register address storage area.

[0042] Optionally, the parsing module is also used to:

[0043] The register address configuration length of the programmable logic controller is multiplied according to a plurality of different multiples to obtain a plurality of different parsed data lengths.

[0044] Optionally, in terms of doubling the register address configuration length of the programmable logic controller according to a plurality of different multiplication factors, the parsing module is specifically configured to:

[0045] The register address configuration length of the programmable logic controller is multiplied by 1, 2, and 4 respectively to obtain three different parsed data lengths.

[0046] Optionally, the parsing module is also used to:

[0047] Use the parsing data to update the parsing record of the starting point in the cache;

[0048] Correspondingly, the above-mentioned display module is specifically used for: when the updated parsing record meets the highlighting condition, displaying the parsing data in a highlighting manner.

[0049] Optionally, the highlighting condition includes at least one of the following:

[0050] In the updated parsing record, the parsing data obtained by the current parsing operation has changed relative to the parsing data obtained by the previous parsing operation;

[0051] In the updated parsing record, the change frequency of the parsing data is greater than or not less than the frequency threshold.

[0052] Optionally, when the updated parsing record meets the highlighting condition, the display module displays the parsing data in a highlighted manner, specifically for:

[0053] When the updated analytical record meets the highlighting condition, the analytical data is placed in the priority display position for display.

[0054] Optionally, in terms of displaying the parsed data in a highlighted manner, the display module is specifically configured to:

[0055] Count the change frequency of the parsed data that meets the highlighting conditions;

[0056] Assigning display priorities to corresponding parsed data according to the change frequency, wherein the display priority of parsed data that meets the highlighting condition is higher than the display priority of parsed data that does not meet the highlighting condition;

[0057] The parsed data is displayed separately in descending order of display priority.

[0058] In a third aspect, the present application provides a computer device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method for displaying register addresses in any one of the programmable logic controllers described above.

[0059] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method for displaying a register address in any one of the programmable logic controllers described above.

[0060] In a fifth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the method for displaying a register address in any one of the programmable logic controllers described above.

[0061] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0062] The present application provides a method, device and equipment for displaying register addresses in a programmable logic controller. In the present application, a register address storage area in the PLC is read, and the starting point position of each register address in the read data is parsed according to different parsed data lengths to obtain multiple parsed data, and the multiple parsed data corresponding to the same starting point position are distinguished and displayed to the user for viewing. The user can compare the data length of the register address displayed in the HMI device with multiple different parsed data lengths, and use the parsed data whose parsed data length matches the data length of the register address in the HMI device as the required register address in the PLC. In this method, the user does not need to know the storage method of the register address, and can directly and efficiently identify the correct register address from the multiple parsed data distinguished and displayed at the same starting point by comparing the data length, thereby improving the efficiency of register address recognition. Moreover, the read data of the PLC is divided into multiple parsed data of different lengths for display. Compared with the method of directly displaying byte data in the form of a continuous character string, the display effect is more concise, thereby reducing the risk of human recognition errors due to complex data. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 It is a schematic diagram of continuous byte data;

[0064] Figure 2 A schematic diagram of a scene of a display method in the prior art;

[0065] Figure 3 A schematic diagram of a scenario of a method for displaying a register address in a programmable logic controller provided in an embodiment of the present application;

[0066] Figure 4 A schematic diagram of a flow chart of a method for displaying a register address in a programmable logic controller provided in one embodiment of the present application;

[0067] Figure 5 A schematic diagram of the principle of a method for displaying a register address in a programmable logic controller provided in one embodiment of the present application;

[0068] Figure 6 A logic diagram of a method for displaying a register address in a programmable logic controller provided in one embodiment of the present application;

[0069] Figure 7 A schematic diagram of functional modules of a display device for register addresses in a programmable logic controller provided in one embodiment of the present application;

[0070] Figure 8 A schematic diagram of the structure of a computer device provided in one embodiment of the present application;

[0071] Fig. 9 A schematic diagram of another scenario of a display method provided in an embodiment of the present application;

[0072] Fig.10 A schematic diagram of another scenario of an existing display method. DETAILED DESCRIPTION

[0073] Figure 3 A scenario diagram showing a method for displaying a register address in a programmable logic controller provided in some embodiments of the present application.

[0074] Among them, PLC (Programmable Logic Controller) is a digitally operated electronic system used for industrial automation control. It uses programmable memory to store instructions for performing operations such as logic operations, sequential control, timing, counting and arithmetic operations, and controls various types of machinery or production processes through digital or analog input / output. PLC stores control data, status information and sensor readings through registers, so these data can be obtained through the register addresses in the PLC.

[0075] HMI (Human Machine Interface) is the medium for interaction and information exchange between the system and the user. It realizes the conversion between the internal form of information and the form acceptable to humans.

[0076] Production equipment refers to electronic equipment used in various life and production scenarios, used to provide functional services such as data processing, data storage and data transmission to the outside world.

[0077] In an exemplary application scenario, see Figure 3 , PLC and HMI are both connected to the production equipment, so that PLC can control the production equipment, and HMI can visualize the operating status, register address, task execution status and other information of the production equipment.

[0078] However, the register address displayed in the HMI is pre-configured. For example, assuming that the nth register displayed by the HMI corresponds to the output, and its corresponding register address (storage address) in the production equipment is pre-configured as XXXY, data can be read from the address XXXY of the production equipment as output data and displayed on the HMI.

[0079] The register address may be flexibly configured according to the demand (for example, it can be configured through the PLC), that is, in reality, the real register address corresponding to the nth register in the PLC may no longer be XXXY. Therefore, the above pre-configuration method is difficult to match the real situation of the register address in the PLC in real time, and cannot accurately display the register address in the PLC.

[0080] This requires the user to manually identify the register address based on the configuration rules of the PLC register address. The existing method can be found in Figure 2 As shown: After the user connects to the PLC through the terminal, the register address in the PLC is read and displayed on the terminal, and the displayed register address is compared with the register address displayed by the HMI for identification.

[0081] In another exemplary application scenario, see Fig. 9 , PLC is connected to the production equipment, and HIM serves as the touch display screen of PLC.

[0082] and Figure 2 , Figure 3 The application scenarios shown are different in that Fig. 9 The HMI shown obtains and displays data from the PLC. Similarly, the register address displayed in the HMI is pre-configured. For example, assuming that the nth register displayed by the HMI corresponds to the output, and its corresponding register address (storage address) in the PLC is pre-configured as XXXY, data can be read from the register address XXXY of the PLC as the output data and displayed on the HMI.

[0083] The register address in the PLC may be flexibly configured according to the requirements. That is, in reality, the real register address corresponding to the nth register in the PLC may no longer be XXXY. At this time, the user is also required to manually identify the register address based on the configuration rules of the PLC register address.

[0084] The existing methods can be found in Fig.10 As shown: After the user connects to the PLC through the terminal, the register address in the PLC is read and displayed on the terminal, and the displayed register address is compared with the register address displayed by the HMI for identification.

[0085] It should be noted that, regardless of the application scenario, the register address is stored in the form of a continuous string. Therefore, the register address displayed on the terminal screen in the existing method is actually a string composed of multiple consecutive bytes, and the specific value of each byte can be called byte data. Some of the byte data are special symbol data used to identify the starting position of the register address. For example, Figure 2As shown, the starting point of the register address can be identified by "00".

[0086] The user needs to distinguish the register address from the displayed continuous string one by one based on his own experience and relevant knowledge, and compare it with the register address displayed by the HMI for identification. This requires the user to have high professional knowledge. In addition, even with high professional knowledge, due to the large amount of byte data, the user needs to spend more energy to identify the register address from a long string of continuous byte data, and it is easy to cause identification errors due to human errors.

[0087] In view of this, the embodiment of the present application adjusts the data read by the terminal from the register address storage area of ​​the PLC from the previous direct display to the starting position of the register address in the read data, and performs parsing operations according to different parsed data lengths to obtain multiple parsed data for differentiated display. The user can select parsed data with the same data length from the parsed data displayed by the terminal according to the data length of the register address displayed by the HMI, and can determine which register address the register address displayed by the HMI corresponds to in the PLC.

[0088] For example, see Figure 3 , the technical solution provided by the present application can be used to achieve: assuming that three types of parsed data lengths (2 bytes, 4 bytes and 8 bytes in length) are used to parse the nth register address to obtain parsed data with three different data lengths (2 bytes, 4 bytes and 8 bytes in length), the terminal can display the parsed data with three different data lengths for the nth register address, and the three parsed data with different data lengths are displayed separately, so that the user can easily distinguish different parsed data.

[0089] The HMI also displays the nth register address, and the data length of the nth register address displayed by the HMI is 4 bytes. It can be determined that the parsed data (XXXX) with a data length of 4 bytes displayed by the terminal is the real register address. By comparison, it can be found that compared with the nth register address "XXXY" displayed by the HMI, the nth register address "XXXX" in the PLC has changed. Of course, this is only an exemplary description, and it can be set according to actual needs, and is not limited here. It can be seen that through the above method, the user can easily distinguish the real register address from each parsed data based on the data length without having to master the storage rules of the register address in the PLC.

[0090] Based on the above scenario, Figure 4As shown, some embodiments of the present application provide a method for displaying a register address in a programmable logic controller. The method for displaying a register address in a programmable logic controller may be the terminal mentioned above. In an embodiment of the present application, the following steps 101 to 103 are included.

[0091] in:

[0092] Step 101: Perform a read operation on a register address storage area of ​​a programmable logic controller to obtain read data.

[0093] The read data includes: a plurality of consecutively arranged byte data, wherein some of the byte data is used to identify the starting position of the register address. In other words, some of the byte data is used as the starting point identification bit of the register address. The starting point flag bit can be identified by using specific symbol data, for example, 00, 01, 02 is used as the value of the starting point flag bit. Those skilled in the art can flexibly set it according to needs, which will not be elaborated here.

[0094] Exemplarily, a user may implement the method for displaying register addresses in a programmable logic controller provided in some embodiments of the present application by utilizing an application, applet or web page with a register address display function on a terminal.

[0095] Specifically, the user can trigger the register address display process (or execution display method) by opening the user interface of the above-mentioned application, mini-program, web page, etc. on the terminal, and enter the information that uniquely identifies the PLC, such as the identification or name of the PLC to be viewed, in the user interface to enable the terminal to read data from the register address storage area of ​​the indicated PLC.

[0096] The above-mentioned register address storage area is a space area for storing register addresses in an editable logic controller. Usually, the register address in the register address storage area is a continuously arranged byte data, and part of the byte data is used as the starting point identification bit of the register address. Adjacent starting point identification bits are separated by a fixed length of bytes, but the specific data length of each register address is not fixed. For example, assuming that there are 8 bytes between adjacent starting point identification bits, but these 8 bytes are not necessarily all used to store register addresses, and some bytes (such as 2 bytes, 4 bytes) of the 8 bytes may also be used to store register addresses. Therefore, the actual length of the register address can be 2 bytes, 4 bytes, 8 bytes, etc. This also leads to the fact that in the existing method, even if the user can distinguish the starting point identification bit, it is difficult to directly determine the register address. Therefore, the embodiment of the present application solves this problem by parsing multiple data lengths, which will be described in detail later.

[0097] Step 101 and subsequent steps may be operations performed in response to the received register address display request after the terminal receives the register address display request.

[0098] The register address display request can be generated based on the user's operation. For example, when the user opens the user interface of the above application, applet, webpage, etc. on the terminal, a register address display request can be generated; or, the user inputs information identifying the PLC in the above user interface, which can be regarded as issuing or generating a register address display request; or, the above user interface has keys, buttons, etc., and the user generates a register address display request by clicking. Those skilled in the art can make flexible designs based on needs, which will not be elaborated here.

[0099] In addition, when the terminal is connected to only one PLC, the terminal may also automatically execute step 101 and subsequent steps after startup.

[0100] Step 102 , performing a parsing operation from the starting position of the register address in the read data according to different parsing data lengths to obtain a plurality of parsing data.

[0101] In an embodiment of the present application, after obtaining the read data in the register address storage area, the terminal will identify the starting point flag therein to find the starting position of each register address. During the parsing process, the parsing will be started from the starting position of each register address according to multiple parsing data lengths, so that parsing data of multiple different parsing data lengths can be obtained for each register address.

[0102] Specifically, the parsed data length can be configured according to the optional data length of the register address. For example, assuming that the minimum byte granularity of the register address is 2 bytes and the maximum length is 8 bytes, then the optional data length of the register address is 2, 4, 6, 8, and 2, 4, 6, 8 can be set as the parsed data length, or 2, 4, 8, etc. can be set as the parsed data length; or assuming that the optional length range of the register address is 1 to 4, then some or all of 1, 2, 3, 4 can be set as the parsed data length. Of course, this is only an exemplary description, as long as the selected parsed data length covers the optional data length of the register address, it can be applied to the embodiments of the present application, otherwise there will be a disadvantage that the complete register address does not exist in the obtained parsed data.

[0103] It should be noted that one of the multiple parsed data corresponding to each starting point is a register address. Figure 5 As an example, let's assume that the continuous string starts from the 0th starting position (which can be called D0, Figure 5D0, D1, etc. in the byte array can be called register address identifiers), and three parsed data are obtained according to 2 bytes, 4 bytes, and 8 bytes, respectively. Among these three parsed data, one is the real register address.

[0104] Step 103, the parsed data is displayed in a differentiated manner.

[0105] In the embodiment of the present application, the terminal displays the obtained parsed data on the display interface. The display method may be to display all the parsed data corresponding to a register address identifier (or a starting point position) separately, for example, Figure 3 As shown, only the nth register address identifier is shown (in Figure 3 The parsed data of each register address (referred to as the nth register address in the figure) are displayed on the display interface, and the parsed data of other register address identifiers are not displayed on the display interface.

[0106] Different display areas may also be used to display the parsed data corresponding to different register addresses, thereby achieving simultaneous display of parsed data corresponding to multiple register addresses.

[0107] The parsed data just parsed may also be displayed one by one according to the parsing order. The specific setting may be based on actual needs and is not limited here.

[0108] It should be noted that, for the sake of easy distinction, the parsed data corresponding to the same register address identifier are also displayed separately. Figure 3 As shown, different lengths of parsed data are displayed in different rows. Of course, they can also be displayed in the same row. In this case, there can be a gap between adjacent parsed data that can be distinguished by the naked eye. In addition, different parsed data can be displayed in different colors, or different fonts and / or different sizes. Those skilled in the art can make flexible settings as long as it is easy for users to distinguish, and no further details will be given here.

[0109] In actual applications, while viewing the displayed parsed data through the terminal, the user can open the HMI display interface to view the register address stored in the HMI, so that the user can know the data length of the register address of the register to be queried. It should be noted here that the content of the register address may change, but the data length of the same register address will not change, which also provides a basis for users to distinguish the register address from the parsed data by data length. The user can select the parsed data whose parsed data length is consistent with the data length of the register address displayed by the HMI from the parsed data displayed on the terminal as the register address in the PLC. For example, still with Figure 3For example, assuming that the address length of the nth register address identifier on the HMI is 4 bytes, the 4-byte parsed data (XXXX) can be selected as the actual register address from the 3 parsed data of the nth register address identifier displayed on the terminal.

[0110] Furthermore, the matching process between the parsed data displayed by the terminal and the register address displayed by the HMI can also be automatically completed by the system. The terminal can obtain the register address in the HMI by connecting with the HMI, and then match the data length of the obtained parsed data by identifying the register address length in the HMI, and the parsed data whose length matches the data length of the register address is displayed on the terminal as the real register address.

[0111] It can be seen that the embodiment of the present application reads the register address storage area in the PLC, parses the starting point position of each register address in the read data according to different parsed data lengths, obtains multiple parsed data, and distinguishes and displays the multiple parsed data corresponding to the same starting point position for the user to view. The user can compare the data length of the register address displayed in the HMI device with the multiple different parsed data lengths, and use the parsed data whose parsed data length matches the data length of the register address in the HMI device as the required register address in the PLC. This method does not require the user to know the storage method of the register address, and can efficiently identify the correct register address from the multiple parsed data displayed at the same starting point directly through the data length, thereby improving the efficiency of register address recognition. Moreover, the read data of the PLC is divided into multiple parsed data of different lengths for display. Compared with the method of directly displaying byte data in the form of a continuous character string, the display effect is simpler, thereby reducing the risk of human recognition errors due to complex data.

[0112] Optionally, step 101 includes: performing a read operation on a register address storage area of ​​a programmable logic controller according to a preset read length to obtain read data, wherein the preset read length is less than a data length of the register address storage area and greater than or equal to a maximum length of the register address.

[0113] In the embodiment of the present application, the preset read length is the data length of each data read from the register address storage area of ​​the editable logic controller.

[0114] In one example, the register address storage area can be divided into multiple data blocks, and each time data is read, a data block can be read at one time and then parsed. The capacity of the data block is the preset reading length.

[0115] After all the byte data of a data block are read out at one time, the subsequent parsing process will parse and display them one by one from each starting point in the data block. In this way, compared with reading and parsing one by one from each starting point, the time spent on reading PLC data is greatly reduced.

[0116] In order to ensure that the data length of the divided data block is too short so that a data block cannot contain at least one complete register address, the preset read length can be set to be at least greater than or equal to the maximum data length of the register address. At the same time, in order to ensure that the divided data block has the effect of improving the response efficiency, the data length of the divided data block needs to be less than the data length of the register address storage area, otherwise, compared with reading all the data in the register address storage area at one time, there will be no difference in the response efficiency.

[0117] Due to different PLC brands, the maximum number of bytes that can be read at one time (referred to as the maximum read byte number) is different. Technical personnel in this field can set the preset read length according to the actual PLC product used, so that it is not greater than the maximum read byte number and not less than the maximum length of the register address.

[0118] Exemplarily, assuming that the maximum number of bytes to be read is 200 and the maximum length of a register address is 9 bytes, the preset read length may be set to any positive integer greater than 9 and less than or equal to 200, such as 10, 20, 50, and the like.

[0119] The embodiment of the present application reduces the time required for data reading and improves the display efficiency of the register address in the PLC by reading the register address storage area according to a preset reading length.

[0120] Optionally, step 101 includes: performing a read operation according to a preset read length from a target position of a register address storage area of ​​a programmable logic controller to obtain read data;

[0121] When actually reading, there may be three situations, which are described below:

[0122] In case 1, the end position of the last read operation does not exist. In this case, the target position is the beginning position of the register address storage area. For example, assuming that the beginning position of the register address storage area is byte 0, the target position is byte 0 in case 2.

[0123] Case 2: The end position of the last read operation is not at the end position of the register address storage area. In this case, the target position is the next byte of the end position. For example, assuming that the preset read length is 200 bytes and the end position of the last read operation is byte 199, the target position of this read operation is byte 200, and 200 bytes (byte 200 - byte 399) of data are read at one time.

[0124] Case 3: the end position of the last read operation is at the end position of the register address storage area. At this time, the target position is the beginning position of the register address storage area.

[0125] In either case, the read data includes the byte data at the target position.

[0126] In an embodiment of the present application, during the segmented reading of the register address storage area of ​​the PLC, the reading position is marked to ensure that the data read each time will not be repeated and no data will be missed.

[0127] Specifically, when the register address storage area is read for the first time, the data can be read from the beginning of the register address storage area according to the preset reading length. Since the preset reading length is less than the total data length of the register address storage area, all the data in the register address storage area will not be read at one time. The end position of this reading process can be marked. When the data is read according to the preset reading length next time, the reading process can be started from the next byte of the end position. By analogy, the starting point of the subsequent reading process is the next byte of the end position of the previous reading process. If the end position of the previous reading process is the end position of the register address storage area, the data can be read again from the beginning of the register address storage area. It can be understood that the reading, parsing and displaying process of the register address storage area is a cyclic process. By continuously reading, parsing and displaying the data in the register address storage area, real-time monitoring and updating of the data in the register address storage area can be achieved, ensuring that the user can view the latest status of the register address in the PLC through the terminal.

[0128] Optionally, before step 102, the method further includes: doubling the register address configuration length of the programmable logic controller according to a plurality of different multiples to obtain a plurality of different parsed data lengths.

[0129] The length of any parsed data should be less than or equal to the maximum length of the register address.

[0130] In the embodiment of the present application, the storage address configuration length refers to the minimum length of data stored in the PLC register address storage area (which can be referred to as the minimum address length), and the length of the register address is an integer multiple of the minimum address length. Therefore, the parsed data length can be set to an integer multiple of the register address configuration length, so that the obtained parsed data length can completely cover the register address, ensuring that the obtained parsed data contains a complete register address.

[0131] For example, assuming that the register address configuration length is 2 bytes, then 2 bytes are doubled to obtain parsed data lengths of 2, 4, 6, 8...2n, respectively, where n is a positive integer. Of course, 2n is not infinitely extended. Usually, 2n will be the maximum length of the register address. If the maximum length of the register address is 8 bytes, n can be 4. If the maximum length of the register address is 10 bytes, n can be 5. Of course, this is only an exemplary description, and it can be set according to actual needs, and is not limited here.

[0132] Optionally, the register address configuration length of the programmable logic controller is multiplied according to a plurality of different multiples, specifically including: multiplying the register address configuration length of the programmable logic controller by 1, 2, and 4 respectively to obtain three different parsed data lengths.

[0133] Usually, the length of the register address is set as 1, 2, or 4 times the minimum address length. Therefore, in the embodiment of the present application, the register address configuration length is multiplied by 1, 2, or 4 respectively to obtain different parsed data lengths.

[0134] For example, refer to Figure 5 , the minimum address length is 2 bytes, Figure 5 The byte data with byte numbers 0, 2, 4, 8, and A are used to identify the starting position of the register address, that is, as the register address identifier. For the sake of distinction, D0, D1, D2, D3, D4, D5, etc. are used to represent different register address identifiers. Here, we obtain three parsing data lengths of 2, 4, and 8 by multiplying the register address configuration length 2 by 1, 2, and 4. In the process of parsing the register address with the register address identifier D0, 2 bytes, 4 bytes, and 8 bytes of data can be read from the starting position of D0 to obtain the parsed data: From the byte number, taking byte 0 corresponding to D0 as the starting position, the data of bytes 0-byte 1 is extracted as a 2-byte parsed data, the byte data of bytes 0-byte 3 is extracted as a 4-byte parsed data, and the byte data of bytes 0-byte 7 is extracted as an 8-byte parsed data. How to parse other starting positions is similar, so I will not go into details here.

[0135] In other embodiments of the present application, after step 102, all the above embodiments may further include:

[0136] Step 201, using the parsing data to update the parsing record of the starting point position in the cache;

[0137] For example, still taking D0 in a data block A as an example, assuming that three parsing data (expressed as XX, XXXX and XXXXXXXX) are obtained for D0, the parsing data can be stored in the cache, and the parsing record corresponding to D0 is updated.

[0138] Assuming that D0 has been parsed three times before this parsing, before the above-mentioned "XX, XXXX and XXXXXXXX" are cached, the parsing record corresponding to D0 includes the parsing data obtained from the first three parsings. After updating it, the parsing record corresponding to D0 in the cache includes the parsing data obtained from the first four parsings.

[0139] Of course, in order to reduce cache pressure, the terminal may also cache only the parsing data generated during the last parsing process.

[0140] In the embodiment of the present application, the terminal caches the parsed data of each register address identifier in the register address storage area, and these data can be distinguished according to the starting position of the register address. The parsed record can be in various forms, for example, in a table form, and those skilled in the art can flexibly design it, which will not be described in detail here.

[0141] In other embodiments of the present application, step 103 in all the above embodiments can be implemented by illustratively using the following steps:

[0142] Step 202: When the updated parsing record meets the highlighting condition, the parsing data is displayed in a highlighting manner.

[0143] In one example, the highlighting condition may include at least one of the following:

[0144] (1) First condition: the parsed data obtained by the current parsing operation in the parsing record has changed relative to the parsed data obtained by the previous parsing operation;

[0145] It should be noted that the current parsing operation and the previous parsing operation are both for the same register address identifier.

[0146] Taking D0 as an example, the last parsed data of D0 can be compared with the parsed data of this parsing. If they are completely consistent, it means that the register address corresponding to D0 has not changed. If there is a data inconsistency, it means that the register address corresponding to D0 may have changed. Then it can be highlighted later to facilitate the user to compare according to the content displayed on the HMI.

[0147] (2) Second condition: the change frequency of the parsed data in the parsed record is greater than or not less than the frequency threshold.

[0148] By highlighting the analytical data satisfying the above-mentioned highlighting conditions, the user can more intuitively see the analytical data that has changed and the analytical data that has changed relatively frequently.

[0149] In another example, the highlighting conditions may include at least one of the frequency of change of the parsed data being greater than or not less than a frequency threshold (second condition), the number of changes being greater than or not less than a number threshold (third condition), the length of the change being greater than or not less than a length threshold (fourth condition), and the degree of change being greater than or not less than a degree threshold (fifth condition).

[0150] The values ​​of each threshold can be flexibly designed according to actual needs and will not be elaborated here.

[0151] In yet another example, the highlighting condition may include at least one of the first to fifth conditions.

[0152] The following is an introduction to the number of changes, frequency of changes, length of changes, and degree of changes.

[0153] Exemplarily, the number of changes may refer to: the cumulative number of times the parsed data has been changed;

[0154] As mentioned before, for the same register address identifier (for example, D0), different parsed data can be obtained according to different parsed data lengths. In an example, the number of changes can be counted for each parsed data length. Assuming that for D0, three types of parsed data are obtained according to 2, 4, and 8 bytes, taking 2 bytes as an example, the corresponding number of changes can be obtained in the following way: compare the 2-byte parsed data of this parsing operation with the 2-byte parsed data of the previous parsing operation. If there is a change, the number of changes is increased by 1. If there is no change, the number of changes remains unchanged. For the 4-byte and 8-byte parsed data of D0, the statistical method of the number of changes is similar to that of 2 bytes, which will not be repeated here;

[0155] When counting the number of changes corresponding to each byte separately, when determining whether the third condition is met (the number of changes in the parsed data is greater than or not less than the number threshold), the following multiple methods can be selected:

[0156] Method 1, independently determining whether the number of changes of the parsed data of each byte is greater than or not less than the number threshold;

[0157] Here is an example: assuming that the 2-byte parsed data starting from D0 has changed more times than the number threshold, while the parsed data corresponding to other bytes have changed less than the number threshold, it can be determined that the 2-byte parsed data meets the third condition, and the 2-byte parsed data will be highlighted subsequently, while the parsed data of other bytes may not be highlighted because they do not meet the third condition (of course, if the highlighting condition includes other conditions, such as the second condition, the parsed data of other bytes may also be highlighted if they meet the other conditions).

[0158] Method 2, the overall judgment method, if the number of changes corresponding to the N analytical data is greater than the number threshold, it is considered that the third condition is met as a whole.

[0159] Among them, N is greater than or equal to 1 and less than or equal to the number of parsed data. For example, for D0, three types of parsed data are obtained according to 2, 4, and 8 bytes, then N is greater than or equal to 1 and less than or equal to 3.

[0160] For example, assuming N=1, for D0, three types of parsed data are obtained based on 2, 4, and 8 bytes. If the number of changes in any type of parsed data is greater than the number threshold, it is considered that the third condition is met as a whole, and these three types of parsed data will be highlighted later.

[0161] In another example, the number of changes of parsed data of different bytes can also be added together, and the total number obtained is used as the number of changes. For example, assuming that the number of changes of 2 bytes, 4 bytes, and 8 bytes are 1, 4, and 5 respectively, then add them up to get 10, which is used as the number of changes of D0. In this example, if the total number is greater than the number threshold, it is considered that the third condition is met as a whole, and these three types of parsed data will be highlighted later.

[0162] The change frequency may refer to: the ratio between the number of times the parsed data is changed (which may be referred to as the number of changes) and the number of parsing operations;

[0163] In one example, the number of changes can be counted for each parsed data length (see the above description for how to count), and then the change frequency for each parsed data length can be calculated. For example, assuming that the number of parsing is 10 times, the number of changes for 2 bytes, 4 bytes, and 8 bytes are 1, 4, and 5 respectively, then their respective change frequencies can be normalized to 0.1, 0.4, and 0.5.

[0164] When counting the change frequency corresponding to each byte separately, when determining whether the second condition is met (the change frequency of the parsed data is greater than or not less than the frequency threshold), it can be implemented by referring to the above-mentioned method 1 and method 2, which will not be elaborated here.

[0165] In another example, the total number of times can be divided by the number of analyses. Using the previous example, the sum of 1, 4, and 5 can be divided by 10 times of analysis, and the resulting change frequency is equal to 1. In this example, if the change frequency 1 is greater than the frequency threshold, it is considered that the second condition is met as a whole, and these three types of analysis data will be highlighted later.

[0166] The changed length may refer to: the length of the data that has changed in the parsed data;

[0167] In one example, the length of non-repeating changed data can be counted for the parsed data corresponding to each starting point position. For example, assuming that the maximum length of the register address is 8 bytes, there are three different parsed data lengths of 2 bytes, 4 bytes, and 8 bytes. If the first two bytes change, the three parsed data will all change. The length of the changed data without deduplication is 6, and the length of the changed data after deduplication is still 2. For another example, if the first two bytes and the last two bytes change, the first two bytes of the 2-byte parsed data, the 4-byte parsed data, and the 8-byte parsed data are all changed (i.e. repeated), and the 8-byte parsed data also has the last two bytes changed alone. The length of the changed data without deduplication is 8, and the length of the changed data after deduplication is 4, and so on.

[0168] In another example, the length of the changed data (referred to as the changed length) can be counted for each length of the parsed data. Continuing with the previous example, assuming that the maximum length of the register address is 8 bytes, there are three different parsed data lengths of 2 bytes, 4 bytes, and 8 bytes. If the first two bytes change, the changed lengths of the three types of parsed data are 2 bytes respectively; assuming that the first two bytes and the last two bytes change, the changed lengths of the 2-byte parsed data and the 4-byte parsed data are 2 bytes, and the changed length of the 8-byte parsed data is 4 bytes.

[0169] The degree of change can be: the ratio of the changed data length in the parsed data to the total data length of the register address;

[0170] In an example, the length of the changed data can be counted for each type of parsed data, and then the ratio of the changed data length to the total data length of the register address can be calculated. For example, assuming that the total data length of the register address is 10 bytes, and the length of the changed data in a certain parsed data belonging to the register address is 2, then the degree of change is 0.2. If the length of the changed data of a certain parsed data is 4, then the degree of change can be obtained by the same token. 0.4.

[0171] In other embodiments of the present application, the parsed data of a specific register address identifier can also be set to always be considered to meet the highlighting condition. The above-mentioned specific register address identifier can be a system default register address identifier, or can be obtained through user marking, so that the user can mark important register address identifiers. Of course, this is only an exemplary description, and can be set according to actual needs, and is not limited here.

[0172] The above-mentioned change frequency, number of changes, change length, and degree of change are all based on the comparison between the parsed data of the current parsing operation and the parsed data of the previous parsing operation. It can be understood that when the data is read for parsing for the first time, the previous parsing data will not exist. In this case, the comparison step is skipped, and there is no need to determine whether the highlighting conditions are met. The parsed data can be displayed in the order of the register address identifier.

[0173] In other embodiments of the present application, at least one of the above-mentioned change frequency, number of changes, change length and degree of change may be recorded in the analysis record.

[0174] The following describes how to highlight.

[0175] In some embodiments of the present application, the highlighting method in step 202 may be to highlight the parsed data that meets the highlighting condition or to display it in a specific color. It may also be to highlight the changed part of the parsed data or to display it in a specific color, so that the user can see the changed parsed data more intuitively. This is only an exemplary description, and the specific highlighting method can be set according to actual needs and is not limited here.

[0176] In some embodiments of the present application, "displaying the parsed data in a highlighted manner" in step 202 of all the above embodiments can be achieved by placing the parsed data (parsed records that meet the highlighting conditions) in a priority display position (or priority display area) for display.

[0177] Furthermore, the priority display position may be a pre-specified position such as the top or bottom of the screen display, or may be set by the user, so that the user can customize the display mode of the terminal according to his or her own viewing habits.

[0178] Taking the above-mentioned highlighting conditions including the aforementioned second condition (the change frequency of the parsed data is greater than or not less than the frequency threshold) as an example, the parsed data with a change frequency greater than the frequency threshold can be directly displayed in a pre-set priority display position, so that the user can intuitively view the parsed data that changes frequently.

[0179] This embodiment can be applied to a scenario where various parsed data at multiple starting points are displayed simultaneously, and the parsed data placed at a priority display position is more easily noticed by the user than other parsed data.

[0180] More specifically, as mentioned above, the change frequency of each parsed data length can be counted respectively, and whether the second condition is met can be determined in at least the following two ways:

[0181] Method 1, independently determining whether the change frequency of the parsed data of each byte is greater than or not less than the frequency threshold;

[0182] Assuming that the change frequency of the 2-byte parsed data starting from D0 is greater than the frequency threshold, while the change frequency of the parsed data corresponding to other bytes is less than the frequency threshold, it can be determined that the 2-byte parsed data meets the second condition, and the 2-byte parsing will be highlighted in the priority display position later, while the parsed data of other bytes will not be highlighted because they do not meet the second condition.

[0183] Method 2, overall judgment method, if the change frequency corresponding to N analytical data is greater than the frequency threshold, it is considered that the second condition is met as a whole.

[0184] Among them, N is greater than or equal to 1 and less than or equal to the number of parsed data. For example, for D0, three types of parsed data are obtained according to 2, 4, and 8 bytes, then N is greater than or equal to 1 and less than or equal to 3.

[0185] Assuming N=1, for D0, three types of parsed data are obtained based on 2, 4, and 8 bytes. If the change frequency of any parsed data in method 2 is greater than the frequency threshold, it is considered that the second condition is met as a whole, and these three types of parsed data will be displayed in the priority display position later.

[0186] Of course, the three types of parsed data can be further sorted and displayed according to the change frequency. For example, assuming that the change frequency of the three types of parsed data corresponding to 2, 4, and 8 bytes of D0 is: the change frequency of 2 bytes> the change frequency of 8 bytes> the change frequency of 4 bytes, then the display position relationship of the three types of parsed data is: the display position of 2 bytes is higher than that of 8 bytes, and the display position of 8 bytes is higher than that of 4 bytes.

[0187] In addition, regardless of method 1 or method 2, if there are multiple parsed data that meet the second condition, the parsed data that meet the second condition can be further sorted and displayed in the priority display area according to the magnitude of the change frequency.

[0188] Taking the case where the priority display position is the topmost area of ​​the screen display as an example, the following describes a specific implementation method for displaying the parsed data that meets the highlighting condition at the priority display position, including the following steps:

[0189] Step 101 , in response to a received register address display request, a read operation is performed on a register address storage area of ​​a programmable logic controller to obtain read data.

[0190] Step 102 , performing a parsing operation from the starting position of the register address in the read data according to different parsing data lengths to obtain a plurality of parsing data.

[0191] Step 201, using the parsing data to update the parsing record of the starting point in the cache;

[0192] Step 101, step 102, and step 201 may refer to the above records and will not be described in detail here.

[0193] Step 2021, counting the change frequency of the parsed data that meets the highlighting condition in the parsed records;

[0194] Exemplarily, the highlighting condition may include the aforementioned second condition, or may include both the aforementioned first condition and the second condition.

[0195] The determination of whether the second condition is met can be found in the above description and will not be elaborated here.

[0196] Step 2022, assigning display priorities to corresponding parsed data according to the change frequency, wherein the display priority of parsed data that meets the highlighting condition is higher than the display priority of parsed data that does not meet the highlighting condition;

[0197] As mentioned above, in this embodiment, the highlighting condition may include the aforementioned second condition, or may include both the aforementioned first condition and the aforementioned second condition.

[0198] If the highlighting condition only includes the second condition, the display priority can be assigned to the corresponding parsed data according to the change frequency. The greater the change frequency, the higher the display priority, that is, the display priority is positively correlated with the change frequency. When the parsed data are displayed in order of display priority from high to low, the parsed data with a change frequency greater than or not less than the frequency threshold can be displayed in the uppermost area, and the greater the change frequency, the higher the position, which is closer to the top of the terminal display interface.

[0199] If the highlighting condition includes both the first condition and the second condition, there are three exemplary display priority allocation methods:

[0200] Method 1: directly assign display priority according to the frequency of change. The greater the frequency of change, the higher the display priority.

[0201] Method 2: The display priority of the parsed data satisfying the first condition is set higher than the display priority of the parsed data satisfying the second condition.

[0202] The following are some examples of what is considered in Method 2:

[0203] Assume that the current parsing operation on D0 is the 100th parsing operation, and assume that the parsing data of D0 changes frequently, and its change frequency is higher than that of other register address tags, but the parsing data obtained in the 100th parsing operation has not changed compared with the 99th parsing operation.

[0204] Assume that the parsing data of D1 does not change frequently, but in its 100th parsing operation, the parsing data changes.

[0205] The current parsing operation (the 100th parsing operation) may also be worthy of the user's attention, so a higher display priority can be assigned to the parsing data of D1.

[0206] Method three: assigning a display priority higher than that of the parsed data satisfying the second condition to the parsed data that meets the first condition and changes for the first time.

[0207] The following are some examples of what is considered in Method 3:

[0208] Assume that the current parsing operation on D0 is the 100th parsing operation, and assume that the parsing data of D0 changes frequently, and its change frequency is higher than that of other register address tags, but the parsing data obtained in the 100th parsing operation has not changed compared with the 99th parsing operation.

[0209] Assume that the parsing data of D1 does not change often, but in its 100th parsing operation, the parsing data changes for the first time.

[0210] The parsed data or register address identifier that changes for the first time may also be worthy of the user's attention. Therefore, a higher display priority may be assigned to the parsed data of D1.

[0211] Step 2023, display the parsed data in order of display priority from high to low.

[0212] Of course, it should be noted that there may be a situation where the change frequency is not greater than or not less than the frequency threshold. In this case, the display priority can be assigned to the corresponding parsing data according to the change frequency, and the parsing data can be displayed in order from high to low display priority. For example: if the interface display order is from top to bottom, the parsing data with a high display priority will be displayed at the top of the display interface. If the interface display order is from left to right, the parsing data with a high display priority will be displayed on the left side of the display interface. Of course, this is only an exemplary description, and it can be set according to actual needs, and it is not limited here.

[0213] In an embodiment of the present application, the display interface of the terminal can display each parsing data in sequence according to the display priority corresponding to the parsing data. The parsing data with a high display priority will be displayed more forward, so that the user can more intuitively see the parsing data with a high change frequency.

[0214] Specifically, first, it is necessary to filter out the parsed data with a change frequency greater than the frequency threshold according to the change frequency. These display data will be assigned corresponding display priorities according to the change frequency. The higher the change frequency, the higher the assigned display priority. For the parsed data that do not meet the highlighting conditions, a lower display priority can be assigned, which will be lower than the lowest display priority of the parsed data that meet the highlighting conditions, so as to ensure that the parsed data that meet the highlighting conditions can always be displayed before the parsed data that does not meet the highlighting conditions.

[0215] The embodiment of the present application mainly allocates display priorities to different parsed data according to the change frequency, so that the parsed data with more frequent changes will be displayed in a more forward position, so that the user can intuitively view the parsed data with frequent changes.

[0216] In addition, you can put the information that has never changed and is 0 at the end.

[0217] Reference Figure 6 , showing a logic schematic diagram of a method for displaying a register address in a programmable logic controller provided by some embodiments of the present application, including:

[0218] S601: Read out byte data according to data block;

[0219] Please refer to the record related to data block reading in the aforementioned step 101, which will not be repeated here.

[0220] S602: Parse each register address according to 2, 4, or 8 bytes;

[0221] For example, for each starting point position in the read data block, the parsing operation can be performed according to 2, 4, and 8 bytes to obtain three parsed data of different lengths. For details, please refer to the above records, which will not be repeated here.

[0222] S603: Cache each parsed data (to update the parsing record of the corresponding starting point position);

[0223] Please refer to the relevant records of the aforementioned step 201, which will not be repeated here.

[0224] S602 and S603 are executed cyclically until all starting positions of the data block are traversed, and the parsed data corresponding to each starting position in the data block is obtained and cached. Then, the process returns to S601 to read the next data block and perform subsequent steps.

[0225] In other embodiments of the present application, after performing the parsing operation on the last starting point of a data block, the process may return to S601 to read the next data block and perform subsequent steps.

[0226] S604: presenting parsed data;

[0227] It should be noted that step S604 is performed when the parsing operation is performed for each starting point position in a data block for the first time. Since it is the first operation, there is no comparison link, and it is not necessary to determine whether it meets the highlighting condition, and the parsed data obtained by parsing can be directly presented.

[0228] S605: monitoring the parsed data in the cache;

[0229] Specifically, for each starting point position, the parsed data of the current parsing operation is compared with the parsed data of the previous parsing operation to determine whether there is a change.

[0230] S606: Record the register address identifiers of the parsed data that often change;

[0231] Exemplarily, frequent changes may refer to a change frequency of the parsed data being greater than or not less than a frequency threshold.

[0232] In addition, at least one of the number of changes, length of changes and degree of changes mentioned above may be statistically obtained and recorded in the analysis record.

[0233] S607: Present the reading (analysis) results to facilitate the comparison of data displayed on the HMI screen.

[0234] Step S607 is used to realize: when the updated parsing record meets the highlighting condition, the parsing data is displayed in a highlighting manner. For details, please refer to the above records, which will not be described here.

[0235] It should be noted that step S607 is performed after the parsing operation is not performed for the first time.

[0236] Among them, step S601 to step S607 is a cyclic process. After turning on the display function of the parsed data, the terminal will continuously perform the process of reading, parsing, and displaying the data blocks in the PLC register address storage area. After the parsing step S603, the terminal will compare the parsed data in the cache to determine whether the parsed data has changed. For the parsed data that has changed, the terminal will adjust the display method of the parsed data so that the user can intuitively know the changed parsed data through the terminal. Through this cyclic process, the user can continuously obtain the real-time changes of the register address in the PLC through the terminal.

[0237] Among them, the terminal is connected to the PLC through the network port / serial port. The terminal reads the data block from the storage space of the PLC according to the preset read data length to obtain the read data, and then parses the starting position of the register address in the read data to obtain the parsed data with the parsed data length of 2, 4, and 8 bytes respectively. The obtained parsed data is displayed on the display interface of the terminal, and the parsed data is stored in the cache. The parsed data in the cache is monitored, the register address of the parsed data that has changed is recorded, and then the parsed data of the changed register address is displayed on the display interface of the terminal, so that the user can intuitively see the parsed data of the changed register address.

[0238] Based on the same inventive concept, the embodiment of the present application also provides a display device for register addresses in a programmable logic controller for implementing the display method for register addresses in a programmable logic controller involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the display device for register addresses in one or more programmable logic controllers provided below can refer to the limitations of the display method for register addresses in a programmable logic controller above, and will not be repeated here.

[0239] In an exemplary embodiment, Figure 7 As shown, a display device 30 for register addresses in a programmable logic controller is provided, comprising:

[0240] The reading module 301 is used to perform a reading operation on the register address storage area of ​​the programmable logic controller in response to the received register address display request to obtain read data, wherein the read data includes: a plurality of consecutively arranged byte data, wherein part of the byte data is used to identify the starting position of the register address;

[0241] The parsing module 302 is used to perform a parsing operation from the starting position of the register address in the read data according to different parsing data lengths to obtain multiple parsing data; one of the multiple parsing data corresponding to each starting position is the register address;

[0242] The display module 303 is used to display the parsed data in a differentiated manner.

[0243] Optionally, the reading module 301 is further used for:

[0244] For the register address storage area of ​​the programmable logic controller, a read operation is performed according to a preset read length to obtain read data, wherein the preset read length is less than the data length of the register address storage area and greater than or equal to the maximum length of the register address.

[0245] Optionally, in terms of performing a read operation on a register address storage area of ​​a programmable logic controller according to a preset read length to obtain read data, the reading module 301 is specifically configured to:

[0246] Performing a read operation according to the preset read length from a target position of a register address storage area of ​​a programmable logic controller to obtain read data;

[0247] Among them, when the end position of the previous read operation does not exist, the target position is the beginning position of the register address storage area; when the end position of the previous read operation is not at the end position of the register address storage area, the target position is the next byte of the end position; when the end position of the previous read operation is at the end position of the register address storage area, the target position is the beginning position of the register address storage area.

[0248] Optionally, the parsing module 302 is further configured to:

[0249] The register address configuration length of the programmable logic controller is multiplied according to a plurality of different multiples to obtain a plurality of different parsed data lengths.

[0250] Optionally, in terms of doubling the register address configuration length of the programmable logic controller according to a plurality of different multiplication factors, the parsing module 302 is specifically configured to:

[0251] The register address configuration length of the programmable logic controller is multiplied by 1, 2, and 4 respectively to obtain three different parsed data lengths.

[0252] Optionally, the parsing module 302 is further configured to:

[0253] Use the parsing data to update the parsing record of the starting point in the cache;

[0254] Correspondingly, the display module 303 is specifically used for: when the updated parsing record meets the highlighting condition, displaying the parsing data in a highlighting manner.

[0255] Optionally, the highlighting condition includes at least one of the following:

[0256] In the updated parsing record, the parsing data obtained by the current parsing operation has changed relative to the parsing data obtained by the previous parsing operation;

[0257] In the updated parsing record, the change frequency of the parsing data is greater than or not less than the frequency threshold.

[0258] Optionally, when the updated parsing record meets the highlighting condition, the parsing data is displayed in a highlighted manner, and the display module 303 is specifically used to:

[0259] When the updated analytical record meets the highlighting condition, the analytical data is placed in the priority display position for display.

[0260] Optionally, in terms of displaying the parsed data in a highlighted manner, the display module 303 is specifically configured to:

[0261] Count the change frequency of the parsed data that meets the highlighting conditions;

[0262] Assigning display priorities to corresponding parsed data according to the change frequency, wherein the display priority of parsed data that meets the highlighting condition is higher than the display priority of parsed data that does not meet the highlighting condition;

[0263] The parsed data is displayed separately in descending order of display priority.

[0264] In an exemplary embodiment, a computer device is provided. The computer device may be a server or a terminal. The internal structure diagram thereof may be as follows: Figure 8As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store display data of register addresses in a programmable logic controller. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for displaying register addresses in a programmable logic controller is implemented.

[0265] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0266] In an exemplary embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0267] In an exemplary embodiment, a computer-readable storage medium is provided, storing a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0268] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0269] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0270] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0271] The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0272] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0273] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A method for displaying register addresses in a programmable logic controller, characterized in that: include: Performing a read operation on a register address storage area of ​​a programmable logic controller to obtain read data, the read data comprising: a plurality of consecutively arranged byte data, wherein part of the byte data is used to identify a starting position of the register address; From the starting position of the register address in the read data, a parsing operation is performed according to different parsing data lengths to obtain a plurality of parsing data; one of the plurality of parsing data corresponding to each starting position is a register address; The analyzed data are displayed in a differentiated manner.

2. The method for displaying register addresses in a programmable logic controller according to claim 1, characterized in that: The step of performing a read operation on the register address storage area of ​​the programmable logic controller to obtain read data includes: A read operation is performed on the register address storage area of ​​the programmable logic controller according to a preset read length to obtain read data, wherein the preset read length is less than the data length of the register address storage area and greater than or equal to the maximum length of the register address.

3. The method for displaying register addresses in a programmable logic controller according to claim 2, characterized in that: The step of performing a read operation on the register address storage area of ​​the programmable logic controller according to a preset read length to obtain read data includes: Performing a read operation according to the preset read length from a target position of a register address storage area of ​​a programmable logic controller to obtain read data; Among them, when the end position of the previous read operation does not exist, the target position is the beginning position of the register address storage area; when the end position of the previous read operation is not at the end position of the register address storage area, the target position is the next byte of the end position; when the end position of the previous read operation is at the end position of the register address storage area, the target position is the beginning position of the register address storage area.

4. The method for displaying register addresses in a programmable logic controller according to claim 1, characterized in that: Before the step of performing a parsing operation from the starting position of the register address in the read data according to different parsed data lengths to obtain a plurality of parsed data, the step further includes: The register address configuration length of the programmable logic controller is multiplied according to a plurality of different multiples to obtain a plurality of different parsed data lengths.

5. The method for displaying register addresses in a programmable logic controller according to claim 4, characterized in that: The step of multiplying the register address configuration length of the programmable logic controller according to a plurality of different magnifications to obtain a plurality of different parsed data lengths comprises: The register address configuration length of the programmable logic controller is multiplied by 1, 2, and 4 respectively to obtain three different parsed data lengths.

6. The method for displaying register addresses in a programmable logic controller according to claim 1, characterized in that: After the step of performing a parsing operation from the starting position of the register address in the read data according to different parsed data lengths to obtain a plurality of parsed data, the method further includes: Using the parsed data to update the parsed record of the starting point in the cache; The step of distinguishing and displaying the parsed data comprises: When the updated parsing record meets the highlighting condition, the parsing data is displayed in a highlighting manner.

7. The method for displaying register addresses in a programmable logic controller according to claim 6, characterized in that: The highlighting condition includes at least one of the following: The parsing data obtained in the current parsing operation in the updated parsing record has changed compared to the parsing data obtained in the previous parsing operation; The change frequency of the parsed data in the updated parsed record is greater than or not less than the frequency threshold.

8. The method for displaying register addresses in a programmable logic controller according to claim 6, characterized in that: The step of displaying the parsed data in a highlighted manner comprises: The parsed data is placed in a priority display position for display.

9. The method for displaying register addresses in a programmable logic controller according to claim 8, characterized in that: The step of placing the parsed data at a priority display position for display comprises: Counting the change frequency of the parsed data satisfying the highlighting condition; assigning display priorities to corresponding parsed data according to the change frequency, wherein the display priority of parsed data that meets the highlighting condition is higher than the display priority of parsed data that does not meet the highlighting condition; The parsed data are displayed in a differentiated manner according to the order of the display priorities from high to low.

10. A display device for register addresses in a programmable logic controller, characterized in that: The display device of the register address in the programmable logic controller comprises: A reading module, used for performing a reading operation on a register address storage area of ​​a programmable logic controller to obtain read data, wherein the read data includes: a plurality of consecutively arranged byte data, wherein part of the byte data is used to identify a starting position of the register address; A parsing module, used for performing a parsing operation according to different parsing data lengths from the starting position of the register address in the read data to obtain a plurality of parsing data; one of the plurality of parsing data corresponding to each starting position is a register address; The display module is used to display the analyzed data in a differentiated manner.

11. A computer device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of a method for displaying register addresses in a programmable logic controller according to any one of claims 1 to 8.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for displaying register addresses in a programmable logic controller described in any one of claims 1 to 8 are implemented.

13. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the steps of the method for displaying a register address in a programmable logic controller according to any one of claims 1 to 8.

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