Gate drive circuit and display panel

Abstract

The invention provides a gate drive circuit and a display panel. The gate drive circuit comprises a signal input module, a low potential write-in module, a high potential control module and a signal output module. Wherein the low potential write-in module is used for directly writing a preset low potential into a first node, the high potential control module is used for controlling the potential of a second node, and the signal output module controls the potential of the signal output end of the level under the control of the potentials of the first node and the second node. According to the gate drive circuit and the display panel provided by the invention, transistor threshold voltage in the gate drive circuit is eliminated, the size of an output step is dynamically adjusted, and the service life performance and uniformity of the display panel are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Art

[0002] Gate Driver On Array (GOA) is a technology that integrates the gate driver circuit on the array substrate of the display panel to achieve line-by-line scanning drive. Figure 1 As shown, the threshold voltage (Vth) of the P-type transistor in the gate drive circuit will shift due to factors such as temperature changes, process differences, and aging of the transistor, which will cause the falling edge step of the drive signal output by the gate drive circuit to change due to the offset of the threshold voltage, affecting the output stability of the gate drive circuit. Summary of the invention

[0003] Embodiments of the present application provide a gate driving circuit and a display panel to solve the problem of poor output stability of the gate driving circuit in the related art.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, the present application provides a gate driving circuit, comprising a plurality of gate driving units arranged in cascade, wherein the gate driving unit comprises:

[0006] A signal input module is used to receive the output signal of the previous level;

[0007] A low potential writing module, electrically connected to the signal input terminal and to the first node, and used for directly writing a preset potential to the first node;

[0008] A high potential control module, electrically connected to the second node and to the potential writing module, the high potential control module being used to control the potential of the second node;

[0009] A signal output module is electrically connected to the signal output terminal of this stage and to the first node and the second node. The signal output module is used to control the potential of the signal output terminal of this stage under the control of the potential of the first node and the potential of the second node.

[0010] In one embodiment, the signal input module includes:

[0011] A first transistor, wherein a gate of the first transistor is connected to a first clock signal, a source of the first transistor is electrically connected to the previous stage output signal, and a drain of the first transistor is electrically connected to the first control module.

[0012] In one embodiment, the low potential writing module includes:

[0013] a second transistor, wherein a gate of the second transistor is connected to a constant low potential signal, a source of the second transistor is electrically connected to a drain of the first transistor, and a drain of the second transistor is electrically connected to the first node;

[0014] a third transistor, wherein a gate of the third transistor is connected to the first node, and a source of the third transistor is connected to a preset high potential signal;

[0015] a fourth transistor, wherein a gate of the fourth transistor is electrically connected to a drain of the third transistor, a source of the fourth transistor is connected to a preset low potential signal, and a drain of the fourth transistor is connected to the first node;

[0016] a fifth transistor, wherein a gate of the fifth transistor is connected to the first node, a source of the fifth transistor is connected to the preset low potential signal, and a drain of the fifth transistor is electrically connected to a drain of the third transistor; and

[0017] a sixth transistor, wherein a gate of the sixth transistor is connected to a reset control signal, a source of the sixth transistor is connected to the constant high potential signal, and a drain of the sixth transistor is electrically connected to a drain of the first transistor;

[0018] Wherein, the voltage value of the preset high potential signal is smaller than that of the constant high potential signal, and the voltage value of the preset low potential signal is smaller than that of the constant low potential signal.

[0019] In one embodiment, the low potential writing module further includes:

[0020] a seventh transistor, wherein a gate of the seventh transistor is connected to the first node, and a source of the seventh transistor is connected to a second clock signal;

[0021] an eighth transistor, wherein a gate of the eighth transistor is connected to the high potential control module, a source of the eighth transistor is connected to a constant high potential signal, and a drain of the eighth transistor is electrically connected to a drain of the seventh transistor; and

[0022] A first capacitor, wherein a first end of the first capacitor is electrically connected to the gate of the seventh transistor, and a second end of the first capacitor is electrically connected to the drain of the third transistor.

[0023] In one embodiment, the low potential writing module further includes:

[0024] A second capacitor, one end of the second capacitor is electrically connected to the first node, and the other end of the second capacitor is connected to the constant high potential signal.

[0025] In one embodiment, the third transistor is a P-type transistor, and the fourth transistor and the fifth transistor are both N-type transistors.

[0026] In one embodiment, the high potential control module includes:

[0027] a ninth transistor, wherein a gate of the ninth transistor is connected to the first clock signal, and a source of the ninth transistor is connected to the constant low potential signal;

[0028] a tenth transistor, wherein a gate of the tenth transistor is connected to the constant low potential signal, and a source of the tenth transistor is electrically connected to a drain of the ninth transistor;

[0029] an eleventh transistor, a gate of the eleventh transistor being electrically connected to the drain of the tenth transistor, and a source of the eleventh transistor being connected to the second clock signal;

[0030] a twelfth transistor, wherein a gate of the twelfth transistor is connected to the second clock signal, a source of the twelfth transistor is electrically connected to a drain of the eleventh transistor, and a drain of the twelfth transistor is electrically connected to the second node;

[0031] a thirteenth transistor, wherein a gate of the thirteenth transistor is electrically connected to a drain of the first transistor, a source of the thirteenth transistor is connected to the first clock signal, and a drain of the thirteenth transistor is electrically connected to a drain of the ninth transistor;

[0032] a fourteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to a source of the second transistor, a source of the fourteenth transistor is connected to the constant high potential signal, and a drain of the fourteenth transistor is electrically connected to the second node; and

[0033] A third capacitor, wherein a first end of the third capacitor is electrically connected to the gate of the eleventh transistor, and a second end of the third capacitor is electrically connected to the drain of the eleventh transistor.

[0034] In one embodiment, the signal output module includes:

[0035] a fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to the first node, a source of the fifteenth transistor is connected to the constant low potential signal, and a drain of the fifteenth transistor is electrically connected to the current-stage signal output terminal;

[0036] a sixteenth transistor, wherein a gate of the sixteenth transistor is electrically connected to the second node, a source of the sixteenth transistor is connected to the constant high potential signal, and a drain of the sixteenth transistor is electrically connected to the current-stage signal output terminal; and

[0037] A fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to the second node, and a second end of the fourth capacitor is electrically connected to the source of the sixteenth transistor.

[0038] In one embodiment, the first transistor, the second transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor and the sixteenth transistor are all P-type transistors.

[0039] In one embodiment, the first clock signal and the second clock signal are signals with the same period and opposite phases.

[0040] In a second aspect, the present application provides a display panel comprising the aforementioned gate driving circuit.

[0041] The embodiment of the present application provides a gate drive circuit and a display panel, wherein the gate drive circuit includes a signal input module, a low potential writing module, a high potential control module and a signal output module. The low potential writing module is used to control the potential of the first node, the high potential control module is used to control the potential of the second node, and the signal output module controls the potential of the signal output terminal of this level under the control of the potential of the first node and the second node. The present application directly writes a preset low potential to the first node by setting a low potential writing module, thereby eliminating the transistor threshold voltage in the gate drive circuit, dynamically adjusting the output step size, and improving the life performance and uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0043] Attached Figure 1 Schematic diagram of the output steps of the gate driving circuit in the embodiment of the present application;

[0044] Attached Figure 2 Schematic diagram of a module of a gate driving unit in an embodiment of the present application;

[0045] Attached Figure 3 This is a circuit diagram of an optional gate driving unit in an embodiment of the present application;

[0046] Attached Figure 4 A circuit diagram of another optional gate driving unit in an embodiment of the present application;

[0047] Attached Figure 5 This is a working timing diagram of the gate driving unit in the embodiment of the present application;

[0048] Attached Figure 6 Another working timing diagram of the gate driving unit in the embodiment of the present application;

[0049] Attached Figure 7 This is a schematic diagram of the effect of eliminating output steps of the gate driving unit in the embodiment of the present application;

[0050] Attached Figure 8 A schematic diagram of a module of an optional display panel in an embodiment of the present application.

[0051] Description of reference numerals in the figures:

[0052] 1. Display panel; 10. Gate drive circuit;

[0053] 100, gate driving unit; 110, signal input module; 120, low potential writing module; 130, high potential control module; 140, signal output module. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0055] According to a first aspect of the present application, a gate driving circuit 10 is provided, comprising a plurality of cascaded gate driving units 100, referring to Figure 2 As shown, the gate driving unit 100 includes a signal input module 110 , a low potential writing module 120 , a high potential control module 130 and a signal output module 140 .

[0056] The signal input module 110 is used to receive the previous stage output signal EM_in. It should be noted that when the gate driving unit 100 is a first stage driving unit, the signal input module 110 receives the frame start signal STV.

[0057] Specifically, the low potential writing module 120 is electrically connected to the signal input terminal and to the first node Q. The low potential writing module 120 is used to directly write a preset potential to the first node Q.

[0058] The high potential control module 130 is electrically connected to the second node P and to the low potential writing module. The high potential control module 130 is used to control the potential of the second node P.

[0059] The signal output module 140 is electrically connected to the signal output terminal of this stage and to the first node Q and the second node P. The signal output module 140 is used to control the potential of the signal output terminal of this stage under the control of the potential of the first node Q and the potential of the second node P.

[0060] Compared with the existing gate driving circuit 10, the gate driving circuit 10 of the embodiment of the present application uses a low potential writing module 120 to directly write a preset low potential to the first node Q, eliminating the output step of the gate driving circuit 10, which is beneficial to improving the life performance and uniformity of the display panel 1.

[0061] In some specific embodiments of the present application, refer to Figure 3 As shown, the signal input module 110 includes: a first transistor T1, a gate of the first transistor T1 is connected to the first clock signal XCK, a source of the first transistor T1 is connected to the previous stage output signal EM_in, and a drain of the first transistor T1 is electrically connected to the first control module.

[0062] In some specific embodiments of the present application, refer to Figure 4 As shown, the low potential writing module 120 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6.

[0063] The gate of the second transistor T2 is connected to a constant low potential signal, the source of the second transistor T2 is electrically connected to the drain of the first transistor T1, and the drain of the second transistor T2 is electrically connected to the first node Q. It should be noted that in some embodiments of the present application, the constant low potential signal may be a gate turn-off voltage VGL.

[0064] The gate of the third transistor T3 is connected to the first node Q, and the source of the third transistor T3 is connected to the preset high potential signal VGHL. It should be noted that the third transistor T3 is a low potential trigger module, which is used to trigger the action of writing the preset low potential VGLL to the first node Q;

[0065] The gate of the fourth transistor T4 is electrically connected to the drain of the third transistor T3, the source of the fourth transistor T4 is connected to the preset low potential signal VGLL, and the drain of the fourth transistor T4 is connected to the first node Q; it should be noted that the fourth transistor T4 writes the preset low potential signal VGLL to the first node Q according to the action of the third transistor T3.

[0066] The gate of the fifth transistor T5 is connected to the first node Q, the source of the fifth transistor T5 is connected to the preset low potential signal VGLL, and the drain of the fifth transistor T5 is electrically connected to the drain of the third transistor T3. It should be noted that the fifth transistor T5 is used to cut off the ultra-low voltage (i.e., the preset low potential VGLL) leading to the first node Q to ensure the voltage stability of the first node Q. It should be noted that in this embodiment, the third transistor T3 is a P-type transistor, and the fourth transistor T4 and the fifth transistor T5 are both N-type transistors. On this basis, when the first node Q is at a low potential, the third transistor T3 is turned on, the fifth transistor T5 is turned off, and the gate of the fourth transistor T4 is connected to the preset high potential signal VGHL, so that the fourth transistor T4 is turned on, and the first node Q is connected to the preset low potential VGLL; when the first node Q is at a high potential, the third transistor T3 is turned off, the fifth transistor T5 is turned on, and the gate of the fourth transistor is connected to the preset low potential signal VGLL, so that the fourth transistor T4 is turned off, and the voltage of the first node Q is stably maintained at a high potential.

[0067] The gate of the sixth transistor T6 is connected to the reset control signal, the source of the sixth transistor T6 is connected to the constant high potential signal, and the drain of the sixth transistor T6 is electrically connected to the drain of the first transistor T1;

[0068] The voltage value of the preset high potential signal VGHL is smaller than the constant high potential signal, and the voltage value of the preset low potential signal VGLL is smaller than the constant low potential signal.

[0069] In some embodiments of the present application, the low potential writing module 120 further includes a seventh transistor T7 and an eighth transistor T8.

[0070] The gate of the seventh transistor T7 is connected to the first node Q, and the source of the seventh transistor T7 is connected to the second clock signal CK;

[0071] an eighth transistor T8, wherein the gate of the eighth transistor T8 is connected to the high potential control module 130, the source of the eighth transistor T8 is connected to the constant high potential signal, and the drain of the eighth transistor T8 is electrically connected to the drain of the seventh transistor T7; and

[0072] The first capacitor C1 has a first end electrically connected to the gate of the seventh transistor T7 , and a second end electrically connected to the drain of the seventh transistor T7 .

[0073] In this embodiment, the seventh transistor T7, the eighth transistor T8 and the first capacitor C1 together form a coupling pull-down module. It should be noted that since the potential of the first node Q can be directly written by the fourth transistor T4, the coupling pull-down module can also be deleted without affecting the output.

[0074] In some specific embodiments of the present application, refer to Figure 4 As shown, the low potential writing module 120 further includes a second capacitor C2, one end of the second capacitor C2 is electrically connected to the first node Q, and the other end of the second capacitor C2 is connected to a constant high potential signal.

[0075] Reference Figure 3 and Figure 4 As shown, in some embodiments of the present application, the high potential control module 130 includes: a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14 and a third capacitor C3.

[0076] The gate of the ninth transistor T9 is connected to the first clock signal XCK, and the source of the ninth transistor T9 is connected to the constant low potential signal.

[0077] The gate of the tenth transistor T10 is connected to a constant low potential signal, and the source of the tenth transistor T10 is electrically connected to the drain of the ninth transistor T9.

[0078] The gate of the eleventh transistor T11 is electrically connected to the drain of the tenth transistor T10 , and the source of the eleventh transistor T11 is connected to the second clock signal CK.

[0079] The gate of the twelfth transistor T12 is connected to the second clock signal CK, the source of the twelfth transistor T12 is electrically connected to the drain of the eleventh transistor T11 , and the drain of the twelfth transistor T12 is electrically connected to the second node P.

[0080] The gate of the thirteenth transistor T13 is electrically connected to the drain of the first transistor T1 , the source of the thirteenth transistor T13 is connected to the first clock signal XCK, and the drain of the thirteenth transistor T13 is electrically connected to the drain of the eighth transistor T8 .

[0081] The gate of the fourteenth transistor T14 is electrically connected to the source of the second transistor T2 , the source of the fourteenth transistor T14 is connected to a constant high potential signal, and the drain of the fourteenth transistor T14 is electrically connected to the second node P.

[0082] A first end of the third capacitor C3 is electrically connected to the gate of the eleventh transistor T11 , and a second end of the third capacitor C3 is electrically connected to the drain of the eleventh transistor T11 .

[0083] In this embodiment, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 constitute a high potential output maintaining module. The third capacitor C3 is used to pull down the coupling. The tenth transistor T10 is used to block the ultra-low potential. The fourteenth transistor T14 is used to prevent the output short circuit.

[0084] In some specific embodiments of the present application, refer to Figure 3 to Figure 4 As shown, the signal output module 140 includes: a fifteenth transistor T15, a sixteenth transistor T16 and a fourth capacitor C4.

[0085] The gate of the fifteenth transistor T15 is electrically connected to the first node Q, the source of the fifteenth transistor T15 is connected to the constant low potential signal, and the drain of the fifteenth transistor T15 is electrically connected to the signal output terminal of this stage.

[0086] The gate of the sixteenth transistor T16 is electrically connected to the second node P, the source of the sixteenth transistor T16 is connected to the constant high potential signal, and the drain of the sixteenth transistor T16 is electrically connected to the signal output terminal of this stage.

[0087] The first end of the fourth capacitor C4 is electrically connected to the second node P, and the second end of the fourth capacitor C4 is electrically connected to the source of the sixteenth transistor T16, that is, a constant high potential signal is connected to achieve voltage stabilization of the second node P.

[0088] It should be noted that, in the aforementioned embodiments, the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are all P-type transistors.

[0089] It should be noted that in the above-mentioned embodiment, the first clock signal XCK and the second clock signal CK are signals with the same period and opposite phases. Figure 5 and Figure 6 As shown in FIG. 1 , a timing diagram of the gate driving unit 100 of the present application is shown in FIG. Figure 4 The timing diagram is explained by taking the circuit diagram of the gate driving unit 100 as an example:

[0090] At t0, the gate drive unit 100 receives the previous level output signal EM_in as a low level, the first clock signal XCK as a low level, and the second clock signal CK as a high level. At this moment, T9 and T1 are turned on under the control of the low level first clock signal XCK, T2 and T10 are turned on under the control of the constant low potential signal, the low level of the constant low potential signal is output to the node C, the node B and the first end of C3, and the low level of the previous level output signal EM_in is output to the node D and the node Q; because the node D is low level, T13 and T14 are turned on, the low level of the first clock signal XCK is output to the node C, and the high level of the constant high potential signal is output to the second node P. At this time, T11 is turned on, and the high level of the second clock signal CK is output to the second end (node ​​A) of C3. At this time, the first node Q remains at a low level, the second node P is at a high level, and the low level of the constant low potential signal is output to the signal output end of this level.

[0091] At time t1, the gate driving unit 100 receives the previous stage output signal EM_in as a low level, the first clock signal XCK as a high level, and the second clock signal CK as a low level. The first node Q begins to change from a low level to a high level, at which time T13 and T14 are turned on, the high level of the first clock signal XCK is output to the node C and the node B and the first end of the capacitor C3, and the high level of the constant high potential signal is output to the second node P and the second end of the capacitor C3. At this time, the first node Q has not yet changed to a high level, the second node P is at a high level, and the low level of the constant low potential signal VGL is output to the signal output terminal OUT of this stage.

[0092] At time t2, when the gate drive unit 100 receives the previous level output signal EM_in as a high level, the first clock signal XCK is a low level, and the second clock signal CK is a high level. T9 and T1 are turned on, the low level of the constant low potential signal is output to node C, node B and the first end of capacitor C3, and the high level of the previous level output signal EM_in is output to node D and the first node Q; since node D is a high level, T13 and T14 are turned off. Since the second clock signal CK is a high level, T12 is turned off, and the second node P maintains a high level. Since node B is a low level, T11 is turned on, and the high level of the second clock signal CK is output to the second end of capacitor C3. At this time, the first node Q is at a high level, the second node P is at a high level, and the low level of the constant low potential signal VGL is output to the signal output end of this level.

[0093] At time t3, when the gate drive unit 100 receives the previous level output signal EM_in and maintains a high level, the first clock signal XCK is a high level, and the second clock signal CK is a low level. The first node Q maintains a high level, and T13 and T14 are closed at this time. Since the second clock signal CK is a low level, T12 is turned on. Since node B is a low level, T11 is turned on, and the low level of the second clock signal CK is output to the second end of the capacitor C3 and the second node P. At this time, the capacitor C3 bootstraps to lower the potential of the node B. At this time, the first node Q is a high level, the second node P is a low level, and the high level of the constant high potential signal is output to the signal output end of this level.

[0094] At time t4, when the gate drive unit 100 receives the previous stage output signal EM_in from high level to low level, the first clock signal XCK is low level, and the second clock signal CK is high level. T1 and T9 are turned on, the low level of the constant low potential signal VGL is output to nodes C, B and the first end of the capacitor C3, the low level of the previous stage output signal EM_in is output to node D, the first node Q, and T14 is turned on. The high level of the second clock signal CK and the high level of the constant high potential signal VGH are output to the second end of the capacitor C3. At this time, T14 is turned on, T12 is turned off, the node P is connected to the constant high potential signal, T16 is turned off, and the low level of the constant low potential signal is output to the signal output end of this stage.

[0095] Reference Figure 7 As shown, out1 is the output step of the gate driving circuit 10 in the related art, and out2 is the output step of the gate driving circuit 10 of the present application. The present application eliminates the output step of the gate driving circuit 10 by setting a low-voltage writing module 120, and the output falling edge is not delayed, thereby improving the life performance and uniformity of the display panel 1.

[0096] According to the second aspect of the present application, referring to Figure 8 As shown, a display panel 1 is provided, which includes the aforementioned gate driving circuit 10 and can achieve all the effects of the aforementioned gate driving circuit 10, which will not be described in detail here.

[0097] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a plurality of gate driving units arranged in cascade, wherein the gate driving unit comprises: A signal input module is used to receive the output signal of the previous level; A low potential writing module, electrically connected to the signal input terminal and to the first node, the low potential writing module being used to directly write a preset low potential to the first node; A high potential control module, electrically connected to the second node and to the low potential writing module, the high potential control module being used to control the potential of the second node; A signal output module is electrically connected to the signal output terminal of this stage and to the first node and the second node. The signal output module is used to control the potential of the signal output terminal of this stage according to the potential of the first node and the potential of the second node.

2. The gate driving circuit according to claim 1, characterized in that: The signal input module comprises: A first transistor, wherein a gate of the first transistor is connected to a first clock signal, a source of the first transistor is electrically connected to the previous stage output signal, and a drain of the first transistor is electrically connected to the first control module.

3. The gate driving circuit according to claim 2, characterized in that: The low potential writing module comprises: a second transistor, wherein a gate of the second transistor is connected to a constant low potential signal, a source of the second transistor is electrically connected to a drain of the first transistor, and a drain of the second transistor is electrically connected to the first node; a third transistor, wherein a gate of the third transistor is connected to the first node, and a source of the third transistor is connected to a preset high potential signal; a fourth transistor, wherein a gate of the fourth transistor is electrically connected to a drain of the third transistor, a source of the fourth transistor is connected to a preset low potential signal, and a drain of the fourth transistor is connected to the first node; a fifth transistor, wherein a gate of the fifth transistor is connected to the first node, a source of the fifth transistor is connected to the preset low potential signal, and a drain of the fifth transistor is electrically connected to a drain of the third transistor; and a sixth transistor, wherein a gate of the sixth transistor is connected to a reset control signal, a source of the sixth transistor is connected to the constant high potential signal, and a drain of the sixth transistor is electrically connected to a drain of the first transistor; Wherein, the voltage value of the preset high potential signal is smaller than that of the constant high potential signal, and the voltage value of the preset low potential signal is smaller than that of the constant low potential signal.

4. The gate driving circuit according to claim 3, characterized in that: The low potential writing module also includes: a seventh transistor, wherein a gate of the seventh transistor is connected to the first node, and a source of the seventh transistor is connected to a second clock signal; an eighth transistor, wherein a gate of the eighth transistor is connected to the high potential control module, a source of the eighth transistor is connected to a constant high potential signal, and a drain of the eighth transistor is electrically connected to a drain of the seventh transistor; and A first capacitor, wherein a first end of the first capacitor is electrically connected to the gate of the seventh transistor, and a second end of the first capacitor is electrically connected to the drain of the seventh transistor.

5. The gate driving circuit according to claim 3, wherein the low potential writing module further comprises: A second capacitor, one end of the second capacitor is electrically connected to the first node, and the other end of the second capacitor is connected to the constant high potential signal.

6. The gate driving circuit according to claim 3, characterized in that: The third transistor is a P-type transistor, and the fourth transistor and the fifth transistor are both N-type transistors.

7. The gate driving circuit according to any one of claims 3 to 6, characterized in that: The high potential control module comprises: a ninth transistor, wherein a gate of the ninth transistor is connected to the first clock signal, and a source of the ninth transistor is connected to the constant low potential signal; a tenth transistor, wherein a gate of the tenth transistor is connected to the constant low potential signal, and a source of the tenth transistor is electrically connected to a drain of the tenth transistor; an eleventh transistor, a gate of the eleventh transistor being electrically connected to the drain of the tenth transistor, and a source of the eleventh transistor being connected to the second clock signal; a twelfth transistor, wherein a gate of the twelfth transistor is connected to the second clock signal, a source of the twelfth transistor is electrically connected to a drain of the eleventh transistor, and a drain of the twelfth transistor is electrically connected to the second node; a thirteenth transistor, wherein a gate of the thirteenth transistor is electrically connected to a drain of the first transistor, a source of the thirteenth transistor is connected to the first clock signal, and a drain of the thirteenth transistor is electrically connected to a drain of the ninth transistor; a fourteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to a source of the second transistor, a source of the fourteenth transistor is connected to the constant high potential signal, and a drain of the fourteenth transistor is electrically connected to the second node; and A third capacitor, wherein a first end of the third capacitor is electrically connected to the gate of the eleventh transistor, and a second end of the third capacitor is electrically connected to the drain of the eleventh transistor.

8. The gate driving circuit according to claim 7, characterized in that: The signal output module comprises: a fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to the first node, a source of the fifteenth transistor is connected to the constant low potential signal, and a drain of the fifteenth transistor is electrically connected to the current-stage signal output terminal; a sixteenth transistor, wherein a gate of the sixteenth transistor is electrically connected to the second node, a source of the sixteenth transistor is connected to the constant high potential signal, and a drain of the sixteenth transistor is electrically connected to the current-stage signal output terminal; and A fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to the second node, and a second end of the fourth capacitor is electrically connected to the source of the sixteenth transistor.

9. The gate driving circuit according to claim 8, characterized in that: The first transistor, the second transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor and the sixteenth transistor are all P-type transistors.

10. The gate driving circuit according to claim 9, characterized in that: The first clock signal and the second clock signal are signals with the same period and opposite phases.

11. A display panel, characterized in that: The gate driving circuit comprises the gate driving circuit as claimed in any one of claims 1 to 11.

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