A gate-controlled pixel driving circuit and a Vth compensation method thereof

Abstract

The application discloses a gate-controlled pixel driving circuit, comprising a first transistor, a second transistor and a third transistor, wherein a first source-drain electrode of the first transistor is coupled to a data signal line, a second source-drain electrode is coupled to a pre-storage capacitor and a gate of the second transistor, and the gate is coupled to a control signal line; a first source-drain electrode of the second transistor is coupled to a reference signal line, and a second source-drain electrode is coupled to a first source-drain electrode of the third transistor; a gate of the third transistor is coupled to a transfer signal line, and a second source-drain electrode is coupled to a pixel capacitor and a holding capacitor.

Description

Technical Field

[0001] This invention relates to the field of pixel driving technology, and more specifically to a gate-controlled pixel driving circuit and its Vth compensation method. Background Technology

[0002] In traditional field-sequential or color-sequential display driving technologies, the backlight can only be turned on after all screen data has been written and the liquid crystal has reached a stable state. Otherwise, image distortion will occur. Therefore, the data writing and liquid crystal deflection time greatly compresses the backlight turn-on time, leading to difficulties in increasing display brightness, refresh rate, and resolution, as well as increased power consumption and backlight material costs. Therefore, how to accelerate the liquid crystal driving time and increase the backlight turn-on time is a crucial issue.

[0003] Taking a traditional pre-storage driving circuit utilizing charge sharing as an example, the pre-storage capacitor Cst is at least on the same order of magnitude as the pixel capacitor Clc, and in some high refresh rate products, it is even tens of times larger than Clc, greatly reducing the pixel aperture ratio. Since the size of Clc is related to the liquid crystal deflection, and the liquid crystal deflection is related to voltage, and the liquid crystal response takes time, the shorter the charging time, the less time Clc has to react to the target potential capacitor, requiring Cst to continuously supply power to it.

[0004] In summary, traditional pre-stored pixel driving circuits suffer from low aperture ratio. Summary of the Invention

[0005] In view of this, the present invention provides a gate-controlled pixel driving circuit, which solves the problem of low aperture ratio in traditional pre-stored pixel driving circuits by improving the circuit structure and driving timing.

[0006] To solve the above problems, the technical solution of the present invention is to adopt a gate-controlled pixel driving circuit, including: a first transistor (M1), a second transistor (M2) and a third transistor (M3), wherein the first source and drain of the first transistor are coupled to a data signal line, the second source and drain are coupled to a pre-storage capacitor and the gate of the second transistor, and the gate is coupled to a control signal line; the first source and drain of the second transistor are coupled to a reference signal line, and the second source and drain are coupled to the first source and drain of the third transistor; the gate of the third transistor is coupled to a transfer signal line, and the second source and drain are coupled to a pixel capacitor and a holding capacitor.

[0007] Optionally, the driving timing of the pixel driving circuit is configured as follows: during the backlight-on phase, the control signal jumps to a high potential, the first transistor turns on, and after the data signal is stored in the pre-storage capacitor, the control signal jumps back to a low potential; during the backlight-off phase, the transfer signal jumps to a high potential, the reference signal jumps to a low potential, the second transistor and the third transistor turn on, the second transistor operates in the linear region and resets the pixel capacitor based on the reference signal, the reference signal jumps to a high potential, the second transistor operates in the saturation region and transmits the data signal to the pixel capacitor, the transfer signal jumps to a low potential, the reference signal jumps to a low potential again, the second transistor operates in the linear region, the third transistor turns off, the second transistor resets the potential at the second source-drain terminal of the second transistor based on the reference signal, and the reference signal jumps to a normal potential.

[0008] Optionally, the pixel driving circuit located outside the pixel display area further includes a detection signal line, which is coupled to the second source and drain of the second transistor and the first source and drain of the third transistor.

[0009] Optionally, the pixel driving circuit disposed in the pixel display area further includes a fourth transistor, the gate of the fourth transistor being coupled to a reset signal line, the first source-drain being coupled to a global signal line, and the second source-drain being coupled to the pixel capacitor and the holding capacitor.

[0010] Optionally, the pre-storage capacitor, the pixel capacitor, and the holding capacitor are coupled to a common signal at the end furthest from the transistor.

[0011] Accordingly, the present invention provides a Vth compensation method for a gate-controlled pixel driving circuit, applied to the aforementioned pixel driving circuit, comprising: acquiring threshold voltage change data of the third transistor affecting the liquid crystal grayscale voltage during the pre-calibration operation phase of the pixel driving circuit; generating a voltage compensation curve that varies with time based on the threshold voltage change data; and generating a data signal based on the voltage compensation curve and the target grayscale voltage.

[0012] Optionally, if the pixel driving circuit located outside the pixel display area includes a detection signal line, the compensation method further includes: generating a threshold voltage change rate based on the threshold voltage change data; generating multiple monitoring time points with varying time intervals based on the threshold voltage change rate; acquiring the measured threshold voltage of the third transistor through the detection signal line at the monitoring time points; and correcting the voltage compensation curve based on the measured threshold voltage.

[0013] Optionally, at the monitoring time point, obtaining the measured threshold voltage of the third transistor through the detection signal line includes: in the frame preceding the monitoring time point, the pixel driving circuit located outside the pixel display area writes the test voltage into the pre-storage capacitor through the data signal line; at this time, the pixel driving circuit located within the pixel display area normally writes the data signal for display; in the current frame at the detection time point, when the transfer signal jumps to a high potential, the measured voltage is obtained based on the detection signal line; and a measured threshold voltage is generated based on the measured voltage and the test voltage.

[0014] Optionally, the test voltage is configured such that the absolute values ​​of the test voltages of the pixel driving circuits in adjacent columns located outside the pixel display area are the same but have opposite polarities.

[0015] The primary improvement of this invention is the provided gate-controlled pixel driving circuit. By setting a pre-storage capacitor in conjunction with a transistor, the grayscale voltage of the next frame is stored in the pre-storage capacitor during the backlight illumination time of the current frame. This enables all pixels to synchronously achieve grayscale voltage when the backlight is off, greatly reducing the pixel voltage writing time and relatively increasing the backlight illumination time. Furthermore, since this pixel driving circuit does not require pre-storage capacitors for charge sharing, but only needs to use the stored potential as a gate control signal, its capacitance value is very small, and it does not need to occupy too much aperture ratio, thus solving the problem of low aperture ratio in traditional pre-storage pixel driving circuits.

[0016] Meanwhile, this invention achieves frame-by-frame voltage reversal across the liquid crystal capacitor through linear region reset and saturation region writing driving timing, avoiding liquid crystal polarization problems. It also eliminates residual data from the previous frame through the first reset and ensures pixel voltage writing with polarity reversal. Furthermore, it reduces the gate-source-drain voltage difference of the driving transistor through the second reset, thereby increasing device stability, reducing Vth drift, improving grayscale voltage accuracy, and enhancing the grayscale display accuracy of the image.

[0017] Furthermore, by constructing a voltage compensation curve, this invention enables further compensation of grayscale voltage through an external processing unit, thereby improving the accuracy of grayscale voltage and enhancing the accuracy of grayscale display. Attached Figure Description

[0018] Figure 1 This is a simplified circuit diagram of the pixel driving circuit of the present invention;

[0019] Figure 2 This is a simplified driving timing diagram of the pixel driving circuit of the present invention;

[0020] Figure 3 This is a simplified circuit diagram of the preferred pixel driving circuit outside the pixel display area of ​​the present invention;

[0021] Figure 4 This is a simplified circuit diagram of the pixel driving circuit in the preferred pixel display area of ​​the present invention;

[0022] Figure 5 This is a simplified driving timing diagram of the pixel driving circuit in the preferred pixel display area of ​​the present invention;

[0023] Figure 6 This is a schematic diagram of the threshold voltage change data of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0027] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0029] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0032] Specifically, such as Figure 1 As shown, the present invention includes: a first transistor M1, a second transistor M2, and a third transistor M3, wherein the first source-drain of the first transistor M1 is coupled to the data signal line Data, the second source-drain is coupled to the pre-storage capacitor Cst1 and the gate of the second transistor M2, and the gate is coupled to the control signal line Scan; the first source-drain of the second transistor M2 is coupled to the reference signal line Vst, and the second source-drain is coupled to the first source-drain of the third transistor M3; the gate of the third transistor M3 is coupled to the transfer signal line Tran, and the second source-drain is coupled to the pixel capacitor Clc and the holding capacitor Cst2.

[0033] Furthermore, such as Figure 2 As shown, the driving timing of the pixel driving circuit can be configured as follows:

[0034] During the backlight-on phase, the control signal jumps to a high potential, the first transistor M1 is turned on, and after the data signal is stored in the pre-storage capacitor Cst1, the control signal jumps back to a low potential.

[0035] During the backlight-off phase, the transfer signal jumps to a high potential and the reference signal jumps to a low potential. The second transistor M2 and the third transistor M3 are turned on. The second transistor M2 operates in the linear region and resets the pixel capacitor based on the reference signal. The reference signal then jumps to a high potential. The second transistor M2 operates in the saturation region and transmits the data signal to the pixel capacitor Clc. The transfer signal jumps to a low potential and the reference signal jumps to a low potential again. The second transistor M2 operates in the linear region and the third transistor M3 is turned off. The second transistor M2 resets the potential at the second source-drain terminal of the second transistor M2 based on the reference signal. The reference signal then jumps to a normal potential.

[0036] This invention, by setting a pre-storage capacitor in conjunction with a transistor, enables the storage of the grayscale voltage of the next frame during the backlight illumination time of the current frame. This allows all pixels to synchronously achieve grayscale voltage when the backlight is off, greatly reducing the pixel voltage writing time and relatively increasing the backlight illumination time. Furthermore, since this pixel driving circuit does not require charge sharing using a pre-storage capacitor, but only needs to use its stored potential as a gate control signal, its capacitance value is very small, and it does not need to occupy too much aperture ratio, thus solving the problem of low aperture ratio in traditional pre-storage pixel driving circuits.

[0037] Furthermore, this invention achieves frame-by-frame voltage reversal across the liquid crystal capacitor through linear region reset and saturation region write driving timing, avoiding liquid crystal polarization problems. It also eliminates residual data from the previous frame through the first reset and ensures pixel voltage writing with polarity reversal, and further ensures that the same column of pixels is driven by the same pixel during positive and negative frame switching through a second reset.

[0038] A Vds=0 value for the tube is beneficial to device stability, reduces Vth drift, improves grayscale voltage accuracy, and enhances the accuracy of grayscale display.

[0039] It should be noted that the high potential of the control signal and transfer signal is defined as the potential that enables the transistor to conduct, and the low potential of the control signal and transfer signal is defined as the potential that enables the transistor to turn off; the high potential of the reference signal is defined as the potential higher than Vop-max, the normal potential is defined as the same as the common signal Com, and the low potential is defined as lower than the common signal Com.

[0040] Furthermore, such as Figure 3 As shown, the pixel driving circuit, located outside the pixel display area, also includes a detection signal line, Signal, which is coupled to the second source / drain of the second transistor M2 and the first source / drain of the third transistor M3. By setting a detection line outside the AA area (pixel display area), this invention enables monitoring of the Vth drift characteristics of circuit devices without affecting the in-plane aperture ratio or in-plane display, and pre-compensates the written data signal using a peripheral data processing unit (T-con).

[0041] Furthermore, such as Figure 4 As shown, the pixel driving circuit disposed in the pixel display area further includes a fourth transistor M4. The gate of the fourth transistor M4 is coupled to the reset signal line Reset, the first source and drain are coupled to the global signal line Ref, and the second source and drain are coupled to the pixel capacitor Clc and the holding capacitor Cst2.

[0042] Specifically, such as Figure 5As shown, the driving timing of the pixel driving circuit including the fourth transistor M4 is configured as follows:

[0043] During the backlight-on phase, the control signal jumps to a high potential, the first transistor turns on, and after the data signal is stored in the pre-storage capacitor, the control signal jumps back to a low potential.

[0044] During the backlight-off phase, the reset signal jumps to a high potential. After the fourth transistor turns on and resets the pixel capacitor based on the global signal, the reset signal jumps back to a low potential. After the fourth transistor, the transfer signal and the reference signal jump to a high potential. The second transistor operates in the saturation region and transmits the data signal to the pixel capacitor. The transfer signal jumps to a low potential, and the reference signal jumps to a low potential again. The second transistor operates in the linear region, and the third transistor turns off. After the second transistor resets the potential at the second source and drain of the second transistor a second time based on the reference signal, the reference signal jumps to a normal potential.

[0045] Furthermore, the pre-storage capacitor Cst1, the pixel capacitor Clc, and the holding capacitor Cst2 are coupled to the common signal Com at the ends furthest from the transistor.

[0046] Accordingly, the present invention provides a Vth compensation method for a gate-controlled pixel driving circuit, applied to the aforementioned pixel driving circuit, comprising:

[0047] S1: During the pre-calibration phase of the pixel driving circuit, the threshold voltage change data of the third transistor M3 that affects the liquid crystal grayscale voltage is obtained.

[0048] Furthermore, the method for obtaining the threshold voltage change data of the third transistor M3 that affects the liquid crystal grayscale voltage can be as follows: Figure 6 As shown, after the driving panel has passed the factory aging stage, one pixel driving circuit or one row of pixel driving circuits outside the AA area of ​​the panel can be pre-powered for a power-on time of t0-t3, and threshold voltage change data can be continuously acquired; or, all pixel driving circuits outside the AA area of ​​one driving panel in a batch of driving panels can be pre-powered for a power-on time of t0-t3, and threshold voltage change data can be continuously acquired.

[0049] Furthermore, there may be slight differences in the threshold voltage change data of each pixel driving circuit. This is due to the slight differences that exist due to the limitations of the fabrication process during the layout preparation. In this case, the average value of the threshold voltage change data of multiple pixel driving circuits can be taken. Subsequent unevenness issues can be compensated by Demura at the software level.

[0050] S2: Generate a voltage compensation curve that changes over time based on the threshold voltage change data.

[0051] Furthermore, methods for generating time-varying voltage compensation curves can include: such as... Figure 6 As shown, a threshold voltage change curve vth=nt is constructed based on the threshold voltage change data. 1 / m Where t = (Vth / n) m If m > 1 and n < 1, a voltage compensation curve can be generated from the threshold voltage change curve.

[0052] S3: Generate a data signal based on the voltage compensation curve and the target grayscale voltage.

[0053] Furthermore, the second gate of the third transistor M3 is coupled to the first reference signal line Ref1 and the second gate of the fourth transistor M4 is coupled to the second reference signal line Ref2. The second source and drain of the third transistor M3 are both coupled to one end of the pixel capacitor Clc, and the second source and drain of the fourth transistor M4 are both coupled to the other end of the pixel capacitor Clc.

[0054] Specifically, when the pixel driving circuit located outside the pixel display area includes a detection signal line Signal, the compensation method further includes:

[0055] S4: Generate the threshold voltage change rate based on the threshold voltage change data.

[0056] Furthermore, the method for generating the threshold voltage change rate is based on the formula vth=nt. 1 / m Construct the threshold voltage change rate (n / m)*t 1 / m-1 , where m and n are both obtained by fitting threshold voltage change data.

[0057] S5: Generate multiple monitoring time points based on the threshold voltage change rate.

[0058] Furthermore, the method for generating multiple monitoring time points of time interval variation includes: generating multiple monitoring time points of time interval variation based on a preset rate of change threshold and the threshold voltage rate of change (e.g., Figure 6As shown in the example, t1, t2, and t3 can be used as monitoring time points. That is, when a fixed rate of change is preset, the time point required to determine the change in the threshold voltage is determined, and this time point is the detection time point. Here, the present invention utilizes the device characteristics of the TFT itself. Since the change in the threshold voltage Vth of the TFT is relatively flat, setting monitoring time points with the same time interval will cause the following problems: if the time interval is set too short, it will unnecessarily increase the computing power load and bandwidth pressure of T-con and the driving IC in the later stage of TFT operation; if the time interval is set too long, it will lead to poor monitoring effect in the early stage of TFT operation (when Vth changes significantly). Therefore, the present invention utilizes the device characteristics of the TFT itself, constructs a threshold voltage change rate to characterize the threshold voltage trend, and characterizes the length of the required monitoring time interval, making full use of the device characteristics to optimize the monitoring and compensation method, thus avoiding the above-mentioned problems.

[0059] S6: At the monitoring time point, the measured threshold voltage of the third transistor (M3) is obtained through the detection signal line (Signal).

[0060] Furthermore, S6 includes: in the frame preceding the monitoring time point, the pixel driving circuit located outside the pixel display area writes the test voltage into the pre-storage capacitor Cst1 through the data signal line Data. At this time, the pixel driving circuit located within the pixel display area normally writes the data signal for display; in the current frame of the detection time point, when the transfer signal jumps to a high potential, the measured voltage is obtained based on the detection signal line; and a measured threshold voltage is generated based on the measured voltage and the test voltage.

[0061] Furthermore, the test voltage is configured such that the absolute values ​​of the test voltages of the pixel driving circuits in adjacent columns located outside the pixel display area are the same but have opposite polarities.

[0062] S7: Correct the voltage compensation curve based on the measured threshold voltage, i.e., the correction formula is vth=nt. 1 / m The values ​​of n and m are used to perform secondary compensation on Vth, thereby further improving the accuracy of grayscale voltage and enhancing the accuracy of grayscale display.

[0063] Furthermore, the backlight can be partitioned for brightness compensation based on the measured threshold voltage, without modifying the voltage compensation curve, thus avoiding the computational load problem that may arise from real-time correction of the voltage compensation curve.

[0064] The foregoing describes a gate-controlled pixel driving circuit and its Vth compensation method according to embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0065] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the invention. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory, memory, read-only memory, electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

Claims

1. A gate-controlled pixel driving circuit, characterized by, Comprises: A first transistor (M1), a second transistor (M2) and a third transistor (M3), wherein, The first source-drain electrode of the first transistor (M1) is coupled to a data signal line (Data), the second source-drain electrode is coupled to a pre-storage capacitor (Cst1) and the gate electrode of the second transistor (M2), and the gate electrode is coupled to a control signal line (Scan); The first source-drain electrode of the second transistor (M2) is coupled to a reference signal line (Vst), and the second source-drain electrode is coupled to the first source-drain electrode of the third transistor (M3); The gate electrode of the third transistor (M3) is coupled to a transfer signal line (Tran), and the second source-drain electrode is coupled to a pixel capacitor (Clc) and a holding capacitor (Cst2).

2. The pixel driving circuit according to claim 1, characterized in that, The driving timing of the pixel driving circuit is configured as: In the backlight-on stage, the control signal jumps to high potential, the first transistor (M1) is opened, the data signal is stored to the pre-storage capacitor (Cst1), and then the control signal jumps back to low potential; In the backlight-off stage, the transfer signal jumps to high potential, the reference signal jumps to low potential, the second transistor (M2) and the third transistor (M3) are opened, the second transistor (M2) works in the linear region and resets the pixel capacitor (Clc) based on the reference signal, then the reference signal jumps to high potential, the second transistor (M2) works in the saturation region and transfers the data signal to the pixel capacitor (Clc), The transfer signal jumps to low potential, the reference signal jumps to low potential again, the second transistor (M2) works in the linear region, the third transistor (M3) is turned off, and after the second transistor (M2) resets the potential at the second source-drain electrode of the second transistor (M2) based on the reference signal, the reference signal jumps to the normal potential.

3. The pixel driving circuit of claim 1, wherein, The pixel driving circuit arranged outside the pixel display area further comprises a detection signal line (Signal), which is coupled to the second source-drain electrode of the second transistor (M2) and the first source-drain electrode of the third transistor (M3).

4. The pixel driving circuit of claim 1, wherein, The pixel driving circuit arranged in the pixel display area further comprises a fourth transistor (M4), the gate electrode of the fourth transistor (M4) is coupled to a reset signal line (Reset), the first source-drain electrode is coupled to a global signal line (Ref), and the second source-drain electrode is coupled to the pixel capacitor (Clc) and the holding capacitor (Cst2).

5. The pixel driving circuit of claim 1, wherein, The far end of the pre-storage capacitor (Cst1), the pixel capacitor (Clc) and the holding capacitor (Cst2) is coupled to a common signal (Com).

6. A Vth compensation method of a gate-controlled pixel driving circuit, applied to the pixel driving circuit of any one of claims 1-5, characterized in that, Comprises: In the pre-designated working stage of the pixel driving circuit, the threshold voltage change data of the third transistor (M3) affecting the liquid crystal gray scale voltage is obtained; A voltage compensation curve varying with time is generated based on the threshold voltage change data; A data signal is generated based on the voltage compensation curve and the target gray scale voltage.

7. The Vth compensation method according to claim 6, characterized in that, In the case that the pixel driving circuit arranged outside the pixel display area comprises a detection signal line (Signal), the compensation method further comprises: generating a threshold voltage change rate based on the threshold voltage change data; generating a plurality of monitoring time points of time interval change based on the threshold voltage change rate; acquiring a measured threshold voltage of the third transistor (M3) through the detection signal line (Signal) at the monitoring time point; correcting the voltage compensation curve based on the measured threshold voltage.

8. The Vth compensation method according to claim 7, characterized in that, acquiring a measured threshold voltage of the third transistor (M3) through the detection signal line (Signal) at the monitoring time point, comprising: at a frame before the monitoring time point, the pixel driving circuit arranged outside the pixel display area writes a test voltage into the pre-storage capacitor (Cst1) through the data signal line (Data), at this time, the pixel driving circuit arranged in the pixel display area normally writes the data signal for display; at the current frame of the monitoring time point, when the transfer signal jumps to high potential, the measured voltage is acquired based on the detection signal line; generating a measured threshold voltage based on the measured voltage and the test voltage.

9. The Vth compensation method according to claim 8, characterized in that, The test voltage is configured as: The absolute values of the test voltages of the pixel driving circuits of adjacent columns arranged outside the pixel display area are the same and the polarities are opposite.

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