Method, device and equipment for determining page scheduling strategy

Abstract

The present invention provides a method, device and equipment for determining a page scheduling strategy, and relates to the field of computer technology. The method comprises: comparing the row address of a storage body to be accessed in a target queue with the historical access row address of the storage body, and obtaining a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment; and determining the memory page scheduling strategy corresponding to the storage body according to the comparison result. The method of the embodiment of the present application realizes the accurate determination of the page scheduling strategy.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device and equipment for determining a page scheduling strategy. Background Art

[0002] DRAM (Dynamic Random Access Memory) plays a vital role in computer systems. It is mainly used to store temporary data and programs to support fast data processing and operation of the system.

[0003] In the related art, the paging strategies supported by DRAM include an open page mode and a closed page mode. In the process of data access, how to select an appropriate paging strategy to reduce memory access latency is a technical problem that those skilled in the art need to solve urgently. Summary of the invention

[0004] The present invention provides a method, device and equipment for determining a page scheduling strategy, which selects a memory page scheduling strategy according to a request to be issued by a processor, thereby realizing collaborative work between the processor and the memory. Compared with the existing method of randomly selecting a page scheduling strategy or a method of fixing a page scheduling strategy, the method realizes accurate determination of page scheduling strategies in different scenarios.

[0005] The present invention provides a method for determining a page scheduling strategy, comprising the following steps.

[0006] Compare the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment;

[0007] A memory page scheduling policy corresponding to the storage body is determined according to the comparison result.

[0008] According to a method for determining a page scheduling strategy provided by the present invention, the row address of a storage body to be accessed in a target queue is compared with a historically accessed row address of the storage body to obtain a comparison result; the historically accessed row address is a row address corresponding to the last time the storage body was accessed before the current moment; and according to the comparison result, a memory page scheduling strategy corresponding to the storage body is determined, including:

[0009] In a case where the row address of the storage body to be accessed is the same as the historical access row address of the storage body, determining that the memory page scheduling policy corresponding to the storage body is a page open policy;

[0010] In a case where the row address of the storage body to be accessed is different from the historical access row address of the storage body, it is determined that the memory page scheduling policy corresponding to the storage body is a page closing policy.

[0011] According to a method for determining a page scheduling strategy provided by the present invention, before comparing the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body, the method further includes:

[0012] In the case that multiple queues all include the row address of the storage body to be accessed, a target queue is determined from the multiple queues according to the priorities of the multiple queues; the target queue is the queue with the highest priority among the multiple queues.

[0013] According to a method for determining a page scheduling strategy provided by the present invention, when the multiple queues include at least two of a memory access invalidation queue, a prefetch queue, and a write-back queue, the priorities of the multiple queues include:

[0014] The priority of the memory access invalidation queue is higher than the priority of the write-back queue;

[0015] The priority of the write-back queue is higher than the priority of the pre-fetch queue.

[0016] According to a method for determining a page scheduling strategy provided by the present invention, after determining the memory page scheduling strategy corresponding to the storage body, the method further includes:

[0017] The row addresses of the multiple storage bodies to be accessed and the memory page scheduling policies corresponding to the multiple storage bodies are sent to a memory controller; the memory controller is used to determine whether to preferentially send the row addresses of the multiple storage bodies to be accessed to the memory device based on the memory page scheduling policies corresponding to the multiple storage bodies.

[0018] According to a method for determining a page scheduling strategy provided by the present invention, an access history table corresponding to each storage body in a memory device is maintained; the access history table is used to record the row address corresponding to the last access to each storage body before the current moment.

[0019] The present invention also provides a device for determining a page scheduling strategy, comprising the following modules:

[0020] A processing module, used for comparing the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment;

[0021] A determination module is used to determine the memory page scheduling strategy corresponding to the storage body according to the comparison result.

[0022] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for determining the page scheduling strategy described above is implemented.

[0023] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method for determining a page scheduling strategy as described in any one of the above is implemented.

[0024] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method for determining any of the page scheduling strategies described above is implemented.

[0025] The method, apparatus and device for determining a page scheduling strategy provided by the present invention determine the memory page scheduling strategy corresponding to a storage body according to the comparison result of the row address of the storage body to be accessed and the historical access row address of the storage body; that is, the memory page scheduling strategy is selected according to the request to be issued by the processor, so as to realize the coordinated work of the processor and the memory. Compared with the existing method of randomly selecting a page scheduling strategy or fixing the page scheduling strategy, the accurate determination of the page scheduling strategy in different scenarios is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 It is a schematic diagram of the memory access process provided by the present invention.

[0028] Figure 2 It is a schematic diagram of the page closing mode provided by the present invention.

[0029] Figure 3 It is a schematic diagram of the page opening mode provided by the present invention.

[0030] Figure 4 This is one of the flow charts of the method for determining the page scheduling strategy provided by the present invention.

[0031] Figure 5 This is the second flow chart of the method for determining the page scheduling strategy provided by the present invention.

[0032] Figure 6This is the third flow chart of the method for determining the page scheduling strategy provided by the present invention.

[0033] Figure 7 It is a schematic diagram of a device for determining a page scheduling strategy provided by the present invention.

[0034] Figure 8 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] Combine the following Figure 1-Figure 8 The present invention describes a method, device and apparatus for determining a page scheduling strategy.

[0037] In order to facilitate a clearer understanding of the technical solutions of the embodiments of the present application, some technical contents related to the embodiments of the present application are first introduced.

[0038] The rapid development of processor architecture technology and the continuous improvement of manufacturing process level have continuously improved the performance of processors and memory. However, the improvement of processor performance and memory performance is not in the same proportion. The performance of the processor is significantly faster than that of the memory, which has greatly aggravated the contradiction between computing and memory access in the processor. The key position of the improvement of storage system speed in improving the performance of the entire processor system is becoming increasingly prominent. The optimization of memory access in the industry has always been a huge driving force for the optimization of processor architecture.

[0039] like Figure 1As shown, DRAM storage cells are usually composed of a three-dimensional address space, including bank addresses, row addresses, and column addresses. DRAM access is divided into three stages: row access cycle, column access cycle, also known as command cycle, and precharge cycle. DRAM consists of multiple banks, each of which has a row buffer, and the data in the row buffer constitutes a page. When a bank in an idle state receives a row address, it enters a row selection cycle, performs a row activation operation (ACT, Activate Row), latches the row address, and reads and amplifies this row into the Row Buffer. When the bank receives a column address and a command, it enters a column selection cycle and performs a corresponding read (RD, Read) or write (WT, Write) operation according to the received command. After the operation is completed, DRAM enters a precharge cycle, performs a precharge operation (PRE, Precharge), and writes the data in the Row Buffer back to the DRAM storage cell. Modern memory DRAM supports page scheduling strategies, including opening page mode and closing page mode. Among them, for the Open Page mode, after the column selection cycle is completed, the page is kept in the row open state (Row Active), that is, the data in the row buffer is not written back to the DRAM storage unit. If the subsequent access is to the same row of the storage bank, the row selection cycle of the subsequent access can be saved. Accordingly, after the operation is completed, the DRAM is precharged, and the mode of writing the data in the Row Buffer back to the DRAM storage unit is called the Close Page mode.

[0040] like Figure 2 As shown in the figure, the operation state switching process of Close Page mode is as follows: the storage body in idle state (Idle) first performs a row activation operation (ACT, Activate Row), then performs a read operation (RD, Read) or a write operation (WT, Write), taking the read operation as an example, and finally performs a precharge operation (PRE, Precharge) and returns to idle state (Idle). Operation latency (Latency) refers to the clock cycle (Cycles) from the issuance of the row activation command to the return of the data, including the row selection time (tRCD) and the column selection time (CL). Among them, CL (CAS Latency refers to the number of clock cycles from the effective column select signal to the sampling of the first read request data. CL is usually 2 or 3. tRCD (RAS to CAS ) represents the number of clock cycles from row selection to column selection, tRCD is usually 2 or 3. tRP (RAS Precharge) represents the number of clock cycles from precharge to the occurrence of the next row selection transaction, and tRP is usually 2 or 3. The specific setting of the number of clock cycles of CL, tRCD and tRP is determined according to the comparison relationship between the system bus clock frequency and the DRAM frequency. In the embodiment of the present invention, CL, tRCD and tRP are set to 2, 3 and 2 respectively. The Latency of the Close Page strategy = tRCD + CL = 3 + 2 = 5.

[0041] like Figure 3 As shown in the figure, the Open Page mode is used to keep the page in the row open state (RowActive) after the column selection cycle is completed. The access latency of DRAM is different in the case of Page hit (Hit) and Page conflict (Miss) (Non-UniformDRAM Access Latency). The read operation state transition process of the Open Page mode is as follows: when accessing a storage body in the row open state (Row Active), if the accessed row is the same as the row in the open state in the accessed storage body, that is, Page hit (Hit), then only a read operation (RD, Read) or a write operation needs to be performed. If the accessed row is different from the row in the open state in the accessed storage body, that is, Page conflict (Miss), a precharge operation (PRE, Precharge) is performed first, then a row activation operation (ACT, Activate Row) is performed, and finally a read operation (RD, Read) or a write operation is performed. In the case of Page hit (Hit), the read operation latency (Latency) only includes the column selection time (CL), that is, Latency = CL = 2. In case of page conflict (Miss), the read operation latency includes precharge time (tRP), row select time (tRCD) and column select time (CL), that is, Latency = tRP + tRCD + CL = 2 + 3 + 2 = 7. Therefore, in order to improve the performance of memory devices and reduce the system memory access latency, only a flexible memory page scheduling strategy can give full play to the technical advantages provided by memory devices.

[0042] Figure 4 This is one of the flow charts of the method for determining the page scheduling strategy provided by the present invention, such as Figure 4 As shown, the method includes the following:

[0043] Step 401: Compare the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment.

[0044] Specifically, the paging strategies supported by DRAM include an open page mode and a closed page mode. In the process of data access, how to select an appropriate paging strategy to reduce memory access latency is a technical problem that those skilled in the art need to solve urgently.

[0045] In order to solve the above problem, in an embodiment of the present application, the row address of the storage body to be accessed in the target queue is first compared with the historical access row address of the storage body to obtain a comparison result; wherein the historical access row address is the row address corresponding to the last access of each storage body before the current moment. For example, in an embodiment of the present application, the addresses of the requests to be issued of all queue items in the processor cache invalidation queue, prefetch queue and write-back queue are compared with the row address of the last access of each storage body of the memory by the processor to obtain a comparison result. Optionally, the comparison result includes two results: the same and the different.

[0046] Step 402: Determine the memory page scheduling policy corresponding to the storage body according to the comparison result.

[0047] Specifically, the embodiment of the present application compares the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body, obtains the comparison result, and then determines the memory page scheduling strategy corresponding to the storage body according to the comparison result. Optionally, the corresponding relationship between the comparison result and the memory page scheduling strategy can be established in advance. If the comparison result is the same, one page scheduling strategy is adopted; if the comparison result is different, another page scheduling strategy is adopted. That is, in the embodiment of the present application, the memory page scheduling strategy corresponding to the storage body is determined by the real future memory access request issued by the processor and the row address of each storage body that was last accessed, and the guidance information for the memory page scheduling strategy is generated. That is, the memory page scheduling strategy is selected according to the request to be issued by the processor, so as to realize the collaborative work of the processor and the memory and reduce the delay of accessing the memory. Compared with the existing random selection of page scheduling strategies or fixed page scheduling strategies, it realizes the accurate determination of page scheduling strategies in different scenarios.

[0048] The method of the above embodiment determines the memory page scheduling policy corresponding to the storage body according to the comparison result of the row address of the storage body to be accessed and the historical access row address of the storage body; that is, the memory page scheduling policy is selected according to the request to be issued by the processor, so as to realize the coordinated work of the processor and the memory. Compared with the existing method of randomly selecting the page scheduling policy or the method of fixing the page scheduling policy, the accurate determination of the page scheduling policy in different scenarios is realized.

[0049] In one embodiment, the row address of the storage body to be accessed in the target queue is compared with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment; according to the comparison result, the memory page scheduling strategy corresponding to the storage body is determined, including:

[0050] When the row address of the storage body to be accessed is the same as the historical access row address of the storage body, determining that the memory page scheduling policy corresponding to the storage body is a page open policy;

[0051] When the row address of the memory bank to be accessed is different from the historical access row address of the memory bank, it is determined that the memory page scheduling policy corresponding to the memory bank is a page closing policy.

[0052] Specifically, when the row address of the memory bank to be accessed is the same as the historically accessed row address of the memory bank, the memory page scheduling strategy corresponding to the memory bank is determined to be the page open strategy. That is, when the row address of the memory bank to be accessed is the same as the historically accessed row address of the memory bank, the row corresponding to the current memory access operation has been activated, and the use of the page open strategy can effectively save the delay (tRCD) of row activation and improve memory access performance.

[0053] When the row address of the memory bank to be accessed is different from the historically accessed row address of the memory bank, the memory page scheduling policy corresponding to the memory bank is determined to be the page closing policy. That is, when the row address of the memory bank to be accessed is different from the historically accessed row address of the memory bank, the use of the page opening policy will generate an additional delay (tRP) introduced by precharging, which will have a negative impact on the memory access performance, so the page closing policy needs to be selected.

[0054] For example, the operation addresses to be sent to the memory controller in the processor include: the address of the miss request to be sent to the memory controller for the last level cache (LLC) access failure (Miss), the prefetch address to be sent to the memory controller, and the address of the processor write-back request to be sent to the memory controller. The address of the miss request to be sent to the memory controller for the processor access failure (Miss) comes from the memory access failure queue; the prefetch address to be sent to the memory controller by the processor comes from the prefetch queue; the address of the processor write-back request to be sent to the memory controller by the processor comes from the write-back queue. This application compares the addresses of the requests to be sent of all queue items in the processor's last level cache miss queue, prefetch queue, and write-back queue with the address of the last memory access that the processor has sent to each memory bank of the memory. For each memory bank of the memory, it is determined whether there is a page hit. If there is no hit for a memory bank and there is a page conflict in the memory bank, the memory bank with such a page conflict is guided to adopt the Close Page mode, and a page scheduling strategy is given for each memory bank whether to adopt the Close Page.

[0055] That is, according to the characteristics of DRAM access, for applications with good locality of memory access operations, the OpenPage strategy is adopted. If the row corresponding to the current memory access operation has been activated, the memory access delay is only the delay from the read command to the data transmission. Compared with the Close Page strategy, the delay caused by row activation is saved, which can greatly reduce the memory access delay. That is, for applications with good locality of memory access operations, the Open Page strategy makes good use of the locality of accessing the same row, and the memory access efficiency is better than the Close Page strategy. In addition, the Close Page strategy requires a precharge operation after the memory access operation. If the memory controller has unprocessed requests, precharge will affect the processing of subsequent read requests. Therefore, for the situation where the processor supports multiple access requests to be issued at the same time and the application is memory-intensive, the Open Page strategy is better than the ClosePage strategy. However, for applications with poor spatial locality of memory access operations, the Close Page strategy performs a precharge operation after each memory access operation, so the memory access delay consists of row activation and read command delay. For the OpenPage strategy, due to the existence of Page conflicts at the beginning of each memory access operation, the memory access delay consists of precharge, row activation and read command delay. That is, for applications with a high probability of page conflicts, the Close Page mode can reduce the precharge delay caused by row address conflicts in memory access delay. Therefore, for applications with poor locality of memory access operations, the memory access efficiency of the Close Page strategy is better than that of the Open Page strategy.

[0056] The method of the above embodiment, when the row address of the storage body to be accessed is the same as the historical access row address of the storage body, determines that the memory page scheduling policy corresponding to the storage body is the page open policy, which can effectively save the delay (tRCD) of row activation; when the row address of the storage body to be accessed is different from the historical access row address of the storage body, determines that the memory page scheduling policy corresponding to the storage body is the page close policy, which can avoid the introduction of additional delay (tRP). That is, the memory page scheduling policy is selected according to the request to be issued by the processor, so that the processor and memory work together, and the accurate determination of the page scheduling policy in different scenarios is realized.

[0057] In one embodiment, before comparing the row address of the memory bank to be accessed in the target queue with the historical access row address of the memory bank, the method further includes:

[0058] In the case that multiple queues all include the row address of the storage body to be accessed, a target queue is determined from the multiple queues according to the priorities of the multiple queues; the target queue is the queue with the highest priority among the multiple queues.

[0059] Specifically, when there are access requests in multiple queues, in an embodiment of the present application, the queue with the highest priority is determined from the multiple queues as the target queue, and then the access requests in the target queue can be sent to the memory controller for processing in priority, thereby realizing batch processing of access requests in multiple queues.

[0060] In one embodiment, when the multiple queues include at least two of a memory access invalidation queue, a pre-fetch queue, and a write-back queue, the priorities of the multiple queues include:

[0061] The priority of the memory access invalidation queue is higher than the priority of the write-back queue;

[0062] The write-back queue has a higher priority than the prefetch queue.

[0063] Specifically, in the embodiment of the present application, when multiple queues include a memory access invalidation queue, a pre-fetch queue, and a write-back queue, since the memory access invalidation queue and the write-back queue contain requests that are determined to be issued, and the pre-fetch queue contains requests that are guessed to be issued, in the embodiment of the present application, the access requests in the memory access invalidation queue and the write-back queue are preferentially sent to the memory controller for processing. Optionally, the request in the memory access invalidation queue is a read request, and the instructions in the processor need to wait for the result of the read request to be returned before being executed, while the request in the write-back queue is a write request, which only needs to be written back to the memory, so in the embodiment of the present application, the access request in the memory access invalidation queue is preferentially sent to the memory controller for processing, and then the access request in the write-back queue is sent to the memory controller for processing.

[0064] The method of the above embodiment sets the priorities of deterministic requests and predictive requests, as well as read requests and write requests, so that the method of combining processor requests with memory page scheduling strategies can play a better role, reduce memory access latency, and improve the overall performance of the processor.

[0065] In one embodiment, after determining the memory page scheduling policy corresponding to the storage body, the method further includes:

[0066] The row addresses of multiple storage bodies to be accessed and the memory page scheduling policies corresponding to the multiple storage bodies are sent to the memory controller; the memory controller is used to determine whether to preferentially send the row addresses of each storage body to be accessed to the memory device based on the memory page scheduling policies corresponding to each storage body.

[0067] Specifically, after the row addresses of multiple storage bodies to be accessed and the memory page scheduling policies corresponding to the multiple storage bodies are sent to the memory controller, the memory controller can control each storage body to process the access request based on the guidance information of the memory page scheduling policy based on the received memory page scheduling policies corresponding to each storage body. Optionally, when it is determined that the page scheduling policy of the storage body is a page open policy, the corresponding access request is sent first for processing.

[0068] For example, in the embodiment of the present application, each queue of the processor no longer selects an item to access the memory according to a random strategy, but instead gives priority to sending an access request to the item with the same row address as the last memory access of the corresponding storage body in the access history table of the storage body. Multiple access requests in the memory controller are also selected according to the principle of page hit priority, and access requests are sent to the DRAM memory device. When the processor sends a request to the memory controller, it schedules it in combination with the page information of the request that has been issued.

[0069] In the method of the above embodiment, the processor sends the row addresses of multiple storage bodies to be accessed and the memory page scheduling policies corresponding to the multiple storage bodies to the memory controller, and then the memory controller can control each storage body to process the access request based on the guidance information of the memory page scheduling policy based on the received memory page scheduling policy corresponding to each storage body, thereby realizing efficient processing of access requests.

[0070] In one embodiment, the method for determining the page scheduling strategy further includes:

[0071] Maintain an access history table corresponding to each storage body in the memory device; the access history table is used to record the row address corresponding to the last access to each storage body before the current moment.

[0072] Specifically, in an embodiment of the present application, the processor can maintain an access history table for each storage body, and record the row address of the last memory access by each storage body, so that the row address of the storage body to be accessed in the target queue and the row address of the last memory access by the storage body in the access history table can be compared, the comparison result can be obtained and the memory page scheduling policy corresponding to the storage body can be determined, thereby realizing accurate determination of the page scheduling policy.

[0073] For example, Figure 5 The processor maintains an access history table for each storage body, and records the row address of the last memory access of each storage body. The address of the memory item to be accessed in the memory access failure queue, pre-fetch queue, and write-back queue is compared with the storage body address and row address in the storage body access history table. If there is no page hit in the corresponding storage body and there is a page conflict, the corresponding storage body with the page conflict is guided to adopt the page closing mode. The processor guides the memory page scheduling strategy through the real access request to be issued in the future. Optionally, when the processor sends a request to the memory controller, it gives priority to each queue item with the same row address as the last memory access of the corresponding storage body, including selecting from the memory access failure queue, pre-fetch queue, and write-back queue. When the addresses of all items in the processor's last-level cache failure queue, pre-fetch queue, and write-back queue can be issued, the priority is that the memory access failure queue is higher than the write-back queue and higher than the pre-fetch queue. Optionally, the number of access history tables of the storage body is equal to the number of storage bodies of the memory chip. In the DDR SDRAM device adopted in the embodiment of the present invention, the number of logical storage banks of each chip is set to n, and there are n storage bank access history tables from 0 to n-1, where n is a positive integer.

[0074] In the method of the above embodiment, the processor can maintain an access history table for each storage body, record the row address of the last memory access by each storage body, and thus determine the memory page scheduling policy corresponding to the storage body based on the last memory access row address of the storage body in the access history table, thereby achieving accurate determination of the page scheduling policy.

[0075] For example, Figure 6 As shown, the memory controller page scheduling strategy on the memory side is as follows:

[0076] When the memory controller determines that the corresponding storage body has unprocessed requests, the corresponding access storage body adopts the OpenPage mode and continues to process subsequent read requests. When the memory controller sends a request to the memory device, it schedules it in combination with the Page status information of the memory device and gives priority to sending requests that hit the Page. When the memory controller determines that the corresponding storage body has no unprocessed requests, it dynamically adjusts the Page mode. If the processor gives a ClosePage mode policy for a storage body with no unprocessed requests, the storage body Bank adopts the Close Page page policy for precharging. After the operation command of each storage body is completed, the specific operation of memory page scheduling is as follows: After the read or write operation command is completed, it is determined whether the currently accessed storage body given by the memory controller is determined to adopt the Close Page mode. If the currently accessed storage body Bank is determined to adopt the Close Page mode, precharging is performed. Otherwise, the currently accessed storage body Bank adopts the Open Page mode and continues to process subsequent read requests.

[0077] The memory page scheduling strategy dynamically adjusts the Page mode according to the guidance of the processor, integrating the advantages of the Open Page strategy and the Close Page strategy. The memory controller switches the Page mode when there is no unprocessed request to avoid affecting the subsequent read request processing due to precharging. Compared with the prior art, the method combining the processor request with the memory page scheduling strategy has the following advantages: it integrates the advantages of the Open Page strategy and the Close Page strategy, compares the addresses of the memory items to be accessed in the processor memory failure queue, prefetch queue, and write-back queue with the row addresses of the access history tables of each storage body Bank, generates guidance information for the memory page scheduling strategy, and schedules the requests of each queue according to the memory access requests that have been issued, and sets priorities based on deterministic requests and predicted requests, as well as read requests and write requests, so that the method combining the processor request with the memory page scheduling strategy can play a better role, reduce memory access latency, and improve the overall performance of the processor.

[0078] The following is a description of the apparatus for determining a page scheduling strategy provided by the present invention. The apparatus for determining a page scheduling strategy described below and the method for determining a page scheduling strategy described above can be referred to in correspondence with each other. Figure 7 As shown, including:

[0079] The processing module 710 is used to compare the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment;

[0080] The determination module 720 is used to determine the memory page scheduling policy corresponding to the storage body according to the comparison result.

[0081] Optionally, the determining module 720 is specifically configured to:

[0082] When the row address of the storage body to be accessed is the same as the historical access row address of the storage body, determining that the memory page scheduling policy corresponding to the storage body is a page open policy;

[0083] When the row address of the memory bank to be accessed is different from the historical access row address of the memory bank, it is determined that the memory page scheduling policy corresponding to the memory bank is a page closing policy.

[0084] Optionally, the processing module 710 is further configured to:

[0085] In the case that multiple queues all include the row address of the storage body to be accessed, a target queue is determined from the multiple queues according to the priorities of the multiple queues; the target queue is the queue with the highest priority among the multiple queues.

[0086] Optionally, the priority of the memory access invalidation queue is higher than the priority of the write-back queue;

[0087] The write-back queue has a higher priority than the prefetch queue.

[0088] Optionally, the determining module 720 is further configured to:

[0089] The row addresses of multiple storage bodies to be accessed and the memory page scheduling policies corresponding to the multiple storage bodies are sent to the memory controller; the memory controller is used to determine whether to preferentially send the row addresses of each storage body to be accessed to the memory device based on the memory page scheduling policies corresponding to each storage body.

[0090] Optionally, the processing module 710 is further configured to:

[0091] Maintain an access history table corresponding to each storage body in the memory device; the access history table is used to record the row address corresponding to the last access to each storage body before the current moment.

[0092] Figure 8An example of a physical structure diagram of an electronic device is provided, and the electronic device may include: a processor 810, a communication interface 820, a memory 830, and a communication bus 840, wherein the processor 810, the communication interface 820, and the memory 830 communicate with each other through the communication bus 840. The processor 810 may call the logic instructions in the memory 830 to execute a method for determining a page scheduling strategy, and the method includes: comparing the row address of a storage body to be accessed in a target queue with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment; and determining the memory page scheduling strategy corresponding to the storage body according to the comparison result.

[0093] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0094] On the other hand, the present invention also provides a computer program product, which includes a computer program, and the computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the page scheduling strategy determination method provided by the above methods, and the method includes: comparing the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last time the storage body was accessed before the current moment; and determining the memory page scheduling policy corresponding to the storage body based on the comparison result.

[0095] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, a method for determining a page scheduling strategy provided by the above-mentioned methods is implemented, the method comprising: comparing the row address of a storage body to be accessed in a target queue with a historically accessed row address of the storage body to obtain a comparison result; the historically accessed row address is the row address corresponding to the last time the storage body was accessed before the current moment; and determining the memory page scheduling strategy corresponding to the storage body based on the comparison result.

[0096] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0097] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for determining a page scheduling strategy, characterized in that: include: Compare the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment; Determining a memory page scheduling strategy corresponding to the storage body according to the comparison result; After determining the memory page scheduling strategy corresponding to the storage body, the method further includes: The row addresses of the multiple storage bodies to be accessed and the memory page scheduling policies corresponding to the multiple storage bodies are sent to a memory controller; the memory controller is used to determine whether to give priority to sending the row addresses of the multiple storage bodies to be accessed to the memory device based on the memory page scheduling policies corresponding to the multiple storage bodies; wherein the processor supports multiple access requests to be issued at the same time; when it is determined that the page scheduling policy of the storage body is a page open policy, the corresponding access request is sent for processing with priority.

2. The method for determining a page scheduling strategy according to claim 1, characterized in that: The row address of the storage body to be accessed in the target queue is compared with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment; Determining a memory page scheduling strategy corresponding to the storage body according to the comparison result includes: In a case where the row address of the storage body to be accessed is the same as the historical access row address of the storage body, determining that the memory page scheduling policy corresponding to the storage body is a page open policy; In a case where the row address of the storage body to be accessed is different from the historical access row address of the storage body, it is determined that the memory page scheduling policy corresponding to the storage body is a page closing policy.

3. The method for determining a page scheduling strategy according to claim 1 or 2, characterized in that: Before comparing the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body, the method further includes: In the case that multiple queues all include the row address of the storage body to be accessed, a target queue is determined from the multiple queues according to the priorities of the multiple queues; the target queue is the queue with the highest priority among the multiple queues.

4. The method for determining a page scheduling strategy according to claim 3, characterized in that: In the case where the multiple queues include a deterministic request queue and a predictive request queue, the priorities of the multiple queues include: The priority of the deterministic request queue is higher than the priority of the predictive request queue; In the case where the multiple queues include a read request queue and a write request queue, the priorities of the multiple queues include: The priority of the read request queue is higher than the priority of the write request queue.

5. The method for determining a page scheduling strategy according to claim 3, characterized in that: In the case where the multiple queues include at least two of a memory access invalidation queue, a pre-fetch queue, and a write-back queue, the priorities of the multiple queues include: The priority of the memory access invalidation queue is higher than the priority of the write-back queue; The priority of the write-back queue is higher than the priority of the pre-fetch queue.

6. The method for determining a page scheduling strategy according to claim 1, characterized in that: The method further comprises: Maintain an access history table corresponding to each storage body in the memory device; the access history table is used to record the row address corresponding to the last access to each storage body before the current moment.

7. The method for determining a page scheduling strategy according to claim 1, characterized in that: The method further comprises: When it is determined that there is no unprocessed request in the target storage body, the memory page scheduling policy corresponding to the target storage body is dynamically adjusted; the target storage body is any storage body in the memory device.

8. A device for determining a page scheduling strategy, characterized in that: include: A processing module, used for comparing the row address of the storage body to be accessed in the target queue with the historical access row address of the storage body to obtain a comparison result; the historical access row address is the row address corresponding to the last access of the storage body before the current moment; A determination module, configured to determine a memory page scheduling policy corresponding to the storage body according to the comparison result; and send the row addresses of the plurality of storage bodies to be accessed and the memory page scheduling policies corresponding to the plurality of storage bodies to a memory controller; The memory controller is used to determine whether to give priority to sending the row address of each storage body to be accessed to the memory device based on the memory page scheduling policy corresponding to each storage body; wherein the processor supports multiple access requests to be issued simultaneously; when it is determined that the page scheduling policy of the storage body is a page open policy, the corresponding access request is sent for processing with priority.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method for determining the page scheduling strategy according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for determining a page scheduling strategy according to any one of claims 1 to 7 is implemented.

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