Memory, read-write method thereof and electronic equipment
By introducing selection circuits and multiple selection lines into each memory array layer, the problem of difficulty in efficiently selecting memory device word lines in the prior art is solved, more efficient read and write operations are achieved, and the performance of memory devices is improved.
Patent Information
- Application Number
- CN202311010849.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-10
- Publication Date
- 2025-02-18
AI Technical Summary
During read and write operations, it is difficult for existing three-dimensional memory devices to efficiently select word lines parallel to the substrate direction that need to be selected, affecting the performance of the memory device.
A memory is designed, wherein each memory array layer includes a selection circuit, a first selection line, a second selection line, a third selection line and a low level potential terminal, through which the first selection line and a second selection line are based on the first selection line and the second selection line. The level state of the selected memory array layer is determined, and the selected word line during the read and write operation is determined based on the level state of the third selection line.
It realizes the precise selection of word lines to be selected during read and write operations, improving the performance and efficiency of memory devices.
Smart Images
Figure CN119479721A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and more specifically, to a memory and a reading and writing method thereof, and an electronic device. Background Art
[0002] Memory is the main medium for data storage. Common memory devices are mostly two-dimensional (2D) memory devices with planar structures. As the demand for integration and storage capacity of various electronic devices continues to increase, three-dimensional (3D) memory devices have emerged.
[0003] Three-dimensional storage devices can realize the storage and transmission of data in three-dimensional space, which can greatly improve the storage capacity of storage devices, reduce storage costs, improve the integration and storage density of storage devices, and help to achieve the miniaturization of storage devices. Summary of the invention
[0004] The embodiment of the present application provides a memory and a read / write method thereof, and an electronic device, and provides a method for selecting a horizontal word line during a read / write operation. In order to achieve the above-mentioned purpose, the technical solution provided by the embodiment of the present application is as follows:
[0005] In a first aspect, an embodiment of the present application provides a memory, including:
[0006] substrate;
[0007] A three-dimensional memory array, located on one side of the substrate, comprising a plurality of memory array layers stacked in a direction perpendicular to the substrate, wherein the memory array layers comprise memory cells arranged in a two-dimensional array, a plurality of bit lines perpendicular to the substrate, and a plurality of word lines parallel to the substrate, wherein in each memory array layer, a row of memory cells is connected to one word line;
[0008] Each storage array layer further includes: a selection circuit, a first selection line, a second selection line, a plurality of third selection lines and a plurality of low-level potential terminals;
[0009] The first selection line and the second selection line are parallel to the substrate, and the third selection line is perpendicular to the substrate and is arranged in one-to-one correspondence with the word lines;
[0010] The selection circuits are respectively connected to the plurality of word lines, the first selection line, the second selection line, the plurality of third selection lines and the plurality of low-level potential ends. The plurality of selection circuits are used to determine the selected storage array layer based on the level states of the first selection line and the second selection line of the corresponding storage array layer, and to determine the selected word line during read and write operations based on the level state of the third selection line of the selected storage array layer.
[0011] Optionally, the plurality of low-level potential ends are a plurality of power lines perpendicular to the substrate;
[0012] In each of the storage array layers, the power lines are arranged in one-to-one correspondence with the word lines;
[0013] A plurality of word lines stacked and arranged along a direction perpendicular to the substrate correspond to one power line.
[0014] Optionally, the low-level potential ends included in all the storage array layers are conductive walls;
[0015] Along a direction perpendicular to the substrate, all the memory array layers share the conductive wall.
[0016] Optionally, the selection circuit includes a first sub-selection circuit and a second sub-selection circuit;
[0017] The first sub-selection circuit is respectively connected to a plurality of the word lines, the first selection line and the third selection line of the same storage array layer, and the first sub-selection circuit of each layer is used to determine the storage array layer to which the word line is connected with the third selection line based on the level state of the first selection line of the corresponding storage array layer, and to determine the selected word line based on the level state of the third selection line of the storage array layer to which the word line is connected with the third selection line;
[0018] The second sub-selection circuit is respectively connected to a plurality of the word lines, the second selection line and the low level potential end of the same storage array layer, and the second sub-selection circuit of each layer is used to determine the storage array layer to which the word line is connected to the low level potential end based on the level state of the second selection line of the corresponding storage array layer; wherein:
[0019] The memory array layer in which the word line is connected to the third selection line is a selected memory array layer, and the memory array layer in which the word line is connected to the low level potential end is an unselected memory array layer.
[0020] Optionally, the first sub-selection circuit is located on one side of the word line, and the second sub-selection circuit is located on the same side of the word line;
[0021] Alternatively, the first sub-selection circuit is located at a first side of the word line, the second sub-selection circuit is located at a second side of the word line, and the first side and the second side are arranged opposite to each other.
[0022] Optionally, the first sub-selection circuit includes a plurality of first transistors, and the first transistors are arranged in a one-to-one correspondence with the word lines;
[0023] A gate of the first transistor is connected to the first selection line, a first electrode of the first transistor is connected to the word line, and a second electrode of the first transistor is connected to the third selection line.
[0024] Optionally, the second sub-selection circuit includes a plurality of second transistors, and the second transistors are arranged in a one-to-one correspondence with the word lines;
[0025] A gate of the second transistor is connected to the second selection line, a first electrode of the second transistor is connected to the word line, and a second electrode of the second transistor is connected to the low level potential terminal.
[0026] Optionally, the first transistor is an N-type transistor, the second transistor is an N-type transistor, and a level state of the first selection line is opposite to a level state of the second selection line;
[0027] Alternatively, the first transistor is a P-type transistor, the second transistor is a P-type transistor, and the level state of the first selection line is opposite to the level state of the second selection line;
[0028] Alternatively, the first transistor is an N-type transistor, the second transistor is a P-type transistor, and the level state of the first selection line is the same as the level state of the second selection line;
[0029] Alternatively, the first transistor is a P-type transistor, the second transistor is an N-type transistor, and a level state of the first selection line is the same as a level state of the second selection line.
[0030] Optionally, the storage unit includes a transistor and a capacitor;
[0031] The gate of the transistor is connected to the word line, the first electrode of the transistor is connected to the bit line, the second electrode of the transistor is connected to one end of the capacitor, and the other end of the capacitor is grounded;
[0032] The memory includes at least one of the following:
[0033] The memory cells located in the same column along the extending direction of the bit line share one bit line;
[0034] A plurality of the word lines stacked and arranged in a direction perpendicular to the substrate correspond to one third selection line;
[0035] For each layer of the storage array, the first electrodes of the transistors are connected to the bit lines in a one-to-one correspondence; or, the first electrodes of two adjacent transistors in a direction perpendicular to the word line are connected to the same bit line.
[0036] Optionally, the memory includes a read / write circuit, a number of bit line selection units, and a number of control lines;
[0037] The bit lines are connected to the bit line selection units in a one-to-one correspondence, and the control lines are connected to the bit line selection units in a one-to-one correspondence;
[0038] The bit line selection unit is used to select the bit line based on the control of the control line, so as to connect the selected bit line to the read / write circuit.
[0039] Optionally, the memory includes a plurality of first connection lines and / or a plurality of second connection lines;
[0040] Each of the first selection lines is connected to a peripheral circuit via one of the first connection lines, the first connection lines are perpendicular to the substrate, and a plurality of the first connection lines are arranged in a staircase manner along a direction perpendicular to the substrate;
[0041] Each of the second selection lines is connected to the peripheral circuit via a second connection line. The second connection line is perpendicular to the substrate, and a plurality of the second connection lines are arranged in a staircase manner along a direction perpendicular to the substrate.
[0042] In a second aspect, an embodiment of the present application provides an electronic device, comprising a memory as described in any one of the first aspects.
[0043] In a third aspect, an embodiment of the present application provides a method for reading and writing a memory, comprising:
[0044] Writing operation stage: applying a first electrical signal to a first selection line corresponding to the storage array layer to which data is to be written, and applying a second electrical signal to a second selection line corresponding to the storage array layer to which data is to be written, so that the word line of the storage array layer to which data is to be written is connected to the third selection line in a one-to-one correspondence, so as to select the storage array layer to which data is to be written;
[0045] Based on the selected storage array layer to which data is to be written, applying a third electrical signal to a third selection line corresponding to a word line connected to a storage cell row to which data is to be written, so that the storage cell row connected to the word line is turned on, so as to select the storage cell row to which data is to be written;
[0046] Based on the selected memory cell row into which data is to be written, data of the bit lines connected to the memory cells in the memory cell row are written into the memory cells.
[0047] Optionally, the write operation stage also includes: applying a second electrical signal to a first selection line corresponding to a storage array layer that does not require data to be written, and applying a first electrical signal to a second selection line that does not require data to be written, so that the word line of the storage array layer that does not require data to be written is connected to the low-level potential end.
[0048] The technical solution provided in the embodiments of the present application has at least the following beneficial effects:
[0049] In the memory provided by the embodiment of the present application, since each storage array layer includes a selection circuit, a first selection line, a second selection line, a third selection line and a low-level potential end, the selection circuit is respectively connected to the word line, the first selection line, the second selection line, the third selection line and the low-level potential end, and the multiple selection circuits are used to determine the selected storage array layer based on the level state of the first selection line and the second selection line of the corresponding storage array layer, and determine the word line selected during the read and write operations based on the level state of the third selection line of the selected storage array layer; therefore, the embodiment of the present application can provide a method for selecting the word line parallel to the substrate direction that needs to be selected during the read and write operations by designing a new peripheral circuit.
[0050] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0052] Figure 1 A schematic diagram of the structure of a k-th storage array layer included in a memory provided in an embodiment of the present application;
[0053] Figure 2 A schematic diagram of a specific structure of a k-th storage array layer included in a memory provided in an embodiment of the present application;
[0054] Figure 3 A schematic diagram of the structure of a transistor included in the memory provided in an embodiment of the present application;
[0055] Figure 4 A schematic diagram of the three-dimensional structure of a memory provided in an embodiment of the present application;
[0056] Figure 5 A flow chart of a method for reading and writing a memory provided in an embodiment of the present application.
[0057] Reference numerals:
[0058] 11-storage array layer; 12-storage unit; 13-selection circuit; 131-first sub-selection circuit; 132-second sub-selection circuit;
[0059] 14-source electrode; 15-drain electrode; 16-semiconductor layer; 17-gate insulating layer; 18-gate electrode. DETAILED DESCRIPTION
[0060] The present application is described in detail below, and examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. In addition, if the detailed description of the known technology is unnecessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.
[0061] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with those in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.
[0062] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.
[0063] With the development of DRAM (Dynamic Random Access Memory) technology, the planar 1T1C (one transistor and one capacitor) memory structure has reached its limit. The current development of 2D memory devices is limited in terms of obtaining higher capacitance, lower leakage, and higher integration.
[0064] For DRAM, by arranging the memory array transistors in 3D instead of 2D, the transistors in the integrated circuit (IC) can be placed close to each other and can be stacked in multiple layers, saving area in the plane. There are currently a variety of 3D-DRAM technologies, and most 3D memory structures are 2D memory cells placed horizontally and then stacked in multiple layers.
[0065] Among the current word line design methods of 3D memory structures, some designs adopt vertical word line design, and some designs adopt horizontal word line design. The horizontal word line design method has the advantage of low bit line parasitic capacitance and can provide a more economical design.
[0066] The memory in the embodiment of the present application is a 3D memory including 1T1C. The word lines included in the 3D memory are designed in a horizontal word line (that is, the extension direction of the word line is parallel to the substrate). The present application designs a new peripheral circuit of the memory, which can accurately select the word line to be selected during the read and write operations, thereby improving the performance of the memory.
[0067] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.
[0068] An embodiment of the present application provides a memory, including: a substrate and a three-dimensional storage array located on one side of the substrate, the three-dimensional storage array includes a plurality of storage array layers stacked in a direction perpendicular to the substrate, and the substrate may be a semiconductor substrate such as a silicon substrate.
[0069] like Figure 1 As shown, Figure 1 Only one storage array layer 11 (eg, the kth storage array layer) located on one side of the substrate is shown. The storage array layer 11 includes a plurality of storage cells 12 arranged in an array, a plurality of word lines parallel to the substrate (eg, Figure 1 WL-k,1, WL-k,2, WL-k,3), several bit lines perpendicular to the substrate (such as Figure 1 BL_1,1, BL_1,2, BL_1,M-1, BL_1,M, etc.), a selection circuit 13, a first selection line WL_layer_k, a second selection line WL_N_layer_k, a plurality of third selection lines (such as Figure 1 WL-row1, WL-row2, WL-row3) and several low-level potential terminals (positions such as Figure 1a plurality of V_low positions in the memory array); a row of memory cells 12 is connected to a word line, and for each memory array layer, a selection circuit 13, a first selection line WL_layer_k, a second selection line WL_N_layer_k and a plurality of low-level potential ends correspond to all memory cells, the first selection line WL_layer_k and the second selection line WL_N_layer_k are parallel to the substrate, the third selection line is perpendicular to the substrate, and are arranged one-to-one with the word lines; the selection circuit 13 is respectively connected to a plurality of word lines, a first selection line WL_layer_k, a second selection line WL_N_layer_k, a plurality of third selection lines and a plurality of low-level potential ends, and a plurality of selection circuits 13 are used to determine a selected memory array layer based on the level state of the first selection line WL_layer_k and the second selection line WL_N_layer_k of the corresponding memory array layer, and to determine a word line selected during a read / write operation based on the level state of the third selection line of the selected memory array layer.
[0070] It should be noted that the substrate in the embodiment of the present application is Figure 1 The word lines extend in a first direction and a second direction, and the word lines extend parallel to the substrate. Figure 1 The third direction refers to the direction perpendicular to the paper surface, that is, the direction perpendicular to the substrate.
[0071] It should be noted that the selection circuit 13 in the embodiment of the present application may be located on one side of the word line, or on two opposite sides of the word line. Figure 1 Only the case where the selection circuits 13 are located on opposite sides of the word line is shown.
[0072] Specifically, Figure 1 As shown, a plurality of word lines extend along the second direction, a first selection line WL_layer_k and a second selection line WL_N_layer_k extend along the first direction, and a third selection line extends along the third direction; each low-level potential end can be connected to a signal line, and these signal lines can extend along the third direction, and each signal line is connected to a low-level potential, for example, each signal line is grounded. Of course, in actual design, all signal lines can be connected together first and then grounded. The low-level potential in the embodiment of the present application refers to a zero potential or a negative potential.
[0073] In the memory provided by the embodiment of the present application, since each storage array layer includes a selection circuit, a first selection line, a second selection line, a third selection line and a low-level potential end, the selection circuit is respectively connected to the word line, the first selection line, the second selection line, the third selection line and the low-level potential end, and the multiple selection circuits are used to determine the selected storage array layer based on the level state of the first selection line and the second selection line of the corresponding storage array layer, and determine the word line selected during the read and write operations based on the level state of the third selection line of the selected storage array layer; therefore, the embodiment of the present application can provide a method for selecting the word line parallel to the substrate direction that needs to be selected during the read and write operations by designing a new peripheral circuit.
[0074] In a specific embodiment, a plurality of word lines stacked in a direction perpendicular to the substrate correspond to a third selection line. The third selection line (eg Figure 1 The WL-row1, WL-row2, and WL-row3 in the memory array are perpendicular to the substrate. For a third selection line (for example, WL-row1), all memory array layers share the third selection line. The third selection line is connected to the peripheral circuit to receive a high-level signal or a low-level signal output by the peripheral circuit. The third selection line is set in a way that saves costs. Of course, in actual design, the third selection lines included in different layers of memory array layers may not be shared. This design method has more wiring and is not conducive to the integration of the device.
[0075] In an optional embodiment, several low-level potential terminals (such as Figure 1 The multiple V_low in (a) are several power lines perpendicular to the substrate, such as Figure 1 As shown, in each storage array layer, power lines and word lines are arranged one by one, and multiple word lines stacked in a direction perpendicular to the substrate correspond to one power line. The power line can be grounded or connected to a negative potential signal terminal; the arrangement of the power lines can save costs.
[0076] In another optional embodiment, the several low-level potential ends included in all the storage array layers in the embodiments of the present application are conductive walls. All storage array layers share the conductive wall in a direction perpendicular to the substrate. The conductive wall can be grounded or connected to a negative potential signal end. In actual production, this implementation only requires one conductive wall to achieve grounding of the low-level potential ends included in all storage array layers, thereby minimizing production costs.
[0077] In a specific embodiment, Figure 2 As shown, the selection circuit in the embodiment of the present application includes a first sub-selection circuit 131 and a second sub-selection circuit 132; the first sub-selection circuit 131 is respectively connected to the word line (such as Figure 2WL-k,1, WL-k,2, WL-k,3), the first selection line WL_layer_k and the third selection line (such as Figure 2 The first sub-selection circuit 131 of each layer is used to determine the storage array layer connected with the word line and the third selection line based on the level state of the first selection line WL_layer_k of the corresponding storage array layer, and the word line that is selected based on the level state of the third selection line of the storage array layer connected with the word line and the third selection line; the second sub-selection circuit 132 is respectively connected to the word line, the second selection line WL_N_layer_k and the low level potential end (such as Figure 2 The second sub-selection circuit 132 of each layer is used to determine the storage array layer where the word line is connected to the low-level potential end based on the level state of the second selection line WL_N_layer_k of the corresponding storage array layer; wherein: the storage array layer where the word line is connected to the third selection line is the selected storage array layer, and the storage array layer where the word line is connected to the low-level potential end is the unselected storage array layer.
[0078] In an optional embodiment, the first sub-selection circuit 131 and the first selection line WL_layer_k are located on one side of the word line, and the second sub-selection circuit 132 and the second selection line WL_N_layer_k are located on the same side of the word line; in another optional embodiment, the first sub-selection circuit 131 and the first selection line WL_layer_k are located on a first side of the word line, and the second sub-selection circuit 132 and the second selection line WL_N_layer_k are located on a second side of the word line, and the first side and the second side are arranged opposite to each other, the first sub-selection circuit 131 and the second sub-selection circuit 132 are arranged opposite to each other, and the first selection line WL_layer_k and the second selection line WL_N_layer _k are relatively arranged; since the first sub-selection circuit 131, the second sub-selection circuit 132, the first selection line WL_layer_k and the second selection line WL_N_layer_k are all located at the edge of the storage array layer, the design of the first sub-selection circuit 131, the second sub-selection circuit 132, the first selection line WL_layer_k and the second selection line WL_N_layer_k will not affect the overall design of the memory, and since the first sub-selection circuit 131 and the second sub-selection circuit 132 are relatively arranged, the first selection line WL_layer_k and the second selection line WL_N_layer_k are relatively arranged, which can make the wiring of the peripheral circuits of the memory more uniform.
[0079] In a specific embodiment, Figure 2As shown, the first sub-selection circuit 131 includes a plurality of first transistors T1, and the first transistors T1 are arranged in a one-to-one correspondence with the word lines; the gate of the first transistor T1 is connected to the first selection line WL_layer_k, the first electrode of the first transistor T1 is connected to the word line (such as the first electrode of the first first transistor T1 is connected to one end of the word line WL-k,1, the first electrode of the second first transistor T1 is connected to one end of the word line WL-k,2, and the first electrode of the third first transistor T1 is connected to one end of the word line WL-k,3), and the second electrode of the first transistor is connected to the third selection line (such as the second electrode of the first first transistor T1 is connected to the third selection line WL-row1, the second electrode of the second first transistor T1 is connected to the third selection line WL-row2, and the second electrode of the third first transistor T1 is connected to the third selection line WL-row3).
[0080] In a specific embodiment, Figure 2 As shown, the second sub-selection circuit 132 includes a plurality of second transistors T2, and the second transistors T2 are arranged in a one-to-one correspondence with the word lines; the gate of the second transistor T2 is connected to the second selection line WL_N_layer_k, the first electrode of the second transistor T2 is connected to the word line (for example, the first electrode of the first second transistor T2 is connected to the other end of the word line WL-k,1, the first electrode of the second second transistor T2 is connected to the other end of the word line WL-k,2, and the first electrode of the third second transistor T2 is connected to the other end of the word line WL-k,3), and the second electrode of the second transistor T2 is connected to the low level potential end (for example, Figure 2 V_low) connection in .
[0081] In an optional embodiment, the first transistor T1 and the second transistor T2 are of the same type. In another optional embodiment, the first transistor T1 and the second transistor T2 are of different types. Since the manufacturing cost is high and the yield is easily reduced when the first transistor T1 and the second transistor T2 are of different types, this is not a preferred design method in actual design, but only a design method that can be implemented.
[0082] In a specific embodiment, the first transistor T1 is an N-type transistor, and the second transistor T2 is an N-type transistor; or, the first transistor T1 is a P-type transistor, and the second transistor T2 is a P-type transistor; the level state of the first selection line WL_layer_k is opposite to the level state of the second selection line WL_N_layer_k; that is, in the embodiment of the present application, if the first transistor T1 and the second transistor T2 are of the same type, the level state of the first selection line WL_layer_k is opposite to the level state of the second selection line WL_N_layer_k.
[0083] Specifically, in the embodiment of the present application, for the storage array layer of the same layer, the level state of the first selection line WL_layer_k and the level state of the second selection line WL_N_layer_k are opposite at any time. For example, if the level state of the first selection line WL_layer_k is a high level (that is, the logic level is 1), then the level state of the second selection line WL_N_layer_k is a low level (that is, the logic level is 0); the level state of the third selection line in the embodiment of the present application can be a high level or a low level, and the level state of the low level potential end is always a low level.
[0084] In another specific embodiment, the first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor; or, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor; the level state of the first selection line WL_layer_k is the same as the level state of the second selection line WL_N_layer_k; that is, in the embodiment of the present application, if the types of the first transistor T1 and the second transistor T2 are different, the level state of the first selection line WL_layer_k is the same as the level state of the second selection line WL_N_layer_k.
[0085] Specifically, in the embodiment of the present application, for the storage array layer of the same layer, the level state of the first selection line WL_layer_k and the level state of the second selection line WL_N_layer_k are the same at any time. For example, if the level state of the first selection line WL_layer_k is a high level (that is, the logic level is 1), then the level state of the second selection line WL_N_layer_k is also a high level; if the level state of the first selection line WL_layer_k is a low level (that is, the logic level is 0), then the level state of the second selection line WL_N_layer_k is also a low level.
[0086] like Figure 2 As shown, the embodiment of the present application is described by taking the first transistor T1 and the second transistor T2 as the same type, and the first transistor T1 is an N-type transistor, and the second transistor T2 is an N-type transistor as an example.
[0087] In the embodiment of the present application, the first selection line WL_layer_k and the second selection line WL_N_layer_k serve as storage array layer selection lines, that is, which storage array layer is selected is determined by the level state of the first selection line WL_layer_k and the level state of the second selection line WL_N_layer_k; specifically, if the k-th storage array layer needs to be selected, the level state of the first selection line WL_layer_k included in the k-th storage array layer is a high level (that is, the peripheral circuit outputs a high level signal for the first selection line WL_layer_k), and the level state of the second selection line WL_N_layer_k included in the k-th storage array layer is a low level (that is, the peripheral circuit outputs a low level signal for the second selection line WL_N_layer_k); for all storage array layers that do not need to be selected, the level state of the first selection line WL_layer_k included in each storage array layer is a low level, and the level state of the second selection line WL_N_layer_k included in each storage array layer is a high level.
[0088] like Figure 2 As shown, the storage unit in the embodiment of the present application includes a transistor T and a capacitor C, wherein the transistor T and the capacitor C can be designed in a horizontal two-dimensional arrangement; the gate of the transistor T is connected to the word line, the first electrode of the transistor T is connected to the bit line, the second electrode of the transistor T is connected to one end of the capacitor C, and the other end of the capacitor C is grounded. The transistor T in the embodiment of the present application is an N-type transistor. Of course, in actual design, the transistor T can also be a P-type transistor.
[0089] It should be noted that the first pole of the transistor (transistor T, first transistor T1 and second transistor T2) in the embodiment of the present application refers to the source of the transistor, and the second pole of the transistor refers to the drain of the transistor, or the first pole of the transistor refers to the drain of the transistor, and the second pole of the transistor refers to the source of the transistor. The first pole and the second pole of the transistor can be interchangeable and are not limited here.
[0090] In a specific embodiment, the channels of the transistor T, the first transistor T1 and the second transistor T2 in the embodiment of the present application are all horizontal channels. Figure 3 As shown, the transistor T includes a source 14, a drain 15, a semiconductor layer 16, a gate insulating layer 17 and a gate 18, wherein the semiconductor layer 16 is arranged around the gate 18. The first transistor T1 and the second transistor T2 may also adopt Figure 3Specifically, the semiconductor layer is preferably a metal oxide semiconductor, such as IGZO (Indium Gallium Zinc Oxide). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory.
[0091] It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO and other materials, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.
[0092] like Figure 2 As shown, in the embodiment of the present application, a plurality of word lines stacked and arranged in a direction perpendicular to the substrate correspond to a third selection line, and the third selection line serves as a word line selection line, that is, which word line in the selected storage array layer is selected is determined by the level state of the third selection line; specifically, if the k-th storage array layer is selected, the plurality of third selection lines of the k-th storage array layer are connected to the plurality of word lines in a one-to-one correspondence, when the level state of the third selection line is a high level, the word line connected to the third selection line with a high level is selected, and when the level state of the third selection line is a low level, the word line connected to the third selection line with a low level is not selected, for example: if the word line WL-k,1 needs to be selected, the third selection line connected to the word line WL-k,1 is connected The level state of the line WL-row1 is high (that is, the peripheral circuit outputs a high-level signal for the third selection line WL-row1), and the level state of the third selection line connected to other word lines is low (that is, the peripheral circuit outputs a low-level signal for the third selection line connected to other word lines). The transistor T connected to the word line WL-k,1 is turned on, and the data of the bit lines BL_1,1, BL_1,2, BL_1,M-1, BL_1,M can be written into the capacitor C, or the data stored in the capacitor C can be read through the bit lines BL_1,1, BL_1,2, BL_1,M-1, BL_1,M. Similarly, when other word lines are selected, the data writing and data reading of the storage cells of the corresponding rows can be realized.
[0093] Specifically, Figure 2As shown, the memory cells located in the same column along the extension direction of the bit line share a bit line, that is, for a bit line (for example, bit line BL_1,1), all memory array layers stacked along the extension direction of the bit line share the bit line; for each memory array layer, the first electrode of the transistor T included in the memory cell is connected to the bit line in a one-to-one correspondence. This design is simple and easy to manufacture.
[0094] In an optional embodiment, for each memory array layer, two transistors T (eg, Figure 2 The first electrodes of two adjacent transistors located in the first column are connected to the same bit line. This design method can save the number of bit lines, reduce the size of the memory, and thus improve the integration of the device.
[0095] like Figure 2 As shown, the memory in the embodiment of the present application includes a read-write circuit, a plurality of bit line selection units and a plurality of control lines, the bit lines are connected to the bit line selection units in a one-to-one correspondence, and the control lines are connected to the bit line selection units in a one-to-one correspondence; the bit line selection units are used to select the bit lines based on the control of the control lines to connect the selected bit lines to the read-write circuit; specifically, the bit line selection units are located at the bottom or top of the three-dimensional storage array, and the bit line selection units form an array, and a row of bit line selection units corresponding to the word lines are opened through the control of the control lines, and this row of storage cells is connected to a row of read-write circuits. Specifically, when writing data, the read-write circuit transmits the data to the row of storage cells through the bit lines, and when reading data, the reading circuit can receive the data transmitted by the row of storage cells through the bit lines to complete the reading of the row of storage cells.
[0096] In a specific embodiment, the memory also includes a plurality of first connection lines and / or a plurality of second connection lines; each first selection line is connected to the peripheral circuit through a first connection line, the first connection line is perpendicular to the substrate, and the plurality of first connection lines are arranged in a step-by-step manner along a direction perpendicular to the substrate; each second selection line is connected to the peripheral circuit through a second connection line, the second connection line is perpendicular to the substrate, and the plurality of second connection lines are arranged in a step-by-step manner along a direction perpendicular to the substrate; through this arrangement, the first selection lines included in different layers of the storage array layers can be connected to the peripheral circuit within the minimum wiring space to receive the electrical signal output by the peripheral circuit; and the second selection lines included in different layers of the storage array layers can be connected to the peripheral circuit to receive the electrical signal output by the peripheral circuit to complete the control of the selection circuit.
[0097] Specifically, Figure 4 As shown, the figure only shows the arrangement of the first selection line and the first connection line, and the arrangement of the second selection line and the second connection line is similar, which will not be repeated here; Figure 4The figure shows three first selection lines included in three adjacent storage array layers. Each first selection line is connected to the peripheral circuit through a corresponding first connection line. The top ends of the plurality of first connection lines are flush, and the bottom ends are respectively located in different storage array layers. Since different storage array layers are stacked, the bottom ends of the first connection lines are located in different planes, thereby making the first connection lines arranged in a stepped manner. During specific production, this can be achieved by setting stepped through holes.
[0098] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including a memory provided in any of the above embodiments.
[0099] The electronic device includes the above-mentioned memory, so the electronic device has the same beneficial effects as the above-mentioned memory, which will not be repeated here.
[0100] Specifically, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.
[0101] Based on the same inventive concept, the present application embodiment provides a method for reading and writing the above-mentioned memory, such as Figure 5 As shown, the write operation phase of the memory includes:
[0102] S101, applying a first electrical signal to a first selection line corresponding to a storage array layer to be written with data, and applying a second electrical signal to a second selection line corresponding to a storage array layer to be written with data, so that a word line of the storage array layer to be written with data is connected to a third selection line in a one-to-one correspondence, so as to select the storage array layer to be written with data;
[0103] S102, based on the selected storage array layer to which data is to be written, applying a third electrical signal to a third selection line corresponding to a word line connected to a storage cell row to which data is to be written, so that transistors included in the storage cell row connected to the word line are turned on, so as to select the storage cell row to which data is to be written;
[0104] S103 . Based on the selected memory cell row into which data is to be written, write data of the bit lines connected to the memory cells in the memory cell row into the memory cells.
[0105] Specifically, the storage array layer included in the memory is arranged in a manner such that Figure 2Taking an example for explanation, in the write operation stage, a high level signal is applied to the first selection line WL_layer_k corresponding to the storage array layer to which data is to be written, and a low level signal is applied to the second selection line WL_N_layer_k, the first transistor T1 is turned on, the second transistor T2 is turned off, and each word line is connected to a third selection line in a one-to-one correspondence; then, a high level signal is applied to the third selection line connected to the word line to which data is to be written, for example, the word line to be written is WL-K,1, then after the word line WL-K,1 receives the high level signal, the transistor T of the first row is controlled to be turned on, so that the data of the bit line connected to the transistor T of the first row can be written; in addition, a low level signal is applied to other third selection lines (that is, the third selection lines connected to the word lines that do not need to be written), so that the other transistors included in the storage unit are all in the off state, and at this time, even if there is data on the bit line, it cannot be written into the storage unit.
[0106] In an optional embodiment, if the storage unit in the embodiment of the present application includes a transistor and a capacitor, the memory applies a high-level signal to the first selection line WL_layer_k corresponding to the storage array layer of the data to be read, and applies a low-level signal to the second selection line WL_N_layer_k in the reading operation stage, the first transistor T1 is turned on, the second transistor T2 is turned off, and each word line is connected to a third selection line one-to-one; then, a high-level signal is applied to the third selection line connected to the word line of the data to be read, for example, the word line of the data to be read is WL-K,1, then after the word line WL-K,1 receives the high-level signal, the transistor T of the first row is controlled to be turned on, so that the data stored in the first row of storage cells can be transferred to the corresponding bit line, and the stored data is read through the read-write circuit connected to the bit line; in addition, a low-level signal is applied to other third selection lines (i.e., the third selection lines connected to the word lines that do not need to be read), so that the other transistors included in the storage unit are all in the off state. In addition, the read operation phase also includes: applying a low level signal to a first selection line WL_layer_k corresponding to a storage array layer that does not need to read data, and applying a high level signal to a second selection line WL_N_layer_k that does not need to read data.
[0107] In a specific embodiment, the write operation stage also includes: applying a second electrical signal to a first selection line corresponding to a storage array layer that does not require data to be written, and applying a first electrical signal to a second selection line that does not require data to be written, so that the word line of the storage array layer that does not require data to be written is connected to the low-level potential end.
[0108] Specifically, the storage array layer included in the memory is arranged in a manner such that Figure 2Taking this as an example, in the write operation phase, a low level signal is applied to the first selection line WL_layer_k corresponding to the storage array layer that does not need to write data, and a high level signal is applied to the second selection line WL_N_layer_k that does not need to write data.
[0109] In summary, by applying the embodiments of the present application, at least the following beneficial effects can be achieved:
[0110] In the memory provided by the embodiment of the present application, since each storage array layer includes a selection circuit, a first selection line, a second selection line, a third selection line and a low-level potential end, the selection circuit is respectively connected to the word line, the first selection line, the second selection line, the third selection line and the low-level potential end, and the multiple selection circuits are used to determine the selected storage array layer based on the level state of the first selection line and the second selection line of the corresponding storage array layer, and determine the word line selected during the read and write operations based on the level state of the third selection line of the selected storage array layer; therefore, the embodiment of the present application can provide a method for selecting the word line parallel to the substrate direction that needs to be selected during the read and write operations by designing a new peripheral circuit.
[0111] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
[0112] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.
[0113] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0114] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.
Claims
1. A memory, comprising: substrate; A three-dimensional memory array, located on one side of the substrate, comprising a plurality of memory array layers stacked in a direction perpendicular to the substrate, wherein the memory array layers comprise memory cells arranged in a two-dimensional array, a plurality of bit lines perpendicular to the substrate, and a plurality of word lines parallel to the substrate, wherein in each memory array layer, a row of memory cells is connected to one word line; It is characterized in that each storage array layer further comprises: a selection circuit, a first selection line, a second selection line, a plurality of third selection lines and a plurality of low-level potential terminals; The first selection line and the second selection line are parallel to the substrate, and the third selection line is perpendicular to the substrate and is arranged in one-to-one correspondence with the word lines; The selection circuits are respectively connected to the plurality of word lines, the first selection line, the second selection line, the plurality of third selection lines and the plurality of low-level potential ends. The plurality of selection circuits are used to determine the selected storage array layer based on the level states of the first selection line and the second selection line of the corresponding storage array layer, and to determine the selected word line during read and write operations based on the level state of the third selection line of the selected storage array layer.
2. The memory according to claim 1, characterized in that: The plurality of low-level potential ends are a plurality of power lines perpendicular to the substrate; In each of the storage array layers, the power lines and the word lines are arranged in one-to-one correspondence; A plurality of word lines stacked and arranged along a direction perpendicular to the substrate correspond to one power line.
3. The memory according to claim 1, characterized in that: All of the storage array layers include a plurality of low-level potential ends that are conductive walls; Along a direction perpendicular to the substrate, all the memory array layers share the conductive wall.
4. The memory according to any one of claims 1 to 3, characterized in that: The selection circuit includes a first sub-selection circuit and a second sub-selection circuit; The first sub-selection circuit is respectively connected to a plurality of the word lines, the first selection line and the third selection line of the same storage array layer, and the first sub-selection circuit of each layer is used to determine the storage array layer to which the word line is connected with the third selection line based on the level state of the first selection line of the corresponding storage array layer, and to determine the selected word line based on the level state of the third selection line of the storage array layer to which the word line is connected with the third selection line; The second sub-selection circuit is respectively connected to a plurality of the word lines, the second selection line and the low level potential end of the same storage array layer, and the second sub-selection circuit of each layer is used to determine the storage array layer to which the word line is connected to the low level potential end based on the level state of the second selection line of the corresponding storage array layer; wherein: The memory array layer in which the word line is connected to the third selection line is a selected memory array layer, and the memory array layer in which the word line is connected to the low level potential end is an unselected memory array layer.
5. The memory according to claim 4, characterized in that: The first sub-selection circuit is located on one side of the word line, and the second sub-selection circuit is located on the same side of the word line; Alternatively, the first sub-selection circuit is located at a first side of the word line, the second sub-selection circuit is located at a second side of the word line, and the first side and the second side are arranged opposite to each other.
6. The memory according to claim 4, characterized in that: The first sub-selection circuit includes a plurality of first transistors, and the first transistors are arranged in a one-to-one correspondence with the word lines; A gate of the first transistor is connected to the first selection line, a first electrode of the first transistor is connected to the word line, and a second electrode of the first transistor is connected to the third selection line.
7. The memory according to claim 6, characterized in that: The second sub-selection circuit includes a plurality of second transistors, and the second transistors are arranged in a one-to-one correspondence with the word lines; A gate of the second transistor is connected to the second selection line, a first electrode of the second transistor is connected to the word line, and a second electrode of the second transistor is connected to the low level potential end.
8. The memory according to claim 7, characterized in that: The first transistor is an N-type transistor, the second transistor is an N-type transistor, and a level state of the first selection line is opposite to a level state of the second selection line; Alternatively, the first transistor is a P-type transistor, the second transistor is a P-type transistor, and the level state of the first selection line is opposite to the level state of the second selection line; Alternatively, the first transistor is an N-type transistor, the second transistor is a P-type transistor, and the level state of the first selection line is the same as the level state of the second selection line; Alternatively, the first transistor is a P-type transistor, the second transistor is an N-type transistor, and a level state of the first selection line is the same as a level state of the second selection line.
9. The memory according to claim 1, characterized in that: The storage unit includes a transistor and a capacitor; The gate of the transistor is connected to the word line, the first electrode of the transistor is connected to the bit line, the second electrode of the transistor is connected to one end of the capacitor, and the other end of the capacitor is grounded; The memory includes at least one of the following: The memory cells located in the same column along the extending direction of the bit line share one bit line; A plurality of the word lines stacked and arranged in a direction perpendicular to the substrate correspond to one third selection line; For each layer of the memory array, the first electrodes of the transistors are connected to the bit lines in a one-to-one correspondence; Alternatively, the first electrodes of two adjacent transistors in a direction perpendicular to the word line are connected to the same bit line.
10. The memory according to claim 9, characterized in that: It includes a read / write circuit, a number of bit line selection units and a number of control lines; The bit lines are connected to the bit line selection units in a one-to-one correspondence, and the control lines are connected to the bit line selection units in a one-to-one correspondence; The bit line selection unit is used to select the bit line based on the control of the control line, so as to connect the selected bit line to the read / write circuit.
11. The memory according to any one of claims 1 to 10, characterized in that: comprising a plurality of first connecting lines and / or a plurality of second connecting lines; Each of the first selection lines is connected to a peripheral circuit via one of the first connection lines, the first connection lines are perpendicular to the substrate, and a plurality of the first connection lines are arranged in a staircase manner along a direction perpendicular to the substrate; Each of the second selection lines is connected to the peripheral circuit via a second connection line. The second connection line is perpendicular to the substrate, and a plurality of the second connection lines are arranged in a staircase manner along a direction perpendicular to the substrate.
12. An electronic device, characterized in that: Comprising the memory as claimed in any one of claims 1 to 11.
13. A method for reading and writing a memory as claimed in any one of claims 1 to 11, characterized in that: include: Writing operation stage: applying a first electrical signal to a first selection line corresponding to the storage array layer to which data is to be written, and applying a second electrical signal to a second selection line corresponding to the storage array layer to which data is to be written, so that the word line of the storage array layer to which data is to be written is connected to the third selection line in a one-to-one correspondence, so as to select the storage array layer to which data is to be written; Based on the selected storage array layer to which data is to be written, applying a third electrical signal to a third selection line corresponding to a word line connected to a storage cell row to which data is to be written, so that the storage cell row connected to the word line is turned on, so as to select the storage cell row to which data is to be written; Based on the selected memory cell row into which data is to be written, data of the bit lines connected to the memory cells in the memory cell row are written into the memory cells.
14. The reading and writing method according to claim 11, characterized in that: The write operation stage also includes: applying a second electrical signal to a first selection line corresponding to a storage array layer that does not need to write data, and applying a first electrical signal to a second selection line that does not need to write data, so that the word line of the storage array layer that does not need to write data is connected to the low-level potential end.