Memory device and method of manufacturing the same

Abstract

The present techniques include memory devices and methods of manufacturing the memory devices. The memory device includes: a memory block in which first and second connection regions and a cell region between the first and second connection regions are designated; a word line included in the memory block; a first drain select line included in the memory block and positioned on the word line; a first drain contact portion contacting a first drain selection line of the first connection region; a second drain contact portion contacting the first drain selection line of the second connection region; and a first drain voltage supply line commonly contacting the first drain contact and the second drain contact.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-1023-0104732 filed in the Korean Intellectual Property Office on August 10, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to memory devices and methods of manufacturing the same, and more particularly, to three-dimensional memory devices and methods of manufacturing the same. Background Art

[0004] The memory device may include a memory cell array in which data is stored and a peripheral circuit configured to perform a program operation, a read operation, or an erase operation of the memory cell array.

[0005] The memory cell array may include a plurality of memory blocks. The memory blocks may be formed in a three-dimensional structure. Different memory blocks may be separated from each other by slits.

[0006] A memory device formed in a three-dimensional structure may include a peripheral circuit stacked on a substrate and a memory block stacked on the peripheral circuit. Since the memory block is positioned above the peripheral circuit, the memory block may include a cell region, a memory cell capable of storing data is included in the cell region, and a connection region electrically connected to the peripheral circuit. The cell region may be positioned between the connection regions.

[0007] The memory block includes a plurality of memory cells for high-capacity data storage capability. As the number of memory cells increases, the size of the memory block may increase, and thus the time required to transfer an operating voltage generated from a peripheral circuit to the memory block may increase. Summary of the invention

[0008] According to one embodiment of the present disclosure, a memory device includes: a memory block, a first connection area and a second connection area and a cell area between the first connection area and the second connection area are designated in the memory block; a word line, which is included in the memory block; a first drain selection line, which is included in the memory block and is positioned on the word line; a first drain contact, which contacts the first drain selection line of the first connection area; a second drain contact, which contacts the first drain selection line of the second connection area; and a first drain voltage supply line, which contacts the first drain contact and the second drain contact together.

[0009] According to one embodiment of the present disclosure, a memory device includes: a first connection region, a second connection region, and a cell region between the first connection region and the second connection region; a first drain selection line extending in a first direction to be located within the first connection region, the second connection region, and the cell region; a bit line positioned on the first drain selection line in the cell region; a first drain contact contacting the first drain selection line of the first connection region; a second drain contact contacting the first drain selection line of the second connection region; a first drain voltage supply line contacting the first drain contact; and a second drain voltage supply line contacting the second drain contact, wherein the first drain voltage supply line, the second drain voltage supply line, and the bit line are positioned on the same plane.

[0010] According to one embodiment of the present disclosure, a memory device includes: a voltage generator configured to output a drain voltage through a global line; a row decoder connected to the voltage generator through the global line and transmitting the drain voltage to a drain voltage supply line; a drain selection line connected to a memory block; and a drain contact connected to both ends of the drain selection line, and the drain contacts are commonly connected to the drain voltage supply line.

[0011] According to one embodiment of the present disclosure, a method for manufacturing a memory device includes: forming a word line and a drain selection line positioned on the word line in a first connection region and a second connection region and in a cell region between the first connection region and the second connection region, forming an interlayer insulating layer on the entire structure including the drain selection line, forming a first drain contact and a second drain contact contacting the drain selection line positioned in the first connection region and the second connection region, forming a word line contact contacting the word line positioned in the first connection region, and forming a drain voltage supply line contacting the first drain contact and the second drain contact on the first drain contact and the second drain contact and the interlayer insulating layer.

[0012] According to one embodiment of the present disclosure, a method for manufacturing a memory device includes: forming a word line, a first drain selection line positioned on the word line, and a second drain selection line positioned on the first drain selection line in a first connection region and a second connection region and in a cell region between the first connection region and the second connection region, forming an interlayer insulating layer on the entire structure including the second drain selection line, forming a first drain contact and a second drain contact that each contact the first drain selection line in the first connection region and the second connection region, forming a third drain contact and a fourth drain contact that each contact the second drain selection line in the first connection region and the second connection region, forming word line contacts that respectively contact the word lines positioned in the first connection region, forming a first drain voltage supply line that commonly contacts the first drain contact and the second drain contact, and forming a second drain voltage supply line that commonly contacts the third drain contact and the fourth drain contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0014] Figure 2 is a perspective view illustrating a memory device.

[0015] Figure 3 is a circuit diagram illustrating a connection structure of a memory device according to one embodiment of the present disclosure.

[0016] Figure 4 is a perspective view illustrating the structure of a memory device according to the first embodiment of the present disclosure.

[0017] Figure 5 is a cross-sectional view illustrating the structure of a memory device according to the first embodiment of the present disclosure.

[0018] Figure 6 is a layout diagram illustrating the structure of a memory device according to the first embodiment of the present disclosure.

[0019] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G , Figure 7H , Fig.7I and Figure 7J is a diagram illustrating a method of manufacturing the memory device according to the first embodiment of the present disclosure.

[0020] Figure 8 is a layout diagram illustrating the structure of a memory device according to a second embodiment of the present disclosure.

[0021] Fig. 9 is a perspective view illustrating the structure of a memory device according to a second embodiment of the present disclosure.

[0022] Fig.10 is a perspective view illustrating the structure of a memory device according to a third embodiment of the present disclosure.

[0023] Fig.11 is a circuit diagram illustrating a connection structure of a memory device according to a fourth embodiment of the present disclosure.

[0024] Fig.12 is a perspective view illustrating the structure of a memory device according to a fourth embodiment of the present disclosure.

[0025] Fig.13 It is a graphic Fig.12 B1-B2 cross-sectional view of the structure shown.

[0026] Fig.14 It is a graphic Fig.12 A view of the C1-C2 cross section of the structure shown.

[0027] Fig.15 is a diagram illustrating one embodiment of a memory card system to which the memory device of the present disclosure is applied.

[0028] Fig.16 is a diagram illustrating one embodiment of a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0029] For the purpose of describing the embodiment of the conception according to the present disclosure, the specific structure or functional description of the embodiment of the conception according to the present disclosure disclosed in this specification or application is illustrated, and the embodiment of the conception according to the present disclosure can be embodied in various forms, and should not be interpreted as being limited to the embodiment described in this specification or application. It will be understood that when an element or layer, etc. is referred to as "on", "connected to" or "coupled to" another element or layer, etc., it can be directly on the other element or layer, etc., directly connected to or directly coupled to the other element or layer, etc., or there can be an intermediate element or layer, etc. In contrast, when an element or layer, etc. is referred to as "directly" on another element or layer, etc., "directly connected to" or "directly coupled to" another element or layer, etc., there is no intermediate element or layer, etc. Similar reference numerals always refer to similar elements. For ease of description, spatial relative terms such as "below", "below", "below", "above", "on", etc. can be used herein to describe the relationship between an element or feature and (one or more) other elements or features as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, the spatial relative terms are intended to cover the different orientations of the device when in use or operation. For example, if the device in the figure is turned over, the element then described as being "below" or "below" other elements or features will be oriented to be "above" the other elements or features. Therefore, the example of the term "below..." can cover both the orientations above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly. It will be understood that although the terms first, second, third, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, but are not used to only define the element itself or mean a specific order.

[0030] Embodiments of the present disclosure provide a memory device and a method of manufacturing the memory device, which can improve the operation speed of the memory device. According to embodiments of the present technology, the operation speed of the memory device can be improved.

[0031] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0032] refer to Figure 1 , the memory device 100 may include a memory cell array 110 and a peripheral circuit 170 .

[0033] The memory cell array 110 may include a first memory block BLK1 to a j-th memory block BLKj. Each of the first memory block BLK1 to the j-th memory block BLKj may include a memory cell capable of storing data. The memory block may be formed in a three-dimensional structure. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first memory block BLK1 to the j-th memory block BLKj, and a bit line BL may be commonly connected to the first memory block BLK1 to the j-th memory block BLKj. In one embodiment, j may be a natural number greater than one.

[0034] The first memory block BLK1 to the j-th memory block BLKj may be formed in a two-dimensional structure or a three-dimensional structure. A memory block having a two-dimensional structure may include memory cells arranged parallel to a substrate. A memory block having a three-dimensional structure may include memory cells stacked on a substrate in a vertical direction. In this embodiment, a memory block formed in a three-dimensional structure is disclosed.

[0035] Depending on the programming method, the memory cell can store 1 bit or 2 bits or more of data. For example, a method in which 1 bit of data is stored in one memory cell is called a single-level cell method, and a method in which 2 bits of data are stored in one memory cell is called a multi-level cell method. A method in which 3 bits of data are stored in one memory cell is called a three-level cell method, and a method in which 4 bits of data are stored in one memory cell is called a four-level cell method. In addition, five or more bits of data can be stored in one memory cell.

[0036] The peripheral circuit 170 may be configured to perform a program operation of storing data in the memory cell array 110, a read operation of outputting data stored in the memory cell array 110, and an erase operation of erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control circuit 180.

[0037] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a reading voltage, a transfer voltage, or an erasing voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the memory block selected by the row decoder 130.

[0038] The programming voltage may be a voltage applied to a selected word line among word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A turn-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the turn-off voltage may be set to 0V. A precharge voltage may be a voltage higher than 0V, and may be applied to a bit line during a read operation. A verification voltage may be used during a verification operation to determine whether the threshold voltage of a selected memory cell is increased to a target level. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0039] During a read operation of a selected memory cell, a read voltage may be applied to a selected word line. For example, the read voltage may be set to various levels according to a programming method of the selected memory cell. The pass voltage may be a voltage applied to an unselected word line among word lines WL during a programming or read operation, and may be used to turn on a memory cell connected to an unselected word line.

[0040] The erase voltage may be used to erase memory cells included in a selected memory block during an erase operation, and may be applied to the source line SL.

[0041] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first memory block BLK1 to the j-th memory block BLKj through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0042] The page buffer group 140 may include page buffers PB1 to PBn (not shown) connected to the first memory block BLK1 to the j-th memory block BLKj. Each of the page buffers (not shown) may be connected to the first memory block BLK1 to the j-th memory block BLKj through a bit line BL. During a read operation, in response to a page buffer control signal PBSIG, the page buffer (not shown) may sense a current or voltage of a bit line that varies according to a threshold voltage of a selected memory cell, and store the sensed data. In one embodiment, n may be a natural number greater than one.

[0043] The column decoder 150 may be configured so that data is transmitted between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL, and an enable signal may be transmitted through the column line CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0044] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 180, and transmit data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0045] The control circuit 180 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control a device included in the peripheral circuit 170 to perform a program operation of a memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control a device included in the peripheral circuit 170 to perform a read operation of a memory block selected by the address and output the read data. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control a device included in the peripheral circuit 170 to perform an erase operation of the selected memory block.

[0046] Figure 2 is a perspective view illustrating a memory device.

[0047] refer to Figure 2 , the first to j-th memory blocks BLK1 to BLKj included in the memory cell array may be positioned on the peripheral circuit 170. For example, the peripheral circuit 170 may be stacked on a substrate (not shown), and the first to j-th memory blocks BLK1 to BLKj may be stacked on the peripheral circuit 170.

[0048] Each memory block of the first memory block BLK1 to the j-th memory block BLKj positioned on the peripheral circuit 170 may extend along the X direction and may be spaced apart from each other along the Y direction. The first memory block BLK1 to the j-th memory block BLKj may be separated from each other by slits extending along the X direction. Each memory block of the first memory block BLK1 to the j-th memory block BLKj may include a source line SL, at least one source selection line SSL, at least one word line WL, and at least one drain selection line DSL. Each memory block of the first memory block BLK1 to the j-th memory block BLKj may include at least one source selection transistor, at least one memory cell, and at least one drain selection transistor. The source selection transistor may be connected to the source selection line, the memory cell may be connected to the word line, and the drain selection transistor may be connected to the drain selection line. The first memory block BLK1 to the j-th memory block BLKj may share at least one bit line BL. The source selection transistor may be configured to be electrically connected or disconnected between the source line and the memory cell. The memory cell may be configured to store data. The drain select transistor may be configured to electrically connect or disconnect the memory cell from the bit line BL.

[0049] The first memory block BLK1 to the j-th memory block BLKj may include a cell region CE configured to store data and a first connection region 1CN and a second connection region 2CN configured to be connected to the peripheral circuit 170. The cell region CE may be positioned between the first connection region 1CN and the second connection region 2CN. The source selection transistor, the memory cell, and the drain selection transistor may be positioned in the cell region CE. The contact portion configured to electrically connect the source selection line, the word line, and the drain selection line to the peripheral circuit 170 may be positioned in the first connection region 1CN and the second connection region 2CN.

[0050] Figure 3 is a circuit diagram illustrating a connection structure of a memory device according to one embodiment of the present disclosure.

[0051] refer to Figure 3 ,exist Figure 1 Among the first to j-th memory blocks BLK1 to BLKj shown in FIG. 2 , the first memory block BLK1 is shown as an example, and the remaining second to j-th memory blocks BLK2 to BLKj may also be configured similarly to the first memory block BLK1 .

[0052] The voltage generator 120 may generate an operating voltage and transmit the operating voltage to the row decoder 130 through the global line GLB. The row decoder 130 may transmit the operating voltage to the memory block selected in response to the row address. For example, when the row address corresponds to the first memory block BLK1, the row decoder 130 may transmit the operating voltage to the gate line GL connected to the first memory block BLK1. The gate line GL may include a first source selection line SSL1 to an mth source selection line SSLm, a first word line WL1 to a kth word line WLk, and a first drain selection line DSL1 to an nth drain selection line DSLn. Although not shown in the drawings, the gate line GL may further include a dummy line. Among the memory blocks connected to the row decoder 130, the gate lines of the unselected memory blocks other than the selected memory blocks may be floating. In one embodiment, m may be a natural number greater than one. In one embodiment, k may be a natural number greater than one.

[0053] The first memory block BLK1 may include a string ST connected between a source line SL and a first bit line BL1 to an i-th bit line BLi. The string ST may be connected to the source line SL in common and may be connected to the first bit line BL1 to the i-th bit line BLi, respectively. The string ST may include a first source selection transistor SST1 to an m-th source selection transistor SSTm, a first memory cell MC1 to a k-th memory cell MCk, and a first drain selection transistor DST1 to an n-th drain selection transistor DSTn. Each of m, k, n, and i may be a positive integer and may vary according to a memory device. The gates of the first source selection transistors SST1 to the m-th source selection transistors SSTm may be connected to the first source selection lines SSL1 to the m-th source selection lines SSLm, the gates of the first memory cells MC1 to the k-th memory cells MCk may be connected to the first word lines WL1 to the k-th word lines WLk, and the first drain selection transistors DST1 to the n-th drain selection transistors DSTn may be connected to the first drain selection lines DSL1 to the n-th drain selection lines DSLn. A group of memory cells connected to the same word line may configure a page PG, and a program operation or a read operation may be performed in units of page PG. In one embodiment, i may be a natural number greater than one.

[0054] In the drawings, although the first source selection transistor SST1 to the mth source selection transistor SSTm, the first memory cell MC1 to the kth memory cell MCk, and the first drain selection transistor DST1 to the nth drain selection transistor DSTn arranged along the XZ plane are shown, in the first memory block BLK1, the first source selection transistor SST1 to the mth source selection transistor SSTm, the first memory cell MC1 to the kth memory cell MCk, and the first drain selection transistor DST1 to the nth drain selection transistor DSTn arranged along the XZ plane can be further connected to the first bit line BL1 to the i-th bit line BLi along the Y direction. The string ST can be selected by the first drain selection transistor DST1 to the nth drain selection transistor DSTn connected along the Y direction. For example, the first drain selection transistor DST1 to the nth drain selection transistor DSTn arranged along the first XZ plane can be turned on, and the remaining first drain selection transistor DST1 to the nth drain selection transistor DSTn connected along the Y direction can be turned off.

[0055] The connection structure between the row decoder 130 and the first memory block BLK1 is described in detail as follows.

[0056] The first source selection lines SSL1 to the m-th source selection lines SSLm of the first memory block BLK1 may be connected to the row decoder 130 through the source contacts CTs and the source voltage supply line SVSL, and the first word lines WL1 to the k-th word lines WLk may be connected to the row decoder 130 through the word line contacts CTw and the word line voltage supply line WVSL. The first drain selection lines DSL1 to the n-th drain selection lines DSLn of the first memory block BLK1 may be connected to the row decoder 130 through the first drain contact group 1CTGd, the second drain contact group 2CTGd, and the drain voltage supply line DVSL.

[0057] The first drain contact group 1CTGd may be connected to one side of the first to nth drain selection lines DSL1 to DSLn, and the second drain contact group 2CTGd may be connected to the other side of the first to nth drain selection lines DSL1 to DSLn. The first and second drain contact groups 1CTGd and 2CTGd may be commonly connected to a drain voltage supply line DVSL.

[0058] For one embodiment, the reason why the first drain selection line DSL1 to the nth drain selection line DSLn are connected to the drain voltage supply line DVSL through the first drain contact group 1CTGd and the second drain contact group 2CTGd is to quickly connect the string ST selected from the multiple strings ST included in the first memory block BLK1 with the first bit line BL1 to the i-th bit line BLi.

[0059] When the second drain contact group 2CTGd does not exist, the first drain selection transistor DST1 to the nth drain selection transistor DSTn can be connected to the drain voltage supply line DVSL through the first drain contact group 1CTGd. Therefore, when the operating voltage is output from the row decoder 130, the operating voltage can be sequentially supplied to the first drain selection transistor DST1 to the nth drain selection transistor DSTn through the drain voltage supply line DVSL and the first drain contact group ICTGd. Therefore, in one embodiment, the first bit line BL1 and the string ST can be connected fastest, and the i-th bit line BL1 and the string ST can be connected slowest. In one embodiment, as the number of bit lines increases, the slowest time for the bit line and the string to be connected may become even slower. That is, in one embodiment, the time difference between the fastest time and the slowest time for the bit line and the string to be electrically connected to each other may increase.

[0060] Therefore, in the present embodiment, in order to supply the operating voltage applied to the drain voltage supply line DVSL through both ends of the first drain selection line DSL1 to the nth drain selection line DSLn, the first drain contact group 1CTGd and the second drain contact group 2CTGd may be used. As described above, since the first drain contact group 1CTGd is connected to one side of the first drain selection line DSL1 to the nth drain selection line DSLn, the second drain contact group 2CTGd is connected to the other side, and the first drain contact group 1CTGd and the second drain contact group 2CTGd are commonly connected to the drain voltage supply line DVSL, the time difference of the electrical connection of the first bit line BL1 to the i-th bit line BLi and the string ST can be reduced. In addition, in one embodiment, since the contact portion electrically connected between the first drain selection line DSL1 to the nth drain selection line DSLn and the drain voltage supply line DVSL is increased, the resistance can be reduced.

[0061] The word line contact CTw is connected to one side of the first to k-th word lines WL1 to WLk, and the source contact CTs is connected to one side of the first to m-th source selection lines SSL1 to SSLm, but these contacts may be connected to the other sides of the first to k-th word lines WL1 to WLk and the first to m-th source selection lines SSL1 to SSLm, respectively. However, since the size of the memory device may increase in this case, in the present embodiment, the first drain contact group 1CTGd may be connected to one side of the first to n-th drain selection lines DSL1 to DSLn, and the second drain contact group 2CTGd may be connected to the other side of the first to n-th drain selection lines DSL1 to DSLn.

[0062] Figure 4 is a perspective view illustrating the structure of a memory device according to the first embodiment of the present disclosure.

[0063] refer to Figure 4 , showing a portion of the memory block in which the first drain selection line DSL1 and the second drain selection line DSL2 are stacked. In the first embodiment, the stacking direction means the Z direction. The first drain selection line DSL1 may be positioned on the k-th word line WLk, and the second drain selection line DSL2 may be positioned on the first drain selection line DSL1. On the second drain selection line DSL2 of the cell region CE, the bit lines BL may be spaced apart from each other and arranged along the X direction.

[0064] The cell region CE may be positioned between the first connection region 1CN and the second connection region 2CN, and assuming that the first connection region 1CN and the second connection region 2CN are Figure 3 The distance between the row decoder 130 is greater than the distance between the second connection area 2CN and Figure 3 The distance between the row decoders 130 is short.

[0065] The k-th word line WLk, the first drain selection line DSL1, and the second drain selection line DSL2 may have a step shape in the first connection region 1CN, and the k-th word line WLk, the first drain selection line DSL1, and the second drain selection line DSL2 may also have a step shape in the second connection region 2CN. In the first connection region 1CN, all gate lines including the k-th word line WLk, the first drain selection line DSL1, and the second drain selection line DSL2 may have a step shape. In the second connection region 2CN, only the first drain selection line DSL1 and the second drain selection line DSL2 may have a step shape, and the remaining gate lines may be cut along the same YZ plane as the longest line in the X direction among the first drain selection line DSL1 and the second drain selection line DSL2. In the first connection region 1CN and the second connection region 2CN, the step shape has a shape in which the length of the step narrows from the lower part to the upper part. Therefore, in the first connection region 1CN and the second connection region 2CN, the upper surface of the first drain selection line DSL1 positioned below the second drain selection line DSL2 may be exposed along the X direction. In the first connection region 1CN, an upper surface of the kth word line WLk positioned under the first drain select line DSL1 may be exposed in the X direction. In the second connection region 2CN, an upper surface of the kth word line WLk positioned under the first drain select line DSL1 may not be exposed.

[0066] The kth word line contact portion kCTw may be positioned on the kth word line WLk exposed in the first connection region 1CN, and the kth word line voltage supply line kWVSL may be positioned on the kth word line contact portion kCTw. The kth word line voltage supply line kWVSL may be connected to Figure 3 The row decoder 130 is provided.

[0067] The 1a-th drain contact 1aCTd may be positioned on the first drain selection line DSL1 exposed in the first connection region 1CN, and the 1b-th drain contact 1bCTd may be positioned on the first drain selection line DSL1 exposed in the second connection region 2CN. The first drain voltage supply line 1DVSL may be positioned on the 1a-th drain contact 1aCTd and the 1b-th drain contact 1bCTd. The first drain voltage supply line 1DVSL may be connected to Figure 3 The row decoder 130 is provided.

[0068] The 2a-th drain contact 2aCTd may be positioned on the second drain selection line DSL2 exposed in the first connection region 1CN, and the 2b-th drain contact 2bCTd may be positioned on the second drain selection line DSL2 exposed in the second connection region 2CN. The second drain voltage supply line 2DVSL may be positioned on the 2a-th drain contact 2aCTd and the 2b-th drain contact 2bCTd. The second drain voltage supply line 2DVSL may be connected to Figure 3 The row decoder 130 is provided.

[0069] According to the above structure, Figure 3 The word line voltage Vw1 output by the row decoder 130 may be applied to the kth word line WLk through the kth word line voltage supply line kWVSL and the kth word line contact portion kCTw, and Figure 3 The drain voltage Vds1 output by the row decoder 130 may be applied to the first drain selection line DSL1 through the first drain voltage supply line 1DVSL, the 1a drain contact 1aCTd, and the 1b drain contact 1bCTd, and may be applied to the second drain selection line DSL2 through the second drain voltage supply line 2DVSL, the 2a drain contact 2aCTd, and the 2b drain contact 2bCTd. The word line voltage Vw1 may be a voltage applied to the word line during a programming operation, a read operation, or an erase operation. For example, the word line voltage Vw1 may be a programming voltage, a transfer voltage, a verification voltage, or a ground voltage, as well as other various voltages that may be applied to the word line. The drain voltage Vds1 may be a voltage for turning on or off the drain selection transistor during a programming operation, a read operation, or an erase operation, and may be a positive voltage, a negative voltage, or a ground voltage.

[0070] As described above, the voltage applied to the gate lines other than the first drain selection line DSL1 and the second drain selection line DSL2 can be applied to the gate lines through the first connection region 1CN, respectively, and the drain voltage Vds1 applied to the first drain selection line DSL1 and the second drain selection line DSL2 can be applied to the first drain selection line DSL1 and the second drain selection line DSL2 through the first connection region 1CN and the second connection region 2CN, respectively.

[0071] Because the drain voltage Vds1 is applied through both ends of the first drain select line DSL1 and the second drain select line DSL2 in one embodiment, the time required to transfer the drain voltage Vds1 to the drain select transistor can be shortened.

[0072] Figure 5 is a cross-sectional view illustrating the structure of a memory device according to the first embodiment of the present disclosure.

[0073] refer to Figure 5 , shows a cross-sectional view of a memory device taken along the XZ plane. Figure 5 , in order to describe the connection structure of the 1a-th drain contact 1aCTd to the na-th drain contact naCTd and the first drain voltage supply line 1DVSL to the n-th drain voltage supply line nDVSL, the first drain voltage supply line 1DVSL to the n-th drain voltage supply line nDVSL are positioned on different layers, but basically the first drain voltage supply line 1DVSL to the n-th drain voltage supply line nDVSL may be arranged on the same layer. For example, the first drain voltage supply line 1DVSL to the n-th drain voltage supply line nDVSL may be arranged on the same layer as the (k-2)-th word line voltage supply line (k-2)WVSL to the k-th word line voltage supply line kWVSL.

[0074] The cell region CE may include cell plugs CP extending in the Z direction and spaced apart from each other in the X and Y directions. Each of the cell plugs CP may include at least one source selection transistor, at least one memory cell, and at least one drain selection transistor. The structure of each of the cell plugs CP is described with reference to an XY plane view.

[0075] The cell plug CP may include a core column CR, a channel layer CH, and a memory layer ML. The memory layer ML includes a tunnel insulating layer (tunnel isolation layer) TX, a charge trapping layer CTL, and a blocking layer BX. The core column CR may have a columnar shape and may be formed of an insulating material or a conductive material. The channel layer CH may have a columnar shape surrounding the side surface of the core column CR and may be formed of polysilicon. The tunnel insulating layer TX may have a columnar shape surrounding the side surface of the channel layer CH and may be formed of an oxide layer. The charge trapping layer CTL may have a columnar shape surrounding the side surface of the tunnel insulating layer TX and may be formed of a nitride layer. The blocking layer BX may have a columnar shape surrounding the side surface of the charge trapping layer CTL and may be formed of an oxide layer.

[0076] The (k-2)th word line WL(k-2) to the kth word line WLk and the first to nth drain selection lines DSL1 to DSLn of the first connection region 1CN may have a staircase shape. The (k-2)th word line WL(k-2) to the kth word line WLk of the second connection region 2CN may not have a staircase shape, and the first to nth drain selection lines DSL1 to DSLn may have a staircase shape.

[0077] Figure 6 is a layout diagram illustrating the structure of a memory device according to the first embodiment of the present disclosure.

[0078] refer to Figure 6 , the bit line BL may be arranged on the k-th word line WLk, the first drain selection line DSL1, and the second drain selection line DSL2 in the Z direction. The bit lines BL may extend along the Y direction and may be spaced apart from each other along the X direction. The k-th word line voltage supply line kWVSL, the first drain voltage supply line 1DVSL, and the second drain voltage supply line 2DVSL may be arranged on the bit line BL in the Z direction. The k-th word line voltage supply line kWVSL, the first drain voltage supply line 1DVSL, and the second drain voltage supply line 2DVSL may extend along the X direction and may be spaced apart from each other along the Y direction.

[0079] The k-th word line voltage supply line kWVSL may be electrically connected to the k-th word line WLk through the k-th word line contact kCTw positioned in the first connection region 1CN. The first drain voltage supply line 1DVSL may be electrically connected to the first drain selection line DSL1 through the 1a-th drain contact 1aCTd positioned in the first connection region 1CN and the 1b-th drain contact 1bCTd positioned in the second connection region 2CN. The second drain voltage supply line 2DVSL may be electrically connected to the second drain selection line DSL2 through the 2a-th drain contact 2aCTd positioned in the first connection region 1CN and the 2b-th drain contact 2bCTd positioned in the second connection region 2CN. Therefore, in one embodiment, the length of the k-th word line voltage supply line kWVSL may be the shortest, the length of the second drain voltage supply line 2DVSL may be longer than the length of the k-th word line voltage supply line kWVSL, and the length of the first drain voltage supply line 1DVSL may be longer than the length of the second drain voltage supply line 2DVSL.

[0080] 7A to 7J is a diagram illustrating a method of manufacturing a memory device according to a first embodiment of the present disclosure, and is Figure 6 0 is a cross-sectional view taken along the A1-A2 direction of the accompanying drawing shown in .

[0081] refer to Fig. 7A, in a memory block of a memory device, a partial area including a drain selection line is shown. The first material layer 1MA and the second material layer 2MA may be alternately stacked. The number of the first material layer 1MA and the second material layer 2MA is not limited to the number shown in the drawings. The first material layer 1MA and the second material layer 2MA may be alternately stacked on a lower structure (not shown). The lower structure may be a peripheral circuit, a source line, or a substrate. The first material layer 1MA may be an insulating layer, and the second material layer 2MA may be a sacrificial layer. For example, the first material layer 1MA may be an oxide layer, and the second material layer 2MA may be a nitride layer. The cell region CE and the first connection region 1CN and the second connection region 2CN separated along the X direction may be specified in the first material layer 1MA and the second material layer 2MA. The cell region CE may be positioned between the first connection region 1CN and the second connection domain 2CN.

[0082] refer to Figure 7B , a first hole 1HA extending in a vertical direction is formed in the first material layer 1MA and the second material layer 2MA of the cell region CE, and a cell plug CP may be formed in the first hole 1HA. The process for forming the first hole 1HA may be performed as an anisotropic etching process. Each of the cell plugs CP formed in the cell plugs CP inside the first hole 1HA may include a core column CR, a channel layer CH, a tunnel insulating layer (tunnel isolation layer) TX, a charge trapping layer CTL, and a blocking layer BX. The core column CR may have a columnar shape and may be formed of an insulating material or a conductive material. The channel layer CH may have a columnar shape surrounding the side surface of the core column CR and may be formed of polysilicon. The tunnel insulating layer TX may have a columnar shape surrounding the side surface of the channel layer CH and may be formed of an oxide layer. The charge trapping layer CTL may have a columnar shape surrounding the side surface of the tunnel insulating layer TX and may be formed of a nitride layer. The blocking layer BX may have a columnar shape surrounding the side surface of the charge trapping layer CTL and may be formed of an oxide layer.

[0083] refer to Figure 7C , can form Figure 2 The slits SLT for separating the memory blocks are formed, and an etching process for removing the second material layer 2MA exposed by the slits may be performed. For example, an isotropic etching process may be performed. When the second material layer 2MA is removed, a recess Rc as an empty space may be formed between the first material layers 1MA.

[0084] refer to Fig.7D, a gate line GL may be formed between the first material layers 1MA. The gate line GL may be a conductive layer. For example, the conductive layer for the gate line GL may be a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), or a semiconductor material such as silicon (Si) or polycrystalline silicon (Poly-Si), but is not limited thereto. The gate line GL may be a source selection line, a word line, or a drain selection line.

[0085] refer to Fig. 7E , a step structure may be formed in the first connection region 1CN and the second connection region 2CN. The first material layer 1MA and the gate line GL that are in contact with each other may form a pair, and a step structure may be formed in each pair. For example, each step in the step may be formed in a structure in which the first material layer 1MA is positioned on the gate line GL, but in contrast, each step in the step may be formed in a structure in which the gate line GL is positioned on the first material layer 1MA. In the present embodiment, a structure in which the first material layer 1MA is positioned on the gate line GL is shown. Therefore, the first material layer 1MA may be exposed at each step.

[0086] In the first connection region 1CN, all pairs of the first material layer 1MA and the gate lines GL may be formed in a stepped structure, and in the second connection region 2CN, only a pair 71 of gate lines GL designated as drain selection lines may be formed in a stepped structure, and the pair positioned therebelow may have a cross-section cut in the Z direction.

[0087] refer to Figure 7F , a first interlayer insulating layer 1ITL may be formed on the entire structure including the stepped structure. The first interlayer insulating layer 1ITL may be an oxide layer. Since the upper surface of the first interlayer insulating layer 1ITL may not be flat due to the height difference between the cell region CE and the first and second connection regions 1CN and 2CN, after forming the first interlayer insulating layer 1ITL, a planarization process for flattening the upper surface of the first interlayer insulating layer 1ITL may be performed.

[0088] refer to Figure 7G , an opening exposing the upper surface of the cell plug CP may be formed, and a bit line BL may be formed in the opening. The bit line BL may be a conductive layer. The bit lines BL may be spaced apart from each other in the X direction.

[0089] refer to Figure 7H, a second interlayer insulating layer 2ITL may be formed on the bit line BL and the first interlayer insulating layer 1ITL. The second interlayer insulating layer 2ITL may be formed of the same material as the first interlayer insulating layer 1ITL. Subsequently, a contact hole Hc exposing the gate line GL of each step may be formed in the first connection region 1CN and the second connection region 2CN. For example, in the first connection region 1CN, since the gate line GL positioned on different layers forms a step, contact holes Hc and Hc' exposing the gate line GL may be formed at each step. In the second connection region 2CN, since only the gate line GL designated as the drain selection line has a stepped structure, contact holes Hc and Hc' may be formed on the gate line GL having the stepped structure. In the second connection region 2CN, since the remaining gate lines GL positioned below the gate line GL designated as the drain selection line do not form a stepped structure, the contact hole Hc is not formed on the gate line GL that does not form a stepped structure. Reference Figure 6 and Figure 7H Since the A1-A2 cross section is a cross section of a portion where the first drain voltage supply line 1DVSL extends, a contact hole Hc may be formed in a region where the 1a-th drain contact 1aCTd and the 1b-th drain contact 1bCTd are to be formed, and in cross sections other than the A1-A2 cross section, a contact hole Hc' exposing the gate line GL included in different steps may be formed.

[0090] refer to Fig.7I By filling the contact holes Hc and Hc' with a conductive material, the 1ath drain contact 1aCTd, the 1bth drain contact 1bCTd, the 2ath drain contact 2aCTd, the 2bth drain contact 2bCTd and the kth word line contact kCTw can be formed.

[0091] refer to Figure 7J A voltage supply line may be formed on the 1a-th drain contact 1aCTd, the 1b-th drain contact 1bCTd, the 2a-th drain contact 2aCTd, the 2b-th drain contact 2bCTd, the k-th word line contact kCTw, and the second interlayer insulating layer 2ITL. For example, a first drain voltage supply line 1DVSL contacting the 1a-th drain contact 1aCTd and the 1b-th drain contact 1bCTd may be formed in the A1-A2 cross section.

[0092] Figure 8 is a layout diagram illustrating a structure of a memory device according to a second embodiment of the present disclosure, and Fig. 9 is a perspective view illustrating the structure of a memory device according to a second embodiment of the present disclosure.

[0093] refer to Figure 8 and Fig. 9, the drain selection lines included in the same memory block may be separated by the drain separation pattern DSP. For example, the first drain selection line DSL1 of the first embodiment may be separated into the eleventh drain selection line DSL11 and the twelfth drain selection line DSL12 in the second embodiment, and the second drain selection line DSL2 of the first embodiment may be separated into the twenty-first drain selection line DSL21 and the twenty-second drain selection line DSL22 in the second embodiment. Because the drain separation pattern DSP extends along the X direction, the eleventh drain selection line DSL11 and the twelfth drain selection line DSL12 may be separated from each other along the Y direction, and the twenty-first drain selection line DSL21 and the twenty-second drain selection line DSL22 may also be separated from each other along the Y direction. The twenty-first drain selection line DSL21 may be positioned on the eleventh drain selection line DSL11, and the twenty-second drain selection line DSL22 may be positioned on the twelfth drain selection line DSL12.

[0094] The 11a-th drain contact 11aCTd may be positioned on the 11th drain selection line DSL11 of the first connection region 1CN, and the 11b-th drain contact 11bCTd may be positioned on the 11th drain selection line DSL11 of the second connection region 2CN. The 11th drain voltage supply line 11DVSL may be positioned on the 11a-th drain contact 11aCTd and the 11b-th drain contact 11bCTd. Therefore, when the drain voltage is supplied to the 11th drain voltage supply line 11DVSL, the drain voltage may be applied to both ends of the 11th drain selection line DSL11 through the 11a-th drain contact 11aCTd and the 11b-th drain contact 11bCTd.

[0095] The 12a-th drain contact 12aCTd may be positioned on the 12th drain selection line DSL12 of the first connection region 1CN, and the 12b-th drain contact 12bCTd may be positioned on the 12th drain selection line DSL12 of the second connection region 2CN. The 12th drain voltage supply line 12DVSL may be positioned on the 12a-th drain contact 12aCTd and the 12b-th drain contact 12bCTd. Therefore, when the drain voltage is supplied to the 12th drain voltage supply line 12DVSL, the drain voltage may be applied to both ends of the 12th drain selection line DSL12 through the 12a-th drain contact 12aCTd and the 12b-th drain contact 12bCTd.

[0096] The 21a-th drain contact 21aCTd may be positioned on the 21st drain selection line DSL21 of the first connection region 1CN, and the 21b-th drain contact 21bCTd may be positioned on the 21st drain selection line DSL21 of the second connection region 2CN. The 21st drain voltage supply line 21DVSL may be positioned on the 21a-th drain contact 21aCTd and the 21b-th drain contact 21bCTd. Therefore, when the drain voltage is supplied to the 21st drain voltage supply line 21DVSL, the drain voltage may be applied to both ends of the 21st drain selection line DSL21 through the 21a-th drain contact 21aCTd and the 21b-th drain contact 21bCTd.

[0097] The 22a-th drain contact 22aCTd may be positioned on the 22nd drain selection line DSL22 of the first connection region 1CN, and the 22b-th drain contact 22bCTd may be positioned on the 22nd drain selection line DSL22 of the second connection region 2CN. The 22nd drain voltage supply line 22DVSL may be positioned on the 22a-th drain contact 22aCTd and the 22b-th drain contact 22bCTd. Therefore, when the drain voltage is supplied to the 22nd drain voltage supply line 22DVSL, the drain voltage may be applied to both ends of the 22nd drain selection line DSL22 through the 22a-th drain contact 22aCTd and the 22b-th drain contact 22bCTd.

[0098] Fig.10 is a perspective view illustrating the structure of a memory device according to a third embodiment of the present disclosure.

[0099] refer to Fig.10 , the first drain selection line DSL1 and the second drain selection line DSL2 may not have a step structure and may be formed as a stack structure having the same length (length in the X direction) in the first connection region 1CN and the second connection region 2CN. Although not shown in the drawings, the word line and the source line positioned under the first drain selection line DSL1 may also be formed as a stack structure having the same length (length in the X direction) without being formed as a step structure.

[0100] As described in the first embodiment or the second embodiment, in the third embodiment, the 1a-th drain contact 1aCTd may be connected to the first connection region 1CN of the first drain voltage supply line 1DVSL, and the 1b-th drain contact 1bCTd may be connected to the second connection region 2CN of the drain voltage supply line 1DVSL. Since the 1a-th drain contact 1aCTd and the 1b-th drain contact 1bCTd need to contact the first drain selection line DSL1, the second hole 2HA may be formed in a portion of the second drain selection line DSL2. The second hole 2HA may be formed in a region through which the 1a-th drain contact 1aCTd and the 1b-th drain contact 1bCTd pass, and may have a width wider than that of the 1a-th drain contact 1aCTd and the 1b-th drain contact 1bCTd. An insulating layer may be formed between the inner wall of the second hole 2HA and the 1a-th and 1b-th drain contacts 1aCTd and 1bCTd to electrically isolate the 1a-th and 1b-th drain contacts 1aCTd and 1bCTd from the second drain select line DSL2.

[0101] The 2a-th drain contact 2aCTd may be connected to the first connection region 1CN of the second drain voltage supply line 2DVSL, and the 2b-th drain contact 2bCTd may be connected to the second connection region 2CN of the second drain voltage supply line 2DVSL. The 2a-th drain contact 2aCTd may contact the first connection region 1CN of the second drain selection line DSL2, and the 2b-th drain contact 2bCTd may contact the second connection region 2CN of the second drain selection line DSL2.

[0102] Fig.11 is a circuit diagram illustrating a connection structure of a memory device according to a fourth embodiment of the present disclosure.

[0103] refer to Fig.11, the drain selection lines included in the drain selection line group DSL_GR may be divided into two groups, and the drain selection lines included in each of the two groups may be connected to the first drain voltage supply line 1DVSL or the second drain voltage supply line 2DVSL. When describing the first memory block BLK1 as an example, the first memory block BLK1 may include a drain selection line group DSL_GR, a word line group WL_GR, and a source selection line group SSL_GR. The drain selection line group DSL_GR may include a drain selection line connected to a drain selection transistor. The word line group WL_GR may include a word line connected to a memory cell. The source selection line group SSL_GR may include a source selection line connected to a source selection transistor. The row decoder 130 may include a first drain selection line transfer transistor 1DSL_PTR and a second drain selection line transfer transistor 2DSL_PTR, a word line transfer transistor WL_PTR, and a source selection line transfer transistor SSL_PTR.

[0104] The first drain selection line transfer transistor 1DSL_PTR and the second drain selection line transfer transistor 2DSL_PTR may be commonly connected to the global drain selection line G_DSL. The first drain selection line transfer transistor 1DSL_PTR may transfer the drain voltage to the first drain voltage supply line 1DVSL, and the second drain selection line transfer transistor 2DSL_PTR may transfer the drain voltage to the second drain voltage supply line 2DVSL. The drain voltages transferred to the first drain voltage supply line 1DVSL and the second drain voltage supply line 2DVSL may be simultaneously supplied to the drain selection lines included in the drain selection line group DSL_GR. The words "simultaneously" and "simultaneously" as used herein with respect to a process mean that the processes occur at overlapping time intervals. For example, if a first process occurs over a first time interval and a second process occurs simultaneously over a second time interval, the first interval and the second interval at least partially overlap each other, so that there is a time when both the first process and the second process occur.

[0105] The word line transfer transistors WL_PTR may be commonly connected to the global word line G_WL. The word line transfer transistors WL_PTR may transfer a word line voltage to a word line voltage supply line WVSL. The word line voltage transferred to the word line voltage supply line WVSL may be supplied to word lines included in the word line group WL_GR.

[0106] The source selection line transfer transistors SSL_PTR may be commonly connected to the global source selection line G_SSL. The source selection line transfer transistors SSL_PTR may transfer the source voltage to the source voltage supply line SVSL. The source voltage transferred to the source voltage supply line SVSL may be simultaneously supplied to the source selection lines included in the source selection line group SSL_GR.

[0107] Fig.12 is a perspective view illustrating the structure of a memory device according to a fourth embodiment of the present disclosure.

[0108] refer to Fig.12 , the first drain voltage supply line 1DVSL and the second drain voltage supply line 2DVSL may be positioned on the same layer as the bit line BL. That is, the lower surface of the first drain voltage supply line 1DVSL, the lower surface of the second drain voltage supply line 2DVSL, and the lower surface of the bit line BL may be positioned on the same XY plane.

[0109] The structure of each area is described in detail below.

[0110] The first to third drain selection lines DSL1 to DSL3 may be sequentially stacked. For example, the second drain selection line DSL2 may be positioned on the first drain selection line DSL1, and the third drain selection line DSL3 may be positioned on the second drain selection line DSL2. The length of the second drain selection line DSL2 in the X direction is shorter than the length of the first drain selection line DSL1 in the X direction, and the length of the third drain selection line DSL3 in the X direction is shorter than the length of the second drain selection line DSL2 in the X direction. Therefore, the upper surface of each of the first to third drain selection lines DSL1 to DSL3 may be exposed in the first connection region 1CN and the second connection region 2CN.

[0111] Cell plugs (not shown) passing through the first to third drain selection lines DSL1 to DSL3 may be positioned in the cell region CE, and the bit line contacts CTb may contact the cell plugs. Figure 5 As shown in Figure 5 The cell plugs CP are the same, so repeated descriptions are omitted. The bit lines BL may be arranged on the bit line contacts CTb. The bit lines BL may extend along the Y direction and may be spaced apart along the X direction. The bit lines BL may be positioned on the same plane. For example, the bit lines BL may be positioned on the plane where the first drain voltage supply line 1DVSL and the second drain voltage supply line 2DVSL are positioned.

[0112] Fig.13 It is a graphic Fig.12 A view of a B1-B2 cross section of the structure shown in FIG. Fig.14 It is a graphic Fig.12 A view of the C1-C2 cross section of the structure shown.

[0113] refer to Fig.13 and Fig.14, the B1-B2 cross section shows the 2ath drain voltage supply line 2aDVSL and the 2bth drain voltage supply line 2bDVSL and the bit line BL, and the C1-C2 cross section shows the 1bth drain voltage supply line 1bDVSL, the 2bth drain voltage supply line 2bDVSL and the 3bth drain voltage supply line 3bDVSL.

[0114] The 2a-th drain contact 2aCTd and the 2b-th drain contact 2bCTd may be positioned on the second drain selection line DSL2 exposed to the first connection region 1CN and the second connection region 2CN. For example, the 2a-th drain contact 2aCTd and the 2b-th drain contact 2bCTd may pass through the first interlayer insulating layer 1ITL to contact the second drain selection line DSL2. The 2a-th drain voltage supply line 2aDVSL may be positioned on the 2a-th drain contact 2aCTd, and the 2b-th drain voltage supply line 2bDVSL may be positioned on the 2b-th drain contact 2bCTd.

[0115] The second interlayer insulating layer 2ITL may be filled between the 2a-th drain voltage supply line 2aDVSL, the 2b-th drain voltage supply line 2bDVSL, and the bit line BL. Therefore, the lower surface of the 2a-th drain voltage supply line 2aDVSL, the lower surface of the 2b-th drain voltage supply line 2bDVSL, and the lower surface of the bit line BL may be positioned on the same plane as the boundary surface between the first interlayer insulating layer 1ITL and the second interlayer insulating layer 2ITL. The thickness of the 2a-th drain voltage supply line 2aDVSL and the 2b-th drain voltage supply line 2bDVSL may be equal to or different from the thickness of the bit line BL.

[0116] The 1b-th drain voltage supply line 1bDVSL, the 2b-th drain voltage supply line 2bDVSL, and the 3b-th drain voltage supply line 3bDVSL respectively contacting different drain selection lines may be positioned on the same plane on the first interlayer insulating layer 1ITL.

[0117] Fig.15 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0118] refer to Fig.15 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0119] The controller 3100 is connected to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 may be configured to control the programming, reading or erasing operations of the memory device 3200, or to control background operations. The controller 3100 is configured to provide an interface between the memory device 3200 and the host. The controller 3100 is configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction circuit.

[0120] The controller 3100 can communicate with an external device through a connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device through at least one of various communication standards, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0121] The memory device 3200 may include a plurality of memory cells and may be Figure 1 The memory device 100 shown in FIG. 1 is configured identically.

[0122] The controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, mini SD, micro SD or SDHC), and a Universal Flash Storage (UFS).

[0123] Fig.16 is a diagram illustrating a solid-state drive (SSD) system to which the memory device of the present disclosure is applied.

[0124] refer to Fig.16, the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001, and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0125] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0126] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be connected to Figure 1 The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0127] The auxiliary power supply 4230 is connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive a power voltage from the host 4100 and be charged with the power voltage. When the power supply from the host 4100 is not smooth, the auxiliary power supply 4230 may provide a power voltage of the SSD 4200. For example, the auxiliary power supply 4230 may be located in the SSD 4200 or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and may provide auxiliary power to the SSD 4200.

[0128] The buffer memory 4240 operates as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Claims

1. A memory device, comprising: a memory block in which a first connection region and a second connection region and a cell region between the first connection region and the second connection region are designated; a word line included in the memory block; a first drain select line included in the memory block and positioned on the word line; a first drain contact portion contacting the first drain selection line of the first connection region; a second drain contact contacting the first drain selection line of the second connection region; and A first drain voltage supply line contacts the first drain contact and the second drain contact in common.

2. The memory device according to claim 1, further comprising: A peripheral circuit is positioned below the memory block.

3. The memory device according to claim 1, further comprising: A cell plug is positioned between a bit line and a source line in the cell region of the memory block.

4. The memory device of claim 3, wherein the cell plug comprises: a first drain selection transistor contacting the first drain selection line; as well as A memory cell contacts the word line. 5 . The memory device of claim 3 , wherein the bit line is positioned between the first drain voltage supply line and the first drain select line. 6 . The memory device of claim 4 , wherein the first drain select transistor is configured to be turned on or off in response to voltages applied from the first connection region and the second connection region of the first drain select line.

7. The memory device of claim 1 , further comprising: a second drain select line positioned above the first drain select line; a third drain contact portion contacting the second drain selection line of the first connection region; a fourth drain contact contacting the second drain selection line of the second connection region; and A second drain voltage supply line contacts the third drain contact and the fourth drain contact in common. 8 . The memory device of claim 7 , wherein in the first connection region and the second connection region, the first drain select line and the second drain select line respectively have a stepped structure in which upper surfaces are exposed. 9 . The memory device of claim 8 , wherein the first drain contact and the second drain contact are spaced apart from the second drain select line. 10 . The memory device of claim 7 , wherein in the first connection region and the second connection region, only an upper surface of the second drain select line of the first drain select line and the second drain select line is exposed. 11 . The memory device of claim 10 , wherein the second drain select line comprises a hole through which the first drain contact and the second drain contact pass. 12 . The memory device of claim 11 , wherein in the hole, the first drain contact and the second drain contact are spaced apart from an inner wall of the hole.

13. The memory device of claim 1 , further comprising: a third drain select line positioned on the same layer as the first drain select line; a drain separation pattern for electrically separating the first drain selection line and the third drain selection line; a fifth drain contact portion contacting the third drain selection line of the first connection region; a sixth drain contact portion contacting the third drain selection line of the second connection region; as well as A third drain voltage supply line contacts the fifth drain contact and the sixth drain contact in common.

14. A memory device comprising: a first connection region and a second connection region and a unit region between the first connection region and the second connection region; a first drain selection line extending in a first direction to be located in the first connection region and the second connection region and in the cell region; a bit line positioned on the first drain selection line in the cell region; a first drain contact portion contacting the first drain selection line of the first connection region; a second drain contact portion contacting the first drain selection line of the second connection region; a first drain voltage supply line contacting the first drain contact; and a second drain voltage supply line contacting the second drain contact, The first drain voltage supply line, the second drain voltage supply line and the bit line are positioned on the same plane.

15. The memory device of claim 14, further comprising: a second drain select line positioned between the first drain select line and the bit line; a third drain contact portion contacting the second drain selection line of the first connection region; a fourth drain contact portion contacting the second drain selection line of the second connection region; a third drain voltage supply line contacting the third drain contact; and a fourth drain voltage supply line contacting the fourth drain contact portion, The first drain voltage supply line to the fourth drain voltage supply line and the bit line are arranged on the same plane.

16. A memory device comprising: a voltage generator configured to output a drain voltage through a global line; a row decoder connected to the voltage generator through the global line and transmitting the drain voltage to a drain voltage supply line; a drain select line connected to the memory block; as well as a drain contact portion connected to both ends of the drain selection line, The drain contacts are commonly connected to the drain voltage supply line.

17. A method of manufacturing a memory device, the method comprising: forming a word line and a drain selection line positioned on the word line in the first connection region and the second connection region and in the cell region between the first connection region and the second connection region; forming an interlayer insulating layer on the entire structure including the drain selection line; forming a first drain contact and a second drain contact contacting the drain select line positioned in the first connection region and the second connection region; forming a word line contact contacting the word line positioned in the first connection region; as well as A drain voltage supply line contacting the first drain contact and the second drain contact is formed on the first drain contact and the second drain contact and the interlayer insulating layer.

18. The method of claim 17, wherein forming the first drain contact and the second drain contact comprises: forming a first contact hole exposing a portion of the drain selection line of the first connection region; forming a second contact hole exposing a portion of the drain selection line of the second connection region; as well as The first contact hole and the second contact hole are filled with a conductive material.

19. The method of claim 18, wherein forming the first contact hole and forming the second contact hole are performed simultaneously.

20. The method of claim 17, wherein forming the first and second drain contacts and forming the word line contact are performed simultaneously.

21. A method of manufacturing a memory device, the method comprising: In the first connection region and the second connection region and in the cell region between the first connection region and the second connection region, a word line, a first drain selection line positioned on the word line, and a second drain selection line positioned on the first drain selection line are formed; forming an interlayer insulating layer on the entire structure including the second drain selection line; forming a first drain contact and a second drain contact respectively contacting the first drain selection line in the first connection region and the second connection region; forming a third drain contact and a fourth drain contact respectively contacting the second drain selection line in the first connection region and the second connection region; forming word line contacts respectively contacting the word lines positioned in the first connection region; forming a first drain voltage supply line commonly contacting the first drain contact and the second drain contact; as well as A second drain voltage supply line commonly contacting the third drain contact and the fourth drain contact is formed. 22 . The method of claim 21 , wherein forming the first and second drain contacts and forming the third and fourth drain contacts are performed simultaneously. 23 . The method of claim 21 , wherein forming the first drain voltage supply line and forming the second drain voltage supply line are performed simultaneously.

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