Memory system, nonvolatile memory device and method of controlling operation thereof

Abstract

A non-volatile memory device, a memory system, and a method of controlling operation of the non-volatile memory device are disclosed. The nonvolatile memory device includes a memory block, a page buffer circuit, and a control circuit. The page buffer circuit is connected to the cell string through a bit line. The control circuit controls a read operation by: latching first sensing data and second sensing data in the page buffer circuit by performing a first read operation on a selected word line specified by an access address based on a read voltage setting; locking third sensing data in the page buffer circuit by performing a second read operation on an interfering word line adjacent to the selected word line based on at least one adjacent read voltage; selecting one of the first sensing data and the second sensing data as hard decision data based on a programming state of the third sensing data; and generating soft decision data by using the first sensing data and the second sensing data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0104814 filed in the Korean Intellectual Property Office (KIPO) on August 10, 2023 and Korean Patent Application No. 10-2023-0113278 filed in the Korean Intellectual Property Office (KIPO) on August 29, 2023, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a memory system, a nonvolatile memory device, and a method of controlling the operation of the nonvolatile memory device. Background Art

[0004] Flash memory devices, resistive memory devices, etc. can store data according to multiple threshold voltage distributions or multiple resistance distributions, where each corresponding distribution is assigned to a corresponding logical state of the stored data. When a predetermined read voltage is applied, the data stored by the memory cell can be read by determining whether the memory cell is turned on / off. During (and / or after) programming of the memory cell, the expected distribution of the memory cell may be undesirably distorted due to multiple events or conditions, including charge leakage, program disturbance, read disturbance, word line and / or bit line coupling, temperature change, voltage change, degradation of the memory cell, etc. For example, the expected distribution may be shifted and / or widened to cause a read failure, so that incorrect data different from the stored data is read out.

[0005] Recently, a three-dimensional structured nonvolatile memory device such as a vertical NAND memory device has been developed to increase the integration and memory capacity of the nonvolatile memory device. As the integration and memory capacity increase, the programming time of the nonvolatile memory device increases. Summary of the invention

[0006] The present disclosure relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a memory system capable of reducing a read error.

[0007] The present disclosure also relates to a method of controlling the operation of a nonvolatile memory device capable of reducing read errors.

[0008] In general, various aspects of the subject matter described in this specification can be implemented in a non-volatile memory device, which includes a memory block, a page buffer circuit, and a control circuit. The memory block includes a plurality of cell strings, wherein each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and arranged between each of a plurality of bit lines and a common source line in a vertical direction. The page buffer circuit is connected to the plurality of cell strings through a plurality of bit lines. The control circuit controls a read operation by performing a first read operation on a selected word line specified by an access address among a plurality of word lines of the memory block based on a read voltage setting, latching first sensing data and second sensing data in the page buffer circuit; performing a second read operation on an interference word line adjacent to the selected word line based on at least one adjacent read voltage, latching third sensing data in the page buffer circuit; selecting one of the first sensing data and the second sensing data as hard decision data based on a programming state of the third sensing data; and generating soft decision data by using the first sensing data and the second sensing data.

[0009] Another general aspect can be implemented in a memory system, which includes a nonvolatile memory device and a memory controller that controls the nonvolatile memory device. The nonvolatile memory device includes a memory block, a page buffer circuit, and a control circuit. The memory block includes a plurality of cell strings, wherein each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor that are connected in series and vertically arranged between each of a plurality of bit lines and a common source line. The page buffer circuit is connected to the plurality of cell strings through a plurality of bit lines. The control circuit controls a read operation by performing a first read operation on a selected word line specified by an access address among a plurality of word lines of the memory block based on a read voltage setting, latching first sensing data and second sensing data in the page buffer circuit; performing a second read operation on an interference word line adjacent to the selected word line based on at least one adjacent read voltage, latching third sensing data in the page buffer circuit; selecting one of the first sensing data and the second sensing data as hard decision data based on a programming state of the third sensing data; and providing the hard decision data to the memory controller.

[0010] Another general aspect can be implemented in a method of controlling the operation of a nonvolatile memory device, the nonvolatile memory device including a memory block having a plurality of cell strings, wherein each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and arranged in a vertical direction between each of a plurality of bit lines and a common source line. The method includes: performing a first read operation on a selected word line specified by an access address among a plurality of word lines of the memory block based on a read voltage setting, latching first sensing data and second sensing data in a page buffer circuit; performing a second read operation on an interference word line adjacent to the selected word line based on at least one group read voltage, latching third sensing data in the page buffer circuit; selecting one of the first sensing data and the second sensing data as hard decision data based on a programming state of the third sensing data; and generating soft decision data by using the first sensing data and the second sensing data.

[0011] Therefore, according to the nonvolatile memory device and the method for controlling the operation of the nonvolatile memory device, hard decision data and soft decision data for compensating the coupling of the selected word line can be generated through one read operation, and ECC decoding can be performed based on the hard decision data and the soft decision data. Therefore, the error correction capability can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a flowchart illustrating an example of a method of controlling the operation of a nonvolatile memory device.

[0013] Figure 2 It is shown Figure 1 A flowchart of an example of operations for selecting hard decision data in a method.

[0014] Figure 3 It is shown Figure 1 A flow chart of an example of operations for generating soft decision data in a method.

[0015] Figure 4 It is shown Figure 1 A flow chart of an example of operations for generating soft decision data in a method.

[0016] Figure 5 It is shown Figure 1 A flowchart of an example of the operation of outputting hard decision data and soft decision data in a method.

[0017] Figure 6 It is shown Figure 1 A flowchart of an example of the operation of outputting hard decision data and soft decision data in a method.

[0018] Figure 7 It is shown Figure 1Flowchart of an example of an operation of selecting a disturb word line performed before performing a second read operation in a method of.

[0019] Figure 8 is a block diagram illustrating an example of a memory system.

[0020] Fig. 9 It is shown Figure 8 A block diagram of an example of a memory controller in a memory system of FIG.

[0021] Fig.10 It is shown Figure 8 A block diagram of an example of a non-volatile memory device in a memory system of FIG.

[0022] Fig.11 It is shown Fig.10 A block diagram of an example of a memory cell array in FIG.

[0023] Fig.12 It is shown Fig.11 Circuit diagram of one of the memory blocks.

[0024] Fig.13 Show Fig.12 An example of the structure of a cell string in a memory block.

[0025] Fig.14 yes Fig.10 Schematic diagram of the connection of the memory cell array to the page buffer circuit.

[0026] Fig.15 An example of a page buffer is shown in detail.

[0027] Fig.16 is a circuit diagram illustrating an example of a cache unit.

[0028] Fig.17 It is shown Fig.10 A block diagram of a control circuit in a nonvolatile memory device.

[0029] Fig.18 It is shown Fig.10 Block diagram of a voltage generator in a nonvolatile memory device.

[0030] Fig.19 and Fig. 20 is a diagram illustrating an example of a programming method for reducing word line coupling.

[0031] Fig.21 is a diagram illustrating example threshold voltage distributions associated with memory cells of a kth word line before and after word line coupling caused when memory cells of a k-1th word line are programmed.

[0032] Fig. 22 The diagram shows a coupled memory cell and an uncoupled memory cell. Fig.21 A diagram of the full threshold voltage distribution in .

[0033] Fig.23A , Fig. 23B and Fig.23C is a diagram illustrating an example of grouping memory cells in a method of controlling an operation of a nonvolatile memory device.

[0034] Fig.24A is a circuit diagram showing an example of the structure of a memory cell array.

[0035] Fig. 24B is shown with Fig.24A A perspective view of an example of a memory block corresponding to the structure.

[0036] Fig.25 is a cross-sectional view for describing an example of a boundary portion included in a memory block.

[0037] Fig.26A and Fig.26B is an example of a timing diagram showing a data recovery read operation when programming proceeds from a string selection line to a substrate.

[0038] Fig. 27 is a diagram of an example of a read operation on a selected word line.

[0039] Fig.28A is a flow chart illustrating an example of a method of operating a memory system.

[0040] Fig.28B is a flow chart illustrating an example of a method of operating a memory system.

[0041] Fig.29 is a block diagram illustrating an example of an ECC decoder.

[0042] Fig.30 is a block diagram illustrating an example of a storage device including a nonvolatile memory device.

[0043] Fig.31 is a cross-sectional view of an example of a nonvolatile memory device.

[0044] Fig.32 is a diagram illustrating an example of a manufacturing process of a stacked semiconductor device.

[0045] Fig.33 is a block diagram illustrating an example of an electronic system including a semiconductor device.

[0046] Like reference numbers may refer to like elements throughout the drawings. DETAILED DESCRIPTION

[0047] Figure 1 is a flow chart illustrating a method of controlling the operation of a nonvolatile memory device.

[0048] Figure 1 A method of controlling the operation of a nonvolatile memory device including a memory block including a plurality of cell strings, wherein each cell string includes a string selection transistor connected between each of a plurality of bit lines and a common source line, a plurality of memory cells, and a ground selection transistor. In some embodiments, the nonvolatile memory device may include a three-dimensional NAND flash memory device or a vertical NAND flash memory device.

[0049] Reference Figure 1 , by performing a first read operation on a selected word line designated by an access address among a plurality of word lines of a memory block based on a read voltage setting, first sensing data and second sensing data are latched in a page buffer circuit connected to a plurality of cell strings through a plurality of bit lines (operation S100).

[0050] In some embodiments, the first read operation may correspond to a data recovery read operation, and the read voltage setting may include at least a first recovery read voltage and a second recovery read voltage. The first sensed data may correspond to data read from a memory cell turned on in response to the first recovery read voltage, and the second sensed data may correspond to data read from a memory cell turned on in response to the second recovery read voltage. The voltage level of the second recovery read voltage may be greater than the voltage level of the first recovery read voltage, and the first recovery read voltage and the second recovery read voltage may be obtained by a valley search operation.

[0051] The third sensing data is latched in the page buffer circuit by performing a second read operation on an aggressor word line adjacent to the selected word line based on at least one adjacent read voltage (operation S200). The third sensing data may be referred to as at least one decision data.

[0052] Based on the programming state of the third sensing data, one of the first sensing data and the second sensing data is selected as hard decision data (operation S300). Soft decision data is generated by using the first sensing data and the second sensing data (operation S400). The hard decision data and the soft decision data are output to the outside of the nonvolatile memory device (operation S500).

[0053] Figure 2 It is shown Figure 1 Flowchart of the operation of selecting hard decision data in the method.

[0054] Reference Figure 2In order to select one of the first sensing data and the second sensing data as hard decision data (operation S300), it is determined whether each of the memory cells coupled to the interference word line is an interference cell based on the programming state of the third sensing data (operation S310). The interference cell may be a memory cell that causes a change in the threshold voltage of other memory cells (i.e., memory cells coupled to word lines adjacent to the interference word line including the interference cell).

[0055] When it is determined that some of the memory cells coupled to the interfering word line are non-interfering cells (No in S310), the first sensing data of each of the first memory cells corresponding to the non-interfering cells among the memory cells coupled to the selected word line is selected as hard decision data (operation S330). That is, when the threshold voltage distribution of the programming state of the third sensing data of each of the non-interfering cells of the memory cells coupled to the interfering word line is less than at least one group read voltage, the first sensing data of each of the first memory cells corresponding to the non-interfering cells is selected as hard decision data, and the first memory cells are not affected by the programming state of the non-interfering cells.

[0056] When it is determined that some of the memory cells coupled to the interfering word line are interfering cells (Yes in S310), the second sensing data of each of the second memory cells corresponding to the interfering cells among the memory cells coupled to the selected word line is selected as hard decision data (operation S350). That is, when the threshold voltage distribution of the programming state of the third sensing data of each of the interfering cells of the memory cells coupled to the interfering word line is equal to or greater than at least one group read voltage, the second sensing data of each of the second memory cells corresponding to the interfering cells is selected as hard decision data, and the second memory cells are affected by the programming state of the interfering cells.

[0057] Figure 3 It is shown Figure 1 Flowchart of the operations of generating soft decision data in the method.

[0058] Reference Figure 3 In order to generate soft decision data (operation S400a), an XOR operation is performed on the first sensing data and the second sensing data (operation S410a), and as a result of the XOR operation, soft decision data is generated.

[0059] Figure 4 It is shown Figure 1 Flowchart of the operations of generating soft decision data in the method.

[0060] Reference Figure 4In order to generate soft decision data (operation S400b), an exclusive OR operation is performed on the first sensing data and the second sensing data (operation S410b), and as a result of the exclusive OR operation, soft decision data is generated.

[0061] Figure 5 It is shown Figure 1 Flowchart of the operation of outputting hard decision data and soft decision data in the method.

[0062] Reference Figure 5 , in order to output the hard decision data and the soft decision data (operation S500a), the hard decision data is output (operation S510a), and then the soft decision data is output after the hard decision data is output (operation S530a).

[0063] Figure 6 It is shown Figure 1 Flowchart of the operation of outputting hard decision data and soft decision data in the method.

[0064] Reference Figure 6 , in order to output the hard decision data and the soft decision data (operation S500b), the soft decision data is output (operation S510b), and then the hard decision data is output after the soft decision data is output (operation S530b).

[0065] Figure 7 It is shown Figure 1 Flowchart of an operation of selecting a disturb word line performed before performing a second read operation in a method of FIG.

[0066] exist Figure 7 In FIG. 5 , it is assumed that a plurality of word lines coupled to a memory block are programmed from bit lines to a common source line.

[0067] Reference Figure 7 , in order to select the interference word line (operation S150), it is determined whether the adjacent word line is a pseudo word line based on the row address and programming progress information included in the access address (operation S160). When the adjacent word line is not a pseudo word line (No in S160), it is determined whether the next word line is programmed (operation S170) because the next word line is a normal word line (e.g., not a pseudo word line). The normal word line may be a word line that is not a pseudo word line.

[0068] When the next word line is programmed (Yes in S170), the next word line is selected as a disturbing word line (operation S180). When the next word line is not programmed (No in S170), the previous word line is selected as a disturbing word line (operation S190).

[0069] When the adjacent word line is a dummy word line (Yes in S160 ), the previous word line is selected as an interference word line (operation S190 ).

[0070] Figure 8 is a block diagram illustrating a memory system.

[0071] Reference Figure 8 , the memory system 50 includes a memory controller 200 and a nonvolatile memory device 400 .

[0072] In some embodiments, each of the memory controller 200 and the nonvolatile memory device 400 may be provided in the form of a chip, a package, or a module. Alternatively, the memory controller 200 and the nonvolatile memory device 400 may be packaged into one of various packages and may be provided as a storage device such as a memory card.

[0073] The nonvolatile memory device 400 may perform an erase operation, a program operation, a normal read operation, or a data recovery read operation under the control of the memory controller 200. The nonvolatile memory device 400 may receive a command CMD, an address ADDR, and data DTA from the memory controller 200 through an input / output line for performing such an operation. The data DTA may include write data WD and read data RD. In addition, the nonvolatile memory device 400 may receive a control signal CTRL from the memory controller 200 through a control line. In addition, the nonvolatile memory device 400 may receive power PWR from the memory controller 200 through a power line.

[0074] The memory controller 200 may include an error correction code (ECC) engine 300, and the ECC engine 300 may include an ECC encoder 310 and an ECC decoder 320. The ECC encoder 310 may perform an ECC encoding operation on data to be stored in the nonvolatile memory device 400. The ECC decoder 320 may perform an ECC decoding operation on data read from the nonvolatile memory device 400.

[0075] Fig. 9 It is shown Figure 8 A block diagram of an example of a memory controller in a memory system of FIG.

[0076] Reference Fig. 9 , the memory controller 200 includes a processor 210 , an ECC engine 300 , an on-chip memory 230 , an Advanced Encryption Standard (AES) engine 240 , a host interface 250 , a ROM 260 , a memory interface 270 , and a read manager 280 connected via a bus 205 .

[0077] The processor 210 controls the overall operation of the memory controller 200. The processor 210 may control the ECC engine 300, the on-chip memory 230, the AES engine 240, the host interface 250, the ROM 260, the memory interface 270, and the read manager 280. The processor 210 may include one or more cores (e.g., homogeneous multi-cores or heterogeneous multi-cores). The processor 210 may be or may include, for example, at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a visual processing unit (VPU), and a neural processing unit (NPU). The processor 210 may execute various application programs (e.g., a flash translation layer (FTL) 235 and firmware) loaded into the on-chip memory 230.

[0078] The on-chip memory 230 may store various application programs that can be executed by the processor 210. The on-chip memory 230 may operate as a cache memory adjacent to the processor 210. The on-chip memory 230 may store commands, addresses, and data to be processed by the processor 210, or may store processing results of the processor 210. The on-chip memory 230 may be, for example, a storage medium or a working memory including a latch, a register, a static random access memory (SRAM), a dynamic random access memory (DRAM), a thyristor random access memory (TRAM), a tightly coupled memory (TCM), etc.

[0079] The processor 210 may execute the FTL 235 loaded onto the on-chip memory 230. The FTL 235 may be loaded onto the on-chip memory 230 as a firmware or program stored in a memory cell of the non-volatile memory device 400. The FTL 235 may manage the mapping between the logical address provided from the host and the physical address of the non-volatile memory device 400, and may include an address mapping table manager that manages and updates the address mapping table. The FTL 235 may also perform garbage collection operations, wear leveling operations, etc., as well as the address mapping described above. The FTL 235 may be executed by the processor 210 to address one or more of the following aspects of the non-volatile memory device 400: rewriting or writing in place is impossible, the life of the memory cell, a limited number of program erase (PE) cycles, and an erase speed that is slower than the write speed.

[0080] Memory cells of the nonvolatile memory device 400 may have physical characteristics that threshold voltage distribution varies due to reasons such as programming elapsed time, temperature, program disturbance, read disturbance, etc. For example, data stored in the nonvolatile memory device 400 becomes incorrect due to the above reasons.

[0081] The memory controller 200 may utilize various error correction techniques to correct such errors. For example, the memory controller 200 may include an ECC engine 300. The ECC engine 300 may correct errors occurring in data stored in the nonvolatile memory device 400. The ECC engine 300 may include an ECC encoder 310 and an ECC decoder 320. The ECC encoder 310 may perform an ECC encoding operation on data to be stored in the nonvolatile memory device 400. The ECC decoder 320 may perform an ECC decoding operation on data read from the nonvolatile memory device 400.

[0082] The ECC decoder 320 may perform a first ECC decoding operation on hard decision data read from a memory block of the nonvolatile memory device 400 , and may perform a second ECC decoding operation on soft decision data read from the memory block.

[0083] The ROM 260 may store various information necessary for the memory controller 200 to operate in firmware.

[0084] The AES engine 240 may perform at least one of an encryption operation and a decryption operation on the data input to the memory controller 200 by using a symmetric key algorithm. Although not shown in detail, the AES engine 240 may include an encryption module and a decryption module. For example, the encryption module and the decryption module may be implemented as separate modules. For another example, one module capable of performing both encryption and decryption operations may be implemented in the AES engine 240.

[0085] The read manager 280 may adjust and manage a plurality of read voltages associated with reading the data DTA stored in the nonvolatile memory device 400. For example, when the ECC engine 300 cannot correct an error in the data DTA read from the nonvolatile memory device 400, the read manager 280 may adjust a plurality of read voltages used in the nonvolatile memory device 400. The read manager 280 may include a read history table (e.g., a history table) 285, and may adjust a plurality of read voltages based on the read history table 285. The read manager 280 may read the data DTA stored in the nonvolatile memory device 400 at least twice, and may adjust a plurality of read voltages based on the read data DTA.

[0086] In some embodiments, the ECC engine 300 may have a given error correction capability. Data including error bits (or failed bits) whose number exceeds the error correction capability of the ECC engine 300 is referred to as "uncorrectable ECC (UECC) data". When the data DTA read from the nonvolatile memory device 400 is UECC data, the read manager 280 may adjust a plurality of read voltages and may perform the read operation again.

[0087] The read history table 285 may store the history of previous read voltages. For example, the read history table 285 may include information of read voltages that have been read through in previous read operations. The expression “read through” indicates that data read through a specific read voltage is normal data that does not include an error, or that an error included in the read data can be corrected by the ECC engine 300.

[0088] In some embodiments, the read manager 280 may adjust a plurality of read voltages based on the read history table 285. That is, because the read voltage is adjusted based on the read voltage of a previous read pass and the data DTA is read by using the adjusted read voltage (or read voltage level), the possibility that an error of the read data DTA is corrected by the ECC engine 300 may be increased. That is, the possibility of a read pass may be improved.

[0089] The read voltage of the previous read pass stored and managed in the read history table 285 is referred to as a “historical read voltage.” The read history table 285 may include information about the historical read voltage of each of the plurality of pages included in the nonvolatile memory device 400. For example, the read history table 285 may include information about the read voltage of the previous read pass for each word line.

[0090] The read manager 280 may update the read history table 285. For example, the read manager 280 may detect an optimal read voltage. The optimal read voltage indicates a read voltage that is read through when reading data. In some embodiments, the read manager 280 may read data from the nonvolatile memory device 400 at least twice or more, and may detect an optimal read voltage based on the read data. The operation of detecting the optimal read voltage is also referred to as a valley search operation.

[0091] The memory controller 200 may communicate with the host through the host interface 250. For example, the host interface 250 may include a universal serial bus (USB), a multimedia card (MMC), an embedded MMC, a peripheral component interconnect (PCI), PCI Express, an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a mobile industry processor interface (MIPI), a non-volatile memory express (NVMe), a universal flash storage (UFS), etc. The memory controller 200 may communicate with the non-volatile memory device 400 through the memory interface 270.

[0092] Fig.10 It is shown Figure 8 A block diagram of an example of a non-volatile memory device in a memory system of FIG.

[0093] Reference Fig.10 , the nonvolatile memory device 400 includes a memory cell array 405, an address decoder 430, a page buffer circuit 410, a data input / output (I / O) circuit 420, a control circuit 450, and a voltage generator 470. The control circuit 450 may include a disturbing word line selector 455, and the page buffer circuit 410 may include a data cooker 440.

[0094] The memory cell array 405 may be coupled to the address decoder 430 through a string selection line SSL, a plurality of word lines WLs, and a ground selection line GSL. In addition, the memory cell array 405 may be coupled to the page buffer circuit 410 through a plurality of bit lines BLs. The memory cell array 405 may include a plurality of nonvolatile memory cells coupled to the plurality of word lines WLs and the plurality of bit lines BLs.

[0095] In some embodiments, the memory cell array 405 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 405 may include a (vertical) cell string vertically oriented so that at least one memory cell is positioned above another memory cell.

[0096] The control circuit 450 may receive a command (signal) CMD and an address (signal) ADDR from the memory controller 200, and control an erase cycle, a program cycle, and a read operation of the nonvolatile memory device 400 based on the command signal CMD and the address signal ADDR. A program cycle may include a program operation and a program verification operation. An erase cycle may include an erase operation and an erase verification operation.

[0097] For example, the control circuit 450 may generate a control signal CTLs to control the voltage generator 470, and may generate a page buffer control signal PCTL based on the command signal CMD to control the page buffer circuit 410. The control circuit 450 may generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 450 may provide the row address R_ADDR to the address decoder 430 and provide the column address C_ADDR to the data input / output circuit 420.

[0098] The address decoder 430 may be coupled to the memory cell array 405 through the string selection line SSL, the plurality of word lines WLs, and the ground selection line GSL. During a program operation or a read operation, the address decoder 430 may determine one of the plurality of word lines WLs as a selected word line based on the row address R_ADDR, and determine the remaining word lines of the plurality of word lines WLs except the selected word line as unselected word lines.

[0099] The voltage generator 470 may generate a word line voltage VWLs associated with the operation of the nonvolatile memory device 400 based on the control signal CTLs. The voltage generator 470 may receive power PWR from the memory controller 200. The word line voltage VWLs may be applied to a plurality of word lines WLs through the address decoder 430.

[0100] For example, during an erase operation, the voltage generator 470 may apply an erase voltage to the channels of the cell strings of the memory block and may apply a ground voltage to all word lines of the memory block. During an erase verification operation, the voltage generator 470 may apply an erase verification voltage to all word lines of the memory block or sequentially apply the erase verification voltage to the word lines on a word line basis.

[0101] For example, during a program operation, the voltage generator 470 may apply a program voltage to a selected word line and may apply a program pass voltage to unselected word lines. In addition, during a program verification operation, the voltage generator 470 may apply a program verification voltage to a selected word line and may apply a verification pass voltage to unselected word lines. For example, during a read operation, the voltage generator 470 may apply a read voltage to a selected word line and may apply a read pass voltage to unselected word lines.

[0102] The page buffer circuit 410 may be coupled to the memory cell array 405 through a plurality of bit lines BLs. The page buffer circuit 410 may include a plurality of page buffers. The page buffer circuit 410 may temporarily store data to be programmed in a selected page or data read out from a selected page.

[0103] The control circuit 450 can control the read operation by the following operations: latching the first sensing data and the second sensing data in the page buffer circuit 410 by performing a first read operation on a selected word line designated by an access address among a plurality of word lines WLs of a memory block based on a read voltage setting (i.e., a restored read voltage); latching the third sensing data in the page buffer circuit 410 by performing a second read operation on an interference word line adjacent to the selected word line based on at least one adjacent read voltage; selecting one of the first sensing data and the second sensing data as hard decision data based on a programming state of the third sensing data; and generating soft decision data by using the first sensing data and the second sensing data.

[0104] The data processor 440 may generate soft decision data by performing one of an XOR operation and an XOR operation on the first sensing data and the second sensing data. The data processor 440 may be referred to as a data manipulator or a data generator because the data processor 440 generates soft decision data by performing a logic operation on the first sensing data and the second sensing data.

[0105] The data input / output circuit 420 may be coupled to the page buffer circuit 410 through a plurality of data lines DLs. During a program operation, the data input / output circuit 420 may receive program data DTA from the memory controller 200 based on a column address C_ADDR received from the control circuit 450, and provide the program data DTA to the page buffer circuit 410. During a read operation, the data input / output circuit 420 may provide read data DTA stored in the page buffer circuit 410 to the memory controller 200 based on the column address C_ADDR received from the control circuit 450.

[0106] Fig.11 It is shown Fig.10 A block diagram of an example of a memory cell array in FIG.

[0107] Reference Fig.11 , the memory cell array 405 includes a plurality of memory blocks BLK1 to BLKz extending along a first direction HD1 (i.e., a first horizontal direction), a second direction HD2 (i.e., a second horizontal direction), and a third direction VD (i.e., a vertical direction). Here, z may be a natural number greater than two. In some embodiments, the memory blocks BLK1 to BLKz are composed of Fig.10 For example, the address decoder 430 may select a memory block corresponding to the block address among the memory blocks BLK1 to BLKz.

[0108] Fig.12 It is shown Fig.11 Circuit diagram of one of the memory blocks.

[0109] Fig.12 The memory block BLKi may be formed in a three-dimensional structure (or a vertical structure) on the substrate SUB. For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a third direction VD perpendicular to the substrate SUB.

[0110] Reference Fig.12 , the memory block BLKi includes (memory) cell strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the cell strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. Fig.12 , each of the cell strings NS11 to NS33 is illustrated as including eight memory cells MC1 to MC8. However, the present disclosure is not limited thereto. In some embodiments, each of the cell strings NS11 to NS33 may include any number of memory cells.

[0111] The string selection transistor SST may be connected to the corresponding string selection lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 may be connected to the corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0112] Word lines (eg, WL1 ) having the same height may be connected in common, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated.

[0113] Fig.13 Show Fig.12 An example of the structure of a cell string in a memory block.

[0114] Reference Fig.12 and Fig.13 , in the cell string NS11 , the pillars PL are disposed on the substrate SUB such that the pillars PL extend in a direction perpendicular to the substrate SUB to make contact with the substrate SUB. Fig.13 Each of the ground selection line GSL1, word lines WL1 to WL8, and string selection line SSL1 shown in FIG. 4 may be formed of a conductive material (eg, a metal material) parallel to the substrate SUB. The pillars PL may contact the substrate SUB through the conductive material forming the string selection line SSL1, word lines WL1 to WL8, and ground selection line GSL1.

[0115] exist Fig.13 A cross section taken along line V-V' is also shown in FIG. In some embodiments, a cross section of a first memory cell MC1 corresponding to a first word line WL1 is shown. The pillar PL may include a cylindrical body BD. An air gap AG may be defined in an inner portion of the body BD.

[0116] The body BD may include P-type silicon and may be a region where a channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI. The blocking insulating layer BI may be disposed between the first word line WL1 and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trapping layer CT, the blocking insulating layer BI, and the first word line WL1 may constitute a charge trapping transistor formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB or be included in a charge trapping transistor formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. The string selection transistor SST, the ground selection transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

[0117] Fig.14 yes Fig.10 Schematic diagram of the connection of the memory cell array to the page buffer circuit.

[0118] Reference Fig.14 , the memory cell array 405 may include first to m-th cell strings NS1, NS2, NS3, ..., NSm, each of which may include a ground selection transistor GST connected to a ground selection line GSL, a plurality of memory cells MC respectively connected to first to n-th word lines WL1, ..., WLn, and a string selection transistor SST connected to a string selection line SSL, and the ground selection transistor GST, the plurality of memory cells MC and the string selection transistor SST may be connected in series to each other. In this case, n may be a positive integer greater than three.

[0119] The page buffer circuit 410 may include a first page buffer unit to an mth page buffer unit PBU1, PBU2, PBU3, ..., PBUm. The first page buffer unit PBU1 may be connected to the first cell string NS1 via the first bit line BL1, and the mth page buffer unit PBUm may be connected to the mth cell string NSm via the mth bit line BLm. For example, m may be 8, and the page buffer circuit 410 may have an eight-level page buffer unit or a structure in which the first page buffer unit to the mth page buffer unit PBU1, PBU2, PBU3, ..., PBUm are in a row. For example, the first page buffer unit to the mth page buffer unit PBU1, PBU2, PBU3, ..., PBUm may be in a row in the extension direction of the first bit line to the mth bit line BL1, BL2, BL3, ..., BLm.

[0120] The page buffer circuit 410 may also include first to m-th cache latches CL1, CL2, CL3, ..., CLm corresponding to the first to m-th page buffer units PBU1, PBU2, PBU3, ..., PBUm, respectively. For example, the page buffer circuit 410 may have an eight-level cache latch or a structure in which the first to m-th cache latches CL1, CL2, CL3, ..., CLm are in a row. For example, the first to m-th cache latches CL1, CL2, CL3, ..., CLm may be in a row in the extension direction of the first bit line to the m-th bit line BL1, BL2, BL3, ..., BLm.

[0121] The sensing node of each of the first to m-th page buffer units PBU1, PBU2, PBU3, ..., PBUm can be connected in common to the combined sensing node SOC. In addition, the first to m-th cache latches CL1, CL2, CL3, ..., CLm can be connected in common to the combined sensing node SOC. Therefore, the first to m-th page buffer units PBU1, PBU2, PBU3, ..., PBUm can be connected to the first to m-th cache latches CL1, CL2, CL3, ..., CLm via the combined sensing node SOC. The first to m-th cache latches CL1, CL2, CL3, ..., CLm can output hard decision data HDRD.

[0122] The page buffer circuit 410 may further include a data processor 440. The data processor 440 may be connected to the first to m-th page buffer units PBU1, PBU2, PBU3, ..., PBUm, may generate soft decision data SDRD by using the first and second sensing data stored in the first to m-th page buffer units PBU1, PBU2, PBU3, ..., PBUm, and may output the soft decision data SDRD.

[0123] Fig.15 The page buffer is shown in detail.

[0124] Reference Fig.15 , the page buffer PB can be connected with Fig.10 The example of the page buffer PB in FIG. 1 corresponds to the example of the page buffer PB in FIG. The page buffer PB may include a page buffer unit PBU and a high-speed buffer unit CU. Because the high-speed buffer unit CU includes a high-speed cache latch (C-LATCH) CL, and the C-LATCH CL is connected to the data input / output line, the high-speed buffer unit CU may be adjacent to the data input / output line. Therefore, the page buffer unit PBU and the high-speed buffer unit CU may be separated from each other, and the page buffer PB may have a structure in which the page buffer unit PBU and the high-speed buffer unit CU are separated from each other.

[0125] The page buffer unit PBU may include a main unit MU. The main unit MU may include a main transistor located in the page buffer PB. The page buffer unit PBU may also include a bit line selection transistor TR_hv connected to the bit line BL and driven by the bit line selection signal BLSLT. The bit line selection transistor TR_hv may include a high voltage transistor, and therefore, the bit line selection transistor TR_hv may be located in a well region different from the main unit MU (i.e., located in the high voltage unit HVU).

[0126] The main unit MU may include a sense latch (S-LATCH) SL, a force latch (F-LATCH) FL, a high latch (M-LATCH) ML, and a low latch (L-LATCH) LL. In some embodiments, S-LATCH SL, F-LATCH FL, M-LATCH ML, or L-LATCH LL may be referred to as a master latch. The main unit MU may also include a precharge circuit PC capable of controlling a precharge operation of a bit line BL or a sense node SO based on a bit line clamp control signal BLCLAMP, and may also include a transistor PM' driven by a bit line setup signal BLSETUP.

[0127] The S-LATCH SL may store data stored in the memory cell MC or a sensing result of the threshold voltage of the memory cell MC during a read or program verification operation. In addition, the S-LATCH SL may be used to apply a program bit line voltage or a program inhibit voltage to the bit line BL during a program operation. The F-LATCH FL may be used to improve the threshold voltage distribution during a program operation. The F-LATCH FL may store forced data. After the forced data is initially set to "1", when the threshold voltage of the memory cell MC enters a forced region having a voltage lower than that of the target region, the forced data may be converted to "0". By utilizing forced data during a program execution operation, the bit line voltage may be controlled, and the program threshold voltage distribution may be formed to be narrower.

[0128] M-LATCH ML, L-LATCH LL, and C-LATCH CL can be used to store data input from the outside during a programming operation, and can be called a data latch. When 3-bit data is programmed in one memory cell MC, the 3-bit data can be stored in M-LATCH ML, L-LATCH LL, and C-LATCH CL, respectively. Until the programming of the memory cell MC is completed, M-LATCH ML, L-LATCH LL, and C-LATCH CL can maintain the stored data. In addition, C-LATCH CL can receive data read from the memory cell MC from S-LATCH SL during a read operation, and output the received data to the outside via a data input / output line.

[0129] In addition, the main unit MU may further include a first transistor NM1 to a fourth transistor NM4. The first transistor NM1 may be connected between the sensing node SO and the S-LATCH SL, and may be driven by the ground control signal SOGND. The second transistor NM2 may be connected between the sensing node SO and the F-LATCH FL, and may be driven by the forced monitoring signal MON_F. The third transistor NM3 may be connected between the sensing node SO and the M-LATCH ML, and may be driven by the high-bit monitoring signal MON_M. The fourth transistor NM4 may be connected between the sensing node SO and the L-LATCH LL, and may be driven by the low-bit monitoring signal MON_L.

[0130] In addition, the main unit MU may further include a fifth transistor NM5 and a sixth transistor NM6 connected in series to each other between the bit line selection transistor TV_hv and the sensing node SO. The fifth transistor NM5 may be driven by the bit line cutoff signal BLSHF, and the sixth transistor NM6 may be driven by the bit line connection control signal CLBLK. In addition, the main unit MU may further include a precharge transistor PM. The precharge transistor PM may be connected to the sensing node SO, driven by the load signal LOAD, and precharge the sensing node SO to a precharge level in the precharge period.

[0131] In some embodiments, the main unit MU may further include a pair of transfer transistors or a first transfer transistor TR and a second transfer transistor TR' connected to the sensing node SO. In some embodiments, the first transfer transistor TR and the second transfer transistor TR' may also be referred to as a first sensing node connection transistor and a second sensing node connection transistor, respectively. The first transfer transistor TR and the second transfer transistor TR' may be driven in response to a transfer control signal SO_PASS. In some embodiments, the transfer control signal SO_PASS may be referred to as a sensing node connection control signal. The first transfer transistor TR may be connected between the first terminal SOC_U and the sensing node SO, and the second transfer transistor TR' may be connected between the sensing node SO and the second terminal SOC_D.

[0132] For example, when the page buffer unit PBU is connected to Fig.14 When corresponding to the second page buffer unit PBU2 in the first to m-th page buffer units, the first terminal SOC_U may be connected to one end of the pass transistor included in the first page buffer unit PBU1, and the second terminal SOC_D may be connected to one end of the pass transistor included in the third page buffer unit PBU3. In this way, the sense node SO may be electrically connected to the combined sense node SOC via the pass transistor included in each of the third to m-th page buffer units PBU3 to PBUm.

[0133] During a program operation, the page buffer PB may verify whether programming is completed in a selected memory cell MC among memory cells MC included in a NAND string connected to a bit line BL. The page buffer PB may store data sensed via the bit line BL during a program verification operation in the S-LATCH SL. The M-LATCH ML and the L-LATCH LL may be set, wherein target data is stored according to the sensed data stored in the S-LATCH SL.

[0134] For example, when the sensing data indicates that programming is completed, the M-LATCH ML and L-LATCH LL may be switched to a program inhibit setting for the selected memory cell MC in a subsequent programming loop. The C-LATCH CL may temporarily store input data provided from the outside. During a programming operation, target data to be stored in the C-LATCH CL may be stored in the M-LATCH ML and L-LATCH LL.

[0135] In the following, it is assumed that signals for controlling elements in the page buffer circuit 410 are included in Fig.10 The page buffer control signal PCTL in.

[0136] Fig.16 is a circuit diagram showing an example of a cache unit.

[0137] Reference Fig.15 and Fig.16 , the cache unit CU may include a monitoring transistor NM7 and a C-LATCH CL, and the C-LATCH CL may include a first inverter INV1 and a second inverter INV2, a dump transistor 132, and transistors 131, 133 to 135. The monitoring transistor NM7 may be driven based on a cache monitoring signal MON_C, and may control a connection between a combined sensing node SOC and the C-LATCH CL.

[0138] The first inverter INV1 may be connected between the first node ND1 and the second node ND2, the second inverter INV2 may be connected between the second node ND2 and the first node ND1, and thus, the first inverter INV1 and the second inverter INV2 may form a latch. The transistor 131 may include a gate connected to the combined sensing node SOC, and may be connected between the dump transistor 132 and the ground voltage VSS.

[0139] The dump transistor 132 may be driven by the dump signal Dump_C and may transmit the data stored in the C-LATCH CL to the master latch (e.g., the S-LATCH SL in the page buffer unit PBU). The transistor 133 may be driven by the data signal DI, the transistor 134 may be driven by the data inversion signal nDI, and the transistor 135 may be driven by the write control signal DIO_W. When the write control signal DIO_W is activated, the voltage levels of the first node ND1 and the second node ND2 may be determined based on the data signal DI and the data inversion signal nDI, respectively.

[0140] The cache unit CU may be connected to a data I / O line (data I / O terminal) RDi via transistors 136 and 137. The transistor 136 may include a gate connected to a second node ND2 and may be turned on or off based on a voltage level of the second node ND2. The transistor 137 may be driven by a read control signal DIO_R. When the read control signal DIO_R is activated and the transistor 137 is turned on, the voltage level of the input / output terminal RDi may be determined to be "1" or "0" based on the state of the C-LATCH CL.

[0141] Fig.17 It is shown Fig.10 A block diagram of a control circuit in a nonvolatile memory device.

[0142] Reference Fig.17 , the control circuit 450 includes a command decoder 451 , an address buffer 452 , a control signal generator 453 and a disturbing word line selector 455 .

[0143] The command decoder 451 decodes the command CMD and supplies the decoded command D_CMD to the control signal generator 453 .

[0144] The address buffer 452 receives the address signal ADDR, provides a row address R_ADDR to the address decoder 430 and the disturbing word line selector 455 , and provides a column address C_ADDR to the data input / output circuit 420 .

[0145] The control signal generator 453 receives the decoded command D_CMD and the voltage level signal VLS, generates a control signal CTLs based on the operation directed by the decoded command D_CMD and the voltage level of the programming pass voltage directed by the voltage level signal VLS, provides the control signal CTLs to the voltage generator 470, generates a page buffer control signal PCTL, and provides the page buffer control signal PCTL to the page buffer circuit 410.

[0146] The disturb word line selector 455 may determine one of word lines adjacent to the selected word line based on the row address R_ADDR and program order information (eg, program progress information) POI.

[0147] Fig.18 It is shown Fig.10 Block diagram of a voltage generator in a nonvolatile memory device.

[0148] Reference Fig.18 The voltage generator 470 may include a high voltage (HV) generator 475 and a low voltage (LV) generator 480 . The voltage generator 470 may further include a negative voltage (NV) generator 485 .

[0149] The high voltage generator 470 may generate a program voltage VPGM, a program pass voltage VPPASS, a verification pass voltage VVPASS, a read pass voltage VRPASS, and an erase voltage VERS in response to a first control signal CTL1 according to an operation directed by a command CMD. The program pass voltage VPPASS, the verification pass voltage VVPASS, and the read pass voltage VRPASS may be referred to as a pass voltage VPASS.

[0150] A program voltage VPGM is applied to a selected word line, a program pass voltage VPPASS, a verification pass voltage VVPASS, a read pass voltage VRPASS may be applied to unselected word lines, and an erase voltage VERS may be applied to a well of a memory block. The first control signal CTL1 may include a plurality of bits indicating an operation directed by a decoded command D_CMD.

[0151] The low voltage generator 480 may generate a program verification voltage VPV, an erase verification voltage VEV, a read voltage VRD, recovery read voltages VDR1 and VDR2, and an adjacent read voltage VAD in response to a second control signal CTL2 according to an operation directed by a command CMD. The program verification voltage VPV, the read voltage VRD, the erase verification voltage VEV, and the recovery read voltages VDR1 and VDR2 may be applied to a selected word line according to an operation of a memory controller 200 (e.g., a nonvolatile memory device). An adjacent read voltage VAD may be applied to a disturbed word line in a data recovery read operation. The second control signal CTL2 may include a plurality of bits indicating an operation directed by a decoded command D_CMD.

[0152] The negative voltage generator 485 may generate a first negative voltage VNEG1 and a second negative voltage VNEG2 having a negative level according to an operation directed by the command CMD in response to the third control signal CTL3. The third control signal CTL3 may include a plurality of bits indicating an operation directed by the decoded command D_CMD. The first negative voltage VNEG1 may be applied to a selected word line and an unselected word line during a program recovery period, and the second negative voltage VNEG2 may be applied to an unselected word line during a bit line setting period.

[0153] Fig.19 and Fig. 20 is a diagram illustrating a programming method for reducing word line coupling.

[0154] Fig.19 A programming method for reducing word line coupling is shown which is performed under the assumption that each memory cell stores 3 bits of data.

[0155] exist Fig.19 , curves (e.g., threshold voltage distributions 510 to 513) show the threshold voltage distribution of memory cells after a next 2-page programming procedure representing logical states such as “00,” “01,” “10,” and “11,” and curves (e.g., threshold voltage distributions 520, 521, 522, 523, 524, 525, 526, and 527 (i.e., 520 to 527)) show the threshold voltage distribution of memory cells after a previous 1-page programming procedure.

[0156] After the lower and upper pages are programmed, Fig.19 As shown in , a memory cell can have any one of eight data states E (erased) and P1, P2, P3, P4, P5, P6, and P7 (ie, P1 to P7).

[0157] exist Fig.19 In the case of the method shown in , the memory cells in threshold voltage distribution 510 are programmed to threshold voltage distribution 520 or threshold voltage distribution 521 after the next 2 pages of programming, and the memory cells in threshold voltage distribution 511 are programmed to threshold voltage distribution 522 or threshold voltage distribution 523 after the next 2 pages of programming. The memory cells in threshold voltage distribution 512 are programmed to threshold voltage distribution 524 or threshold voltage distribution 525 after the next 2 pages of programming, and the memory cells in threshold voltage distribution 513 are programmed to threshold voltage distribution 526 or threshold voltage distribution 527 after the next 2 pages of programming.

[0158] Fig. 20 A programming method for reducing word line coupling is shown which is performed under the assumption that each memory cell stores 3 bits of data.

[0159] exist Fig. 20 , curves (e.g., threshold voltage distributions 530, 531, 532, and 533 (i.e., 530 to 533)) show the threshold voltage distributions of the memory cells after the next 2-page programming procedure, and curves (threshold voltage distributions 540, 541, 542, 543, 544, 545, 546, and 547 (i.e., 540 to 547)) show the threshold voltage distributions of the memory cells after the previous 1-page programming procedure. After the next and previous pages are programmed, as shown in FIG. Fig. 20 As shown in , the memory cell can have any one of eight data states E and P1 to P7.

[0160] exist Fig. 20 In the case of the method shown in , the memory cells in threshold voltage distribution 530 are programmed to threshold voltage distribution 540 or threshold voltage distribution 541 after the next 2 pages of programming, and the memory cells in threshold voltage distribution 531 are programmed to threshold voltage distribution 542 or threshold voltage distribution 543 after the next 2 pages of programming. The memory cells in threshold voltage distribution 532 are programmed to threshold voltage distribution 544 or threshold voltage distribution 545 after the next 2 pages of programming, and the memory cells in threshold voltage distribution 533 are programmed to threshold voltage distribution 546 or threshold voltage distribution 547 after the next 2 pages of programming.

[0161] Fig. 20 The programming method described in Fig.19 The programming method described in is different in that a negative verify voltage is used. Fig.19 In the case of the programming method described in , the verification voltages corresponding to the programming states P1 to P7 can be set to positive voltages, respectively. In other words, each of the programming states P1 to P7 can be judged when a positive voltage is applied to the selected word line. On the other hand, in Fig. 20 In the case of the programming method described in , the verification voltages corresponding to the programming states P1 and P2, respectively, may be set to negative voltages, and the verification voltages corresponding to the programming states P3 to P7, respectively, may be set to positive voltages. In other words, one or more of the programming states P1 to P7 may be judged when a negative voltage is applied to the selected word line. It will be well understood that the number of programming states (or data states) judged by a negative voltage is not limited to the present disclosure.

[0162] Fig.21 is a diagram showing threshold voltage distributions associated with memory cells of a kth word line before and after word line coupling caused when memory cells of a k-1th word line are programmed.

[0163] Fig.21The example in shows two adjacent threshold voltage distributions 610 and 620 associated with memory cells of the kth word line (ie, the second word line) before programming of memory cells of the k-1th word line (the third word line) (ie, before word line coupling).

[0164] exist Fig.21 In FIG. 1 , two threshold voltage distributions are shown. However, the skilled person will appreciate that more threshold voltage distributions may be provided depending on the number of bits per cell. The number of threshold voltage distributions may be determined based on the number of bits of data stored in the memory cell. For example, when p-bit data (p is an integer of 2 or greater) is stored in the memory cell, two threshold voltage distributions may be provided. The threshold voltage distributions 610 and 620 may be determined using a read voltage VRD between the threshold voltage distributions 610 and 620. Although not shown in FIG. 1 , the threshold voltage distributions 610 and 620 may be determined using a read voltage VRD between the threshold voltage distributions 610 and 620. Fig.21 , but the remaining threshold voltage distributions can be judged using the read voltages between adjacent threshold voltage distributions. This read operation is named a normal read operation, and the read voltage VRD used in the normal read operation is named a normal read voltage.

[0165] Fig.21 611 and 621 in show threshold voltage distributions associated with memory cells of the k-th word line after experiencing word line coupling caused when memory cells of the k-1-th word line are programmed. Threshold voltage distributions 611 and 621 may include threshold voltage distributions associated with memory cells that experience word line coupling and memory cells that do not experience word line coupling when memory cells of the k-1-th word line are programmed.

[0166] Fig. 22 The diagram shows a coupled memory cell and an uncoupled memory cell. Fig.21 A diagram of the full threshold voltage distribution in .

[0167] exist Fig. 22 In the example of , threshold voltage distributions 613 and 623 show the threshold voltage distribution of memory cells (or uncoupled memory cells) that do not experience a threshold voltage shift due to word line coupling. Threshold voltage distributions 615 and 625 show the threshold voltage distribution of memory cells (or coupled memory cells) that experience a threshold voltage shift due to word line coupling. That is, threshold voltage distributions 615 and 625 indicate the threshold voltage shift of memory cells programmed to data states SDT1 and SDT2.

[0168] The programmed memory cells of the kth word line may belong to the uncoupled threshold voltage distributions 613 and 623 or the coupled threshold voltage distributions 615 and 625 based on the threshold voltage shift caused by the programming of the memory cells of the k-1th word line. Fig. 22As shown in , the first recovery read voltage VDR1 can be used to read uncoupled memory cells, that is, to distinguish memory cells within threshold voltage distributions 613 and 623. The second recovery read voltage VDR2 can be used to read coupled memory cells, that is, to distinguish memory cells within threshold voltage distributions 615 and 625.

[0169] Two read operations can be performed for a threshold voltage distribution (or data state) (formed by a coupled distribution and an uncoupled distribution) using a first recovery read voltage VDR1 and a second recovery read voltage VDR2, so as to reduce the read error caused by word line coupling. The number of read operations performed for one data state can be determined according to the number of groups formed by the interference cells (or the programming state caused by coupling). For example, the interference cells constitute one group or two or more groups. If the interference cells constitute one group, the read operation can be performed twice, once for the uncoupled nth word line, and once for the coupled nth word line. If the interference cells constitute two groups, the read operation can be performed three times, once for the uncoupled nth word line, and twice for the coupled nth word lines of the two groups.

[0170] Referring to the diagram showing a read operation performed when the interference units constitute a group Fig. 22 , a read operation using the first recovery read voltage VDR1 is performed to distinguish memory cells within the uncoupled distributions 613 and 623 , and a read operation using the second recovery read voltage VDR2 is performed to distinguish memory cells within the coupled distributions 615 and 625 .

[0171] The first sensing data SDT1 is read from the kth word line based on the first recovery read voltage VDR1 and is latched in Fig.10 The first sensing data SDT1 and the second sensing data SDT2 are selected as hard decision data based on the programming state of the third sensing data, and the second sensing data SDT2 is latched in the second latch of the page buffer in the page buffer circuit 410. The second sensing data SDT2 is read from the k-th word line based on the second recovery read voltage VDR2, and the second sensing data SDT2 is latched in the second latch of the page buffer in the page buffer circuit 410. The third sensing data is read from the k-1-th word line (i.e., the interference word line) based on the adjacent read voltage, and the third sensing data is latched in the third latch of the page buffer in the page buffer circuit 410. One of the first sensing data SDT1 and the second sensing data SDT2 is selected as hard decision data based on the programming state of the third sensing data, and Fig.14 The data processor 440 in FIG. 4 may generate the soft decision data SDRD by performing an XOR operation on the first sensing data SDT1 and the second sensing data SDT2 .

[0172] Memory cells to be read using the first recovery read voltage VDR1 and memory cells to be read using the second recovery read voltage VDR2 may be divided based on data read from memory cells of a disturbed word line.

[0173] In one example, in the case of 3-bit data, if the interference cells constitute a group, the interference cells may be programmed to have Fig.19 and Fig. 20 In another example, in the case of 3-bit data, if the interfering cells constitute a group, the interfering cells may be programmed to have Fig.19 and Fig. 20 If the interfering cells constitute two groups, the interfering cells may be memory cells programmed to have at least three of the programming states shown in FIG. Fig.19 The memory cells of the programming state P1 in the program state and the remaining programming states P2 to P7 therein. However, the programming state for defining the group of interference cells is not limited thereto. For example, the programming state for defining the group of interference cells can be determined differently according to the programming mode and the coupling level.

[0174] In addition, Fig. 22 , when the threshold voltage distributions 611 and 621 are threshold voltage distributions representing lower program states, as the time (retention time) after the program operation performed on the memory cells is completed increases, the threshold voltage distributions 611 and 621 associated with the memory cells of the k-th word line tend to widen toward the positive direction (i.e., increasing direction) of the threshold voltage Vth. As the retention time increases, the threshold voltage distributions 611 and 621 tend to widen in the negative direction (i.e., decreasing direction) along the threshold voltage Vth.

[0175] Furthermore, the amount of widening of threshold voltage distributions 611 and 621 associated with memory cells of the kth word line may depend on the programmed states of memory cells of the (k-1)th word line.

[0176] Fig.23A , Fig. 23B and Fig.23C is a diagram illustrating an example of grouping memory cells in a method of controlling an operation of a nonvolatile memory device.

[0177] Fig.23A A selected word line WLsel and one disturbing word line WLa adjacent to the selected word line WLsel are shown. The selected word line WLsel may include a plurality of selected memory cells CE1 to CE9, and the disturbing word line WLa may include a plurality of disturbing memory cells CE1' to CE9' adjacent to the selected memory cells CE1 to CE9, respectively.

[0178] Fig. 23B An example is shown in which the interfering memory cells of the interfering word line WLa are grouped into two interfering cell groups (i.e., a first interfering cell group G1' and a second interfering cell group G2') based on one adjacent read voltage VAD. The first interfering cell group G1' may include interfering memory cells having a relatively low threshold voltage, and the second interfering cell group G2' may include interfering memory cells having a relatively high threshold voltage.

[0179] For example, Fig.23A As shown in FIG. 1 , the interfering memory cells CE2 ′, CE5 ′, CE6 ′, and CE7 ′ may be included in the first interfering cell group G1 ′, and the interfering memory cells CE1 ′, CE3 ′, CE4 ′, CE8 ′, and CE9 ′ may be included in the second interfering cell group G2 ′.

[0180] The selected memory cells CE1 to CE9 of the selected word line WLsel may be grouped into corresponding selected cell groups according to corresponding disturbing cell groups of disturbing memory cells adjacent to the selected memory cell. Fig.23A In the example, selected memory cells CE2, CE5, CE6 and CE7 corresponding to the interfering memory cells CE2', CE5', CE6' and CE7' of the first interfering unit group G1' may be included in the first selected unit group G1, and selected memory cells CE1, CE3, CE4, CE8 and CE9 corresponding to the interfering memory cells CE1', CE3', CE4', CE8' and CE9' of the second interfering unit group G2' may be included in the second selected unit group G2.

[0181] Fig.23C An example is shown in which the interfering memory cells of the interfering word line are grouped into three interfering cell groups (i.e., a first interfering cell group G1', a second interfering cell group G2', and a third interfering cell group G3') based on two adjacent read voltages VAD1 and VAD2. In this way, the interfering memory cells can be grouped into first to third interfering cell groups G1' to G3' having different threshold voltage ranges based on the first adjacent read voltage VAD1 and the second adjacent read voltage VAD2.

[0182] When two or more adjacent read voltages are applied to the interference word line WLa, a first read operation is performed on the selected word line WLsel by applying three or more recovery read voltages to the selected word line WLsel, and three or more sense data may be latched in the first latch of the page buffer of the page buffer circuit 410. In addition, a second read operation is performed on the interference word line WLa, and two or more decision data may be latched in the second latch of the page buffer of the page buffer circuit 410.

[0183] The control circuit 450 may control the read operation by selecting one of three or more sensing data as hard decision data and by generating soft decision data based on the three or more sensing data.

[0184] Fig.24A is a circuit diagram showing the structure of a memory cell array, and Fig. 24B is shown with Fig.24A A three-dimensional diagram of a memory block corresponding to the structure.

[0185] For ease of explanation, Fig.24A A memory block including cell strings connected to one bit line BL and one common source line CSL is shown, but a skilled person will appreciate that a memory block may have a plurality of cell strings connected to one bit line BL and one common source line CSL. Fig.11 and Fig.12 A three-dimensional structure of multiple bit lines is described.

[0186] Reference Fig.24A and Fig. 24B , the memory block includes a plurality of cell strings STR1, STR2, ..., STRm connected between the bit line BL and the common source line CSL. The cell strings STR1, STR2, ..., STRm may respectively include string selection transistors SST1, SST2, ..., SSTm controlled by string selection lines SSL1, SSL2, ..., SSLm, memory cells controlled by word lines WL, pseudo memory cells DMC11, DMC12, ..., DMC1m controlled by pseudo word lines, and ground selection transistors GST1, GST2, ..., GSTm controlled by ground selection lines GSL. The plurality of cell strings STR1, STR2, ..., STRm may be divided into a first stack ST1 and a second stack ST2 along a vertical direction VD. The second stack ST2 is disposed at a position higher than the first stack ST1 in the vertical direction VD. The memory cells coupled to at least one word line located at the edge of each of the first stack ST1 and the second stack ST2 may be pseudo memory cells. The dummy memory cells may not store valid data or may store smaller bits of data than other memory cells.

[0187] Dummy memory cells DMC11 , DMC12 , . . . , DMC1 m may be included in the second stack ST1 .

[0188] Fig.24A An example is shown in which the ground selection transistors GST1, GST2, ..., GSTm are connected to the same ground selection line GSL. In other examples, the ground selection transistors are connected to corresponding ground selection lines.

[0189] In some embodiments, Fig.24AAs shown in FIG. 1 , the boundary portion BND may include one gate line corresponding to the dummy word line DWL that simultaneously activates the dummy memory cells DMC11 , DMC12 , . . . , DMC1 m connected thereto.

[0190] In some embodiments, Fig. 24B As shown in , the boundary portion BND may include two gate lines corresponding to dummy word lines DWL11 and DWL12. The dummy word line DWL11 may be included in the first stack ST1, and the dummy word line DWL12 may be included in the second stack ST2.

[0191] That is, the memory block may be implemented in a multi-stack structure including two or more stacks, and a dummy word line is placed at a boundary of the stack.

[0192] exist Fig.24A and Fig. 24B In the embodiment, although the memory block includes the first stack ST1 and the second stack ST2 , the memory block may include three or more stacks in other embodiments.

[0193] Fig.25 is a cross-sectional view of an example of a boundary portion included in a memory block.

[0194] Reference Fig.25 , the channel hole of each cell string STR may include a first sub-channel hole 640 and a second sub-channel hole 650. The channel hole may be referred to as a pillar. The first sub-channel hole 640 may include a channel layer 641, an internal material 642, and an insulating layer 643. The second sub-channel hole 650 may include a channel layer 651, an internal material 652, and an insulating layer 653. The channel layer 641 of the first sub-channel hole 640 may be connected to the channel layer 651 of the second sub-channel hole 650 through a P-type silicon pad SIP. The sub-channel holes 640 and 650 may be formed using a stop layer GTL5 having an appropriate etching rate. For example, the stop layer GTL5 may be formed of polysilicon, and the other gate lines GTL1 to GTL4 and GTL6 to GTL8 may be formed of a metal such as tungsten to implement an appropriate etching rate.

[0195] The above-mentioned boundary portion BND may correspond to the stop layer GTL5 for forming a plurality of sub-channel holes. The cell in the stop layer GTL5 may not be suitable for storing data, and the stop layer may be used as the boundary portion BND to form a pseudo memory cell. The examples in the present disclosure are not limited to the boundary portion of one stop layer, and the boundary portion may include two or more gate layers.

[0196] The dummy memory cell may be implemented with a cell type or a transistor type. The cell type may include a floating gate as a flash memory cell, and the transistor type may not include a floating gate.

[0197] Fig.26A and Fig.26B is a timing diagram illustrating a data recovery read operation when programming proceeds from a string selection line to a substrate.

[0198] The way in which programming is performed from top to bottom is called top-to-bottom (T2B) programming. Fig.26A An example is shown where the next word line is a normal word line, and Fig.26B An example is shown in which the next word line is a dummy word line.

[0199] Reference Fig.26A , the k+1th word line WLk+1 is the previous word line, the kth word line WLk is the selected word line, and the k-1th word line WLk-1 is the next word line. Fig.10 ) can perform a first read operation on the kth word line.

[0200] During the first read operation on the selected word line, the first recovery read voltage VDR1 and the second recovery read voltage VDR2 may be provided to the kth word line, and the first sensing data and the second sensing data may be obtained. The pass voltage VPASS may be provided to the adjacent word lines WLk+1 and WLk-1. After the first read operation, a second read operation may be performed to compensate for the threshold voltage of the selected word line.

[0201] After the first read operation, the nonvolatile memory device 400 may detect the current interference level of the selected word line through an additional sensing operation (second read operation), and may compensate for the interference based on the monitoring result. In this case, the word line for this additional sensing operation is the interference word line and is Fig.26A The k-1th word line WLk-1 in FIG. The adjacent read voltage VAD for determining the compensation level may be provided to the k-1th word line WLk-1. In this case, the pass voltage VPASS may be applied to the k+1th word line WLk+1, and the pass voltage VPSS may be applied to the kth word line WLk.

[0202] The third sensing data may be obtained through the second read operation, and one of the first sensing data and the second sensing data may be selected as hard decision data based on a program state of the third sensing data.

[0203] Reference Fig.26B , the k+1th word line WLk+1 is the previous word line, the kth word line WLk is the selected word line, and the k-1th word line WLk-1 is the next word line. Fig.26B In the example of , the next word line is a dummy word line DWL.

[0204] After the first read operation on the selected word line, a second read operation may be performed to compensate for the threshold voltage of the selected word line. In this case, the word line for the second read operation is the interference word line. When the next word line is a dummy word line, the interference word line is the previous word line and is Fig.26B The k+1th word line WLk+1 in .

[0205] An adjacent read voltage VAD for determining a compensation level may be provided to the k+1th word line WLk+1. In this case, a pass voltage VPASS may be applied to the k-1th word line WLk-1 and the kth word line WLk.

[0206] The third sensing data may be obtained through the second read operation, and one of the first sensing data and the second sensing data may be selected as hard decision data based on a program state of the third sensing data.The threshold voltage of the selected word line may be distorted due to lateral expansion caused by the previous word line WLk+1.

[0207] exist Fig.26A and Fig.26B , the k+1th word line WLk+1 is the first word line, the kth word line WLk is the second word line, and the k-1th word line WLk-1 is the third word line.

[0208] In addition, when Fig.26A and Fig.26B When programming proceeds from the substrate SUB to the string selection line SSL, the k-1th word line WLk+1 is the previous word line, the kth word line WLk is the selected word line, and the k+1th word line WLk+1 is the next word line.

[0209] Fig. 27 is a diagram of a read operation on a selected word line.

[0210] Reference Fig.15 and Fig. 27 , the read operation on the selected word line may include a bit line precharge period BLPRECHARGE 661, a sense node development period SO DEVELOP 662, a latch period LATCH 663, a sense node precharge period SO PRECHARGE 664, a sense node development period SO DEVELOP 665, and a latch period LATCH 666. The read operation on the selected word line may also include a bit line recovery period after the latch period LATCH 666.

[0211] During the bit line precharge period BL PRECHARGE 661 , the bit line BL is precharged at a predetermined voltage level by the precharge circuit PC, and the sense node SO is precharged at the power supply voltage Vdd.

[0212] During the sensing node development period 662, current supply from the precharge circuit PC to the sensing node SO may be blocked, and the transistors TR_hv, NM5, and NM6 may be turned on. In this case, the sensing node SO may be developed.

[0213] In the latch period 663 after the sense node development period 662, a latch operation may be performed via the latch SL, and the first sense data of the memory cell of the selected word line is latched in the latch FL. The sense node SO may be precharged in the sense node precharge period 664 after the latch period 663. During the sense node development period 665, the current supply from the precharge circuit PC to the sense node SO may be blocked, and the transistors TR_hv, NM5, and NM6 may be turned on. In this case, the sense node SO may be developed. In the latch period 666 after the sense node development period 665, a latch operation may be performed via the latch SL, and the second sense data of the memory cell of the selected word line is latched in the latch ML.

[0214] Therefore, according to the nonvolatile memory device and the method for controlling the operation of the nonvolatile memory device, hard decision data and soft decision data for compensating for the coupling of the selected word line can be generated through one read operation, and ECC decoding can be performed based on the hard decision data and the soft decision data. Therefore, the error correction capability can be enhanced.

[0215] Fig.28A is a flow chart illustrating a method of operating a memory system.

[0216] Fig.28A A method of operating a memory system is shown, the memory system comprising: a nonvolatile memory device including a memory block, the memory block including a plurality of cell strings, wherein each cell string includes a string selection transistor connected between each of a plurality of bit lines and a common source line, a plurality of memory cells, and a ground selection transistor; and a memory controller for controlling the nonvolatile memory device.

[0217] Reference Fig.28A , by performing a first read operation on a selected word line designated by an access address among a plurality of word lines of a memory block based on a read voltage setting, first sensing data and second sensing data are latched in a page buffer circuit connected to a plurality of cell strings through a plurality of bit lines (operation S610). By performing a second read operation on an interference word line adjacent to the selected word line based on at least one adjacent read voltage, third sensing data are latched in the page buffer circuit (operation S620).

[0218] One of the first sensing data and the second sensing data is selected as hard decision data based on the programming state of the third sensing data (operation S630). The hard decision data is output to the external memory controller (operation S640). The first sensing data and the second sensing data are output to the external memory controller (operation S650).

[0219] Soft decision data is generated by using the first sensing data and the second sensing data in the memory controller (operation S660). The memory controller may generate the soft decision data by performing one of an XOR operation and an XOR operation on the first sensing data and the second sensing data. An ECC engine in the memory controller performs ECC decoding on the hard decision data and the soft decision data (operation S670).

[0220] Fig.28B is a flow chart illustrating a method of operating a memory system.

[0221] Fig.28B A method of operating a memory system is shown, the memory system comprising: a nonvolatile memory device including a memory block, the memory block including a plurality of cell strings, wherein each cell string includes a string selection transistor connected between each of a plurality of bit lines and a common source line, a plurality of memory cells, and a ground selection transistor; and a memory controller for controlling the nonvolatile memory device.

[0222] Reference Fig.28B , by performing a first read operation on a selected word line designated by an access address among a plurality of word lines of a memory block based on a read voltage setting, first sensing data and second sensing data are latched in a page buffer circuit connected to a plurality of cell strings through a plurality of bit lines (operation S710). By performing a second read operation on an interference word line adjacent to the selected word line based on at least one adjacent read voltage, third sensing data are latched in the page buffer circuit (operation S720).

[0223] One of the first sensing data and the second sensing data is selected as hard decision data based on the programming state of the third sensing data (operation S730). The data processor 440 generates soft decision data by using the first sensing data and the second sensing data (operation S740). The hard decision data is output to the external memory controller (operation S750).

[0224] The ECC decoder in the memory controller performs a first ECC decoding based on the hard decision data (operation S760). When the first ECC decoding fails, the memory controller sends a request for soft decision data to the nonvolatile memory device 400 (operation S770). The nonvolatile memory device 400 sends the soft decision data to the memory controller in response to the request and the ECC decoder in the memory controller performs a second ECC decoding based on the soft decision data (operation S780).

[0225] Fig.29 is a block diagram illustrating an example of an ECC decoder.

[0226] The nonvolatile memory device 400 may perform a read operation including a hard decision read operation and / or a soft decision read operation on a plurality of sectors in a target page. When a default read voltage is applied to a target word line, the hard decision read operation reads hard decision data stored in a memory cell as 1 or 0, depending on whether the memory cell coupled to the target word line is a cell turned on or off. The ECC decoder 320 in the memory controller 200 may perform hard decision type error correction based on the hard decision data and an error correction code (i.e., an LDPC code). When an offset read voltage having an offset relative to the default read voltage is applied to the target word line, the soft decision read operation reads soft decision data having reliability information about the hard decision data from the memory cell coupled to the target word line. The ECC decoder 320 may perform soft decision type error correction based on the hard decision data, the reliability information about the hard decision data, and the error correction code (i.e., an LDPC code).

[0227] Reference Fig.29 , the ECC decoder 320 includes an input manager 330 , a pre-decoder 350 , a main decoder 360 , and an output manager 390 .

[0228] The input manager 330 may sequentially receive the hard decision data HDRD and the soft decision data SDRD read from a plurality of sectors of a target page in units of sectors.

[0229] The predecoder 350 may sequentially receive the hard decision data HDRD in parallel with the input manager 330 receiving the hard decision data HDRD in units of sectors, may sequentially generate syndromes SDR of the hard decision data HDRD, and may provide the syndromes SDR to the main decoder 360 .

[0230] The main decoder 360 may sequentially receive the hard decision data HDRD from the input manager 330, may sequentially perform first ECC decoding on the hard decision data HDRD in sectors based on corresponding syndromes SDR, and may determine pass / fail of the first ECC decoding on each of the hard decision data HDRD.

[0231] In response to a failure in the first ECC decoding of the hard decision data HDRD, the input manager 330 may perform a second ECC decoding on the soft decision data SDRD corresponding to the hard decision data HDRD and may provide a result DRD of the second ECC decoding to the output manager 390 .

[0232] The output manager 390 may output decoded data CD or a read error message ERR based on the result DRD of the second ECC decoding.

[0233] Fig.30 is a block diagram illustrating a storage device including a nonvolatile memory device.

[0234] Reference Fig.30 , the storage device 1000 includes a plurality of non-volatile memory devices (NVM) 1100 and a controller 1200. For example, the storage device 1000 may be any storage device such as an embedded multimedia card (eMMC), a universal flash memory (UFS), a solid state disk or a solid state drive (SSD).

[0235] Controller 1200 may be connected to nonvolatile memory device 1100 via a plurality of channels CCH1, CCH2, CCH3, . . . , CCHk. Controller 1200 may include one or more processors 1210, buffer memory 1220, error correction code (ECC) engine 1230, host interface 1250, and nonvolatile memory (NVM) interface 1260.

[0236] The buffer memory 1220 may store data used to drive the controller 1200. The ECC engine 1230 may calculate an error correction code value of data to be programmed during a programming operation, and may use the error correction code value to correct errors of read data during a read operation. In a data recovery operation, the ECC engine 1230 may correct errors of data recovered from the nonvolatile memory device 1100. The host interface 1250 may provide an interface with an external device. The nonvolatile memory interface 1260 may provide an interface with the nonvolatile memory device 1100.

[0237] In some embodiments, each of the nonvolatile memory devices 1100 may correspond to a nonvolatile memory device and may be optionally supplied with an external high voltage VPP.

[0238] Fig.31 is a cross-sectional view of a nonvolatile memory device.

[0239] Reference Fig.31, the nonvolatile memory device (or memory device) 5000 has a chip-to-chip (C2C) structure. At least one upper chip including a cell area and a lower chip including a peripheral circuit area PREG can be manufactured separately, and then, at least one upper chip and the lower chip can be connected to each other by a bonding method to realize a C2C structure. For example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0240] The memory device 5000 may include at least one upper chip having a cell region. Fig.31 As shown in , the memory device 5000 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 5000 includes two upper chips, a first upper chip including a first cell region CREG1, a second upper chip including a second cell region CREG2, and a lower chip including a peripheral circuit region PREG may be manufactured separately. The first upper chip, the second upper chip, and the lower chip may then be connected to each other by a bonding method to manufacture the memory device 5000. The first upper chip may be flipped and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first upper chip and the second upper chip will be defined based on before each of the first upper chip and the second upper chip is flipped. In other words, the upper portion of the lower chip may represent an upper portion defined based on the positive third direction VD, and the upper portion of each of the first upper chip and the second upper chip may represent an upper portion defined based on the positive third direction VD. Fig.31 The upper portion is defined by the negative third direction VD in the embodiment. However, the bonding method of the present disclosure is not limited thereto. In some embodiments, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0241] Each of the peripheral circuit region PREG and the first and second cell regions CREG1 and CREG2 of the memory device 5000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0242] The peripheral circuit region PREG may include a first substrate 5210 and a plurality of circuit elements 5220a, 5220b, and 5220c formed on the first substrate 5210. An interlayer insulating layer 5215 including one or more insulating layers may be provided on the plurality of circuit elements 5220a, 5220b, and 5220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 5220a, 5220b, and 5220c may be provided in the interlayer insulating layer 5215. For example, the plurality of metal lines may include first metal lines 5230a, 5230b, and 5230c connected to the plurality of circuit elements 5220a, 5220b, and 5220c, and second metal lines 5240a, 5240b, and 5240c formed on the first metal lines 5230a, 5230b, and 5230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 5230a, 5230b, and 5230c may be formed of tungsten having a relatively high resistivity, and the second metal lines 5240a, 5240b, and 5240c may be formed of copper having a relatively low resistivity.

[0243] In this example, the first metal lines 5230a, 5230b, and 5230c and the second metal lines 5240a, 5240b, and 5240c are shown and described. However, the examples of the present disclosure are not limited thereto. In some embodiments, at least one or more additional metal lines may also be formed on the second metal lines 5240a, 5240b, and 5240c. In this case, the second metal lines 5240a, 5240b, and 5240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 5240a, 5240b, and 5240c may be formed of copper having a resistivity lower than the resistivity of the aluminum of the second metal lines 5240a, 5240b, and 5240c.

[0244] The interlayer insulating layer 5215 may be disposed on the first substrate 5210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0245] Each of the first cell region CREG1 and the second cell region CREG2 may include at least one memory block. The first cell region CREG1 may include a second substrate 5310 and a common source line 5320. A plurality of word lines 5330 (5331 to 5338) may be stacked on the second substrate 5310 in a third direction VD perpendicular to the top surface of the second substrate 5310. A string selection line and a ground selection line may be disposed on and below the word line 5330, and a plurality of word lines 5330 may be disposed between the string selection line and the ground selection line. Similarly, the second cell region CREG2 may include a third substrate 5410 and a common source line 5420, and a plurality of word lines 5430 (5431 to 5438) may be stacked on the third substrate 5410 in a direction perpendicular to the top surface of the third substrate 5410 (e.g., a Z-axis direction). Each of the second substrate 5310 and the third substrate 5410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CREG1 and the second cell region CREG2.

[0246] In some embodiments, as shown in region "A1", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 5310 to penetrate the word line 5330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 5350c and the second metal line 5360c in the bit line bonding region BLBA. For example, the second metal line 5360c may be a bit line and may be connected to the channel structure CH through the first metal line 5350c. The bit line 5360c may extend in a second direction HD2 parallel to the top surface of the second substrate 5310.

[0247] In some embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 5310 to penetrate the common source line 5320 and the lower word lines 5331 and 5332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 5333 to 5338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer of the upper channel UCH may be electrically connected to the first metal line 5350c and the second metal line 5360c. As the length of the channel increases, it may be difficult to form a channel having a substantially uniform width due to the characteristics of the manufacturing process. In some embodiments, the memory device 5000 may include channels having improved width uniformity due to the formation of the lower channel LCH and the upper channel UCH through sequentially performed processes.

[0248] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in area "A2", a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a pseudo word line. For example, word lines 5332 and 5333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be pseudo word lines. In this case, data may not be stored in memory cells connected to the pseudo word lines. Alternatively, the number of pages corresponding to memory cells connected to the pseudo word lines may be less than the number of pages corresponding to memory cells connected to ordinary word lines. The level of the voltage applied to the pseudo word line may be different from the level of the voltage applied to the ordinary word line, and thus it is possible to reduce the effect of the non-uniform channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device.

[0249] At the same time, in region "A2", the number of lower word lines 5331 and 5332 penetrated by the lower channel LCH is less than the number of upper word lines 5333 to 5338 penetrated by the upper channel UCH. However, the present disclosure is not limited thereto. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationships of the channel structure CH disposed in the second cell region CREG2 may be substantially the same as the structural features and connection relationships of the channel structure CH disposed in the first cell region CREG1.

[0250] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell region CREG1, and the second through electrode THV2 may be disposed in the second cell region CREG2. Fig.31 As shown in , the first through electrode THV1 may penetrate the common source line 5320 and the plurality of word lines 5330. In some embodiments, the first through electrode THV1 may also penetrate the second substrate 5310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0251] In some embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 5372d and the second through metal pattern 5472d. The first through metal pattern 5372d may be formed at the bottom end of the first upper chip including the first cell region CREG1, and the second through metal pattern 5472d may be formed at the top end of the second upper chip including the second cell region CREG2. The first through electrode THV1 may be electrically connected to the first metal line 5350c and the second metal line 5360c. The second through electrode THV2 may be electrically connected to the first metal line 5450c and the second metal line 5460c. For example, the second metal line 5460c may be a bit line and may be connected to the channel structure CH through the first metal line 5450c. The lower via 5371d may be formed between the first through electrode THV1 and the first through metal pattern 5372d, and the upper via 5471d may be formed between the second through electrode THV2 and the second through metal pattern 5472d. The first through metal pattern 5372d and the second through metal pattern 5472d may be connected to each other by a bonding method.

[0252] In addition, in the bit line bonding area BLBA, an upper metal pattern 5252 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 5392 having the same shape as the upper metal pattern 5252 may be formed in the uppermost metal layer of the first cell area CREG1. The upper metal pattern 5392 of the first cell area CREG1 and the upper metal pattern 5252 of the peripheral circuit area PREG may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 5360c may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some of the circuit elements 5220c of the peripheral circuit area PREG may constitute a page buffer, and the bit line 5360c may be electrically connected to the circuit element 5220c constituting the page buffer through the upper bonding metal pattern 5370c of the first cell area CREG1 and the upper bonding metal pattern 5270c of the peripheral circuit area PERI.

[0253] Continue to refer to Fig.31, in the word line bonding area WLBA, the word lines 5330 of the first cell region CREG1 may extend in the first direction HD1 parallel to the top surface of the second substrate 5310, and may be connected to a plurality of cell contact plugs 5340 (5341 to 5347). The first metal line 5350b and the second metal line 5360b may be sequentially connected to the cell contact plugs 5340 connected to the word lines 5330. In the word line bonding area WLBA, the cell contact plugs 5340 may be connected to the peripheral circuit region PREG through the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PERI.

[0254] The cell contact plug 5340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some of the circuit elements 5220b of the peripheral circuit region PREG may constitute a row decoder, and the cell contact plug 5340 may be electrically connected to the circuit element 5220b constituting the row decoder through the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PERI. In some embodiments, the operating voltage of the circuit element 5220b constituting the row decoder may be different from the operating voltage of the circuit element 5220c constituting the page buffer. For example, the operating voltage of the circuit element 5220c constituting the page buffer may be greater than the operating voltage of the circuit element 5220b constituting the row decoder.

[0255] Likewise, in the word line bonding area WLBA, the word lines 5430 of the second cell region CREG2 may extend in the first direction HD1 parallel to the top surface of the third substrate 5410 and may be connected to a plurality of cell contact plugs 5440 (5441 to 5447). The cell contact plugs 5440 may be connected to the peripheral circuit region PREG through the upper metal pattern of the second cell region CREG2 and the lower and upper metal patterns and the cell contact plugs 5348 of the first cell region CREG1.

[0256] In the word line bonding area WLBA, the upper bonding metal pattern 5370b may be formed in the first cell region CREG1, and the upper bonding metal pattern 5270b may be formed in the peripheral circuit region PERI. The upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG may be electrically connected to each other by a bonding method. The upper bonding metal pattern 5370b and the upper bonding metal pattern 5270b may be formed of aluminum, copper, or tungsten.

[0257] In the external pad bonding area PA, the lower metal pattern 5371e may be formed in the lower portion of the first unit region CREG1, and the upper metal pattern 5472a may be formed in the upper portion of the second unit region CREG2. The lower metal pattern 5371e of the first unit region CREG1 and the upper metal pattern 5472a of the second unit region CREG2 may be connected to each other by a bonding method in the external pad bonding area PA. Similarly, the upper metal pattern 5372a may be formed in the upper portion of the first unit region CREG1, and the upper metal pattern 5272a may be formed in the upper portion of the peripheral circuit region PERI. The upper metal pattern 5372a of the first unit region CREG1 and the upper metal pattern 5272a of the peripheral circuit region PREG may be connected to each other by a bonding method.

[0258] The common source line contact plugs 5380 and 5480 may be disposed in the external pad bonding area PA. The common source line contact plugs 5380 and 5480 may be formed of a conductive material such as a metal, a metal compound, and / or doped polysilicon. The common source line contact plug 5380 of the first cell region CREG1 may be electrically connected to the common source line 5320, and the common source line contact plug 5480 of the second cell region CREG2 may be electrically connected to the common source line 5420. The first metal line 5350a and the second metal line 5360a may be sequentially stacked on the common source line contact plug 5380 of the first cell region CREG1, and the first metal line 5450a and the second metal line 5460a may be sequentially stacked on the common source line contact plug 5480 of the second cell region CREG2.

[0259] The input / output pads 5205, 5405, and 5406 may be disposed in the external pad bonding area PA. Fig.31 , a lower insulating layer 5201 may cover the bottom surface of the first substrate 5210, and a first input / output pad 5205 may be formed on the lower insulating layer 5201. The first input / output pad 5205 may be connected to at least one of a plurality of circuit elements 5220a provided in the peripheral circuit region PREG through a first input / output contact plug 5203, and may be separated from the first substrate 5210 by the lower insulating layer 5201. In addition, a side insulating layer may be provided between the first input / output contact plug 5203 and the first substrate 5210 to electrically isolate the first input / output contact plug 5203 from the first substrate 5210.

[0260] An upper insulating layer 5401 covering the top surface of the third substrate 5410 may be formed on the third substrate 5410. Second input / output pads 5405 and / or third input / output pads 5406 may be disposed on the upper insulating layer 5401. The second input / output pads 5405 may be connected to at least one of the plurality of circuit elements 5220a disposed in the peripheral circuit region PREG through second input / output contact plugs 5403 and 5303, and the third input / output pads 5406 may be connected to at least one of the plurality of circuit elements 5220a disposed in the peripheral circuit region PREG through third input / output contact plugs 5404 and 5304.

[0261] In some embodiments, the third substrate 5410 may not be disposed in a region in which the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 5404 may be separated from the third substrate 5410 in a direction parallel to the top surface of the third substrate 5410, and may penetrate the interlayer insulating layer 5415 of the second cell region CREG2 to be connected to the third input / output pad 5406. In this case, the third input / output contact plug 5404 may be formed by at least one of various processes.

[0262] In some embodiments, as shown in region "B1", the third input / output contact plug 5404 may extend in the third direction VD, and the diameter of the third input / output contact plug 5404 may gradually increase toward the upper insulating layer 5401. In other words, the diameter of the channel structure CH described in region "A1" may gradually decrease toward the upper insulating layer 5401, but the diameter of the third input / output contact plug 5404 may gradually increase toward the upper insulating layer 5401. For example, the third input / output contact plug 5404 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded to each other by a bonding method.

[0263] In some embodiments, as shown in region "B2", the third input / output contact plug 5404 may extend in the third direction VD, and the diameter of the third input / output contact plug 5404 may gradually decrease toward the upper insulating layer 5401. In other words, like the channel structure CH, the diameter of the third input / output contact plug 5404 may gradually decrease toward the upper insulating layer 5401. For example, the third input / output contact plug 5404 may be formed together with the cell contact plug 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other.

[0264] In some embodiments, the input / output contact plug may overlap the third substrate 5410. For example, as shown in region "C", the second input / output contact plug 5403 may penetrate the interlayer insulating layer 5415 of the second cell region CREG2 in the third direction VD, and may be electrically connected to the second input / output pad 5405 through the third substrate 5410. In this case, the connection structure of the second input / output contact plug 5403 and the second input / output pad 5405 may be implemented by various methods.

[0265] In some embodiments, as shown in region "C1", the opening 5408 may be formed to penetrate the third substrate 5410, and the second input / output contact plug 5403 may be directly connected to the second input / output pad 5405 through the opening 5408 formed in the third substrate 5410. In this case, as shown in region "C1", the diameter of the second input / output contact plug 5403 may gradually increase toward the second input / output pad 5405. However, the present disclosure is not limited thereto, and the diameter of the second input / output contact plug 5403 may gradually decrease toward the second input / output pad 5405.

[0266] In some embodiments, as shown in region "C2", an opening 5408 penetrating the third substrate 5410 may be formed, and a contact 5407 may be formed in the opening 5408. One end of the contact 5407 may be connected to the second input / output pad 5405, and the other end of the contact 5407 may be connected to the second input / output contact plug 5403. Therefore, the second input / output contact plug 5403 may be electrically connected to the second input / output pad 5405 through the contact 5407 in the opening 5408. In this case, as shown in region "C2", the diameter of the contact 5407 may gradually increase toward the second input / output pad 5405, and the diameter of the second input / output contact plug 5403 may gradually decrease toward the second input / output pad 5405. For example, the second input / output contact plug 5403 may be formed together with the cell contact plug 5440 before bonding the second cell region CREG2 and the first cell region CREG1 to each other, and the contact 5407 may be formed after bonding the second cell region CREG2 and the first cell region CREG1 to each other.

[0267] In some embodiments, in the region "C3", the stopper 5409 may also be formed on the bottom end of the opening 5408 of the third substrate 5410, instead of being formed in the region "C2". The stopper 5409 may be a metal line formed in the same layer as the common source line 5420. Alternatively, the stopper 5409 may be a metal line formed in the same layer as at least one of the word lines 5430. The second input / output contact plug 5403 may be electrically connected to the second input / output pad 5405 through the contact 5407 and the stopper 5409.

[0268] Like the second input / output contact plug 5403 and the third input / output contact plug 5404 of the second unit region CREG2, the diameter of each of the second input / output contact plug 5303 and the third input / output contact plug 5304 of the first unit region CREG1 can gradually decrease toward the lower metal pattern 5371e, or can gradually increase toward the lower metal pattern 5371e.

[0269] In some embodiments, the slit 5411 may be formed in the third substrate 5410. For example, the slit 5411 may be formed at a specific position of the external pad bonding area PA. For example, as shown in area "D", when viewed in a plan view, the slit 5411 may be located between the second input / output pad 5405 and the cell contact plug 5440. Alternatively, when viewed in a plan view, the second input / output pad 5405 may be located between the slit 5411 and the cell contact plug 5440.

[0270] In some embodiments, as shown in region "D1", the slit 5411 may be formed to penetrate the third substrate 5410. For example, the slit 5411 may be used to prevent the third substrate 5410 from being finely cracked when the opening 5408 is formed. However, the present disclosure is not limited thereto, and the slit 5411 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 5410.

[0271] In some embodiments, as shown in region "D2", a conductive material 5412 may be formed in the slit 5411. For example, the conductive material 5412 may be used to discharge leakage current that occurs when driving circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 5412 may be connected to an external ground line.

[0272] In some embodiments, as shown in region "D3", an insulating material 5413 may be formed in the slit 5411. For example, the insulating material 5413 may be used to electrically isolate the second input / output pad 5405 and the second input / output contact plug 5403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Since the insulating material 5413 is formed in the slit 5411, a voltage provided through the second input / output pad 5405 may be prevented from affecting a metal layer on the third substrate 5410 disposed in the word line bonding region WLBA.

[0273] In some embodiments, the first to third input / output pads 5205, 5405, and 5406 may be selectively formed. For example, the memory device 5000 may be implemented to include only the first input / output pad 5205 disposed on the first substrate 5210, only the second input / output pad 5405 disposed on the third substrate 5410, or only the third input / output pad 5406 disposed on the upper insulating layer 5401.

[0274] In some embodiments, at least one of the second substrate 5310 of the first cell region CREG1 and the third substrate 5410 of the second cell region CREG2 may be used as a sacrificial substrate and may be completely removed or partially removed before or after the bonding process. Additional layers may be stacked after the substrate is removed. For example, the second substrate 5310 of the first cell region CREG1 may be removed before or after the bonding process of the peripheral circuit region PREG and the first cell region CREG1, and subsequently, an insulating layer covering the top surface of the common source line 5320 or a conductive layer for connection may be formed. Similarly, the third substrate 5410 of the second cell region CREG2 may be removed before or after the bonding process of the first cell region CREG1 and the second cell region CREG2, and subsequently, an upper insulating layer 5401 covering the top surface of the common source line 5420 or a conductive layer for connection may be formed.

[0275] Fig.32 is a diagram illustrating a manufacturing process of a stacked semiconductor device.

[0276] Reference Fig.32 , corresponding integrated circuits may be formed on the first wafer WF1 and the second wafer WF2. The memory cell array may be formed in the first wafer WF1, and the peripheral circuit may be formed in the second wafer WF2.

[0277] After various integrated circuits have been formed on the first wafer WF1 and the second wafer WF2, respectively, the first wafer WF1 and the second wafer WF2 may be bonded together. The bonded wafers WF1 and WF2 may then be cut (or divided) into separate chips, wherein each chip corresponds to a semiconductor device (such as a memory device 5000 including a first semiconductor die SD1 and a second semiconductor die SD2 vertically stacked (e.g., the first semiconductor die SD1 is stacked on the second semiconductor die SD2, etc.) as an example). Each cut portion of the first wafer WF1 corresponds to the first semiconductor die SD1, and each cut portion of the second wafer WF2 corresponds to the second semiconductor die SD2. For example, the memory device 5000 may be formed based on the first and second semiconductor dies SD1 and SD2. Fig.32 Manufacturing process to manufacture Fig.31 Memory device 5000.

[0278] Fig.33 is a block diagram showing an electronic system including a semiconductor device.

[0279] Reference Fig.33 , the electronic system 3000 includes a semiconductor device 3100 and a controller 3200 electrically connected to the semiconductor device 3100. The electronic system 3000 may be a storage device including one or more semiconductor devices 3100 or an electronic device including a storage device. For example, the electronic system 3000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that may include one or more semiconductor devices 3100.

[0280] The semiconductor device 3100 may be a nonvolatile memory device (eg, Figures 8 to 26B NAND flash memory device shown), and can perform reference Figures 1 to 7 The first programming operation and the second programming operation described. The semiconductor device 3100 includes a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure, and the peripheral circuit structure includes a decoder circuit 3110, a page buffer circuit (PBC) 3120, and a logic circuit 3130. The second structure 3100S may be a memory cell structure, and the memory cell structure includes a bit line BL, a common source line CSL, a word line WL located between the bit line BL and the common source line CSL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR.

[0281] In the second structure 3100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be changed according to the disclosed examples.

[0282] In some embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0283] In some embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 that may be connected in series to each other. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation of erasing data stored in the memory cell transistor MCT by a gate-induced drain leakage (GIDL) phenomenon.

[0284] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 3110 through the first connection wiring 3115 extending from the first structure 3100F to the second structure 3110S. The bit line BL may be electrically connected to the page buffer circuit 3120 through the second connection wiring 3125 extending from the first structure 3100F to the second structure 3100S.

[0285] In the first structure 3100F, the decoder circuit 3110 and the page buffer circuit 3120 may perform a control operation for at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 3110 and the page buffer circuit 3120 may be controlled by the logic circuit 3130. The semiconductor device 3100 may communicate with the controller 3200 through an input / output pad 3101 electrically connected to the logic circuit 3130. The input / output pad 3101 may be electrically connected to the logic circuit 3130 through an input / output connection wiring 3135 extending from the first structure 3100F to the second structure 3100S.

[0286] The controller 3200 may include a processor 3210, a NAND controller 3220, and a host interface (I / F) 3230. The electronic system 3000 may include a plurality of semiconductor devices 3100, and in this case, the controller 3200 may control the plurality of semiconductor devices 3100.

[0287] The processor 3210 may control the operation of the electronic system 3000 including the controller 3200. The processor 3210 may operate through firmware and may control the NAND controller 3220 to access the semiconductor device 3100. The NAND controller 3220 may include a NAND interface 3221 for communicating with the semiconductor device 3100. Through the NAND interface 3221, a control command for controlling the semiconductor device 3100, data to be written into the memory cell transistor MCT of the semiconductor device 3100, data to be read from the memory cell transistor MCT of the semiconductor device 3100, etc. may be transmitted. The host interface 3230 may provide communication between the electronic system 3000 and an external host. When a control command is received from the external host through the host interface 3230, the processor 3210 may control the semiconductor device 3100 in response to the control command.

[0288] In some implementations, non-volatile memory devices or storage devices may be packaged using various package types or package configurations.

[0289] The present disclosure can be applied to various electronic devices and systems including non-volatile memory devices and memory packages. For example, the present disclosure can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, cars, etc.

[0290] Although the present disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope that can be claimed. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in a specific combination and even initially claimed as such, one or more features from the combination may be removed from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0291] The above is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

Claims

1. A non-volatile memory device, comprising: a memory block including a plurality of cell strings, each of the plurality of cell strings including a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and disposed in a vertical direction between a plurality of bit lines and a common source line; a page buffer circuit connected to the plurality of cell strings through the plurality of bit lines; as well as A control circuit is configured to control the read operation by: latching first sense data and second sense data in the page buffer circuit by performing a first read operation on a selected word line designated by an access address among a plurality of word lines of the memory block based on a read voltage setting; latching third sensing data in the page buffer circuit by performing a second read operation on a disturbing word line adjacent to the selected word line based on at least one adjacent read voltage; selecting one of the first sensing data and the second sensing data as hard decision data based on a programming state of the third sensing data; as well as Soft decision data is generated by using the first sensing data and the second sensing data.

2. The nonvolatile memory device according to claim 1, wherein: The control circuit is configured to control the page buffer circuit to generate the soft decision data by performing an XOR operation on the first sensing data and the second sensing data.

3. The nonvolatile memory device according to claim 1, wherein: The control circuit is configured to control the page buffer circuit to generate the soft decision data by performing an exclusive OR operation on the first sensing data and the second sensing data.

4. The nonvolatile memory device according to claim 1, wherein: When a threshold voltage distribution of a programming state of the third sensing data of each of the non-interfering cells of the memory cells coupled to the interfering word line is less than the at least one adjacent read voltage, the control circuit is configured to select the first sensing data of each of the first memory cells corresponding to the non-interfering cells among the memory cells coupled to the selected word line as the hard decision data.

5. The nonvolatile memory device according to claim 1, wherein: When a threshold voltage distribution of a programming state of third sensing data of each of the interfering cells of the memory cells coupled to the interfering word line is equal to or greater than the at least one adjacent read voltage, the control circuit is configured to select second sensing data of each of second memory cells corresponding to the interfering cell among the memory cells coupled to the selected word line as the hard decision data.

6. The nonvolatile memory device according to claim 1, wherein: The page buffer circuit comprises: a plurality of page buffers, wherein each of the plurality of page buffers is connected to a corresponding cell string among the plurality of cell strings through a corresponding bit line among the plurality of bit lines; and A data processor is connected to the plurality of page buffers, wherein the data processor is configured to generate the soft decision data by using the first sensing data and the second sensing data.

7. The nonvolatile memory device according to claim 6, wherein: The control circuit is configured to control the page buffer circuit: storing the first sensing data in a first latch of a corresponding page buffer among the plurality of page buffers; storing the second sensing data in a second latch of a corresponding page buffer among the plurality of page buffers; as well as The third sensing data is stored in a third latch of a corresponding page buffer among the plurality of page buffers.

8. The nonvolatile memory device according to claim 1, wherein: The page buffer circuit comprises: a plurality of page buffers, wherein each of the plurality of page buffers is connected to a corresponding cell string among the plurality of cell strings through a corresponding bit line among the plurality of bit lines; and a data processor connected to the plurality of page buffers, wherein the data processor is configured to generate the soft decision data by using the first sensing data and the second sensing data, Wherein, the control circuit is configured to control the page buffer circuit: storing three or more sense data in first latches of corresponding page buffers among the plurality of page buffers by applying a read voltage setting including three or more data recovery read voltages to the selected word line; and storing two or more decision data in a second latch of a corresponding page buffer among the plurality of page buffers by applying the at least one adjacent read voltage among the two or more adjacent read voltages to the disturbing word line, and The control circuit is configured to: select one of three or more sensing data as the hard decision data based on the two or more decision data; and generate the soft decision data by using the three or more sensing data.

9. The nonvolatile memory device according to claim 1, wherein: The control circuit is configured to control the page buffer circuit: outputting the soft decision data after outputting the hard decision data; or The hard decision data is outputted after the soft decision data is outputted.

10. The nonvolatile memory device according to claim 1, wherein: The control circuit includes a disturbing word line selector configured to select the disturbing word line based on a row address included in the access address, wherein the plurality of word lines are programmed from the bit lines to the common source line, Wherein, the plurality of word lines include: First word line; a second word line located on the first word line in a direction perpendicular to the substrate and adjacent to the first word line; and a third word line located on the second word line and adjacent to the second word line in the direction perpendicular to the substrate, and The second word line is the selected word line.

11. The nonvolatile memory device according to claim 10, wherein: When the first word line is a normal word line, the interference word line selector is configured to select the first word line as the interference word line.

12. The nonvolatile memory device according to claim 10, wherein: When the first word line is a dummy word line, the interfering word line selector is configured to select the third word line as the interfering word line, The memory block is implemented in a multi-stack structure including two or more stacks, and the dummy word line is placed at a boundary of the stack.

13. The nonvolatile memory device according to claim 10, wherein: When the first word line is a word line on which programming is not performed, the interference word line selector is configured to select the third word line as the interference word line.

14. A memory system, comprising: a non-volatile memory device; and a memory controller configured to control the nonvolatile memory device, Wherein, the non-volatile memory device comprises: a memory block including a plurality of cell strings, each of the plurality of cell strings including a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and disposed in a vertical direction between a plurality of bit lines and a common source line; a page buffer circuit connected to the plurality of cell strings through the plurality of bit lines; and A control circuit is configured to control the read operation by: latching first sense data and second sense data in the page buffer circuit by performing a first read operation on a selected word line designated by an access address among a plurality of word lines of the memory block based on a read voltage setting; latching third sensing data in the page buffer circuit by performing a second read operation on a disturbing word line adjacent to the selected word line based on at least one group read voltage; selecting one of the first sensing data and the second sensing data as hard decision data based on a programming state of the third sensing data; and The hard decision data is provided to the memory controller.

15. The memory system of claim 14, wherein: The memory controller includes an error correction code decoder configured to perform a first error correction code decoding on the hard decision data, The memory controller is configured to send a request for soft decision data to the nonvolatile memory device when decoding of the first error correction code fails, The control circuit is further configured to control the read operation by providing the soft decision data to the memory controller in response to the request, and The error correction code decoder is configured to perform second error correction code decoding on the soft decision data provided from the nonvolatile memory device.

16. The memory system of claim 14, wherein: The control circuit is further configured to control the read operation by: generating soft decision data by using the first sensing data and the second sensing data; as well as providing the soft decision data to the memory controller; and Wherein, the memory controller includes an error correction code decoder, and the error correction code decoder is configured to: performing first error correction code decoding on the hard decision data; as well as When the first error correction code decoding fails, a second error correction code decoding is performed on the soft decision data.

17. The memory system according to claim 14, in, The control circuit is further configured to control the read operation by providing the first sensing data and the second sensing data to the memory controller, wherein the memory controller is configured to generate soft decision data by using the first sensing data and the second sensing data, and Wherein, the memory controller includes an error correction code decoder, and the error correction code decoder is configured to: performing a first error correction code decoding on the hard decision data; and When the first error correction code decoding fails, a second error correction code decoding is performed on the soft decision data.

18. A method of controlling an operation of a nonvolatile memory device, the nonvolatile memory device comprising a memory block having a plurality of cell strings, each of the plurality of cell strings comprising a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and disposed in a vertical direction between a plurality of bit lines and a common source line, the method comprising: latching first sense data and second sense data in a page buffer circuit by performing a first read operation on a selected word line designated by an access address among a plurality of word lines of the memory block based on a read voltage setting; latching third sensing data in the page buffer circuit by performing a second read operation on a disturbing word line adjacent to the selected word line based on at least one group read voltage; selecting one of the first sensing data and the second sensing data as hard decision data based on a programming state of the third sensing data; as well as Soft decision data is generated by using the first sensing data and the second sensing data.

19. The method according to claim 18, wherein: Generating the soft decision data includes performing one of an exclusive-NOR operation and an exclusive-OR operation on the first sensing data and the second sensing data.

20. The method of claim 18, further comprising selecting one of at least two word lines adjacent to the selected word line as the interference word line based on a row address and program progress information included in the word line specified by the access address before performing the second read operation.

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