Test circuit of Flash unit

Abstract

The invention discloses a test circuit of a Flash unit, which comprises a Flash unit erasing and programming circuit, a Sense tube test circuit and a Switch tube test circuit, the Sense tube test circuit reads back the state of a Sense tube in the Flash unit after erasing and programming, and a high level signal read back after erasing and a low level signal read back after programming are output through a register chain; the Switch tube test circuit reads back the state of the Switch tube in the Flash unit after erasing and programming, and a high level signal read back after erasing and a low level signal read back after programming are output through a register chain; and judging the state of the Flash unit according to a read-back result of the register chain so as to judge the stability of the Flash type FPGA. The method is suitable for testing the configurable Flash unit in the Flash type FPGA, and the problem that the state of the Flash unit in the Flash type FPGA can be monitored is solved.

Description

Technical Field

[0001] The invention relates to integrated circuit technology, and in particular to a test circuit for a Flash unit. Background Art

[0002] Flash FPGAs have the characteristics of non-volatility, high reliability, immunity to firmware errors, and high confidentiality. They are widely used in various complex electromagnetic radiation environments such as industrial control, military, and aerospace.

[0004] The Flash unit is composed of a pair of Flash transistors with a common floating gate (G) sense-switch structure. Figure 3 As shown. The Flash unit determines the state of the Flash FPGA through charging and discharging. The characteristics of the Flash unit determine the non-volatility of the Flash FPGA when it is powered off. The Flash unit is the most basic programmable configuration unit of the Flash FPGA. The Sense tube in the Flash unit is used for the verification operation of the Flash FPGA. The Switch tube in the Flash unit is used for the logic configuration and wiring path connection of the Flash FPGA. Therefore, it is very important to test and study the Flash unit. Summary of the invention

[0005] The purpose of the present invention is to provide a test circuit for a Flash unit, which monitors the state of the Flash unit after an erase operation and a program operation, so as to determine whether the Flash unit is completely erased and programmed, thereby ensuring the stability of the circuit.

[0006] The technical solution for achieving the purpose of the present invention is: a test circuit for a Flash unit, including a Flash unit erasing and programming circuit, a Sense tube test circuit and a Switch tube test circuit, wherein the Sense tube test circuit reads back the state of the Sense tube in the Flash unit after erasure and programming, and the high level signal read back after erasure and the low level signal read back after programming are output through a register chain; the Switch tube test circuit reads back the state of the Switch tube in the Flash unit after erasure and programming, and the high level signal read back after erasure and the low level signal read back after programming are output through a register chain; the state of the Flash unit is determined according to the result of the register chain readback, thereby determining the stability of the Flash type FPGA.

[0007] Furthermore, the Flash unit includes a pair of Flash transistors with a common floating gate and a Sense-Switch structure, and the floating gates of all Flash units are connected to the word line; the S1 terminals of all Sense tubes are connected to the bit line row, the D1 terminals are connected to the bit line row, and the S1 terminals and the D1 terminals are also connected to the Sense tube test circuit respectively; the S2 terminals and the D2 terminals of all Switch tubes are connected to each other through metal wires, and the S2 terminals and the D2 terminals are also connected to the Switch tube test circuit respectively.

[0008] Furthermore, the erasing, programming and selection of the Flash cell are completed by branch ①, branch ② and branch ③ respectively, and the output ends of the three branches are connected to the same word line, where:

[0009] The erasing operation of the Flash unit is completed by branch ①, which is composed of four NMOS tubes N1, N2, N3, and N4 connected in series. The drain of the NMOS tube N1, that is, the port GS1, is added with negative high voltage, and the source of the NMOS tube N4 is connected to the word line. The NMOS tubes N1, N2, N3, and N4 are turned on by adding a high level, and the negative high voltage acts on the floating gate in the Flash unit through the word line, realizing the erasing operation of a pair of Flash transistors with a common floating gate Sense-Switch structure in the Flash unit. At this time, the state of the Sense tube and the Switch tube is a pass transistor, which is equivalent to an on-resistance;

[0010] The programming operation of the Flash unit is completed by branch ②, which is composed of three PMOS tubes P1, P2, and P3 connected in series. The source of the PMOS tube P1, that is, the port VS1, is added with a positive high voltage, and the drain of the PMOS tube P3 is connected to the word line. The PMOS tubes P1, P2, and P3 are turned on by adding a low level, and the positive high voltage acts on the floating gate in the Flash unit through the word line WL, realizing the programming operation of a pair of Flash transistors with a common floating gate Sense-Switch structure in the Flash unit. At this time, the Sense tube and the Switch tube are in the off state, which is equivalent to an open circuit;

[0011] Branch ③ is used to select the Flash unit to be tested on the word line. Branch ③ is composed of a PMOS tube P0. The source of the PMOS tube P0, that is, the port VS2, is connected to the power supply. The drain of the PMOS tube P0 is connected to the word line. The PMOS tube P0 is turned on by adding a low level, and the VS2 power supply is transmitted to the word line and acts on the floating gate. The Flash unit on the word line is tested through the corresponding test circuit.

[0012] Furthermore, the Sense tube test circuit is composed of five NMOS tubes E1, E2, E3, E4, and E5 connected in series. The drain of the NMOS tube E1, that is, the port GND, is grounded, and the source port VCC of the NMOS tube E5 is connected to the power supply VCC. Among them, the source and drain of the NMOS tube E2 are respectively connected to the S1 terminal and the D1 terminal of the Sense tube, that is, the Sense tube and the NMOS tube E2 are connected in parallel to the test circuit; the source of the NMOS tube E4 is the test point A, and the test point A is connected to the input terminal of the selector MUX1 in the 1184 register chain after passing through a 1-stage inverter, and the 1184 register chain outputs the voltage of the node A to the port TDO.

[0013] Further, the Sense tube testing process is as follows:

[0014] (1) Select branch ①, close branch ② and branch ③, and perform an erase operation on the Flash unit;

[0015] Branch ① is composed of four NMOS tubes N1, N2, N3, and N4 connected in series. The drain of NMOS tube N1, i.e., port GS1, is connected to a negative high voltage. The source of NMOS tube N4 is connected to the word line. NMOS tubes N1, N2, N3, and N4 are turned on by a high level. The negative high voltage acts on the floating gate in the Flash unit through the word line, thereby realizing the erasing operation of a pair of Flash transistors with a common floating gate in the Flash unit.

[0016] (2) Select branch ③, close branch ① and branch ②, and test the Sense transistor in the erased Flash unit;

[0017] In the Sense tube test circuit, NMOS tubes E1, E3, E4, and E5 are turned on by adding a high level, and NMOS tube E2 is turned off by adding a low level. Port VCC is powered, and port GND is grounded. If the Flash unit is completely erased, that is, the Sense tube is in the "on" state, node A should be at a low level at this time. The low level becomes a high level after passing through a first-level inverter, and the high level is connected to the 1184 register chain for reading back. When the port TDO output of the 1184 register chain is a high level, it is determined that the Flash unit is completely erased; when the port TDO output of the 1184 register chain is a low level, it is determined that the Flash unit is not completely erased;

[0018] (3) Select branch ②, close branch ① and branch ③, and perform programming operation on the completely erased Flash cell;

[0019] Branch ② is composed of three PMOS tubes P1, P2, and P3 connected in series. The source of PMOS tube P1, i.e., port VS1, is connected to a positive high voltage. The drain of PMOS tube P3 is connected to the word line. PMOS tubes P1, P2, and P3 are turned on by a low level. The positive high voltage acts on the floating gate in the Flash unit through the word line WL, thereby realizing programming operation of a pair of Flash transistors with a common floating gate in the Flash unit.

[0020] (4) Select branch ③, close branch ① and branch ②, and test the Sense transistor in the programmed Flash unit;

[0021] In the Sense tube test circuit, NMOS tubes E1, E3, E4, and E5 are turned on by adding a high level, and NMOS tube E2 is turned off by adding a low level. Port VCC is powered and port GND is grounded. If the Flash unit is fully programmed, the Sense tube is in an "open circuit" state. At this time, node A should be high. The high level becomes a low level after passing through a first-level inverter. The low level is connected to the 1184 register chain for reading back. When the port TDO output of the 1184 register chain is low, it is determined that the Flash unit is fully programmed; when the port TDO output of the 1184 register chain is high, it is determined that the Flash unit is not fully programmed.

[0022] Furthermore, the switch test circuit is composed of 138 register chains that provide enable configuration signals for 66 inverters G1<1:66> and 48 three-input and three-output transmission gates G2<1:48>. The inputs of all inverters are connected to the same port RST. <2> The output end, i.e. node B, is connected to transmission gate G2 <1> The input terminal T3 is connected to the transmission gate G2. <1> The output terminal R3 is connected to the input terminal of the selector MUX3 in the 1056 register chain; the inverter G1 <1> The output end, node C, is connected to the transmission gate G2 <1> The input terminal T1 is connected to the transmission gate G2. <1> The output terminal R1 is connected to the input terminal of the selector MUX1 in the 1056 register chain; the D2 terminal of the Switch tube is connected to the node B, the S2 terminal of the Switch tube is connected to the node C, the node C is the test point, and the 1056 register chain outputs the voltage of the node C to the port TDQ.

[0023] Furthermore, the Switch tube test process is as follows:

[0024] (1) Select branch ①, close branch ② and branch ③, and perform an erase operation on the Flash unit;

[0025] Branch ① is composed of four NMOS tubes N1, N2, N3, and N4 connected in series. The drain of NMOS tube N1, i.e., port GS1, is connected to a negative high voltage. The source of NMOS tube N4 is connected to the word line. NMOS tubes N1, N2, N3, and N4 are turned on by a high level. The negative high voltage acts on the floating gate in the Flash unit through the word line, thereby realizing the erasing operation of a pair of Flash transistors with a common floating gate in the Flash unit.

[0026] (2) Select branch ③, close branch ① and branch ②, and test the switch tube in the erased Flash unit;

[0027] In the switch test circuit, the port RST is low level, and the inverter G1 <1> The enable configuration signal is turned off by adding a low level, and node C is at a low level; inverter G1 <2> The enable configuration signal is turned on with a high level, and node B is at a high level at this time; if the Flash unit is completely erased, that is, the Switch tube is in the "pass" state, the high level of node B is transmitted to the S2 terminal through the Switch tube D2 terminal and then to node C. At this time, node C changes from a low level to a high level, and the high level is connected to the 1056 register chain for reading back. When the port TDQ output of the 1056 register chain is a high level, it is determined that the Flash unit is completely erased; when the port TDQ output of the 1056 register chain is a low level, it can be determined that the Flash unit is not completely erased;

[0028] (3) Select branch ②, close branch ① and branch ③, and perform programming operation on the completely erased Flash cell;

[0029] Branch ② is composed of three PMOS tubes P1, P2, and P3 connected in series. The source of PMOS tube P1, i.e., port VS1, is connected to a positive high voltage. The drain of PMOS tube P3 is connected to the word line. PMOS tubes P1, P2, and P3 are turned on by a low level. The positive high voltage acts on the floating gate in the Flash unit through the word line WL, thereby realizing programming operation of a pair of Flash transistors with a common floating gate in the Flash unit.

[0030] (4) Select branch ③, close branch ① and branch ②, and test the switch tube in the programmed Flash unit;

[0031] In the switch test circuit, the port RST is low level, and the inverter G1 <1> The enable configuration signal is turned off by adding a low level, and node C is at a low level; inverter G1 <2> The enable configuration signal is turned on with a high level, and node B is at a high level at this time; if the Flash unit is fully programmed, that is, the Switch tube is in the "open circuit" state, the high level of node B cannot be transmitted to node C. At this time, node C is still at a low level, and the low level is connected to the 1056 register chain for readback; when the port TDQ output of the 1056 register chain is a low level, it is determined that the Flash unit is fully programmed; when the port TDQ output of the 1056 register chain is a high level, it is determined that the Flash unit is not fully programmed.

[0032] Furthermore, a level 1 register chain is composed of a selector, a trigger and a latch, and 1184 level 1 register chains are cascaded into a 1184-level register chain, 138 level 1 register chains are cascaded into a 138-level register chain, and 1056 level 1 register chains are cascaded into a 1056-level register chain.

[0033] Compared with the prior art, the present invention has the following significant advantages: by testing the "pass" state of the Sense tube after the erasing operation and the "break" state of the Sense tube after the programming operation of the Flash unit, traversal monitoring of the Sense tubes on all word lines (WL) can be realized; by testing the "pass" state of the Switch tube after the erasing operation and the "break" state of the Switch tube after the programming operation of the Flash unit, traversal monitoring of the Switch tube on a single word line (WL) line or monitoring of the series connection of Switch tubes on multiple word lines (WL) lines can be realized, which is suitable for testing configurable Flash units in Flash-type FPGAs and solves the problem of Flash unit state monitorability in Flash-type FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The present invention is a Flash unit erasing and programming circuit and a test circuit for the Sense tube in the Flash unit. The "on" state of the Sense tube after the erasing operation and the "off" state of the Sense tube after the programming operation of the Flash unit are tested, and the traversal monitoring of the Sense tubes on all word lines (WL) can be realized.

[0035] Figure 2 The invention is a test circuit for the Switch tube in the Flash unit. The "on" state of the Switch tube after the erase operation and the "off" state of the Switch tube after the programming operation of the Flash unit are tested, and the traversal monitoring of the Switch tube on a single word line (WL) or the monitoring of the series connection of the Switch tubes on multiple word lines (WL) can be realized.

[0036] Figure 3 It is a schematic diagram of the existing Flash unit circuit structure. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] The present invention discloses a test circuit for a Flash unit, comprising a Flash unit erasing and programming circuit, a Sense tube test circuit and a Switch tube test circuit. After erasing and programming the Flash unit, the state of the Sense tube can be determined by a designed Figure 1 The Sense test circuit in the Flash unit is read back. The high-level signal read back after erasing and the low-level signal read back after programming are output through the 1184 register chain; the state of the Switch tube can be controlled by the designed Figure 2 The Switch test circuit in the FPGA is read back. The high-level signal read back after erasing and the low-level signal read back after programming are output through the 1056 register chain. The state of the Flash unit can be determined based on the result of the register chain read back, thereby determining the stability of the Flash FPGA. The test circuit of the Flash unit plays an important role in process development and subsequent production stages.

[0039] The Flash unit includes a pair of Flash transistors with a common floating gate (G) and a Sense-Switch structure. The floating gates (G) of all Flash units are connected to the word line (WL); the S1 end of all Sense tubes is connected to the bit line (BL) row, and the D1 end is connected to the bit line (SL) row, and the S1 end and the D1 end are also connected to the Sense tube test circuit respectively; the S2 end and the D2 end of all Switch tubes are connected to each other through metal wires to realize the wiring connection of the entire chip, and the S2 end and the D2 end are also connected to the Switch tube test circuit respectively. The erasing, programming and selection of the Flash unit are respectively performed by Figure 1 The output ends of the three branches are all connected to the same word line (WL).

[0040] The erasing operation of the Flash unit is completed by branch ①, which is composed of four NMOS tubes N1, N2, N3, and N4 connected in series. The drain of the NMOS tube N1 (i.e., port GS1) is added with negative high voltage, and the source of the NMOS tube N4 is connected to the word line (WL). The NMOS tubes N1, N2, N3, and N4 are turned on by adding a high level, and the negative high voltage acts on the floating gate (G) in the Flash unit through the word line (WL), realizing the erasing operation of a pair of Sense-Switch structure Flash transistors with a common floating gate (G) in the Flash unit. At this time, the state of the Sense tube and the Switch tube is a pass transistor, which is equivalent to an on-resistance.

[0041] The programming operation of the Flash unit is completed by branch ②. Branch ② is composed of three PMOS tubes P1, P2, and P3 connected in series. The source of the PMOS tube P1 (i.e., port VS1) is added with positive high voltage, and the drain of the PMOS tube P3 is connected to the word line (WL). The PMOS tubes P1, P2, and P3 are turned on by adding a low level, and the positive high voltage acts on the floating gate (G) in the Flash unit through the word line WL, realizing the programming operation of a pair of Sense-Switch structure Flash transistors with a common floating gate (G) in the Flash unit. At this time, the Sense tube and the Switch tube are in the off state, which is equivalent to an open circuit.

[0042] Branch ③ is used to select the Flash unit to be tested on the word line (WL). Branch ③ consists of a PMOS tube P0. The source of the PMOS tube P0 (i.e., port VS2) is powered, and the drain of the PMOS tube P0 is connected to the word line (WL). The PMOS tube P0 is turned on by a low level, and the VS2 power supply is transmitted to the word line (WL) and acts on the floating gate (G), that is, the word line (WL) is selected, and the Flash unit on the word line (WL) can be tested through the corresponding test circuit. When the Flash unit on a word line (WL) needs to be tested, the corresponding word line (WL) can be powered through branch ③.

[0043] The existing level 1 register chain is composed of a selector (MUX1), a trigger (DFF1) and a latch (LAT1). 1184 level 1 register chains are cascaded into a 1184-level register chain, 138 level 1 register chains are cascaded into a 138-level register chain, and 1056 level 1 register chains are cascaded into a 1056-level register chain to meet the Flash unit test requirements of the entire chip.

[0044] Figure 1The Sense tube test circuit in the figure is composed of five NMOS tubes E1, E2, E3, E4, and E5 connected in series. The drain of NMOS tube E1 (i.e., port GND) is grounded, and the source of NMOS tube E5 (i.e., port VCC) is connected to the power supply VCC. Among them, the source and drain of NMOS tube E2 are respectively connected to the S1 terminal and D1 terminal of the Sense tube, that is, the Sense tube and NMOS tube E2 are connected in parallel to the test circuit. The source of NMOS tube E4 (i.e., node A) is the test point. After passing through a 1-stage inverter, the node A is connected to the input terminal of the selector (MUX1) in the 1184 register chain. The 1184 register chain can output the voltage (high / low signal) of node A to the port TDO.

[0045] Figure 2 The switch test circuit in Figure 1 is composed of 138 register chains that provide enable configuration signals for 66 inverters (G1<1:66>) and 48 three-input and three-output transmission gates (G2<1:48>). The inputs of all inverters are connected to the same port (RST). <2> ) is connected to the output end (i.e., node B) of the transmission gate (G2 <1> ) input terminal (T3), through the transmission gate (G2 <1> ) is connected to the input of the selector (MUX3) in the 1056 register chain; the inverter (G1 <1> ) is connected to the output end (i.e., node C) of the transmission gate (G2 <1> ) input terminal (T1), through the transmission gate (G2 <1> ) is connected to the input of the selector (MUX1) in the 1056 register chain; the D2 end of the Switch tube is connected to the node B, and the S2 end of the Switch tube is connected to the node C. Node C is the test point. The 1056 register chain can output the voltage (high / low signal) of node C to the port TDQ.

[0046] The Sense tube testing process is as follows:

[0047] (1) Select branch ①, close branch ② and branch ③, and perform an erase operation on the Flash unit;

[0048] Branch ① is composed of four NMOS tubes N1, N2, N3, and N4 connected in series. A negative high voltage is applied to the drain of the NMOS tube N1 (i.e., port GS1), and the source of the NMOS tube N4 is connected to the word line (WL). The NMOS tubes N1, N2, N3, and N4 are turned on by a high level, and the negative high voltage acts on the floating gate (G) in the Flash unit through the word line (WL), thereby realizing the erasing operation of a pair of Flash transistors with a common floating gate (G) in the Sense-Switch structure in the Flash unit.

[0049] (2) Select branch ③, close branch ① and branch ②, and test the Sense transistor in the erased Flash unit;

[0050] In the Sense tube test circuit, NMOS tubes E1, E3, E4, and E5 are turned on by adding a high level, and NMOS tube E2 is turned off by adding a low level. Port VCC is connected to power, and port GND is connected to ground. If the Flash unit is completely erased, that is, the Sense tube is in the "on" state, node A should be low level (0 signal) at this time. This low level (0 signal) becomes a high level (1 signal) after passing through a first-level inverter. This high level (1 signal) is connected to the 1184 register chain for readback. When the port TDO output of the 1184 register chain is a high level (1 signal), it can be determined that the Flash unit is completely erased; when the port TDO output of the 1184 register chain is a low level (0 signal), it can be determined that the Flash unit is not completely erased.

[0051] (3) Select branch ②, close branch ① and branch ③, and perform programming operation on the completely erased Flash cell;

[0052] Branch ② is composed of three PMOS tubes P1, P2, and P3 connected in series. A positive high voltage is applied to the source of the PMOS tube P1 (i.e., port VS1), and a drain of the PMOS tube P3 is connected to the word line (WL). The PMOS tubes P1, P2, and P3 are turned on by applying a low level, and the positive high voltage acts on the floating gate (G) in the Flash unit through the word line WL, thereby realizing the programming operation of a pair of Flash transistors with a common floating gate (G) in the Flash unit.

[0053] (4) Select branch ③, close branch ① and branch ②, and test the Sense transistor in the programmed Flash unit;

[0054] In the Sense tube test circuit, NMOS tubes E1, E3, E4, and E5 are turned on by high level, NMOS tube E2 is turned off by low level, port VCC is powered, and port GND is grounded. If the Flash unit is fully programmed, that is, the Sense tube is in the "open circuit" state, node A should be high level (1 signal) at this time, and the high level (1 signal) becomes low level (0 signal) after passing through a first-level inverter, and the low level (0 signal) is connected to the 1184 register chain for readback. When the port TDO output of the 1184 register chain is low level (0 signal), it can be determined that the Flash unit is fully programmed; when the port TDO output of the 1184 register chain is high level (1 signal), it can be determined that the Flash unit is not fully programmed.

[0055] The Switch tube testing process is as follows:

[0056] (1) Select branch ①, close branch ② and branch ③, and perform an erase operation on the Flash unit;

[0057] Branch ① is composed of four NMOS tubes N1, N2, N3, and N4 connected in series. A negative high voltage is applied to the drain of the NMOS tube N1 (i.e., port GS1), and the source of the NMOS tube N4 is connected to the word line (WL). The NMOS tubes N1, N2, N3, and N4 are turned on by a high level, and the negative high voltage acts on the floating gate (G) in the Flash unit through the word line (WL), thereby realizing the erasing operation of a pair of Flash transistors with a common floating gate (G) in the Sense-Switch structure in the Flash unit.

[0058] (2) Select branch ③, close branch ① and branch ②, and test the switch tube in the erased Flash unit;

[0059] In the switch test circuit, the port RST is low level, the inverter (G1 <1> ) enables the configuration signal and closes it with a low level. At this time, node C is at a low level (0 signal); the inverter (G1 <2> ) Enable configuration signal plus high level to open, at this time node B is high level (1 signal); if the Flash unit is completely erased, that is, the Switch tube is in the "pass" state, at this time the high level (1 signal) of node B is transmitted to the S2 end through the Switch tube D2 end and then to the node C. At this time, node C changes from low level (0 signal) to high level (1 signal), and the high level (1 signal) is connected to the 1056 register chain for readback. When the port TDQ output of the 1056 register chain is high level (1 signal), it can be determined that the Flash unit is completely erased; when the port TDQ output of the 1056 register chain is low level (0 signal), it can be determined that the Flash unit is not completely erased.

[0060] (3) Select branch ②, close branch ① and branch ③, and perform programming operation on the completely erased Flash cell;

[0061] Branch ② is composed of three PMOS tubes P1, P2, and P3 connected in series. A positive high voltage is applied to the source of the PMOS tube P1 (i.e., port VS1), and a drain of the PMOS tube P3 is connected to the word line (WL). The PMOS tubes P1, P2, and P3 are turned on by applying a low level, and the positive high voltage acts on the floating gate (G) in the Flash unit through the word line WL, thereby realizing the programming operation of a pair of Flash transistors with a common floating gate (G) in the Flash unit.

[0062] (4) Select branch ③, close branch ① and branch ②, and test the switch tube in the programmed Flash unit;

[0063] In the switch test circuit, the port RST is low level, the inverter (G1 <1> ) enables the configuration signal and closes it with a low level. At this time, node C is at a low level (0 signal); the inverter (G1 <2> ) Enable configuration signal plus high level to open, at this time node B is high level (1 signal); if the Flash unit is fully programmed, that is, the Switch tube is in the "open circuit" state, the high level (1 signal) of node B cannot be transmitted to node C, and node C is still low level (0 signal) at this time. This low level (0 signal) is connected to the 1056 register chain for readback. When the port TDQ output of the 1056 register chain is low level (0 signal), it can be determined that the Flash unit is fully programmed; when the port TDQ output of the 1056 register chain is high level (1 signal), it can be determined that the Flash unit is not fully programmed.

[0064] Figure 1 and Figure 2 The two circuits realize the erasing and programming operations of the Flash unit, and test the status of the Sense tube and the Switch tube in the Flash unit after erasing and programming respectively, which plays an important role in determining the performance of the Flash type FPGA chip.

[0065] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A test circuit for a Flash unit, characterized in that: It includes a Flash unit erasing and programming circuit, a Sense tube test circuit and a Switch tube test circuit, wherein the Sense tube test circuit reads back the state of the Sense tube in the Flash unit after erasure and programming, and the high level signal read back after erasure and the low level signal read back after programming are output through a register chain; the Switch tube test circuit reads back the state of the Switch tube in the Flash unit after erasure and programming, and the high level signal read back after erasure and the low level signal read back after programming are output through a register chain; the state of the Flash unit is determined according to the result of the register chain readback, thereby determining the stability of the Flash type FPGA.

2. The test circuit of the Flash unit according to claim 1, characterized in that: The Flash unit includes a pair of Flash transistors with a common floating gate and a Sense-Switch structure. The floating gates of all Flash units are connected to the word line; the S1 terminals of all Sense tubes are connected to the bit line row, the D1 terminals are connected to the bit line row, and the S1 terminals and D1 terminals are also connected to the Sense tube test circuit respectively; the S2 terminals and D2 terminals of all Switch tubes are connected to each other through metal wires, and the S2 terminals and D2 terminals are also connected to the Switch tube test circuit respectively.

3. The test circuit of the Flash unit according to claim 2, characterized in that: The erasing, programming and selection of the Flash unit are completed by branch ①, branch ② and branch ③ respectively. The output ends of the three branches are connected to the same word line, where: The erasing operation of the Flash unit is completed by branch ①, which is composed of four NMOS tubes N1, N2, N3, and N4 connected in series. The drain of the NMOS tube N1, that is, the port GS1, is added with negative high voltage, and the source of the NMOS tube N4 is connected to the word line. The NMOS tubes N1, N2, N3, and N4 are turned on by adding a high level, and the negative high voltage acts on the floating gate in the Flash unit through the word line, realizing the erasing operation of a pair of Flash transistors with a common floating gate Sense-Switch structure in the Flash unit. At this time, the state of the Sense tube and the Switch tube is a pass transistor, which is equivalent to an on-resistance; The programming operation of the Flash unit is completed by branch ②, which is composed of three PMOS tubes P1, P2, and P3 connected in series. The source of the PMOS tube P1, that is, the port VS1, is added with a positive high voltage, and the drain of the PMOS tube P3 is connected to the word line. The PMOS tubes P1, P2, and P3 are turned on by adding a low level, and the positive high voltage acts on the floating gate in the Flash unit through the word line WL, realizing the programming operation of a pair of Flash transistors with a common floating gate Sense-Switch structure in the Flash unit. At this time, the Sense tube and the Switch tube are in the off state, which is equivalent to an open circuit; Branch ③ is used to select the Flash unit to be tested on the word line. Branch ③ is composed of a PMOS tube P0. The source of the PMOS tube P0, that is, the port VS2, is connected to the power supply. The drain of the PMOS tube P0 is connected to the word line. The PMOS tube P0 is turned on by adding a low level, and the VS2 power supply is transmitted to the word line and acts on the floating gate. The Flash unit on the word line is tested through the corresponding test circuit.

4. The test circuit of the Flash unit according to claim 3, characterized in that: The Sense tube test circuit is composed of five NMOS tubes E1, E2, E3, E4, and E5 connected in series. The drain of NMOS tube E1, that is, port GND, is grounded, and the source port VCC of NMOS tube E5 is connected to the power supply VCC. Among them, the source and drain of NMOS tube E2 are respectively connected to the S1 terminal and D1 terminal of the Sense tube, that is, the Sense tube and NMOS tube E2 are connected in parallel to the test circuit; the source of NMOS tube E4 is test point A, which is connected to the input terminal of selector MUX1 in the 1184 register chain after passing through a 1-stage inverter, and the 1184 register chain outputs the voltage of node A to port TDO.

5. The test circuit of the Flash unit according to claim 4, characterized in that: The Sense tube testing process is as follows: (1) Select branch ①, close branch ② and branch ③, and perform an erase operation on the Flash unit; Branch ① is composed of four NMOS tubes N1, N2, N3, and N4 connected in series. The drain of NMOS tube N1, i.e., port GS1, is connected to a negative high voltage. The source of NMOS tube N4 is connected to the word line. NMOS tubes N1, N2, N3, and N4 are turned on by a high level. The negative high voltage acts on the floating gate in the Flash unit through the word line, thereby realizing the erasing operation of a pair of Flash transistors with a common floating gate in the Flash unit. (2) Select branch ③, close branch ① and branch ②, and test the Sense transistor in the erased Flash unit; In the Sense tube test circuit, NMOS tubes E1, E3, E4, and E5 are turned on by adding a high level, and NMOS tube E2 is turned off by adding a low level. Port VCC is powered, and port GND is grounded. If the Flash unit is completely erased, that is, the Sense tube is in the "on" state, node A should be at a low level at this time. The low level becomes a high level after passing through a first-level inverter, and the high level is connected to the 1184 register chain for reading back. When the port TDO output of the 1184 register chain is a high level, it is determined that the Flash unit is completely erased; when the port TDO output of the 1184 register chain is a low level, it is determined that the Flash unit is not completely erased; (3) Select branch ②, close branch ① and branch ③, and perform programming operation on the completely erased Flash cell; Branch ② is composed of three PMOS tubes P1, P2, and P3 connected in series. The source of PMOS tube P1, i.e., port VS1, is connected to a positive high voltage. The drain of PMOS tube P3 is connected to the word line. PMOS tubes P1, P2, and P3 are turned on by a low level. The positive high voltage acts on the floating gate in the Flash unit through the word line WL, thereby realizing programming operation of a pair of Flash transistors with a common floating gate in the Flash unit. (4) Select branch ③, close branch ① and branch ②, and test the Sense transistor in the programmed Flash unit; In the Sense tube test circuit, NMOS tubes E1, E3, E4, and E5 are turned on by adding a high level, and NMOS tube E2 is turned off by adding a low level. Port VCC is powered and port GND is grounded. If the Flash unit is fully programmed, the Sense tube is in an "open circuit" state. At this time, node A should be high. The high level becomes a low level after passing through a first-level inverter. The low level is connected to the 1184 register chain for reading back. When the port TDO output of the 1184 register chain is low, it is determined that the Flash unit is fully programmed; when the port TDO output of the 1184 register chain is high, it is determined that the Flash unit is not fully programmed.

6. The test circuit of the Flash unit according to claim 3, characterized in that: The switch test circuit consists of 138 register chains that provide enable configuration signals for 66 inverters G1<1:66> and 48 three-input and three-output transmission gates G2<1:48>. The inputs of all inverters are connected to the same port RST. <2> The output end, i.e. node B, is connected to transmission gate G2 <1> The input terminal T3 is connected to the transmission gate G2. <1> The output terminal R3 is connected to the input terminal of the selector MUX3 in the 1056 register chain; the inverter G1 <1> The output end, i.e. node C, is connected to the transmission gate G2 <1> The input terminal T1 is connected to the transmission gate G2. <1> The output terminal R1 is connected to the input terminal of the selector MUX1 in the 1056 register chain; the D2 terminal of the Switch tube is connected to the node B, the S2 terminal of the Switch tube is connected to the node C, the node C is the test point, and the 1056 register chain outputs the voltage of the node C to the port TDQ.

7. The test circuit of the Flash unit according to claim 6, characterized in that: The Switch tube testing process is as follows: (1) Select branch ①, close branch ② and branch ③, and perform an erase operation on the Flash unit; Branch ① is composed of four NMOS tubes N1, N2, N3, and N4 connected in series. The drain of NMOS tube N1, i.e., port GS1, is connected to a negative high voltage. The source of NMOS tube N4 is connected to the word line. NMOS tubes N1, N2, N3, and N4 are turned on by a high level. The negative high voltage acts on the floating gate in the Flash unit through the word line, thereby realizing the erasing operation of a pair of Flash transistors with a common floating gate in the Flash unit. (2) Select branch ③, close branch ① and branch ②, and test the switch tube in the erased Flash unit; In the switch test circuit, the port RST is low level, and the inverter G1 <1> The enable configuration signal is turned off by adding a low level, and node C is at a low level; inverter G1 <2> The enable configuration signal is turned on with a high level, and node B is at a high level at this time; if the Flash unit is completely erased, that is, the Switch tube is in the "pass" state, the high level of node B is transmitted to the S2 terminal through the Switch tube D2 terminal and then to node C. At this time, node C changes from a low level to a high level, and the high level is connected to the 1056 register chain for reading back. When the port TDQ output of the 1056 register chain is a high level, it is determined that the Flash unit is completely erased; when the port TDQ output of the 1056 register chain is a low level, it can be determined that the Flash unit is not completely erased; (3) Select branch ②, close branch ① and branch ③, and perform programming operation on the completely erased Flash cell; Branch ② is composed of three PMOS tubes P1, P2, and P3 connected in series. The source of PMOS tube P1, i.e., port VS1, is connected to a positive high voltage. The drain of PMOS tube P3 is connected to the word line. PMOS tubes P1, P2, and P3 are turned on by a low level. The positive high voltage acts on the floating gate in the Flash unit through the word line WL, thereby realizing programming operation of a pair of Flash transistors with a common floating gate in the Flash unit. (4) Select branch ③, close branch ① and branch ②, and test the switch tube in the programmed Flash unit; In the switch test circuit, the port RST is low level, and the inverter G1 <1> The enable configuration signal is turned off by adding a low level, and node C is at a low level; inverter G1 <2> The enable configuration signal is turned on with a high level, and node B is at a high level at this time; if the Flash unit is fully programmed, that is, the Switch tube is in the "open circuit" state, the high level of node B cannot be transmitted to node C, and node C is still at a low level at this time, and the low level is connected to the 1056 register chain for readback; when the port TDQ output of the 1056 register chain is at a low level, it is determined that the Flash unit is fully programmed; when the port TDQ output of the 1056 register chain is at a high level, it is determined that the Flash unit is not fully programmed.

8. The test circuit of the Flash unit according to claim 4 or 6, characterized in that: A level 1 register chain is composed of a selector, a trigger, and a latch. 1184 level 1 register chains are cascaded into a 1184-level register chain, 138 level 1 register chains are cascaded into a 138-level register chain, and 1056 level 1 register chains are cascaded into a 1056-level register chain.

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