Verification and error correction method, verification and error correction circuit and memory

Abstract

The embodiment of the invention provides a check error correction method, a check error correction circuit and a memory, and the check error correction method comprises the steps: carrying out the one-to-one corresponding XOR comparison of a first check sequence and a second check sequence, and outputting an initial error correction sequence; if the first odd-even value is different from the second odd-even value, outputting the initial error correction sequence as a target error correction sequence, and determining the position of error data based on a preset check matrix; and if the first parity value and the second parity value are the same, shielding the initial error correction sequence.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a check and error correction method, a check and error correction circuit, and a memory. Background Art

[0002] As the manufacturing process of dynamic random access memory (DRAM) becomes more and more advanced and the storage density becomes higher and higher, the data stored in DRAM may be erroneous, which seriously affects the performance of DRAM. Therefore, DRAM usually uses error checking and correcting (ECC) technology to detect or correct errors in stored data.

[0003] The ECC circuit can adopt the error correction mechanism of Hamming Code. In the ECC circuit based on Hamming Code, Hamming Code is effective for single-bit errors. However, when there are multi-bit errors in DRAM, it will still be corrected as a single-bit error, which will lead to miscorrection, increase the number of error bits, and increase the error pattern. Summary of the invention

[0004] The embodiments of the present disclosure provide a verification and error correction method, a verification and error correction circuit, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a verification and error correction method, the method comprising:

[0006] Calculating the written data set, outputting a first check sequence and a first parity value; and calculating the read data set, outputting a second check sequence and a second parity value; wherein the first parity value represents that the value of an odd number or an even number of data in the written data set is a first preset value; and the second parity value represents that the value of an odd number or an even number of data in the read data set is the first preset value;

[0007] Performing a one-to-one XOR comparison on the first check sequence and the second check sequence, and outputting an initial error correction sequence;

[0008] If the first parity value and the second parity value are different, outputting the initial error correction sequence as a target error correction sequence; if the first parity value and the second parity value are the same, shielding the initial error correction sequence;

[0009] The target error correction sequence is decoded based on a preset check matrix to determine the location of the erroneous data.

[0010] In some embodiments, the preset check matrix includes a plurality of sub-check columns, and each of the sub-check columns corresponds to a bit of data in the data set;

[0011] The decoding process of the target error correction sequence based on a preset check matrix to determine the location of the erroneous data includes:

[0012] The sub-check column that is the same as the target error correction sequence is determined in the preset check matrix, and data corresponding to the determined sub-check column is determined as the error data.

[0013] In some embodiments, the data set includes a low-order data portion and a high-order data portion;

[0014] The binary expression of the sub-check column corresponding to each data in the low-order data portion has an odd number of the first preset values;

[0015] The binary expression of the sub-check column corresponding to each data in the high-order data portion has an even number of the first preset values.

[0016] In some embodiments, the initial error correction sequence and the target error correction sequence each include N bits of data;

[0017] If the first parity value and the second parity value are different, outputting the initial error correction sequence as a target error correction sequence; if the first parity value and the second parity value are the same, shielding the initial error correction sequence, comprising:

[0018] Performing an XOR comparison on the first parity value and the second parity value to generate a parity check value;

[0019] Performing a logical operation on the parity check value and the i-th bit data of the initial error correction sequence to generate the i-th bit data of the target error correction sequence;

[0020] Wherein, N is an integer greater than 0, and i is an integer greater than 0 and less than or equal to N.

[0021] In some embodiments, when the data set includes 128-bit data, the low-order data portion includes the 0th data group, the 1st data group, the 2nd data group and the 3rd data group, and the high-order data portion includes the 4th data group, the 5th data group, the 6th data group and the 7th data group; each of the data groups includes 16-bit data;

[0022] For the 0th data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 104, 97, 98, 107, 100, 109, 110, 103, 112, 121, 122, 115, 124, 117, 118, 127;

[0023] For the first data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 168, 161, 162, 171, 164, 173, 174, 167, 176, 185, 186, 179, 188, 181, 182, 191;

[0024] For the second data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 200, 193, 194, 203, 196, 205, 206, 199, 208, 217, 218, 211, 220, 213, 214, 223;

[0025] For the third data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 248, 241, 242, 251, 244, 253, 254, 247, 224, 233, 234, 227, 236, 229, 230, 239;

[0026] For the fourth data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 40, 33, 34, 43, 36, 45, 46, 39, 48, 57, 58, 51, 60, 53, 54, 63;

[0027] For the fifth data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 72, 65, 66, 75, 68, 77, 78, 71, 80, 89, 90, 83, 92, 85, 86, 95;

[0028] For the sixth data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 184, 177, 178, 187, 180, 189, 190, 183, 160, 169, 170, 163, 172, 165, 166, 175;

[0029] For the 7th data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 216, 209, 210, 219, 212, 221, 222, 215, 192, 201, 202, 195, 204, 197, 198, 207 respectively.

[0030] In some embodiments, the first check sequence includes the 0th check value to the 7th check value, and the calculating the written data set to output the first check sequence and the first parity value includes:

[0031] For each of the data groups, performing an XOR operation on the 0th, 3rd, 5th, and 6th bit data to generate a first intermediate value_0, performing an XOR operation on the 9th, 10th, 12th, and 15th bit data to generate a first intermediate value_1; performing an XOR operation on the first intermediate value_0 and the first intermediate value_1 to generate a first intermediate value_2;

[0032] Performing an XOR operation on the first intermediate value_2 of the 0th data group and the first intermediate value_2 of the 1st data group to generate a first intermediate value_4A; performing an XOR operation on the first intermediate value_2 of the 2nd data group and the first intermediate value_2 of the 3rd data group to generate a first intermediate value_4B; performing an XOR operation on the first intermediate value_2 of the 4th data group and the first intermediate value_2 of the 5th data group to generate a first intermediate value_4C; performing an XOR operation on the first intermediate value_2 of the 6th data group and the first intermediate value_2 of the 7th data group to generate a first intermediate value_4D;

[0033] Calculate the first intermediate value_4A, the first intermediate value_4B, the first intermediate value_4C and the first intermediate value_4D to generate a third check value;

[0034] as well as,

[0035] For each of the data groups, performing an XOR operation on the 1st, 3rd, 5th and 7th bits of data to generate a second intermediate value_0, performing an XOR operation on the 9th, 11th, 13th and 15th bits of data to generate a second intermediate value_1; performing an XOR operation on the second intermediate value_0 and the second intermediate value_1 to generate a second intermediate value_2;

[0036] Performing an XOR operation on the second intermediate value_2 of the 0th data group and the second intermediate value_2 of the 1st data group to generate a second intermediate value_4A; performing an XOR operation on the second intermediate value_2 of the 2nd data group and the second intermediate value_2 of the 3rd data group to generate a second intermediate value_4B; performing an XOR operation on the second intermediate value_2 of the 4th data group and the second intermediate value_2 of the 5th data group to generate a second intermediate value_4C; performing an XOR operation on the second intermediate value_2 of the 6th data group and the second intermediate value_2 of the 7th data group to generate a second intermediate value_4D;

[0037] Perform an XOR operation on the second intermediate value_4A, the second intermediate value_4B, the second intermediate value_4C and the second intermediate value_4D to generate a 0th check value;

[0038] as well as,

[0039] For each of the data groups, performing an XOR operation on the 2nd, 3rd, 6th and 7th bit data to generate a third intermediate value_0, performing an XOR operation on the 10th, 11th, 14th and 15th bit data to generate a third intermediate value_1; performing an XOR operation on the third intermediate value_0 and the third intermediate value_1 to generate a third intermediate value_2;

[0040] Performing an XOR operation on the third intermediate value_2 of the 0th data group and the third intermediate value_2 of the 1st data group to generate a third intermediate value_4A; performing an XOR operation on the third intermediate value_2 of the 2nd data group and the third intermediate value_2 of the 3rd data group to generate a third intermediate value_4B; performing an XOR operation on the third intermediate value_2 of the 4th data group and the third intermediate value_2 of the 5th data group to generate a third intermediate value_4C; performing an XOR operation on the third intermediate value_2 of the 6th data group and the third intermediate value_2 of the 7th data group to generate a third intermediate value_4D;

[0041] Performing an XOR operation on the third intermediate value_4A, the third intermediate value_4B, the third intermediate value_4C and the third intermediate value_4D to generate a first check value;

[0042] as well as,

[0043] For each of the data groups, performing an XOR operation on the 4th, 5th, 6th and 7th bits of data to generate a fourth intermediate value_0, performing an XOR operation on the 12th, 13th, 14th and 15th bits of data to generate a fourth intermediate value_1; performing an XOR operation on the fourth intermediate value_0 and the fourth intermediate value_1 to generate a fourth intermediate value_2;

[0044] Performing an XOR operation on the fourth intermediate value_2 of the 0th data group and the fourth intermediate value_2 of the 1st data group to generate a fourth intermediate value_4A; performing an XOR operation on the fourth intermediate value_2 of the 2nd data group and the fourth intermediate value_2 of the 3rd data group to generate a fourth intermediate value_4B; performing an XOR operation on the fourth intermediate value_2 of the 4th data group and the fourth intermediate value_2 of the 5th data group to generate a fourth intermediate value_4C; performing an XOR operation on the fourth intermediate value_2 of the 6th data group and the fourth intermediate value_2 of the 7th data group to generate a fourth intermediate value_4D;

[0045] An XOR operation is performed on the fourth intermediate value_4A, the fourth intermediate value_4B, the fourth intermediate value_4C and the fourth intermediate value_4D to generate a second check value.

[0046] In some embodiments, the step of calculating the written data set and outputting a first check sequence and a first parity value further includes:

[0047] For each of the data groups, performing an XOR operation on the 0th, 1st, 2nd and 3rd bit data to generate a fifth intermediate value_0, and performing an XOR operation on the 8th, 9th, 10th and 11th bit data to generate a fifth intermediate value_1;

[0048] Performing an XOR operation on the fourth intermediate value_0 and the fifth intermediate value_0 to generate a sixth intermediate value_0; performing an XOR operation on the fourth intermediate value_1 and the fifth intermediate value_1 to generate a sixth intermediate value_1;

[0049] Performing an XOR operation on the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_1 of the 1st data group, the sixth intermediate value_1 of the 2nd data group, the sixth intermediate value_0 of the 3rd data group, the sixth intermediate value_1 of the 4th data group, the sixth intermediate value_1 of the 5th data group, the sixth intermediate value_0 of the 6th data group, and the sixth intermediate value_0 of the 7th data group to generate a fourth check value;

[0050] Perform an XOR operation on the sixth intermediate value_0 of the 0th data group, the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_0 of the 1st data group, the sixth intermediate value_1 of the 1st data group, the sixth intermediate value_0 of the 3rd data group, the sixth intermediate value_1 of the 3rd data group, the sixth intermediate value_0 of the 4th data group, the sixth intermediate value_1 of the 4th data group, the sixth intermediate value_0 of the 6th data group, and the sixth intermediate value_1 of the 6th data group to generate a fifth check value;

[0051] Perform an XOR operation on the sixth intermediate value_0 of the second data group, the sixth intermediate value_1 of the second data group, the sixth intermediate value_0 of the third data group, the sixth intermediate value_1 of the third data group, the sixth intermediate value_0 of the 0th data group, the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_0 of the 5th data group, the sixth intermediate value_1 of the 5th data group, the sixth intermediate value_0 of the 7th data group, and the sixth intermediate value_1 of the 7th data group to generate a sixth check value;

[0052] The sixth intermediate value_0 of the second data group, the sixth intermediate value_1 of the second data group, the sixth intermediate value_0 of the third data group, the sixth intermediate value_1 of the third data group, the sixth intermediate value_0 of the first data group, the sixth intermediate value_1 of the first data group, the sixth intermediate value_0 of the sixth data group, the sixth intermediate value_1 of the sixth data group, the sixth intermediate value_0 of the sixth data group, the sixth intermediate value_1 of the sixth data group, the sixth intermediate value_0 of the seventh data group and the sixth intermediate value_1 of the seventh data group are XOR-ed to generate a seventh check value.

[0053] In some embodiments, the step of calculating the written data set and outputting a first check sequence and a first parity value further includes:

[0054] An exclusive OR operation is performed on the sixth intermediate value_0 of the 0th data group, the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_0 of the 1st data group, the sixth intermediate value_1 of the 1st data group, the sixth intermediate value_0 of the 2nd data group, the sixth intermediate value_1 of the 2nd data group, the sixth intermediate value_0 of the 3rd data group, the sixth intermediate value_1 of the 3rd data group, the sixth intermediate value_0 of the 4th data group, the sixth intermediate value_1 of the 4th data group, the sixth intermediate value_0 of the 5th data group, the sixth intermediate value_1 of the 5th data group, the sixth intermediate value_0 of the 6th data group, the sixth intermediate value_1 of the 6th data group, the sixth intermediate value_0 of the 7th data group, and the sixth intermediate value_1 of the 7th data group to generate the first parity value.

[0055] In a second aspect, an embodiment of the present disclosure provides a check and error correction circuit, the check and error correction circuit comprising:

[0056] A check module is configured to calculate the written data set and output a first check sequence and a first parity value; and to calculate the read data set and output a second check sequence and a second parity value; wherein the first parity value represents that the value of the odd or even number of data in the written data set is a first preset value; and the second parity value represents that the value of the odd or even number of data in the read data set is the first preset value;

[0057] a calculation module, connected to the verification module, configured to perform a one-to-one XOR comparison on the first verification sequence and the second verification sequence, and output an initial error correction sequence;

[0058] a gating module connected to the calculation module and configured to output the initial error correction sequence as a target error correction sequence if the first parity value and the second parity value are different; and to shield the initial error correction sequence if the first parity value and the second parity value are the same;

[0059] The positioning module is configured to decode the target error correction sequence and output a target error address; wherein the target error address indicates the location of the error data.

[0060] In some embodiments, the initial error correction sequence and the target error correction sequence each include N bits of data; the gating module includes a comparison module and N logic units;

[0061] The comparison module is configured to perform an XOR comparison on the first parity value and the second parity value to generate a parity check value;

[0062] The i-th logic unit is configured to perform a logic operation on the parity check value and the i-th bit data of the initial error correction sequence to generate the i-th bit data of the target error correction sequence;

[0063] Wherein, N is an integer greater than 0, and i is an integer greater than 0 and less than or equal to N.

[0064] In some embodiments, the logic unit includes a first trigger, a first NOT gate, a second trigger, a second NOT gate and a first AND gate; wherein:

[0065] The first clock terminal of the first trigger is used to receive a first clock signal, the input terminal of the first trigger is used to receive the parity check value, the inverting output terminal of the first trigger is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is used to output the parity sampling check value;

[0066] The first clock terminal of the second flip-flop is used to receive the first clock signal, the input terminal of the second flip-flop is used to receive the i-th bit data of the initial error correction sequence, the inverting output terminal of the second flip-flop is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is used to output the i-th bit data of the initial sampling error correction sequence;

[0067] The first input end of the first AND gate is used to receive the parity sampling check value, the second input end of the first AND gate is used to receive the i-th bit data of the initial sampling error correction sequence, and the output end of the first AND gate is used to output the i-th bit data of the target error correction sequence.

[0068] In some embodiments, the decoding logic of the positioning module is determined based on a preset check matrix, the preset check matrix includes multiple sub-check columns, and each of the sub-check columns has a corresponding relationship with a bit of data in the data set, and the error data refers to the data corresponding to the sub-check column that is the same as the target error correction sequence.

[0069] In some embodiments, the data set includes a low-order data portion and a high-order data portion; the low-order data portion or the high-order data portion includes multiple data groups, and each of the data groups includes multi-bit data; the positioning module includes a first decoding submodule, a second decoding submodule and a logic processing module, wherein:

[0070] The first decoding submodule is configured to receive and decode a portion of the data of the target error correction sequence, and output a first error address signal, wherein the first error address signal indicates a data group number to which the error data belongs;

[0071] The second decoding submodule is configured to receive and decode the remaining data of the target error correction sequence, and output a second error address signal, wherein the second error address signal indicates the position number of the error data in the data group to which it belongs;

[0072] The logic processing module is configured to receive and perform a logic operation on the first error address signal and the second error address signal, and output the target error address;

[0073] Among them, the binary expression form of the sub-check column corresponding to each data in the low-order data part has an odd number of the first preset values; the binary expression form of the sub-check column corresponding to each data in the high-order data part has an even number of the first preset values.

[0074] In some embodiments, the second decoding submodule is configured to receive the 0th to 3rd bit data of the target error correction sequence and output the second error address signal;

[0075] The first decoding submodule is configured to receive the 4th to 7th bits of the target error correction sequence and output the first error address signal;

[0076] The logic processing module is configured to receive and perform an OR operation on the first error address signal and the second error address signal, and output the target error address.

[0077] In a third aspect, an embodiment of the present disclosure provides a memory, which at least includes a check and error correction circuit as described in any one of the second aspects.

[0078] The embodiments of the present disclosure provide a verification and error correction method, a verification and error correction circuit, and a memory. The verification and error correction method includes calculating a written data set, outputting a first verification sequence and a first parity value; and calculating a read data set, outputting a second verification sequence and a second parity value; wherein the first parity value represents that there are an odd or even number of data values ​​in the written data set, which is a first preset value; the second parity value represents that there are an odd or even number of data values ​​in the read data set, which is a first preset value; performing a one-to-one XOR comparison on the first verification sequence and the second verification sequence, and outputting an initial error correction sequence; if the first parity value and the second parity value are different, outputting the initial error correction sequence as a target error correction sequence; if the first parity value and the second parity value are the same, shielding the initial error correction sequence; decoding the target error correction sequence based on a preset check matrix to determine the location of the erroneous data. In this way, based on the first parity value calculated based on the written data set and the second parity value calculated based on the read data set, it is determined whether to output the initial error correction sequence as the target error correction sequence and determine the location of the erroneous data, or to shield the initial error correction sequence. Therefore, when there are multiple erroneous data in the data set, correction is performed when an odd number of erroneous data occurs, based on the parity of the number of erroneous data, to control the spread of the miscorrection; when an even number of erroneous data occurs, no correction is performed. In this way, the memory performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 A schematic diagram of the composition of data;

[0080] Figure 2 A schematic diagram of a process for checking and correcting errors provided in an embodiment of the present disclosure Figure 1 ;

[0081] Figure 3 A schematic diagram of a process for checking and correcting errors provided in an embodiment of the present disclosure Figure 2 ;

[0082] Figure 4 A schematic diagram of the structure of a check and error correction circuit provided in an embodiment of the present disclosure;

[0083] Figures 5 to 10 A schematic diagram of the structure of a verification module provided in an embodiment of the present disclosure Figures 1 to 6 ;

[0084] Fig.11 A schematic diagram of the structure of a gate control module provided in an embodiment of the present disclosure Figure 1 ;

[0085] Fig.12 A schematic diagram of the structure of an inverting module provided in an embodiment of the present disclosure;

[0086] Fig.13A schematic diagram of the structure of a gate control module provided in an embodiment of the present disclosure Figure 2 ;

[0087] Fig.14 A schematic diagram of the structure of a positioning module provided in an embodiment of the present disclosure;

[0088] Fig.15 A schematic diagram of the composition structure of a first decoding submodule provided in an embodiment of the present disclosure;

[0089] Fig.16 A schematic diagram of the composition structure of a second decoding submodule provided in an embodiment of the present disclosure;

[0090] Fig.17 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0091] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant applications, rather than to limit the present disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant applications are shown in the drawings.

[0092] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0093] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0094] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0095] Hamming code is a linear block code. In the one-hot code, the 1st, 2nd, 4th, ..., 2nd mThe data bits (m is an integer greater than or equal to 0) are set with check bits, and grouped according to the position of 1 in the binary expression of the check bits, and the grouped data is written into the check bits for parity check, and then the data bits and check bits are combined and sent to the receiving end, which performs parity check again. If a single-bit (also called single data) error occurs during data transmission, the error syndrome obtained after verification is the position of the data bit where the error occurred; if a multi-bit (also called multiple data) error occurs, the error syndrome obtained will be the mutual exclusive OR result of the single-bit error syndrome.

[0096] Taking 128-bit data as an example, a fault in DRAM may only affect some bits in the 128-bit data. Such an error is called a bounded fault. In the fifth-generation double data rate (DDR5) standard, for bounded faults, each data group (Data, DQ) contains 16 bits of data, and 8 DQs are divided into two nibbles. When a bounded fault occurs and multiple bit errors occur in the defined Nibble, the DDR5 standard stipulates that the on-die ECC error correction position can only be the check bit or the Nibble where the error occurs, and will not affect other DQs.

[0097] The rank-level ECC circuit used in the integrated memory controller (IMC) can provide Chipkill-level full-device data correction for X4 DRAM and half-device data correction for X8 DRAM. Therefore, for the integrated memory controller, it is hoped that the X8DRAM provided by the DRAM vendor will concentrate the errors in 4 DQs to facilitate data correction and improve system reliability.

[0098] See also Figure 1 , which shows a schematic diagram of the composition of data. Figure 1 As shown, 128-bit data is divided into 8 DQs, each DQ contains 16-bit data, that is, the same burst contains 16-bit data; the 8 DQs are divided into two Nibbles, namely Nibble A and Nibble B, each Nibble includes 4 DQs, forming a boundary, specifically, Nibble A includes DQ0 to DQ3, and Nibble B includes DQ4 to DQ7. It can be understood that the boundary containing 64-bit data has a stronger coverage capability for miscorrection caused by the ECC circuit.

[0099] However, when encountering multi-bit errors, the ECC circuit based on Hamming code still treats it as a single-bit error and corrects it, resulting in an increase in error modes. In order to reduce the number of error modes recognized by the memory controller (MC), the design can prevent the miscorrection from spreading to other DQs at will, thereby facilitating correction by the ECC circuit at the hierarchical level.

[0100] Based on this, an embodiment of the present disclosure provides a verification and error correction method, which determines whether to output an initial error correction sequence as a target error correction sequence and determine the location of the erroneous data, or to mask the initial error correction sequence, based on a first parity value calculated based on a written data set and a second parity value calculated based on a read data set. Thus, when there are multiple erroneous data in a data set, correction is performed when an odd number of erroneous data occurs, thereby controlling the spread of the miscorrection, and no correction is performed when an even number of erroneous data occurs. In this way, the memory performance can be improved.

[0101] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0102] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of a process of a verification and error correction method provided by an embodiment of the present disclosure Figure 1 .like Figure 2 As shown, the method may include:

[0103] S101, calculating the written data set, and outputting a first check sequence and a first parity value; and calculating the read data set, and outputting a second check sequence and a second parity value.

[0104] It should be noted that, in the embodiment of the present disclosure, the first parity value represents that the value of an odd or even number of data in the written data set is the first preset value; the second parity value represents that the value of an odd or even number of data in the read data set is the first preset value.

[0105] It should also be noted that the embodiment of the present disclosure provides a verification and error correction method, specifically an ECC circuit design method for bounded faults, which relates to on-chip error correction circuit design in integrated circuits, and in particular to calculating the check bits (first check sequence and first parity value) when writing a data set in a DRAM chip, and storing them in a specific storage array, and calculating the check bits (second check sequence and second parity value) again when reading the data set, and then comparing them with the stored check bit values ​​to obtain an error representation of the erroneous data, and correcting the erroneous data based on this information. Among them, the method can be applied to related circuit designs that perform on-chip error correction functions in DRAM chips, and can also be applied to other circuit designs for bounded faults and reducing error modes, which are not specifically limited by the embodiment of the present disclosure.

[0106] Here, the data set may include 128 bits of data (also referred to as 128 bits of data), or may include 256 bits of data, etc., without specific limitation; illustratively, the specific implementation of the embodiment of the present disclosure is described in detail by taking the data set including 128 bits of data as an example. In addition, both the first check sequence and the second check sequence include an 8-bit check value; that is, by calculating the 128-bit data bit (i.e., the data set), a 9-bit check bit (i.e., the first check sequence and the first parity value, or the second check sequence and the second parity value) can be obtained.

[0107] The 8-bit check value, the first parity value and the second parity value included in the first check sequence and the second check sequence can be 1 or 0, and there is no limitation on this. In addition, the first preset value is logic "1", indicating a high level state.

[0108] This embodiment may adopt even parity check, that is, when the first parity value is 1, the value of "1" is taken to indicate that there are an odd number of data in the written data set; when the first parity value is 0, the value of "1" is taken to indicate that there are an even number of data in the written data set; similarly, when the second parity value is 1, the value of "1" is taken to indicate that there are an odd number of data in the read data set; when the second parity value is 0, the value of "1" is taken to indicate that there are an even number of data in the read data set. This embodiment may also adopt odd parity check, that is, when the first parity value is 1, the value of "1" is taken to indicate that there are an even number of data in the written data set; when the first parity value is 0, the value of "1" is taken to indicate that there are an odd number of data in the written data set; similarly, when the second parity value is 1, the value of "1" is taken to indicate that there are an even number of data in the read data set; when the second parity value is 0, the value of "1" is taken to indicate that there are an odd number of data in the read data set. Among them, even number of data also includes zero data, that is, the value of "1" is taken when there is no data; illustratively, the specific implementation of the disclosed embodiment is described in detail by taking the even parity check as an example.

[0109] S102, performing a one-to-one XOR comparison on the first check sequence and the second check sequence, and outputting an initial error correction sequence.

[0110] After obtaining the first check sequence according to the written data set and obtaining the second check sequence according to the read data set, it is also necessary to perform a one-to-one XOR comparison on each check value in the first check sequence and the second check sequence to output an initial error correction sequence. For example, if the first check sequence is (10001010) and the second check sequence is (00101010), then the initial error correction sequence is (10100000).

[0111] S103: If the first parity value and the second parity value are different, output the initial error correction sequence as the target error correction sequence; if the first parity value and the second parity value are the same, mask the initial error correction sequence.

[0112] When the first parity value is 1 and the second parity value is 0, or when the first parity value is 0 and the second parity value is 1, and the first parity value and the second parity value are different, the first parity value, the second parity value and the initial error correction sequence are calculated to obtain a target error correction sequence; when the first parity value and the second parity value are both 0, or when the first parity value and the second parity value are both 1, and the first parity value and the second parity value are the same, the initial error correction sequence is shielded and the initial error correction sequence is not output.

[0113] It should be noted that, when the first parity value and the second parity value are different, it means that the read data set has an odd number of erroneous data compared to the written data set; when the first parity value and the second parity value are the same, it means that the read data set has an even number of erroneous data compared to the written data set, wherein the even number of erroneous data also includes zero erroneous data. At this time, the read data set has no data error compared to the written data set.

[0114] S104: Decode the target error correction sequence based on a preset check matrix to determine the location of the erroneous data.

[0115] When the first parity value and the second parity value are different, after obtaining the target error correction sequence according to the initial error correction sequence, the position of the erroneous data can be obtained according to the preset check matrix, and the erroneous data can be corrected.

[0116] The disclosed embodiment provides an ECC circuit design method using a (137, 128) Hamming code (i.e., 128 data bits and 9 check bits). When the ECC circuit using the Hamming code encounters a multi-bit error caused by a bounded fault, the parity of the number of multi-bit errors is determined, and correction is initiated when an odd-numbered bit error occurs. The spread of the miscorrection is controlled so that it does not affect other data and does not cause an uncorrected error to occur in the ECC circuit at the hierarchical level. When an even-numbered bit error occurs, no correction is performed.

[0117] In another embodiment of the present disclosure, see Figure 3 , which shows a schematic diagram of a process of a verification and error correction method provided by an embodiment of the present disclosure Figure 2 .like Figure 3 As shown, the method may include:

[0118] S201, calculating the written data set, and outputting a first check sequence and a first parity value; and calculating the read data set, and outputting a second check sequence and a second parity value.

[0119] S202, performing a one-to-one XOR comparison on the first check sequence and the second check sequence, and outputting an initial error correction sequence.

[0120] S203 , performing an XOR comparison on the first parity value and the second parity value to generate a parity check value.

[0121] S204 , performing a logical operation on the parity check value and the i-th bit data of the initial error correction sequence to generate the i-th bit data of the target error correction sequence.

[0122] S205: Determine a sub-check column that is identical to a target error correction sequence in a preset check matrix, and determine data corresponding to the determined sub-check column as error data.

[0123] It should be noted that in the embodiment of the present disclosure, steps S201 and S202 correspond to steps S101 and S102 in the aforementioned embodiment, respectively, and for the sake of brevity, they are not described here in detail. In addition, steps S203 and S204 are a specific implementation of step S103 in the aforementioned embodiment, and step S205 is a specific implementation of step S104 in the aforementioned embodiment, which will be described in detail below.

[0124] It should also be noted that both the initial error correction sequence and the target error correction sequence include N-bit data, where N is an integer greater than 0, and i is an integer greater than 0 and less than or equal to N. Step S204 is a specific implementation of outputting the initial error correction sequence as the target error correction sequence when the first parity value and the second parity value are different; and shielding the initial error correction sequence when the first parity value and the second parity value are the same.

[0125] For step S204, specifically, an AND logic operation can be performed on the parity check value and the i-th bit data of the initial error correction sequence to obtain the i-th bit data of the target error correction sequence; it can be understood that after the parity check value and each bit data in the initial error correction sequence are ANDed, the target error correction sequence can be obtained.

[0126] When writing a data set, i.e., during the encoding process, the first check sequence and the first parity value are calculated based on the written data set to record the status; when reading a data set, i.e., during the correction process, the read data set is recalculated to obtain the second check sequence and the second parity value; then the first parity value and the second parity value are XOR-ed to determine the parity of the number of erroneous data. Specifically, when the XOR result of the first parity value and the second parity value, i.e., the parity check value, is 1, it means that the first parity value and the second parity value are different, and an odd number of erroneous data has occurred, so it is corrected; when the parity check value is 0, it means that the first parity value and the second parity value are the same, and an even number of erroneous data has occurred or no data error has occurred, so no correction is performed.

[0127] It should also be noted that the preset check matrix includes multiple sub-check columns, and each sub-check column has a corresponding relationship with a bit of data in the data set; specifically, the data in the data set is in decimal expression, and the sub-check column is a binary expression corresponding to the data in the data set. For step S205, after obtaining the target error correction sequence, the sub-check column that is the same as the target error correction sequence is determined in the multiple sub-check columns of the preset check matrix, and then the position of the erroneous data is determined, and the erroneous data is corrected.

[0128] In some embodiments, the data set includes a low-order data portion and a high-order data portion; the binary expression of the sub-check column corresponding to each data in the low-order data portion has an odd number of first preset values; the binary expression of the sub-check column corresponding to each data in the high-order data portion has an even number of first preset values.

[0129] It should be noted that the data in the data set corresponding to the binary expression with an odd number of first preset values ​​"1" can be called odd weight, and the data in the data set corresponding to the binary expression with an even number of first preset values ​​"1" can be called even weight. It can be understood that the sub-check column with even weight is obtained after two sub-check columns with odd weights or two sub-check columns with even weights are different or obtained, and the sub-check column with odd weights and the sub-check column with even weights are different or obtained; wherein, the two sub-check columns are different or refer to the corresponding position data in the sub-check columns being different or one by one, so as to obtain a new sub-check column.

[0130] Here, the data set containing 128 bits of data can be divided into two Nibbles, namely, a low-order data part and a high-order data part, and the low-order data part and the high-order data part respectively include 4 data groups. Exemplarily, the specific implementation of the embodiment of the present disclosure is described in detail by taking the sub-check columns with odd weights corresponding to each data in the low-order data part and the sub-check columns with even weights corresponding to each data in the high-order data part as an example.

[0131] In some embodiments, when the data set includes 128-bit data, the lower data portion includes the 0th data group, the 1st data group, the 2nd data group, and the 3rd data group, and the upper data portion includes the 4th data group, the 5th data group, the 6th data group, and the 7th data group; each data group includes 16-bit data;

[0132] For the 0th data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 104, 97, 98, 107, 100, 109, 110, 103, 112, 121, 122, 115, 124, 117, 118, 127;

[0133] For the first data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 168, 161, 162, 171, 164, 173, 174, 167, 176, 185, 186, 179, 188, 181, 182, 191;

[0134] For the second data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 200, 193, 194, 203, 196, 205, 206, 199, 208, 217, 218, 211, 220, 213, 214, 223;

[0135] For the third data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 248, 241, 242, 251, 244, 253, 254, 247, 224, 233, 234, 227, 236, 229, 230, 239;

[0136] For the fourth data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 40, 33, 34, 43, 36, 45, 46, 39, 48, 57, 58, 51, 60, 53, 54, 63;

[0137] For the fifth data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 72, 65, 66, 75, 68, 77, 78, 71, 80, 89, 90, 83, 92, 85, 86, 95;

[0138] For the sixth data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 184, 177, 178, 187, 180, 189, 190, 183, 160, 169, 170, 163, 172, 165, 166, 175;

[0139] For the 7th data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 216, 209, 210, 219, 212, 221, 222, 215, 192, 201, 202, 195, 204, 197, 198, 207.

[0140] It should be noted that the data set includes 128 bits of data, which are the 0th bit data D <0> , the first data D <1> , ..., 127th data D <127> , the data set can be represented by D<127:0>, where D<127:0> is <0> To D <127> A total of 128 bits of data can be written in a merged manner. In addition, the 0th data group can be represented by DQ0, which includes data D<15:0>; the 1st data group can be represented by DQ1, which includes data D<31:16>; the 2nd data group can be represented by DQ2, which includes data D<47:32>; the 3rd data group can be represented by DQ3, which includes data D<63:48>; the 4th data group can be represented by DQ4, which includes data D<79:64>; the 5th data group can be represented by DQ5, which includes data D<95:80>; the 6th data group can be represented by DQ6, which includes data D<111:96>; the 7th data group can be represented by DQ7, which includes data D<127:112>; the low-order data part can be represented by Nibble A, which includes DQ0~DQ3; the high-order data part can be represented by Nibble B, which includes DQ4~DQ7.

[0141] The preset check matrix can be as follows, where the brackets are sub-check columns in binary expression corresponding to each data in the data set:

[0142] Data group 0: 104 (01101000), 97 (01100001), 98 (01100010), 107 (01101011), 100 (01100100), 109 (01101101), 110 (01101110), 103 (01100111), 112 (01110000), 121 (01111001), 122 (01111010), 115 (01110011), 124 (01111100), 117 (01110101), 118 (01110110), 127 (01111111);

[0143] Data group 1: 168 (10101000), 161 (10100001), 162 (10100010), 171 (10101011), 164 (10100100), 173 (10101101), 174 (10101110), 167 (10100111), 176 (10110000), 185 (10111001), 186 (10111010), 179 (10110011), 188 (10111100), 181 (10110101), 182 (10110110), 191 (10111111);

[0144] Data group 2: 200 (11001000), 193 (11000001), 194 (11000010), 203 (11001011), 196 (11000100), 205 (11001101), 206 (11001110), 199 (11000111), 208 (11010000), 217 (11011001), 218 (11011010), 211 (11010011), 220 (11011100), 213 (11010101), 214 (11010110), 223 (11011111);

[0145] Data group 3: 248 (11111000), 241 (11110001), 242 (11110010), 251 (11111011), 244 (11110100), 253 (11111101), 254 (11111110), 247 (11110111), 224 (11100000), 233 (11101001), 234 (11101010), 227 (11100011), 236 (11101100), 229 (11100101), 230 (11100110), 239 (11101111);

[0146] Data group 4: 40 (00101000), 33 (00100001), 34 (00100010), 43 (00101011), 36 (00100100), 45 (00101101), 46 (00101110), 39 (00100111), 48 (00110000), 57 (00111001), 58 (00111010), 51 (00110011), 60 (00111100), 53 (00110101), 54 (00110110), 63 (00111111);

[0147] Data group 5: 72 (01001000), 65 (01000001), 66 (01000010), 75 (01001011), 68 (01000100), 77 (01001101), 78 (01001110), 71 (01000111), 80 (01010000), 89 (01011001), 90 (01011010), 83 (01010011), 92 (01011100), 85 (01010101), 86 (01010110), 95 (01011111);

[0148] Data group 6: 184 (10111000), 177 (10110001), 178 (10110010), 187 (10111011), 180 (10110100), 189 (10111101), 190 (10111110), 183 (10110111), 160 (10100000), 169 (10101001), 170 (10101010), 163 (10100011), 172 (10101100), 165 (10100101), 166 (10100110), 175 (10101111);

[0149] Data group 7: 216 (11011000), 209 (11010001), 210 (11010010), 219 (11011011), 212 (11010100), 221 (11011101), 222 (11011110), 215 (11010111), 192 (11000000), 201 (11001001), 202 (11001010), 195 (11000011), 204 (11001100), 197 (11000101), 198 (11000110), 207 (11001111).

[0150] It can be seen from the above preset check matrix that the upper 4 bits of data in the binary expression of the sub-check column corresponding to the data in each data group are the same; and in the same data group, the lower 3 bits of data in the binary expression of the sub-check column corresponding to the 0th to 7th data and the 8th to 15th data are all the same, specifically, the 0th data corresponds to the 8th data, the 1st data corresponds to the 9th data, the 2nd data corresponds to the 10th data, the 3rd data corresponds to the 11th data, the 4th data corresponds to the 12th data, the 5th data corresponds to the 13th data, the 6th data corresponds to the 14th data, and the 7th data corresponds to the 15th data. Exemplarily, for the 0th data group, the upper 4 bits of the binary expressions of the sub-check columns corresponding to the data 104, 97, 98, 107, 100, 109, 110, 103, 112, 121, 122, 115, 124, 117, 118 and 127 are all (0110); the lower 3 bits of the binary expressions of the sub-check columns corresponding to the 0th data 104 and the 8th data 112 are all (000).

[0151] When a bounded fault causes multiple erroneous data to occur in a Nibble (Nibble A or Nibble B) including 4 DQs, the generated odd-numbered erroneous data are corrected, and the odd-numbered erroneous data in Nibble A corresponding to the odd-weighted sub-check column is still an odd-weighted sub-check column after ECC calculation. The erroneous data is either corrected back to Nibble A, or corrected to the check value or an unused error representation in the preset check matrix. Exemplarily, the three erroneous data in Nibble A occur in the first bit data (Burst0) of DQ0, DQ1 and DQ2, that is, data 104, 168 and 200, and after ECC calculation, the error representation obtained is data 8, which is corrected to the check value; if the three errors occur in data 98, 186 and 254, respectively, the error representation obtained after calculation is data 38, which is corrected to the unused error representation. In particular, when an odd number of erroneous data occurs on the same DQ, the miscorrection will always be corrected to the same DQ.

[0152] Similarly, the odd-numbered error data in Nibble B corresponding to the even-weighted sub-check column is still an even-weighted sub-check column after ECC calculation, but the error data will only be corrected back to Nibble B. For example, if three errors occur in data 40, 72, and 184 respectively, the error representation obtained after calculation is data 216.

[0153] It should be noted that the error representations finally obtained by the multiple error data are the result of the XOR of the error representations of each single error data, that is, the final error representations of the multiple error data can be obtained according to the result of the XOR of the corresponding bits in the binary expression corresponding to each single error data. Exemplarily, when three error data occur, specifically, errors occur at positions 104 (01101000), 168 (10101000), and 200 (11001000), the final error representation is (00001000), which is data 8.

[0154] According to Table 1, the range of the final miscorrected positions of multiple erroneous data can be predicted. The first row and the first column in Table 1 represent the data range covered by the 8-bit check value, that is, data 0 to 255, and the middle of Table 1 is the result of the mutual XOR of the corresponding position data. As shown in Table 1, the result obtained by the mutual XOR of the 8 bits of binary expression corresponding to the same data range is always in data 0_31, and the result obtained by the mutual XOR of the 8 bits of binary expression corresponding to data 0_31 and other ranges is always within the data range. Exemplarily, the result obtained by the mutual XOR of the 8 bits of binary expression corresponding to data 32_63 and data 32_63 is in data 0_31; the result obtained by the mutual XOR of the 8 bits of binary expression corresponding to data 0_31 and data 64_95 is in data 64_95; the result obtained by the mutual XOR of the 8 bits of binary expression corresponding to data 96_127 and data 160_191 is in data 192_223.

[0155] When selecting a sub-check column with an odd weight, it is necessary to select a continuous column, which is not only convenient for the implementation of the encoding and decoding circuits, but also in the error representation of each 32-bit data, when an odd number of erroneous data occurs, the error representation caused by multiple erroneous data will always return to the original range. Since the data 0_31, 32_63, 64_95 and 128_159 all include check values ​​(data 1, 2, 4, 8, 16, 32, 64 and 128), the sub-check column with an odd weight is selected as shown in Table 1; for the sub-check column with an even weight, it is necessary to select a simple error representation, so as to facilitate the implementation of the circuit. It can be seen from Table 1 that the sub-check column with an even weight should be selected from the data group that is symmetrical above and below. Since there is a sub-check column with all zeros, the sub-check column with an even weight is selected from data 32~95 and 160~223.

[0156] Table 1

[0157] / 0_31 32_63 64_95 96_127 128_159 160_191 192_223 224_255 0_31 0_31 32_63 64_95 96_127 128_159 160_191 192_223 224_255 32_63 32_63 0_31 96_127 64_95 160_191 128_159 224_255 192_223 64_95 64_95 96_127 0_31 32_63 192_223 224_255 128_159 160_191 96_127 96_127 64_95 32_63 0_31 224_255 192_223 160_191 128_159 128_159 128_159 160_191 192_223 224_255 0_31 32_63 64_95 96_127 160_191 160_191 128_159 224_255 192_223 32_63 0_31 96_127 64_95 192_223 192_223 224_255 128_159 160_191 64_95 96_127 0_31 32_63 224_255 224_255 192_223 160_191 128_159 96_127 64_95 32_63 0_31

[0158] To summarize, the 128-bit data in the data set is grouped according to the above-mentioned 0th to 7th data groups, so that correction can be performed when an odd number of erroneous data occurs, and the miscorrection is controlled to spread only in the same data part (low-order data part or high-order data part); when an even number of erroneous data occurs, no correction is performed.

[0159] In some embodiments, the first check sequence includes the 0th check value to the 7th check value, and the written data set is calculated to output the first check sequence and the first parity value, including:

[0160] For each data group, the 0th, 3rd, 5th, and 6th bits of data are XORed to generate a first intermediate value_0, and the 9th, 10th, 12th, and 15th bits of data are XORed to generate a first intermediate value_1; the first intermediate value_0 and the first intermediate value_1 are XORed to generate a first intermediate value_2;

[0161] Perform an XOR operation on the first intermediate value _2 of the 0th data group and the first intermediate value _2 of the 1st data group to generate a first intermediate value _4A; perform an XOR operation on the first intermediate value _2 of the 2nd data group and the first intermediate value _2 of the 3rd data group to generate a first intermediate value _4B; perform an XOR operation on the first intermediate value _2 of the 4th data group and the first intermediate value _2 of the 5th data group to generate a first intermediate value _4C; perform an XOR operation on the first intermediate value _2 of the 6th data group and the first intermediate value _2 of the 7th data group to generate a first intermediate value _4D;

[0162] The first intermediate value_4A, the first intermediate value_4B, the first intermediate value_4C and the first intermediate value_4D are operated to generate a third check value.

[0163] It should be noted that, for each data group, it contains 16 bits of data, namely, the 0th bit data D <0> , the first data D <1> , ..., 15th data D <15> , the data group can be represented by D<15:0>, where D<15:0> is D <0> To D <15> In addition, the 16-bit data can be divided into two parts, each with 8 bits of data, namely the 0th to 7th bit data, which can be represented by D<7:0>; and the 8th to 15th bit data, which can be represented by D<15:8>; among which D<7:0> is D <0> To D <7> A total of 8 bits of data are written together, D<15:8> is D <8> To D <15> A total of 8 bits of data are combined and written.

[0164] It should also be noted that the 0th, 3rd, 5th, and 6th bits of data are D in D<15:0> <0> , D <3> , D <5> , D <6> , that is, D in D<7:0> <0> , D <3> , D <5> , D <6> ; The 9th, 10th, 12th, and 15th bits are D in D<15:0> <9> , D <10> , D <12> , D <15> , that is, D in D<15:8> <1> , D <2> , D <4> , D <7> In addition, the first intermediate value_0 is D0356 in D<7:0>, the first intermediate value_1 is D1247 in D<15:8>; the first intermediate value_2 can be represented by D0356_2B; the first intermediate value_4A, the first intermediate value_4B, the first intermediate value_4C and the first intermediate value_4D can all be represented by D0356_4B, and the difference between them is that they are obtained by performing an XOR operation on the first intermediate value_2 of two different data groups; the third check value can be represented by PAR <3> express.

[0165] as well as,

[0166] For each data group, the 1st, 3rd, 5th, and 7th bits of data are XORed to generate a second intermediate value_0, and the 9th, 11th, 13th, and 15th bits of data are XORed to generate a second intermediate value_1; the second intermediate value_0 and the second intermediate value_1 are XORed to generate a second intermediate value_2;

[0167] The second intermediate value _2 of the 0th data group and the second intermediate value _2 of the 1st data group are subjected to an XOR operation to generate a second intermediate value _4A; the second intermediate value _2 of the 2nd data group and the second intermediate value _2 of the 3rd data group are subjected to an XOR operation to generate a second intermediate value _4B; the second intermediate value _2 of the 4th data group and the second intermediate value _2 of the 5th data group are subjected to an XOR operation to generate a second intermediate value _4C; the second intermediate value _2 of the 6th data group and the second intermediate value _2 of the 7th data group are subjected to an XOR operation to generate a second intermediate value _4D;

[0168] An XOR operation is performed on the second intermediate value_4A, the second intermediate value_4B, the second intermediate value_4C, and the second intermediate value_4D to generate a 0th check value.

[0169] It should be noted that the 1st, 3rd, 5th, and 7th bits of data are D in D<15:0> <1> , D <3> , D <5> , D <7> , that is, D in D<7:0> <1> , D <3> , D <5> , D <7> ; The 9th, 11th, 13th, and 15th bits are D in D<15:0> <9> , D <11> , D <13> , D <15> , that is, D in D<15:8> <1> , D <3> , D <5> , D <7> In addition, the second intermediate value_0 is D1357 in D<7:0>, the second intermediate value_1 is D1357 in D<15:8>; the second intermediate value_2 can be represented by D1357_2B; the second intermediate value_4A, the second intermediate value_4B, the second intermediate value_4C and the second intermediate value_4D can all be represented by D1357_4B. The difference between them is that they are obtained by performing an XOR operation on the second intermediate values_2 of two different data groups; the 0th check value can be represented by PAR <0> express.

[0170] as well as,

[0171] For each data group, the 2nd, 3rd, 6th and 7th bits of data are XORed to generate a third intermediate value_0, and the 10th, 11th, 14th and 15th bits of data are XORed to generate a third intermediate value_1; the third intermediate value_0 and the third intermediate value_1 are XORed to generate a third intermediate value_2;

[0172] Perform an XOR operation on the third intermediate value_2 of the 0th data group and the third intermediate value_2 of the 1st data group to generate a third intermediate value_4A; perform an XOR operation on the third intermediate value_2 of the 2nd data group and the third intermediate value_2 of the 3rd data group to generate a third intermediate value_4B; perform an XOR operation on the third intermediate value_2 of the 4th data group and the third intermediate value_2 of the 5th data group to generate a third intermediate value_4C; perform an XOR operation on the third intermediate value_2 of the 6th data group and the third intermediate value_2 of the 7th data group to generate a third intermediate value_4D;

[0173] An XOR operation is performed on the third intermediate value_4A, the third intermediate value_4B, the third intermediate value_4C and the third intermediate value_4D to generate a first check value.

[0174] It should be noted that the 2nd, 3rd, 6th, and 7th bits of data are D in D<15:0> <2> , D <3> , D <6> , D <7> , that is, D in D<7:0> <2> , D <3> , D <6> , D <7> ; The 10th, 11th, 14th, and 15th bits are D in D<15:0> <10> , D <11> , D <14> , D <15> , that is, D in D<15:8> <2> , D <3> , D <6> , D <7> In addition, the third intermediate value_0 is D2367 in D<7:0>, the third intermediate value_1 is D2367 in D<15:8>; the third intermediate value_2 can be represented by D2367_2B; the third intermediate value_4A, the third intermediate value_4B, the third intermediate value_4C and the third intermediate value_4D can all be represented by D2367_4B, and the difference between them is that they are obtained by performing an XOR operation on the third intermediate value_2 of two different data groups; the first check value can be represented by PAR <1> express.

[0175] as well as,

[0176] For each data group, the 4th, 5th, 6th, and 7th bits of data are XORed to generate a fourth intermediate value_0, and the 12th, 13th, 14th, and 15th bits of data are XORed to generate a fourth intermediate value_1; the fourth intermediate value_0 and the fourth intermediate value_1 are XORed to generate a fourth intermediate value_2;

[0177] The fourth intermediate value_2 of the 0th data group and the fourth intermediate value_2 of the 1st data group are subjected to an XOR operation to generate a fourth intermediate value_4A; the fourth intermediate value_2 of the 2nd data group and the fourth intermediate value_2 of the 3rd data group are subjected to an XOR operation to generate a fourth intermediate value_4B; the fourth intermediate value_2 of the 4th data group and the fourth intermediate value_2 of the 5th data group are subjected to an XOR operation to generate a fourth intermediate value_4C; the fourth intermediate value_2 of the 6th data group and the fourth intermediate value_2 of the 7th data group are subjected to an XOR operation to generate a fourth intermediate value_4D;

[0178] An XOR operation is performed on the fourth intermediate value_4A, the fourth intermediate value_4B, the fourth intermediate value_4C and the fourth intermediate value_4D to generate a second check value.

[0179] It should be noted that the 4th, 5th, 6th, and 7th bits of data are D in D<15:0> <4> , D <5> , D <6> , D <7> , that is, D in D<7:0> <4> , D <5> , D <6> , D <7> ; The 12th, 13th, 14th, and 15th bits are D in D<15:0> <12> , D <13> , D <14> , D <15> , that is, D in D<15:8> <4> , D <5> , D <6> , D <7> In addition, the fourth intermediate value_0 is D4567 in D<7:0>, the fourth intermediate value_1 is D4567 in D<15:8>; the fourth intermediate value_2 can be represented by D4567_2B; the fourth intermediate value_4A, the fourth intermediate value_4B, the fourth intermediate value_4C and the fourth intermediate value_4D can all be represented by D4567_4B, and the difference between them is that they are obtained by performing an XOR operation on the fourth intermediate value_2 of two different data groups; the second check value can be represented by PAR <2> express.

[0180] In some embodiments, calculating the written data set and outputting a first check sequence and a first parity value further includes:

[0181] For each data group, the 0th, 1st, 2nd, and 3rd bits of data are XORed to generate a fifth intermediate value_0, and the 8th, 9th, 10th, and 11th bits of data are XORed to generate a fifth intermediate value_1;

[0182] Perform an XOR operation on the fourth intermediate value_0 and the fifth intermediate value_0 to generate a sixth intermediate value_0; perform an XOR operation on the fourth intermediate value_1 and the fifth intermediate value_1 to generate a sixth intermediate value_1;

[0183] performing an XOR operation on the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_1 of the 1st data group, the sixth intermediate value_1 of the 2nd data group, the sixth intermediate value_0 of the 3rd data group, the sixth intermediate value_1 of the 4th data group, the sixth intermediate value_1 of the 5th data group, the sixth intermediate value_0 of the 6th data group, and the sixth intermediate value_0 of the 7th data group to generate a fourth check value;

[0184] Performing an XOR operation on the sixth intermediate value_0 of the 0th data group, the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_0 of the 1st data group, the sixth intermediate value_1 of the 1st data group, the sixth intermediate value_0 of the 3rd data group, the sixth intermediate value_1 of the 3rd data group, the sixth intermediate value_0 of the 4th data group, the sixth intermediate value_1 of the 4th data group, the sixth intermediate value_0 of the 6th data group, and the sixth intermediate value_1 of the 6th data group to generate a fifth check value;

[0185] Performing an XOR operation on the sixth intermediate value_0 of the second data group, the sixth intermediate value_1 of the second data group, the sixth intermediate value_0 of the third data group, the sixth intermediate value_1 of the third data group, the sixth intermediate value_0 of the 0th data group, the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_0 of the 5th data group, the sixth intermediate value_1 of the 5th data group, the sixth intermediate value_0 of the 7th data group, and the sixth intermediate value_1 of the 7th data group to generate a sixth check value;

[0186] The sixth intermediate value_0 of the second data group, the sixth intermediate value_1 of the second data group, the sixth intermediate value_0 of the third data group, the sixth intermediate value_1 of the third data group, the sixth intermediate value_0 of the first data group, the sixth intermediate value_1 of the first data group, the sixth intermediate value_0 of the sixth data group, the sixth intermediate value_1 of the sixth data group, the sixth intermediate value_0 of the sixth data group, the sixth intermediate value_1 of the sixth data group, the sixth intermediate value_0 of the seventh data group and the sixth intermediate value_1 of the seventh data group are XORed to generate the seventh check value.

[0187] It should be noted that the 0th, 1st, 2nd, and 3rd bits of data are D in D<15:0> <0> , D <1> , D <2> , D <3> , that is, D in D<7:0> <0> , D <1> , D <2> , D <3> ; The 8th, 9th, 10th, and 11th bits are D in D<15:0> <8> , D <9> , D <10> , D <11> , that is, D in D<15:8> <0> , D <1> , D <2> , D <3> In addition, the fifth intermediate value_0 is D0123 in D<7:0>, and the fifth intermediate value_1 is D0123 in D<15:8>; the sixth intermediate value_0 can be represented by ALL_B0, and the sixth intermediate value_1 can be represented by ALL_B1; the fourth check value can be represented by PAR <4> Indicates that the fifth check value can be used with PAR <5> Indicates that the sixth check value can be used with PAR <6> Indicates that the seventh check value can be used with PAR <7> express.

[0188] Specifically, the sixth intermediate value_0 of the 0th data group can be represented by All_B0(L), the sixth intermediate value_1 of the 0th data group can be represented by All_B1(L), the sixth intermediate value_0 of the 1st data group can be represented by All_B2(L), the sixth intermediate value_1 of the 1st data group can be represented by All_B3(L), ​​the sixth intermediate value_0 of the 2nd data group can be represented by All_B4(L), the sixth intermediate value_1 of the 2nd data group can be represented by All_B5(L), the sixth intermediate value_0 of the 3rd data group can be represented by All_B6(L), and the sixth intermediate value_1 of the 3rd data group can be represented by All_B7(L). The sixth intermediate value_0 of the 4th data group can be represented by All_B0(R), the sixth intermediate value_1 of the 4th data group can be represented by All_B1(R), the sixth intermediate value_0 of the 5th data group can be represented by All_B2(R), the sixth intermediate value_1 of the 5th data group can be represented by All_B3(R), the sixth intermediate value_0 of the 6th data group can be represented by All_B4(R), the sixth intermediate value_1 of the 6th data group can be represented by All_B5(R), the sixth intermediate value_0 of the 7th data group can be represented by All_B6(R), and the sixth intermediate value_1 of the 7th data group can be represented by All_B7(R). Here, L represents the lower data portion, and R represents the higher data portion.

[0189] For the fourth check value, All_B1(L), All_B3(L), ​​All_B5(L) and All_B6(L) can be XORed to obtain All1356L; at the same time, All_B1(R), All_B3(R), All_B4(R) and All_B6(R) can be XORed to obtain All1346R; then All1356L and All1346R can be XORed to obtain the fourth check value PAR <4> .

[0190] For the fifth check value, All_B0(L), All_B1(L), All_B2(L) and All_B3(L) can be XORed to obtain All0123L; All_B6(L) and All_B7(L) can be XORed to obtain All67L; All0123L and All67L can be XORed to obtain the fifth check value PAR. <5> .

[0191] For the sixth check value, All_B4(L), All_B5(L), All_B6(L) and All_B7(L) can be XORed to obtain All4567L; All_B0(L) and All_B1(L) can be XORed to obtain All01L; All_B2(R), All_B3(R), All_B6(R) and All_B7(R) can be XORed to obtain All2367R; All4567L, All01L and All2367R can be XORed to obtain the sixth check value PAR <6> .

[0192] For the 7th check value, All_B4(L), All_B5(L), All_B6(L) and All_B7(L) can be XORed to obtain All4567L; All_B2(L) and All_B3(L) can be XORed to obtain ALL23L; All_B4(R), All_B5(R), All_B6(R) and All_B7(R) can be XORed to obtain All4567R; All4567L, ALL23L and All4567R can be XORed to obtain the 7th check value PAR <7> .

[0193] In some embodiments, calculating the written data set and outputting a first check sequence and a first parity value further includes:

[0194] The sixth intermediate value_0 of the 0th data group, the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_0 of the 1st data group, the sixth intermediate value_1 of the 1st data group, the sixth intermediate value_0 of the 2nd data group, the sixth intermediate value_1 of the 2nd data group, the sixth intermediate value_0 of the 3rd data group, the sixth intermediate value_1 of the 3rd data group, the sixth intermediate value_0 of the 4th data group, the sixth intermediate value_1 of the 4th data group, the sixth intermediate value_0 of the 5th data group, the sixth intermediate value_1 of the 5th data group, the sixth intermediate value_0 of the 6th data group, the sixth intermediate value_1 of the 6th data group, the sixth intermediate value_0 of the 6th data group, the sixth intermediate value_1 of the 6th data group, the sixth intermediate value_0 of the 7th data group and the sixth intermediate value_1 of the 7th data group are XOR-ed to generate a first parity value.

[0195] The first parity value can be used with PAR <8> For the first parity value, All_B0(L), All_B1(L), All_B2(L), All_B3(L), ​​All_B4(L), All_B5(L), All_B6(L) and All_B7(L) can be XORed to obtain ALL_L; at the same time, All_B0(R), All_B1(R), All_B2(R), All_B3(R), All_B4(R), All_B5(R), All_B6(R) and All_B7(R) can be XORed to obtain ALL_R; then ALL_L and ALL_R can be XORed to obtain the first parity value PAR. <8> .

[0196] It should be noted that the method of calculating the read data set and outputting the second check sequence and the second parity value is similar to the method of calculating the first check sequence and the first parity value, which will not be repeated here and can be understood by referring to the description of the aforementioned embodiment.

[0197] In another embodiment of the present disclosure, see Figure 4 , which shows a schematic diagram of the structure of a check and error correction circuit provided by an embodiment of the present disclosure. Figure 4 As shown, the check and error correction circuit 30 may include:

[0198] The check module 31 is configured to calculate the written data set and output a first check sequence and a first parity value; and to calculate the read data set and output a second check sequence and a second parity value;

[0199] The calculation module 32 is connected to the verification module 31 and is configured to perform a one-to-one XOR comparison on the first verification sequence and the second verification sequence, and output an initial error correction sequence;

[0200] The gating module 33 is connected to the calculation module 32 and is configured to output the initial error correction sequence as the target error correction sequence if the first parity value and the second parity value are different; and to shield the initial error correction sequence if the first parity value and the second parity value are the same;

[0201] The positioning module 34 is configured to decode the target error correction sequence and output a target error address.

[0202] It should be noted that, in the embodiment of the present disclosure, the first parity value represents that there are an odd or even number of data in the written data set, which is a first preset value; the second parity value represents that there are an odd or even number of data in the read data set, which is a first preset value; and the target error address indicates the location of the error data.

[0203] It should also be noted that in the embodiment of the present disclosure, the check error correction circuit 30 can be applied to a memory. Among them, the memory can be such as a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., which are not specifically limited here. In addition, the check error correction circuit 30 is specifically an ECC circuit for bounded faults, and the circuit can be implemented by applying the check error correction method in the aforementioned embodiment. For details not disclosed in the embodiment of the present disclosure, please refer to the description of the aforementioned embodiment for understanding.

[0204] Here, the first check sequence and the first parity value calculated according to the data set written by the check module 31 can be first stored in the storage array, and after the second check sequence and the second parity value are obtained, the first check sequence and the first parity value are taken out from the storage array for subsequent XOR operations, etc.

[0205] For the verification module 31, see Figures 5 to 10 , which shows a schematic diagram of the composition structure of a verification module provided by an embodiment of the present disclosure Figures 1 to 6 .like Figure 5 As shown, D<7:0> is inverted to obtain DB<7:0>; specifically, DB <0> Yes D <0> After inversion, DB <1> Yes D <1> After inversion, DB <2> Yes D <2> After inversion, DB <3> Yes D <3> After inversion, DB <4> Yes D <4> After inversion, DB <5> Yes D <5> After inversion, DB <6> Yes D <6> After inversion, DB <7> Yes D <7> Obtained by reverse phase treatment.

[0206] For the 8-bit data D<7:0> or D<15:8> in each data group, you can first <5> and D <6> Perform XOR operation to get D56; at the same time, D <0> and D <3> Perform an XOR operation on D56 and D03 to obtain D0356, which is the first intermediate value _0. <5> and D <7> Perform XOR operation to get D57; at the same time, D <1> and D <3> Perform an XOR operation on D57 and D13 to obtain D1357, which is the second intermediate value_0 or the second intermediate value_1. <6> and D <7> Perform XOR operation to get D67; at the same time, D <2> and D <3> Perform an XOR operation on D67 and D23 to obtain D2367, which is the third intermediate value_0 or the third intermediate value_1. <6> and D <7> Perform XOR operation to get D67; at the same time, D <4> and D <5> Perform an XOR operation on D45 to obtain D45; then perform an XOR operation on D67 and D45 to obtain D4567, which is the fourth intermediate value_0 or the fourth intermediate value_1. <2> and D <3> Perform XOR operation to get D23; at the same time, D <0> and D <1> Perform an XOR operation on D23 and D01 to obtain D0123, which is the fifth intermediate value_0 or the fifth intermediate value_1. <4> and D <7> Perform XOR operation to get D47; at the same time, D <1> and D <2> Perform an XOR operation to obtain D12; then perform an XOR operation on D47 and D12 to obtain D1247, which is the first intermediate value_1. It should be noted that the specific calculation order for obtaining each value is not specifically limited in the embodiments of the present disclosure.

[0207] like Figure 5 As shown, D0356B is the complementary signal of D0356, D1357B is the complementary signal of D1357, D2367B is the complementary signal of D2367, D4567B is the complementary signal of D4567, and D0123B is the complementary signal of D0123.

[0208] exist Figure 6 In the example, D1247B is the complementary signal of D1247. Similarly, D1357B_2B is the complementary signal of D1357_2B, D2367B_2B is the complementary signal of D2367_2B, D4567B_2B is the complementary signal of D4567_2B, D0356B_2B is the complementary signal of D0356_2B, ALLB_B0 is the complementary signal of ALL_B0, and ALLB_B1 is the complementary signal of ALL_B1. Figure 6The circuit shown can obtain the first intermediate value_2 (D0356_2B), the second intermediate value_2 (D1357_2B), the third intermediate value_2 (D2367_2B), the fourth intermediate value_2 (D4567_2B), the sixth intermediate value_0 (ALL_B0) and the sixth intermediate value_1 (ALL_B1).

[0209] like Figure 7 As shown, D1357B_4B is the complementary signal of D1357_4B. Similarly, D2367B_4B is the complementary signal of D2367_4B, D4567B_4B is the complementary signal of D4567_4B, D0356B_4B is the complementary signal of D0356_4B, ALLB_B2 is the complementary signal of ALL_B2, and ALLB_B3 is the complementary signal of ALL_B3. Figure 7 The circuit shown can obtain the first intermediate value_4A, the first intermediate value_4B, the first intermediate value_4C, the first intermediate value_4D (D0356_4B), the second intermediate value_4A, the second intermediate value_4B, the second intermediate value_4C, the second intermediate value_4D (D1357_4B), the third intermediate value_4A, the third intermediate value_4B, the third intermediate value_4C, the third intermediate value_4D (D2367_4B), the fourth intermediate value_4A, the fourth intermediate value_4B, the fourth intermediate value_4C and the fourth intermediate value_4D (D4567_4B).

[0210] It should be noted that in Figure 6 and Figure 7 In the FPGA, VSS represents the ground voltage and VDD represents the power supply voltage; VDD is used to provide a high-level signal (logic "1") and VSS is used to provide a low-level signal (logic "0").

[0211] For the lower data portion (0th to 3rd data groups), according to Figure 8 The circuit shown can produce ALL1356L, ALL4567L, ALL0123L and ALL_L. Figure 8 As shown, ALL1356LB is the complementary signal of ALL1356L, ALL4567LB is the complementary signal of ALL4567L, ALL0123LB is the complementary signal of ALL0123L, and ALL_LB is the complementary signal of ALL_L.

[0212] For the high-order data portion (4th to 7th data groups), according to Fig. 9The circuit shown can be used to obtain ALL1346 (i.e. ALL1346R), ALL4567 (i.e. ALL4567R), ALL2367 (i.e. ALL2367R), ALL0145 (i.e. ALL0145R), ALL0123 (i.e. ALL0123R) and ALL_R. Fig. 9 As shown, ALL1346B is the complementary signal of ALL1346, ALL4567B is the complementary signal of ALL4567, ALL2367B is the complementary signal of ALL2367, ALL0145B is the complementary signal of ALL0145, ALL0123B is the complementary signal of ALL0123, and ALL_RB is the complementary signal of ALL_R.

[0213] Fig.10 The circuit shown combines the last XOR operation together to obtain the fourth check value PAR. <4> , the fifth check value PAR <5> , the sixth check value PAR <6> , 7th check value PAR <7> and the first parity value PAR <8> Alternatively, you can Fig.10 The calculation method shown in the figure obtains the 0th check value PAR <0> , the first calibration value PAR <1> , the second calibration value PAR <2> and the third calibration value PAR <3> For example, D1357_0123 represents the XOR sum of the 1st, 3rd, 5th, and 7th bits of all positions in the bytes of bytes 0, 1, 2, and 3; PAR <3> It is the exclusive OR of the 0th, 3rd, 5th, 6th data bits and the 1st, 2nd, 4th, 7th data bits in every two bytes.

[0214] It should be noted that, for each data group, each data group consists of two bytes, D<7:0> is one byte, and D<15:8> is another byte. Fig.10 As shown, a represents the 10th bit of data, b represents the 11th bit of data, c represents the 12th bit of data, d represents the 13th bit of data, e represents the 14th bit of data, and f represents the 15th bit of data.

[0215] It can be understood that the check module 31 is composed of XOR gates, and each check value (first check sequence, first parity value, second check sequence, and second parity value) is obtained by XORing many data bits. According to the special grouping of the above data set, after the first check sequence, the first parity value, the second check sequence, and the second parity value are obtained by XORing the check module 31, when there are multiple erroneous data in the data set, correction can be performed when an odd number of erroneous data occurs, and no correction can be performed when an even number of erroneous data occurs.

[0216] In some embodiments, the calculation module 32 may be composed of an XOR gate or a comparator to perform a one-to-one XOR comparison on the first check sequence and the second check sequence, which is not specifically limited.

[0217] For the gate control module 33, see Fig.11 , which shows a schematic diagram of the composition structure of a door control module provided by an embodiment of the present disclosure Figure 1 ,like Fig.11 As shown, in some embodiments, the initial error correction sequence and the target error correction sequence both include N-bit data.

[0218] The gate control module 33 may include a comparison module 331 and N logic units 332; wherein:

[0219] A comparison module 331 is configured to perform an XOR comparison on the first parity value and the second parity value to generate a parity check value;

[0220] The i-th logic unit 332 is configured to perform a logic operation on the parity check value and the i-th bit data of the initial error correction sequence to generate the i-th bit data of the target error correction sequence.

[0221] It should be noted that N is an integer greater than 0, and i is an integer greater than 0 and less than or equal to N.

[0222] It should also be noted that Fig.11 The schematic diagram of the composition structure of only one logic unit 332 is shown by way of example. For the N logic units 332 included in the gating module 33, only the data in the received initial error correction sequence is different, and other received signals and circuit structures are the same. That is, different logic units 332 are used to receive data in different initial error correction sequences to obtain the target error correction sequence.

[0223] For the i-th logic unit 332, in some embodiments, Fig.11 As shown, the logic unit 332 may include a first trigger U1, a first NOT gate U2, a second trigger U3, a second NOT gate U4 and a first AND gate U5; wherein:

[0224] The first clock terminal of the first trigger U1 is used to receive the first clock signal, the input terminal of the first trigger U1 is used to receive the parity check value, the inverting output terminal of the first trigger U1 is connected to the input terminal of the first NOT gate U2, and the output terminal of the first NOT gate U2 is used to output the parity sampling check value;

[0225] The first clock terminal of the second flip-flop U3 is used to receive the first clock signal, the input terminal of the second flip-flop U3 is used to receive the i-th bit data of the initial error correction sequence, the inverting output terminal of the second flip-flop U3 is connected to the input terminal of the second NOT gate U4, and the output terminal of the second NOT gate U4 is used to output the i-th bit data of the initial sampling error correction sequence;

[0226] The first input end of the first AND gate U5 is used to receive the parity sampling check value, the second input end of the first AND gate U5 is used to receive the i-th bit data of the initial sampling error correction sequence, and the output end of the first AND gate U5 is used to output the i-th bit data of the target error correction sequence.

[0227] It should be noted that, in the disclosed embodiment, the first trigger U1 and the second trigger U3 may be D-type triggers (Data Flip-Flop or Delay Flip-Flop, DFF). The D-type trigger is an information storage device with a memory function and two stable states. It is the most basic logic unit constituting a variety of sequential circuits and an important unit circuit in digital logic circuits. Here, the D-type trigger has two stable states, namely "0" and "1", and can flip from one stable state to another stable state under the action of the signal received at the clock end.

[0228] It should also be noted that, in the embodiment of the present disclosure, the first trigger U1 and the second trigger U3 may include an input terminal (D), a first clock terminal (CK), a second clock terminal (CKB) and an inverting output terminal (QN); in addition, a first output terminal (Q), a set terminal (SET) and a reset terminal (RST) may also be included, but not shown in the figure. The first trigger U1 and the second trigger U3 may also receive the parity check value and the i-th bit data of the initial error correction sequence through a latch respectively to achieve sampling, but this is not specifically limited.

[0229] Here, the input end of the first trigger U1 serves as the first input end of the i-th logic unit 332, for receiving the parity check value; the input end of the second trigger U3 serves as the second input end of the i-th logic unit 332, for receiving the i-th bit data of the initial error correction sequence; the output end of the first AND gate U5 serves as the output end of the i-th logic unit 332, for outputting the i-th bit data of the target error correction sequence.

[0230] It should also be noted that the first clock signal is generated using a read command and bank group (BG) information. The first clock signal utilizes the read data set to be used as an enable signal for calculation in the verification module 31, so that it passes through the same number of XOR gates and some delay units as in the verification module 31 to match the delay of the second verification sequence and the second parity value calculation, thereby ensuring that the result calculated by the verification module 31 can be sampled.

[0231] like Fig.11 As shown, the first trigger U1 and the second trigger U3 also include a second clock terminal for receiving a second clock signal. The first clock signal and the second clock signal are differential clock signals. Fig.12 As shown, in some embodiments, the gating module 33 may further include an inverting module 333, wherein:

[0232] The inversion module 333 is used to receive the first clock signal, and perform inversion processing on the first clock signal to obtain a second clock signal.

[0233] like Fig.12 As shown, the inversion module 333 may include a third NOT gate U6 , an input end of the third NOT gate U6 is used to receive the first clock signal, and an output end of the third NOT gate U6 is used to output the second clock signal.

[0234] In addition, the parity sampling check value can be used PART <8> Indicates that the initial sampling error correction sequence can be represented by PART<7:0>, the first clock signal can be represented by RD_ECC_CLKT, and the second clock signal can be represented by RD_ECC_CLKB.

[0235] In another implementation, Fig.11 Based on Fig.13 , which shows a schematic diagram of the composition structure of a door control module provided by an embodiment of the present disclosure Figure 2 ,like Fig.13 As shown, the first AND gate U5 can also be replaced by a first NAND gate U7 and a fourth NAND gate U8, wherein:

[0236] The first input end of the first NAND gate U7 is used to receive the parity sampling check value, the second input end of the first NAND gate U7 is used to receive the i-th bit data of the initial sampling error correction sequence, the output end of the first NAND gate U7 is connected to the input end of the fourth NAND gate U8, and the output end of the fourth NAND gate U8 is used to output the i-th bit data of the target error correction sequence.

[0237] In summary, the parity check value indicates the parity of the number of erroneous data in the data set. The parity check value of 0 represents an even number of erroneous data, so the initial error correction sequence is shielded and no correction is performed. The specific method is to change the initial error correction sequence to (00000000) through the first AND gate U5, and the error representation of all zeros will not be corrected; the parity check value of 1 represents an odd number of erroneous data, so the initial error correction sequence is output as the target error correction sequence for correction. That is to say, 128 bits of data (i.e., data set) are calculated by the check module 31 to obtain 9 bits of check bits (i.e., initial error correction sequence and parity check value), and the other check bits (i.e., initial sampling error correction sequence) are ANDed with the full check bits of the data (i.e., parity sampling check value) after being latched by the first trigger U1 and the second trigger U3. When an even number of erroneous data occurs, the error representation of all zeros is used to correct the 128 bits of data, and the error representation of all zeros will not be corrected; when an odd number of erroneous data occurs, the calculated error representation (i.e., target error correction sequence) is output to correct the 128 bits of data.

[0238] For the positioning module 34, in some embodiments, the decoding logic of the positioning module 34 is determined based on a preset check matrix, which includes multiple sub-check columns, and each sub-check column has a corresponding relationship with a bit of data in the data set, and the error data refers to the data corresponding to the sub-check column that is the same as the target error correction sequence.

[0239] That is, after a sub-check column identical to a target error correction sequence is determined in the preset check matrix, data corresponding to the determined sub-check column is determined as erroneous data.

[0240] In some embodiments, the data set includes a low-order data portion and a high-order data portion; the low-order data portion or the high-order data portion includes multiple data groups, and each data group includes multiple bits of data.

[0241] When the data set includes 128 bits of data, there are 8 data groups in total, the low-order data part includes the 0th data group, the 1st data group, the 2nd data group and the 3rd data group, and the high-order data part includes the 4th data group, the 5th data group, the 6th data group and the 7th data group; each data group contains 16 bits of data.

[0242] See also Fig.14 , which shows a schematic diagram of the composition structure of a positioning module provided by an embodiment of the present disclosure. Fig.14 As shown, the positioning module 34 includes a first decoding submodule 341, a second decoding submodule 342 and a logic processing module 343, wherein:

[0243] A first decoding submodule 341 is configured to receive and decode data of a portion of a target error correction sequence, and output a first error address signal, wherein the first error address signal indicates a data group number to which the error data belongs;

[0244] The second decoding submodule 342 is configured to receive and decode the data of the remaining target error correction sequence, and output a second error address signal, wherein the second error address signal indicates the position number of the error data in the data group to which it belongs;

[0245] The logic processing module 343 is configured to receive and perform a logic operation on the first error address signal and the second error address signal, and output a target error address;

[0246] The sub-check column corresponding to each data in the low-order data part has an odd number of first preset values ​​in its binary expression; the sub-check column corresponding to each data in the high-order data part has an even number of first preset values ​​in its binary expression.

[0247] It should be noted that the target error correction sequence includes 8 bits of data, which are the 0th bit data PAR' <0> , 1st bit data PAR' <1> , ..., 7th data PAR' <7> , the target error correction sequence can be represented by PAR'<7:0>, PAR'<7:0> is PAR' <0> To PAR' <7> A total of 8 bits of data are combined and written.

[0248] It should also be noted that the data set is divided into 8 data groups, each data group contains 16 bits of data, and the first error address signal is used to determine the data group number to which the error data belongs, that is, which data group of the 8 data groups the error data belongs to; after determining the data group number to which the error data belongs, the second error address signal is used to determine the position number of the error data in the data group to which it belongs, that is, which position of the error data is in the data group to which it belongs.

[0249] Specifically, Fig.14 As shown, in some embodiments, the second decoding submodule 342 is configured to receive the 0th to 3rd bit data of the target error correction sequence and output a second error address signal;

[0250] The first decoding submodule 341 is configured to receive the 4th to 7th bits of the target error correction sequence and output a first error address signal;

[0251] The logic processing module 343 is configured to receive and perform an OR operation on the first error address signal and the second error address signal, and output a target error address.

[0252] Here, if Fig.14As shown, the second decoding submodule 342 may further include a fifth NOT gate a1, and an output terminal of the fifth NOT gate a1 is used to output a second error address signal.

[0253] The logic processing module 343 may include a first NOR gate a2 and a sixth NOR gate a3, wherein: the first input end of the first NOR gate a2 is used to receive the second error address signal, the second input end of the first NOR gate a2 is used to receive the first error address signal, the output end of the first NOR gate a2 is connected to the input end of the sixth NOR gate a3, and the output end of the sixth NOR gate a3 is used to output the target error address.

[0254] The first error address signal may be represented by CODE1B, the second error address signal may be represented by CODE0B<7:0>, and the target error address may be represented by COR_BIT<7:0>; the input end of the fifth NOT gate a1 is used to receive CODE0<7:0>.

[0255] like Fig.14 As shown, PAR' <0> It can also be expressed as COR <0> , PAR' <1> It can also be expressed as COR <1> , PAR' <2> It can also be expressed as COR <2> , PAR' <3> It can also be expressed as COR <3> , PAR' <7> Can also be expressed as BIT_B <0> , PAR' <4> Can also be expressed as BIT_B <1> , PAR' <5> Can also be expressed as BIT_T <2> , PAR' <6> Can also be expressed as BIT_T <3> .

[0256] In addition, the first decoding submodule 341 is also connected to a power supply voltage and a ground voltage. In the embodiment of the present disclosure, VDD, VDD1 and VDD2 all represent power supply voltages, which are used to provide a high-level signal (logic "1"); VSS represents a ground voltage, which is used to provide a low-level signal (logic "0"). Fig.14 As shown, VSS can also be expressed as BIT_B <2> , VDD1 can also be expressed as BIT_T <0> , VDD2 can also be expressed as BIT_T <1> .

[0257] It should be noted that BIT_B <x>and BIT_T <x>(X represents any one of the 8-bit data of the target error correction sequence) are mutually inverted signals; BIT_T <x>Represents the input is 1, BIT_B <x>Represents the input signal is 0. Fig.14 This is just an example. The data group to which the erroneous data to be decoded belongs is a data group in which the upper 4 bits of the binary expression of the sub-check column corresponding to the data in the data group are (0110), and no limitation is made to this.

[0258] based on Fig.14 The positioning module 34 shown in FIG. 1 has a corresponding first decoding submodule 341 having a structure as shown in FIG. Fig.15 As shown, through Fig.15 The circuit shown in FIG. 1 can obtain the first error address signal CODE1B. And, based on Fig.14 The positioning module 34 shown in FIG. 1 has a corresponding second decoding submodule 342 as shown in FIG. Fig.16 As shown, through Fig.16 The circuit shown can obtain the second error address signal CODE0B<7:0>.

[0259] In another embodiment of the present disclosure, see Fig.17 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Fig.17 As shown, the memory 40 includes the check and error correction circuit 30 described in any one of the aforementioned embodiments.

[0260] In some embodiments, the memory 40 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., which are not specifically limited here.

[0261] In the disclosed embodiment, for the memory 40, a first parity value calculated based on the written data set and a second parity value calculated based on the read data set is used to determine whether to output the initial error correction sequence as the target error correction sequence and determine the location of the erroneous data, or to mask the initial error correction sequence. Thus, when there are multiple erroneous data in the data set, correction is performed when an odd number of erroneous data occurs, thereby controlling the spread of the miscorrection, and no correction is performed when an even number of erroneous data occurs. In this way, the memory performance can be improved.

[0262] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0263] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0264] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0265] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0266] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0267] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0268] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.< / x> < / x> < / x> < / x>

Claims

1. A verification and error correction method, characterized in that: The method comprises: Calculating the written data set, outputting a first check sequence and a first parity value; and calculating the read data set, outputting a second check sequence and a second parity value; wherein the first parity value represents that the value of an odd number or an even number of data in the written data set is a first preset value; and the second parity value represents that the value of an odd number or an even number of data in the read data set is the first preset value; Performing a one-to-one XOR comparison on the first check sequence and the second check sequence, and outputting an initial error correction sequence; If the first parity value and the second parity value are different, outputting the initial error correction sequence as a target error correction sequence; if the first parity value and the second parity value are the same, shielding the initial error correction sequence; The target error correction sequence is decoded based on a preset check matrix to determine the location of the erroneous data.

2. The error checking and correction method according to claim 1, characterized in that: The preset check matrix includes a plurality of sub-check columns, and each of the sub-check columns corresponds to a bit of data in the data set; The decoding process of the target error correction sequence based on a preset check matrix to determine the location of the erroneous data includes: The sub-check column that is the same as the target error correction sequence is determined in the preset check matrix, and data corresponding to the determined sub-check column is determined as the error data.

3. The error checking and correction method according to claim 2, characterized in that: The data set includes a low-order data portion and a high-order data portion; The binary expression of the sub-check column corresponding to each data in the low-order data portion has an odd number of the first preset values; The binary expression of the sub-check column corresponding to each data in the high-order data portion has an even number of the first preset values.

4. The error checking and correction method according to claim 1, characterized in that: The initial error correction sequence and the target error correction sequence both include N-bit data; If the first parity value and the second parity value are different, outputting the initial error correction sequence as a target error correction sequence; If the first parity value and the second parity value are the same, shielding the initial error correction sequence comprises: Performing an XOR comparison on the first parity value and the second parity value to generate a parity check value; Performing a logical operation on the parity check value and the i-th bit data of the initial error correction sequence to generate the i-th bit data of the target error correction sequence; Wherein, N is an integer greater than 0, and i is an integer greater than 0 and less than or equal to N.

5. The error checking and correction method according to claim 3, characterized in that: In the case where the data set includes 128-bit data, the low-order data portion includes the 0th data group, the 1st data group, the 2nd data group and the 3rd data group, and the high-order data portion includes the 4th data group, the 5th data group, the 6th data group and the 7th data group; each of the data groups includes 16-bit data; For the 0th data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 104, 97, 98, 107, 100, 109, 110, 103, 112, 121, 122, 115, 124, 117, 118, 127; For the first data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 168, 161, 162, 171, 164, 173, 174, 167, 176, 185, 186, 179, 188, 181, 182, 191; For the second data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 200, 193, 194, 203, 196, 205, 206, 199, 208, 217, 218, 211, 220, 213, 214, 223; For the third data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 248, 241, 242, 251, 244, 253, 254, 247, 224, 233, 234, 227, 236, 229, 230, 239; For the fourth data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 40, 33, 34, 43, 36, 45, 46, 39, 48, 57, 58, 51, 60, 53, 54, 63; For the fifth data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 72, 65, 66, 75, 68, 77, 78, 71, 80, 89, 90, 83, 92, 85, 86, 95; For the sixth data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 184, 177, 178, 187, 180, 189, 190, 183, 160, 169, 170, 163, 172, 165, 166, 175; For the 7th data group, the decimal expressions of the sub-check columns corresponding to the 16-bit data contained therein are: 216, 209, 210, 219, 212, 221, 222, 215, 192, 201, 202, 195, 204, 197, 198, 207 respectively.

6. The error checking and correction method according to claim 5, characterized in that: The first check sequence includes the 0th check value to the 7th check value, and the step of calculating the written data set and outputting the first check sequence and the first parity value includes: For each of the data groups, performing an XOR operation on the 0th, 3rd, 5th, and 6th bit data to generate a first intermediate value_0, performing an XOR operation on the 9th, 10th, 12th, and 15th bit data to generate a first intermediate value_1; performing an XOR operation on the first intermediate value_0 and the first intermediate value_1 to generate a first intermediate value_2; Performing an XOR operation on the first intermediate value_2 of the 0th data group and the first intermediate value_2 of the 1st data group to generate a first intermediate value_4A; performing an XOR operation on the first intermediate value_2 of the 2nd data group and the first intermediate value_2 of the 3rd data group to generate a first intermediate value_4B; performing an XOR operation on the first intermediate value_2 of the 4th data group and the first intermediate value_2 of the 5th data group to generate a first intermediate value_4C; performing an XOR operation on the first intermediate value_2 of the 6th data group and the first intermediate value_2 of the 7th data group to generate a first intermediate value_4D; Calculate the first intermediate value_4A, the first intermediate value_4B, the first intermediate value_4C and the first intermediate value_4D to generate a third check value; as well as, For each of the data groups, performing an XOR operation on the 1st, 3rd, 5th and 7th bits of data to generate a second intermediate value_0, performing an XOR operation on the 9th, 11th, 13th and 15th bits of data to generate a second intermediate value_1; performing an XOR operation on the second intermediate value_0 and the second intermediate value_1 to generate a second intermediate value_2; Performing an XOR operation on the second intermediate value_2 of the 0th data group and the second intermediate value_2 of the 1st data group to generate a second intermediate value_4A; performing an XOR operation on the second intermediate value_2 of the 2nd data group and the second intermediate value_2 of the 3rd data group to generate a second intermediate value_4B; performing an XOR operation on the second intermediate value_2 of the 4th data group and the second intermediate value_2 of the 5th data group to generate a second intermediate value_4C; performing an XOR operation on the second intermediate value_2 of the 6th data group and the second intermediate value_2 of the 7th data group to generate a second intermediate value_4D; Perform an XOR operation on the second intermediate value_4A, the second intermediate value_4B, the second intermediate value_4C and the second intermediate value_4D to generate a 0th check value; as well as, For each of the data groups, performing an XOR operation on the 2nd, 3rd, 6th and 7th bit data to generate a third intermediate value_0, performing an XOR operation on the 10th, 11th, 14th and 15th bit data to generate a third intermediate value_1; performing an XOR operation on the third intermediate value_0 and the third intermediate value_1 to generate a third intermediate value_2; Performing an XOR operation on the third intermediate value_2 of the 0th data group and the third intermediate value_2 of the 1st data group to generate a third intermediate value_4A; performing an XOR operation on the third intermediate value_2 of the 2nd data group and the third intermediate value_2 of the 3rd data group to generate a third intermediate value_4B; performing an XOR operation on the third intermediate value_2 of the 4th data group and the third intermediate value_2 of the 5th data group to generate a third intermediate value_4C; performing an XOR operation on the third intermediate value_2 of the 6th data group and the third intermediate value_2 of the 7th data group to generate a third intermediate value_4D; Performing an XOR operation on the third intermediate value_4A, the third intermediate value_4B, the third intermediate value_4C and the third intermediate value_4D to generate a first check value; as well as, For each of the data groups, performing an XOR operation on the 4th, 5th, 6th and 7th bits of data to generate a fourth intermediate value_0, performing an XOR operation on the 12th, 13th, 14th and 15th bits of data to generate a fourth intermediate value_1; performing an XOR operation on the fourth intermediate value_0 and the fourth intermediate value_1 to generate a fourth intermediate value_2; Performing an XOR operation on the fourth intermediate value_2 of the 0th data group and the fourth intermediate value_2 of the 1st data group to generate a fourth intermediate value_4A; performing an XOR operation on the fourth intermediate value_2 of the 2nd data group and the fourth intermediate value_2 of the 3rd data group to generate a fourth intermediate value_4B; performing an XOR operation on the fourth intermediate value_2 of the 4th data group and the fourth intermediate value_2 of the 5th data group to generate a fourth intermediate value_4C; performing an XOR operation on the fourth intermediate value_2 of the 6th data group and the fourth intermediate value_2 of the 7th data group to generate a fourth intermediate value_4D; An XOR operation is performed on the fourth intermediate value_4A, the fourth intermediate value_4B, the fourth intermediate value_4C and the fourth intermediate value_4D to generate a second check value.

7. The error checking and correction method according to claim 6, characterized in that: The step of calculating the written data set and outputting a first check sequence and a first parity value further includes: For each of the data groups, performing an XOR operation on the 0th, 1st, 2nd and 3rd bit data to generate a fifth intermediate value_0, and performing an XOR operation on the 8th, 9th, 10th and 11th bit data to generate a fifth intermediate value_1; Performing an XOR operation on the fourth intermediate value_0 and the fifth intermediate value_0 to generate a sixth intermediate value_0; performing an XOR operation on the fourth intermediate value_1 and the fifth intermediate value_1 to generate a sixth intermediate value_1; Performing an XOR operation on the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_1 of the 1st data group, the sixth intermediate value_1 of the 2nd data group, the sixth intermediate value_0 of the 3rd data group, the sixth intermediate value_1 of the 4th data group, the sixth intermediate value_1 of the 5th data group, the sixth intermediate value_0 of the 6th data group, and the sixth intermediate value_0 of the 7th data group to generate a fourth check value; Perform an XOR operation on the sixth intermediate value_0 of the 0th data group, the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_0 of the 1st data group, the sixth intermediate value_1 of the 1st data group, the sixth intermediate value_0 of the 3rd data group, the sixth intermediate value_1 of the 3rd data group, the sixth intermediate value_0 of the 4th data group, the sixth intermediate value_1 of the 4th data group, the sixth intermediate value_0 of the 6th data group, and the sixth intermediate value_1 of the 6th data group to generate a fifth check value; Perform an XOR operation on the sixth intermediate value_0 of the second data group, the sixth intermediate value_1 of the second data group, the sixth intermediate value_0 of the third data group, the sixth intermediate value_1 of the third data group, the sixth intermediate value_0 of the 0th data group, the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_0 of the 5th data group, the sixth intermediate value_1 of the 5th data group, the sixth intermediate value_0 of the 7th data group, and the sixth intermediate value_1 of the 7th data group to generate a sixth check value; The sixth intermediate value_0 of the second data group, the sixth intermediate value_1 of the second data group, the sixth intermediate value_0 of the third data group, the sixth intermediate value_1 of the third data group, the sixth intermediate value_0 of the first data group, the sixth intermediate value_1 of the first data group, the sixth intermediate value_0 of the sixth data group, the sixth intermediate value_1 of the sixth data group, the sixth intermediate value_0 of the sixth data group, the sixth intermediate value_1 of the sixth data group, the sixth intermediate value_0 of the seventh data group and the sixth intermediate value_1 of the seventh data group are XOR-ed to generate a seventh check value.

8. The error checking and correction method according to claim 7, characterized in that: The step of calculating the written data set and outputting a first check sequence and a first parity value further includes: An exclusive OR operation is performed on the sixth intermediate value_0 of the 0th data group, the sixth intermediate value_1 of the 0th data group, the sixth intermediate value_0 of the 1st data group, the sixth intermediate value_1 of the 1st data group, the sixth intermediate value_0 of the 2nd data group, the sixth intermediate value_1 of the 2nd data group, the sixth intermediate value_0 of the 3rd data group, the sixth intermediate value_1 of the 3rd data group, the sixth intermediate value_0 of the 4th data group, the sixth intermediate value_1 of the 4th data group, the sixth intermediate value_0 of the 5th data group, the sixth intermediate value_1 of the 5th data group, the sixth intermediate value_0 of the 6th data group, the sixth intermediate value_1 of the 6th data group, the sixth intermediate value_0 of the 7th data group, and the sixth intermediate value_1 of the 7th data group to generate the first parity value.

9. A calibration and error correction circuit, characterized in that: The check and error correction circuit comprises: A check module is configured to calculate the written data set and output a first check sequence and a first parity value; and to calculate the read data set and output a second check sequence and a second parity value; wherein the first parity value represents that the value of the odd or even number of data in the written data set is a first preset value; and the second parity value represents that the value of the odd or even number of data in the read data set is the first preset value; a calculation module, connected to the verification module, configured to perform a one-to-one XOR comparison on the first verification sequence and the second verification sequence, and output an initial error correction sequence; a gating module connected to the calculation module and configured to output the initial error correction sequence as a target error correction sequence if the first parity value and the second parity value are different; and to shield the initial error correction sequence if the first parity value and the second parity value are the same; The positioning module is configured to decode the target error correction sequence and output a target error address; wherein the target error address indicates the location of the error data.

10. The check and error correction circuit according to claim 9, characterized in that: The initial error correction sequence and the target error correction sequence both include N bits of data; the gating module includes a comparison module and N logic units; The comparison module is configured to perform an XOR comparison on the first parity value and the second parity value to generate a parity check value; The i-th logic unit is configured to perform a logic operation on the parity check value and the i-th bit data of the initial error correction sequence to generate the i-th bit data of the target error correction sequence; Wherein, N is an integer greater than 0, and i is an integer greater than 0 and less than or equal to N.

11. The error correction circuit according to claim 10, characterized in that: The logic unit includes a first trigger, a first NOT gate, a second trigger, a second NOT gate and a first AND gate; wherein: The first clock terminal of the first trigger is used to receive a first clock signal, the input terminal of the first trigger is used to receive the parity check value, the inverting output terminal of the first trigger is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is used to output the parity sampling check value; The first clock terminal of the second flip-flop is used to receive the first clock signal, the input terminal of the second flip-flop is used to receive the i-th bit data of the initial error correction sequence, the inverting output terminal of the second flip-flop is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is used to output the i-th bit data of the initial sampling error correction sequence; The first input end of the first AND gate is used to receive the parity sampling check value, the second input end of the first AND gate is used to receive the i-th bit data of the initial sampling error correction sequence, and the output end of the first AND gate is used to output the i-th bit data of the target error correction sequence.

12. The check and error correction circuit according to claim 9, characterized in that: The decoding logic of the positioning module is determined based on a preset check matrix, which includes multiple sub-check columns, and each of the sub-check columns has a corresponding relationship with a bit of data in the data set, and the error data refers to the data corresponding to the sub-check column that is the same as the target error correction sequence.

13. The error correction circuit according to claim 12, characterized in that: The data set includes a low-order data portion and a high-order data portion; the low-order data portion or the high-order data portion includes multiple data groups, and each of the data groups includes multi-bit data; the positioning module includes a first decoding submodule, a second decoding submodule and a logic processing module, wherein: The first decoding submodule is configured to receive and decode a portion of the data of the target error correction sequence, and output a first error address signal, wherein the first error address signal indicates a data group number to which the error data belongs; The second decoding submodule is configured to receive and decode the remaining data of the target error correction sequence, and output a second error address signal, wherein the second error address signal indicates the position number of the error data in the data group to which it belongs; The logic processing module is configured to receive and perform a logic operation on the first error address signal and the second error address signal, and output the target error address; Among them, the binary expression form of the sub-check column corresponding to each data in the low-order data part has an odd number of the first preset values; the binary expression form of the sub-check column corresponding to each data in the high-order data part has an even number of the first preset values.

14. The check and error correction circuit according to claim 13, characterized in that: The second decoding submodule is configured to receive the 0th to 3rd bit data of the target error correction sequence and output the second error address signal; The first decoding submodule is configured to receive the 4th to 7th bits of the target error correction sequence and output the first error address signal; The logic processing module is configured to receive and perform an OR operation on the first error address signal and the second error address signal, and output the target error address.

15. A memory, characterized in that: The memory comprises the parity error correction circuit as claimed in any one of claims 9 to 14.

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