SOI wafer grinding and polishing method and SOI wafer

Abstract

The invention provides an SOI wafer grinding and polishing method and an SOI wafer, and the SOI wafer grinding and polishing method comprises the steps: providing an SOI wafer which comprises a substrate silicon layer, a buried oxide layer and a top silicon layer which are sequentially stacked from bottom to top; performing a grinding process on the top silicon layer, so that after grinding, the top silicon layer is concave, the thickness range value of the top silicon layer is X [mu] m, and the thickness of an edge area of the top silicon layer above a carrier is Z [mu] m; and performing a double-sided polishing process on the top silicon layer located above the carrier, and when the double-sided polishing process is performed, controlling the removal rate of the central region of the top silicon layer to be a [mu] m / min, the thickness range value of the top silicon layer removed per minute to be Y [mu] m, and the total removal time to be t min, wherein X, Y, Z, a and t meet the following conditions: Z < = at + X, Z < = at + Yt, and Yt-X < = 0 and < = 0.2. According to the SOI wafer obtained by adopting the SOI wafer grinding and polishing method provided by the invention, the thickness uniformity of the top silicon layer is effectively controlled.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a SOI wafer grinding and polishing method and an SOI wafer. Background Art

[0002] Silicon on Insulator (SOI) technology has become one of the mainstream products in most electronic materials fields. SOI is an integrated circuit manufacturing technology that achieves insulation between the silicon layer and the substrate by growing a thin silicon layer on an insulating substrate. SOI technology can improve the performance and reliability of integrated circuits, reduce power consumption and noise, and achieve a smaller device size. With the rapid development of new energy vehicles, the integration of automotive-grade SOI material on-board chips has gradually increased. Therefore, the market demand for high-uniformity SOI is getting higher and higher. How to further improve the uniformity of SOI materials has become an important trend in current development.

[0003] Chemical mechanical polishing is one of the main polishing processes in the SOI wafer manufacturing process. It can not only further improve the uniformity of SOI, but also repair the mechanical damage to the wafer surface caused by DSP to obtain a wafer with high flatness and low roughness. Chemical mechanical polishing (CMP) is a global flattening process. Its working principle combines chemical corrosion and mechanical grinding. The chemicals in the polishing liquid first react chemically with the silicon on the surface of the SOI wafer to passivate it. Then the polishing head applies pressure, and the wafer and the polishing pad move relative to each other. The abrasive particles distributed on the polishing pad remove the passivated silicon.

[0004] The uneven thickness of the top silicon layer of the SOI wafer may lead to unstable device performance, inconsistent current density of the local electron channel, uneven thermal effects and even line width changes. Since the top silicon layer of the SOI wafer is very thin, usually only a few microns or even thinner, the target thickness of the SOI wafer is generally obtained through grinding and polishing processes. The grinding and polishing process needs to consider the thinness and surface flatness of the silicon layer, and also needs to avoid damage to the insulating substrate to ensure the performance and reliability of the device.

[0005] However, after grinding and polishing the top silicon layer of the SOI wafer, there is still a problem of uneven thickness that is difficult to control. Summary of the invention

[0006] The object of the present invention is to provide a SOI wafer grinding and polishing method and an SOI wafer to solve one or more problems in the prior art.

[0007] In order to solve the above problems, the present invention provides a method for grinding and polishing a SOI wafer, which is characterized by comprising:

[0008] Providing an SOI wafer, wherein the SOI wafer comprises a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top;

[0009] Performing a grinding process on the top silicon layer so that after grinding, the top silicon layer is concave, the thickness range of the top silicon layer is X μm, and the thickness of the edge region of the top silicon layer above the carrier is Z μm; and,

[0010] Performing a double-sided polishing process on the top silicon layer located on the carrier, when performing the double-sided polishing process, controlling the removal rate of the central area of ​​the top silicon layer to be a μm / min, the thickness range of the top silicon layer removed per minute to be Y μm, and the total removal time to be t min;

[0011] Among them, X, Y, Z, a, and t satisfy: Z≤at+X, Z≤at+Yt, 0≤Yt-X≤0.2.

[0012] Optionally, in the SOI wafer grinding and polishing method, the thickness of the carrier is 10 μm to 12 μm greater than the thickness of the substrate silicon layer.

[0013] Optionally, in the SOI wafer grinding and polishing method, the thickness of the substrate silicon layer is 773 μm to 775 μm, and the thickness of the carrier is 783 μm to 787 μm.

[0014] Optionally, in the SOI wafer grinding and polishing method, when performing the double-sided polishing process, the pressure applied by the polishing disk to the edge region of the substrate silicon layer is greater than the pressure applied to the center region of the substrate silicon layer.

[0015] Optionally, in the SOI wafer grinding and polishing method, when polishing the portion of the top silicon layer higher than the upper surface of the carrier, the removal rate of the central area of ​​the top silicon layer is controlled to be 0.5 μm / min to 1 μm / min.

[0016] Optionally, in the SOI wafer grinding and polishing method, the method further comprises:

[0017] During the polishing process, a laser thickness meter is used to monitor the thickness of the top silicon layer, and polishing parameters are adjusted according to the monitoring results so that the removal rate of the central area of ​​the top silicon layer is 0.5 μm / min to 1 μm / min.

[0018] Optionally, in the SOI wafer grinding and polishing method, the thickness range of the substrate silicon layer is less than 0.5 μm.

[0019] Optionally, in the SOI wafer grinding and polishing method, the carrier is a planetary wheel.

[0020] The present invention also provides an SOI wafer, wherein the SOI wafer is processed by the method described in any one of the preceding items.

[0021] Optionally, in the SOI wafer, the thickness of the central area of ​​the top silicon layer of the processed SOI wafer is less than that of the edge area, and the thickness range is less than 0.2 μm.

[0022] In summary, the SOI wafer grinding and polishing method provided by the present invention includes: providing an SOI wafer, the SOI wafer includes a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top; performing a grinding process on the top silicon layer, so that after grinding, the top silicon layer is concave, the thickness range of the top silicon layer is Xμm, and the thickness of the edge area of ​​the top silicon layer located above the carrier is Zμm; and performing a double-sided polishing process on the top silicon layer located above the carrier, when performing the double-sided polishing process, the removal rate of the central area of ​​the top silicon layer is controlled to be aμm / min, the thickness range of the top silicon layer removed per minute is Yμm, and the total removal time is t min; wherein X, Y, Z, a, t satisfy: Z≤at+X, Z≤at+Yt, 0≤Yt-X≤0.2. The SOI wafer obtained by the SOI wafer grinding and polishing method provided by the present invention has the top silicon layer thickness uniformity effectively controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A flow chart of a method for thinning the top silicon layer of a SOI wafer provided in an embodiment of the present invention;

[0024] Figure 2 Schematic diagram of the structure corresponding to step S1 in an embodiment of the present invention;

[0025] Figure 3 Schematic diagram of the structure corresponding to step S2 in an embodiment of the present invention;

[0026] Figure 4 and Figure 5 Schematic diagram of the structure corresponding to step S3 in an embodiment of the present invention;

[0027] Figure 6 A schematic diagram of the positions of the central area and the edge area in an embodiment of the present invention;

[0028] The descriptions of the reference numerals are as follows:

[0029] 10-substrate silicon layer; 20-buried oxide layer; 30-top silicon layer; 40-carrier; 50-polishing plate;

[0030] 100-central area; 200-peripheral area. DETAILED DESCRIPTION

[0031] The following is a further detailed description of the SOI wafer grinding and polishing method and SOI wafer proposed in the present invention in conjunction with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0032] See also Figure 1 The present invention provides a wafer grinding and polishing method, comprising the following steps:

[0033] S1, providing an SOI wafer, wherein the SOI wafer comprises a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top;

[0034] S2, performing a grinding process on the top silicon layer, so that after grinding, the top silicon layer is concave, the thickness range of the top silicon layer is X μm, and the thickness of the edge area of ​​the top silicon layer above the carrier is Z μm; and,

[0035] S3, performing a double-sided polishing process on the top silicon layer located on the carrier, when performing the double-sided polishing process, controlling the removal rate of the central area of ​​the top silicon layer to be a μm / min, the thickness range of the top silicon layer removed per minute to be Y μm, and the total removal time to be t min;

[0036] Among them, X, Y, Z, a, and t satisfy: Z≤at+X, Z≤at+Yt, 0≤Yt-X≤0.2.

[0037] The wafer grinding and polishing method provided in an embodiment of the present invention first controls the thickness extreme value of the top silicon layer after grinding and the thickness of the edge area of ​​the top silicon layer located above the carrier after grinding when performing a grinding process on the top silicon layer, and then controls the removal rate of the central area of ​​the top silicon layer, the thickness extreme value of the top silicon layer removed per minute, and the total removal time when performing a double-sided polishing process, so that each parameter satisfies the set relationship. In this way, the thickness uniformity of the top silicon layer is effectively controlled, and finally the thickness of the central area of ​​the top silicon layer is less than the thickness of the edge area, and the thickness extreme value of the top silicon layer is less than 0.2μm.

[0038] The following combination Figure 2 to Figure 6 The wafer grinding and polishing method provided by the embodiment of the present invention is further described in detail.

[0039] First, execute step S1, see Figure 1 , providing an SOI wafer, the SOI wafer comprising a substrate silicon layer 10, a buried oxide layer 20 and a top silicon layer 30 stacked in sequence from bottom to top. The substrate silicon layer 10 and the top silicon layer 30 are isolated and bonded together by the buried oxide layer 20.

[0040] The buried oxide layer 20 can be formed by performing a thermal oxidation process and / or a plasma enhanced chemical vapor deposition (PECVD) process on the surface of the substrate silicon layer 10 and / or the top silicon layer 30. In this embodiment, preferably, a highly dense silicon dioxide interface layer is first formed by a thermal dry oxygen oxidation process, and then a relatively loose silicon dioxide layer is prepared by a wet oxygen oxidation process.

[0041] The diameter of the substrate silicon layer 10 and the top silicon layer 30 may be 200 mm or 300 mm, and the thickness of the substrate silicon layer 10 may be 773 μm to 775 μm, and the thickness range is less than 0.5 μm, but the present application is not limited thereto. It is understandable that the thickness of the silicon layer may be different at different positions, and the difference between the maximum thickness and the minimum thickness is the thickness range.

[0042] In this embodiment, after the substrate silicon layer 10 and the top silicon layer 30 are bonded together, the bonding wafer may be subjected to a reinforcement heat treatment, the reinforcement temperature is 900-1250°C, the time is 0.5-3h, and the atmosphere is an oxygen- or hydrogen-containing inert gas (Ar, N2, He, etc.); and the bonding wafer may be subjected to an edge chamfering treatment and an etching treatment, the edge chamfering treatment is used to remove part of the unbonded area of ​​the top silicon layer 30, and the edge etching treatment is used to eliminate edge damage. The SOI wafer as described in step S1 is obtained by the reinforcement heat treatment, the edge chamfering treatment, and the edge etching treatment.

[0043] Next, execute step S2, see Figure 3 , a grinding process is performed on the top silicon layer so that after grinding, the top silicon layer 30 is concave, the thickness range of the top silicon layer is Xμm, and the thickness of the edge area of ​​the top silicon layer 30 located above the carrier is Zμm.

[0044] The grinding process can be specifically completed using a double-axis grinder, but the present application is not limited thereto.

[0045] See also Figure 4 The carrier 40 is the carrier 40 used in the double-sided polishing process on the top silicon layer 30 in step S3. The carrier 40 with a suitable thickness can be selected according to the expected value of Z; or, when the thickness of the carrier 40 is constant, the thickness of the portion of the carrier 40 located above the substrate silicon layer 10 can be calculated, and the grinding process can be controlled according to the calculated value so that the thickness Z of the top silicon layer 30 located above the carrier 40 after grinding is the expected value.

[0046] Preferably, the thickness of the carrier 40 is 10 μm to 12 μm greater than the thickness of the substrate silicon layer 10, so that the support force of the carrier 40 for the SOI wafer can be improved, so that when the SOI wafer is polished, the removal rate of the edge area of ​​the substrate silicon layer 10 can be increased. Since the thickness of the substrate silicon layer 10 is 773 μm to 775 μm, the thickness of the carrier 40 can be 783 μm to 787 μm, for example, 785 μm.

[0047] Next, execute step S3, see Figure 4 and Figure 5 , a double-sided polishing process is performed on the top silicon layer 30 located above the carrier 40. When performing the double-sided polishing process, the removal rate of the central area of ​​the top silicon layer 30 is controlled to be aμm / min, the thickness range of the top silicon layer 30 removed per minute is Yμm, and the total removal time is t min.

[0048] When performing the double-sided polishing process, since the top silicon layer 30 is concave, the pressure applied by the polishing disk 50 to the edge region of the top silicon layer 30 is greater than the pressure applied to the central region of the top silicon layer 30, so that the removal rate of the edge region of the top silicon layer 30 is greater than the removal rate of the central region of the top silicon layer 30. Optionally, an alkaline solution is used for polishing, and the removal rate of the central region of the top silicon layer 30 is controlled to be 0.5 μm / min to 1 μm / min.

[0049] After the double-sided polishing process is performed on the top silicon layer 30 located above the carrier 40, the edge area removal amount is R edge =(a+Y)t, the amount of removal in the central area is R center=at; In order to ensure that the polished wafer is completely removed from the carrier, the edge area removal amount must meet R edge ≥Z, the amount of removal in the central area must meet R center ≥ZX, that is, it needs to satisfy: Z≤at+X, Z≤at+Yt.

[0050] In order to ensure that the thickness uniformity of the top silicon layer after polishing is controllable, it is necessary to satisfy the maximum thickness difference between the edge area and the center area of ​​the remaining top silicon layer ≤0.2μm, and the thickness of the center area of ​​the remaining top silicon layer is smaller than that of the edge area, that is, it is necessary to satisfy: 0≤{[(ZX)-at]-[Z-(a+Y)t]}≤0.2, that is, it is necessary to satisfy: 0≤Yt-X≤0.2.

[0051] Therefore, since the above parameters satisfy the following relationship, the thickness of the top silicon layer 30 after polishing can be controlled:

[0052] ①Z≤at+X;

[0053] ②Z≤at+Yt;

[0054] ③0≤Yt-X≤0.2;

[0055] Optionally, the carrier 40 may be a planetary wheel, and a plurality of workpiece holes are provided on the planetary wheel body. When double-sided polishing is performed, the SOI wafer is placed in the workpiece holes of the planetary wheel, and the thickness of the planetary wheel affects the polishing removal amount of the SOI wafer.

[0056] Optionally, during the polishing process, a laser thickness meter is used to monitor the thickness of the top silicon layer 30, and polishing parameters are adjusted according to the monitoring results so that the removal rate of the central area of ​​the top silicon layer 30 is maintained at 0.5 μm / min to 1 μm / min.

[0057] Optionally, after polishing is completed, a step of cleaning the SOI wafer is also included to remove residual polishing liquid and silicon chips.

[0058] Although "middle" and "edge" are not restrictive, it should be understood that in the above description, the edge area is relative to the central area. The central area refers to the area passing through the center of the silicon wafer, and the edge area refers to the area on the surface of the silicon wafer other than the central area, and the edge area surrounds the central area. In practical applications, the size of the area occupied by the central area and the edge area can be defined artificially, but the relative position relationship between the two remains unchanged. As an example, Figure 6As shown in , when the radius R of the top silicon layer 30 is 150nm, the central area 100 may be a circular area with a radius of 10nm and an axis of the top silicon layer 30 as the center, and the edge area 200 may be a circumferential area 140nm to 147nm away from the axis of the top silicon layer 30.

[0059] An embodiment of the present invention also provides an SOI wafer, which is obtained using the method provided by the embodiment of the present invention. Therefore, the thickness of the central area of ​​the top silicon layer of the SOI wafer provided by the embodiment of the present invention is less than the thickness of the edge area, and the thickness range is less than 0.2μm.

[0060] The wafer grinding and polishing method provided by the embodiment of the present invention is further illustrated by means of several examples below.

[0061] In each example, the thickness of the substrate silicon layer 10 is 775 μm, the thickness of the top silicon layer 30 is 8 μm, the thickness of the carrier 40 is 785 μm, the top silicon layer 30 is concave after grinding, and the polishing removal amount Y is 8 μm.

[0062] Table 1

[0063]

[0064] In Example 1 and Example 4, the thickness range X of the top silicon layer 30 after grinding, the thickness Y of the portion of the top silicon layer 30 higher than the thickness of the carrier 40 after grinding, and the polishing removal amount Z satisfy: (0.2X-0.06) / Y≤Z≤0.2X / Y, so that in Example 1 and Example 4, after grinding and polishing, the thickness range of the top silicon layer 30 is less than 0.2μm.

[0065] In Example 2 and Example 3, the thickness range X of the top silicon layer 30 after grinding, the thickness Y of the portion of the top silicon layer 30 higher than the thickness of the carrier 40 after grinding, and the polishing removal amount Z do not satisfy: (0.2X-0.06) / Y≤Z≤0.2X / Y, so that in Example 2 and Example 3, after grinding and polishing, the thickness range of the top silicon layer 30 is greater than 0.2μm.

[0066] It can be seen from the above four examples that the thickness uniformity of the top silicon layer 30 can be effectively controlled by using the method provided by the embodiment of the present invention.

[0067] In summary, the SOI wafer grinding and polishing method provided by the embodiment of the present invention includes: providing an SOI wafer, the SOI wafer includes a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top; performing a grinding process on the top silicon layer, so that after grinding, the top silicon layer is concave, the thickness range of the top silicon layer is Xμm, and the thickness of the edge area of ​​the top silicon layer located above the carrier is Zμm; and performing a double-sided polishing process on the top silicon layer located above the carrier, when performing the double-sided polishing process, the removal rate of the central area of ​​the top silicon layer is controlled to be aμm / min, the thickness range of the top silicon layer removed per minute is Yμm, and the total removal time is t min; wherein X, Y, Z, a, t satisfy: Z≤at+X, Z≤at+Yt, 0≤Yt-X≤0.2. The SOI wafer obtained by the SOI wafer grinding and polishing method provided by the embodiment of the present invention has the top silicon layer thickness uniformity effectively controlled.

[0068] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for grinding and polishing a SOI wafer, characterized in that: include: Providing an SOI wafer, wherein the SOI wafer comprises a substrate silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top; Performing a grinding process on the top silicon layer, so that after grinding, the top silicon layer is concave, the thickness range of the top silicon layer is X μm, and the thickness of the edge area of ​​the top silicon layer above the carrier is Z μm; as well as, Performing a double-sided polishing process on the top silicon layer located on the carrier, when performing the double-sided polishing process, controlling the removal rate of the central area of ​​the top silicon layer to be a μm / min, the thickness range of the top silicon layer removed per minute to be Y μm, and the total removal time to be t min; Among them, X, Y, Z, a, and t satisfy: Z≤at+X, Z≤at+Yt, 0≤Yt-X≤0.

2.

2. The SOI wafer grinding and polishing method according to claim 1, characterized in that: The thickness of the carrier is 10 μm to 12 μm greater than the thickness of the substrate silicon layer.

3. The SOI wafer grinding and polishing method according to claim 2, characterized in that: The thickness of the substrate silicon layer is 773 μm to 775 μm, and the thickness of the carrier is 783 μm to 787 μm.

4. The SOI wafer grinding and polishing method according to claim 1, characterized in that: When performing the double-side polishing process, the pressure applied by the polishing disk to the edge region of the substrate silicon layer is greater than the pressure applied to the center region of the substrate silicon layer.

5. The SOI wafer grinding and polishing method according to claim 1, characterized in that: When polishing the portion of the top silicon layer that is higher than the upper surface of the carrier, the removal rate of the central area of ​​the top silicon layer is controlled to be 0.5 μm / min to 1 μm / min.

6. The SOI wafer grinding and polishing method according to claim 1, characterized in that: The method further comprises: During the polishing process, a laser thickness meter is used to monitor the thickness of the top silicon layer, and polishing parameters are adjusted according to the monitoring results so that the removal rate of the central area of ​​the top silicon layer is 0.5 μm / min to 1 μm / min.

7. The SOI wafer grinding and polishing method according to claim 1, characterized in that: The thickness range of the substrate silicon layer is less than 0.5 μm.

8. The SOI wafer grinding and polishing method according to claim 1, characterized in that: The vehicle is a planetary wheel.

9. A SOI wafer, characterized in that: The SOI wafer is obtained by processing using the method according to any one of claims 1 to 8.

10. The SOI wafer according to claim 9, characterized in that: In the SOI wafer obtained after processing, the thickness of the central area of ​​the top silicon layer is less than the thickness of the edge area, and the thickness range is less than 0.2 μm.

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