Through hole interconnection structure and preparation method thereof

Abstract

The invention provides a through hole interconnection structure and a preparation method thereof. The preparation method of the through hole interconnection structure comprises the following steps: forming a plurality of blind holes in a substrate; a plurality of conductive parts are prepared on the front face, each conductive part comprises a conductive column and a first signal line which are mutually connected, the blind holes are filled with the conductive columns, and the first signal lines are formed on the front face; etching the substrate for the first time by using a first etching agent, so that the substrate is thinned until a preset distance is formed between the back surface and the conductive column; second etching is carried out on the substrate by using a second etching agent, so that the substrate is thinned until the conductive columns protrude out of the back surface, the etching rate of the second etching agent on the substrate is smaller than that of the first etching agent on the substrate, and the second etching agent selectively etches the substrate in the substrate and the conductive columns; a plurality of second signal lines are prepared on the side where the back face is located, and the second signal lines are connected with the conductive columns. According to the invention, the preparation difficulty of the through hole interconnection structure can be reduced, and the reliability of the through hole interconnection structure can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip packaging, and in particular to a through-hole interconnect structure and a preparation method thereof. Background Art

[0002] Through Glass Via (TGV) interconnection technology has the advantages of excellent high-frequency electrical properties, low cost, simple process flow, and strong mechanical stability. Therefore, it is widely used in RF devices, Micro-Electro-Mechanical Systems (MEMS) packaging, optoelectronic system integration and other fields.

[0003] In the related art, there are deficiencies in the method for preparing the through-hole interconnection structure. Summary of the invention

[0004] The embodiments of the present application provide a through-hole interconnect structure and a method for preparing the same, aiming to reduce the difficulty of preparing the through-hole interconnect structure and improve the reliability of the through-hole interconnect structure.

[0005] An embodiment of the first aspect of the present application provides a method for preparing a through-hole interconnection structure, which comprises the following steps: forming a plurality of blind holes in a substrate, the substrate having a front side and a back side opposite to each other, each blind hole extending from the front side to the back side; preparing a plurality of conductive parts on the front side, each conductive part comprising a conductive column and a first signal line connected to each other, the conductive column filling the blind hole, and the first signal line formed on the front side; using a first etchant to perform a first etching on the substrate to thin the substrate until a preset spacing is provided between the back side and the conductive column; using a second etchant to perform a second etching on the substrate to thin the substrate until the conductive column protrudes from the back side, the etching rate of the second etchant on the substrate is lower than the etching rate of the first etchant on the substrate, and the second etchant selectively etches the substrate between the substrate and the conductive column; preparing a plurality of second signal lines on the side where the back side is located, each second signal line is connected to each conductive column.

[0006] According to any of the aforementioned embodiments of the first aspect of the present application, the preparation method satisfies at least one of the following conditions: the substrate is a glass substrate; the ratio of the etching rate of the first etchant on the substrate to the etching rate of the second etchant on the substrate is 5~20; based on the thinning thickness, the etching rate of the first etchant on the substrate is 1μm / min~10μm / min; based on the thinning thickness, the etching rate of the second etchant on the substrate is 0.1μm / min~1μm / min; the first etchant is an acidic etchant; and the second etchant is an alkaline etchant.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the preparation method satisfies at least one of the following conditions: the preset spacing is 0~10μm; the depth of the blind hole is 0~200μm; before the step of etching the substrate for the first time using the first etchant, the thickness of the substrate is not less than 500μm.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, the conductive column includes an inner wall seed layer covering the inner wall of the blind hole and a conductive core arranged on the inner wall seed layer; the first signal line includes a seed layer island arranged on the front side and a first routing line arranged on the seed layer island; wherein the inner wall seed layer and the seed layer island are an integrated structure, and the conductive core and the first routing line are an integrated structure.

[0009] According to any of the aforementioned implementations of the first aspect of the present application, the thickness of the first wiring is 0-5 μm.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the step of preparing multiple conductive parts on the front side includes: depositing a seed material on the front side to form an inner wall seed layer covering the inner wall of the blind hole and a seed layer covering the front side; preparing a patterned first pattern layer on the seed layer, the first pattern layer having multiple first holes to be deposited, each first hole to be deposited exposes each blind hole and exposes the seed layer to form a first deposition area; depositing a metal material in the first holes to be deposited to form a conductive core on the inner wall seed layer and a first routing on the first deposition area; stripping off the first pattern layer to expose the seed layer to form multiple areas to be etched; etching the areas to be etched to pattern the seed layer to form multiple seed layer islands.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, the preparation method satisfies at least one of the following conditions: each first deposition area is arranged around each blind hole; in the step of depositing the metal material in the first hole to be deposited, the deposition is performed by electroplating process; the thickness of the first routing line is 0~5μm.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the first trace on the substrate does not exceed the orthographic projection range of the integrated structure formed by the inner wall seed layer and the seed layer island on the substrate.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the first trace on the substrate coincides with the orthographic projection of the integrated structure formed by the inner wall seed layer and the seed layer island on the substrate.

[0014] According to any of the aforementioned embodiments of the first aspect of the present application, after the step of etching the substrate for a second time using a second etchant and before the step of preparing a plurality of second signal lines on the back side, the preparation method further includes: preparing a dielectric layer on the back side, the dielectric layer covering the back side and the conductive pillars; and thinning the dielectric layer to expose the conductive pillars.

[0015] According to any of the aforementioned embodiments of the first aspect of the present application, in the step of thinning the dielectric layer, the dielectric layer is ground and thinned.

[0016] According to any of the aforementioned embodiments of the first aspect of the present application, the dielectric layer is thinned until the conductive pillar is ground and thinned.

[0017] According to any of the aforementioned embodiments of the first aspect of the present application, the step of preparing a plurality of second signal lines on the back side includes: forming a patterned second pattern layer on the dielectric layer, the second pattern layer having a plurality of second holes to be deposited, each second hole to be deposited exposing each conductive column and exposing the dielectric layer to form a second deposition area; depositing metal material in the second holes to be deposited to form a plurality of second signal lines on the second deposition area.

[0018] According to any of the aforementioned embodiments of the first aspect of the present application, each second deposition area is arranged around each conductive column; or / and, after the step of depositing metal material in the second hole to be deposited, the step of preparing a plurality of second signal lines on the back side also includes: peeling off the second pattern layer.

[0019] According to any of the aforementioned embodiments of the first aspect of the present application, before the step of using the first etchant to perform a first etching on the substrate, the preparation method further includes: attaching a protective film, wherein the protective film covers the multiple conductive parts.

[0020] According to any of the aforementioned embodiments of the first aspect of the present application, after the step of etching the substrate for a second time using a second etchant and before the step of preparing a dielectric layer on the back side, the preparation method further includes: removing the protective film and temporarily bonding the front side to the carrier.

[0021] According to any of the aforementioned embodiments of the first aspect of the present application, after the step of depositing the metal material in the second hole to be deposited, the preparation method further includes: debonding the front side from the carrier.

[0022] The second aspect of the present application further provides a through-hole interconnect structure, which is prepared by the method for preparing a through-hole interconnect structure of any of the above-mentioned embodiments of the first aspect.

[0023] In the preparation method of the through-hole interconnection structure of the present application, by preparing multiple conductive parts on the front side of the substrate formed with multiple blind holes, a substrate with a larger thickness can be selected to improve the mechanical strength of the substrate, thereby reducing the risk of substrate fragmentation in the process; and compared with the through-hole double-sided deposition process, the blind hole deposition process can control the thickness of the metal layer formed on the front side within the thickness range directly used as the front wiring, so the front wiring and the filling of the blind hole can be made simultaneously, thereby reducing the process steps. At the same time, in the process of etching the substrate to thin the substrate to the conductive column protruding from the back side, the first etchant and the second etchant are used to etch the substrate step by step, and the step-by-step etching process not only has high process reliability, but also has little damage to the conductive column in the hole. Therefore, the preparation method of the through-hole interconnection structure prepared by combining the blind hole process and the step-by-step etching thinning process to expose the conductive column can not only reduce the difficulty of preparing the through-hole interconnection structure, but also improve the reliability of the through-hole interconnection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0025] Figure 1 is a flow chart of a method for preparing a through-hole interconnect structure provided by an embodiment of the first aspect of the present application; Figure 2 It is a flow chart of preparing multiple conductive parts on the front side provided by the embodiment of the first aspect of the present application; Figure 3 is a flow chart of a method for preparing a through-hole interconnect structure provided by an embodiment of the first aspect of the present application; Figure 4 is a flow chart of preparing a plurality of second signal lines on the back side provided by an embodiment of the first aspect of the present application; Figures 5 to 18 It is a structural schematic diagram of an intermediate product in the process of preparing a through-hole interconnection structure provided by an embodiment of the first aspect of the present application; Fig.19 It is a structural schematic diagram of a through-hole interconnect structure prepared by the method for preparing a through-hole interconnect structure provided in the embodiment of the first aspect of the present application.

[0026] Description of reference numerals: 1. Substrate; 11. Blind hole; 13. Front side; 15. Back side; 3. Conductive part; 31. Conductive pillar; 311. Inner wall seed layer; 313. Conductive core; 33. First signal line; 330. Seed layer; 33A. First deposition area; 33B. Area to be etched; 331. Seed layer island; 333. First routing line; 4. first pattern layer; 41. first hole to be deposited; 5. Second signal line; 6. dielectric layer; 6A. second deposition area; 7. second pattern layer; 71. second hole to be deposited; 8. Protective film; 9. Carrier board; 10. Peelable adhesive; D. Preset spacing. DETAILED DESCRIPTION

[0027] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0028] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0029] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0030] Through Glass Via (TGV) interconnection technology has the advantages of excellent high-frequency electrical properties, low cost, simple process flow, and strong mechanical stability. Therefore, it is widely used in RF devices, Micro-Electro-Mechanical Systems (MEMS) packaging, optoelectronic system integration and other fields.

[0031] In the related art, the preparation method of the through-hole interconnection structure can be divided into the following two process routes: 1. Blind hole technology: first make a blind hole on the glass substrate, then fill the blind hole and make a metal wiring layer on the front side, grind the back side of the glass substrate so that the metal wiring layer on the front side is exposed from the back side, and then make another metal wiring layer on the back side, so as to achieve the interconnection between the front and back sides. However, grinding will produce a large shear stress, which is easy to cause defects such as the breakage of the glass substrate; in order to reduce the amount of grinding, ultra-thin glass can be used, but the ultra-thin glass itself is not strong enough and is easy to break in the subsequent process, which is not conducive to large-area preparation.

[0032] 2. Through-hole technology: First, make through-holes on the glass substrate, fill the through-holes by double-sided electroplating, and make metal wiring layers on the front and back sides. However, filling through-holes is difficult, and the process and equipment requirements for double-sided electroplating of through-holes are high. In addition, after through-hole electroplating, the metal thickness on the front and back sides of the glass substrate is relatively thick, and the metal layers on the front and back sides need to be ground and removed.

[0033] In order to solve the above technical problems, this application is proposed. In order to better understand this application, Figures 1 to 19 The through hole interconnect structure and the preparation method thereof according to the embodiment of the present application are described in detail.

[0034] See also Figure 1 , Figure 1 It is a flow chart of the method for preparing a through-hole interconnection structure provided in the embodiment of the first aspect of the present application.

[0035] like Figure 1 As shown, an embodiment of the first aspect of the present application provides a method for preparing a through-hole interconnection structure, comprising the following steps: Step S01: Figure 5 As shown, a plurality of blind holes 11 are formed in a substrate 1 , and the substrate 1 has a front side 13 and a back side 15 that are opposite to each other.

[0036] Each blind hole 11 extends from the front surface 13 to the back surface 15 .

[0037] The front surface 13 and the back surface 15 are two surfaces at two opposite sides of the substrate 1 , that is, the front surface 13 and the back surface 15 are arranged at an interval.

[0038] Optionally, the front surface 13 and the back surface 15 are arranged in parallel or nearly parallel.

[0039] The front surface 13 and the back surface 15 are arranged nearly in parallel, which means that although the front surface 13 and the back surface 15 have an angle, the angle between the two is relatively small, and the embodiments of the present application do not make any specific limitation on this.

[0040] For example, when the front surface 13 and the back surface 15 are nearly parallel, the angle between the front surface 13 and the back surface 15 can be 0.1°, 0.2°, 0.2°, 0.3°, 0.4°, 0.5°, 0.6°, 0.7°, 0.8°, 0.9° or 1.0°, etc. Of course, the angle between the front surface 13 and the back surface 15 can also be any combination range of the above values.

[0041] Step S02: Fig.10 As shown, a plurality of conductive parts 3 are prepared on the front surface 13 , each conductive part 3 includes a conductive column 31 and a first signal line 33 connected to each other, the conductive column 31 fills the blind hole 11 , and the first signal line 33 is formed on the front surface 13 .

[0042] Optionally, a plurality of conductive parts 3 are arranged at intervals.

[0043] Step S03: Fig.12 As shown, the substrate 1 is etched for the first time using a first etchant to thin the substrate 1 until a preset distance D exists between the back surface 15 and the conductive pillar 31 .

[0044] The predetermined distance D prevents the conductive pillars 31 from being etched by the first etchant.

[0045] Optionally, the preset distance D is a minimum distance between the conductive pillar 31 and the back surface 15 .

[0046] Step S04: Fig.13 As shown, the substrate 1 is etched for the second time using a second etchant to thin the substrate 1 until the conductive pillars 31 protrude from the back surface 15 .

[0047] The etching rate of the second etchant on the substrate 1 is lower than the etching rate of the first etchant on the substrate 1. And among the substrate 1 and the conductive pillar 31, the second etchant selectively etches the substrate 1, that is, the conductive pillar 31 is not etched by the second etchant. Since the etching rate of the first etchant on the substrate 1 is higher than the etching rate of the second etchant on the substrate 1, the first etchant has a stronger etching performance. If the first etchant contacts the conductive pillar 31, it is easy to cause the first etchant to etch the conductive pillar 31, and the conductive pillar 31 is more easily etched relative to the substrate 1. Therefore, when the first etchant contacts the conductive pillar 31, a gap will appear between the conductive pillar 31 and the substrate 1, thereby causing reliability risks. Therefore, the first etchant only etches the substrate 1 until the substrate 1 is thinned to a preset spacing D between the back side 15 and the conductive pillar 31. By making the substrate 1 retain the thickness of the preset spacing D, the conductive pillar 31 can be prevented from being etched by the first etchant.

[0048] Step S05: Fig.18 As shown, a plurality of second signal lines 5 are prepared on the side where the back surface 15 is located, and each second signal line 5 is connected to each conductive column 31 .

[0049] Optionally, a plurality of second signal lines 5 are arranged at intervals.

[0050] In the preparation method of the through-hole interconnection structure of the present application, by preparing multiple conductive parts 3 on the front side 13 of the substrate 1 formed with multiple blind holes 11, a substrate with a larger thickness can be selected to improve the mechanical strength of the substrate, thereby reducing the risk of substrate fragmentation in the process; and compared with the through-hole double-sided deposition process, the blind hole 11 deposition process can control the thickness of the metal layer formed on the front side 13 within the thickness range directly used as the front wiring, so the front wiring and the filling of the blind hole 11 can be made simultaneously, thereby reducing the process steps. At the same time, in the process of etching the substrate 1 to thin the substrate 1 to the conductive column 31 protruding from the back side 15, the first etchant and the second etchant are used to etch the substrate 1 step by step, and the step-by-step etching process not only has high process reliability, but also has little damage to the conductive column 31 in the hole. Therefore, the preparation method of the through-hole interconnection structure prepared by combining the blind hole process and the step-by-step etching thinning process to expose the conductive column can not only reduce the difficulty of preparing the through-hole interconnection structure, but also improve the reliability of the through-hole interconnection structure.

[0051] In some embodiments, the substrate 1 is a glass substrate. The glass substrate has good heat resistance and corrosion resistance and is not easily deformed, which is beneficial to improving the stability and reliability of the through-hole interconnection structure.

[0052] In some embodiments, the blind hole 11 can be formed by sandblasting, ultrasonic drilling, wet etching, deep reactive ion etching, photosensitive etching, laser etching, laser induced deep etching and focused discharge pore forming, but the embodiments of the present application are not limited to the above forming processes.

[0053] In some embodiments, the ratio of the etching rate of the first etchant on the substrate 1 to the etching rate of the second etchant on the substrate 1 is 5 to 20. On the one hand, it is beneficial to control the preset distance D after the first etchant etches the substrate 1, and on the other hand, it can effectively reduce the etching time of the substrate 1.

[0054] Illustratively, the ratio of the etching rate of the first etchant on the substrate 1 to the etching rate of the second etchant on the substrate 1 can be 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 or 20. Of course, the ratio of the etching rate of the first etchant on the substrate 1 to the etching rate of the second etchant on the substrate 1 can also be any combination range of the above values.

[0055] In some embodiments, the etching rate of the first etchant on the substrate 1 is 1 μm / min to 10 μm / min in terms of thinning thickness.

[0056] Exemplarily, the etching rate of the first etchant on the substrate 1 can be 1 μm / min, 2 μm / min, 3 μm / min, 4 μm / min, 5 μm / min, 6 μm / min, 7 μm / min, 8 μm / min, 9 μm / min or 10 μm / min. Of course, the etching rate of the first etchant on the substrate 1 can also be any combination range of the above values.

[0057] In some embodiments, the etching rate of the second etchant on the substrate 1 is 0.1 μm / min to 1 μm / min in terms of thinning thickness.

[0058] Exemplarily, the etching rate of the second etchant on the substrate 1 can be 0.1 μm / min, 0.2 μm / min, 0.3 μm / min, 0.4 μm / min, 0.5 μm / min, 0.6 μm / min, 0.7 μm / min, 0.8 μm / min, 0.9 μm / min or 1 μm / min. Of course, the etching rate of the second etchant on the substrate 1 can also be any combination range of the above values.

[0059] In these embodiments, the thickness of the substrate 1 is the thickness of the substrate 1 in the direction from the front surface 13 to the back surface 15 .

[0060] In some embodiments, the first etchant is an acidic etchant.

[0061] Optionally, the acidic etchant includes hydrofluoric acid and a first solvent. The hydrofluoric acid reacts with SiO2, the main component of the glass substrate. Although the etching rate of the glass substrate by hydrofluoric acid is fast, the etching uniformity is poor, and the hydrofluoric acid can corrode the conductive column 31. Therefore, if the first etchant is directly used to etch the substrate 1 until the substrate 1 is thinned to the point where the conductive column 31 protrudes from the back 15, the first etchant will corrode the conductive column 31, resulting in pores at the connection interface between the conductive column 31 and the substrate 1, thereby causing reliability risks. Therefore, the first etchant only etches the substrate 1 until the substrate 1 is thinned to the point where there is a preset spacing D between the back 15 and the conductive column 31, and the conductive column 31 is prevented from being etched by keeping the thickness of the preset spacing D on the substrate 1.

[0062] Optionally, the acidic etchant further includes other acids. The other acids are used to increase the solubility of byproducts after the reaction of hydrofluoric acid and SiO2. When the concentration of hydrofluoric acid is the same, the addition of other acids is beneficial to increase the etching rate of the acidic etchant on the substrate 1; when the etching rate on the substrate 1 is the same, it is beneficial to reduce the concentration requirement of hydrofluoric acid.

[0063] Alternatively, other acids include but are not limited to sulfuric acid, hydrochloric acid, and the like.

[0064] Optionally, the first solvent is water.

[0065] Optionally, the components of the acidic etchant and the content of each component can be specifically designed according to the requirements of the etching rate of the first etchant on the substrate 1.

[0066] In some embodiments, the second etchant is an alkaline etchant. Although the alkaline etchant has a low etching rate on the substrate 1, it has good uniformity and is friendly to the conductive pillars 31, so it will not cause the conductive pillars 31 to be etched.

[0067] Optionally, the alkaline etchant includes a second solvent and an alkaline substance.

[0068] Optionally, the alkaline substance includes but is not limited to sodium hydroxide, potassium hydroxide and the like.

[0069] Optionally, the second solvent is water.

[0070] Optionally, the alkaline etchant components and the content of each component can be specifically designed according to the requirements of the etching rate of the second etchant on the substrate 1.

[0071] In some embodiments, the preset spacing D is 0-10 μm. On the one hand, the first etchant can be prevented from etching the conductive pillar 31, and on the other hand, since the etching rate of the first etchant on the substrate 1 is greater than the etching rate of the second etchant on the substrate 1, the etching thickness of the substrate 1 by the second etchant can be reduced, thereby reducing the etching time of the substrate 1.

[0072] Exemplarily, the preset distance D may be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm. Of course, the etching rate of the second etchant on the substrate 1 may also be any combination range of the above values.

[0073] In these embodiments, the preset spacing D is 10 μm. On the one hand, it can effectively avoid the substrate 1 being thinned to the point where the conductive pillar 31 protrudes from the back surface 15 after the first etching due to the molding error of the blind hole 11 , and on the other hand, it can ensure the etching time of the substrate 1 .

[0074] In some embodiments, the depth of the blind hole 11 is 0-200 μm. The depth of the blind hole 11 is designed according to the thickness of the glass substrate in the through-hole interconnection structure.

[0075] In these embodiments, the depth of the blind via 11 is greater than the thickness of the glass substrate in the through-hole interconnection structure.

[0076] Exemplarily, the depth of the blind hole 11 can be 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm or 200 μm. Of course, the depth of the blind hole 11 can also be any combination range of the above values.

[0077] In these embodiments, before step S03, the thickness of the substrate 1 is not less than 500 μm, that is, the thickness of the substrate 1 in step S01 and step S02 is not less than 500 μm. The strength of the substrate in the process of blind hole forming and preparing the conductive part can be improved, which is conducive to improving the yield and reliability of the prepared through-hole interconnection structure.

[0078] In some embodiments, Fig.10 As shown, the conductive column 31 prepared in step S02 includes an inner wall seed layer 311 covering the inner wall of the blind hole 11 and a conductive core 313 arranged on the inner wall seed layer 311; the first signal line 33 includes a seed layer island 331 arranged on the front side 13 and a first routing line 333 arranged on the seed layer island 331; wherein, the inner wall seed layer 311 and the seed layer island 331 are an integrated structure, and the conductive core 313 and the first routing line 333 are an integrated structure.

[0079] In these embodiments, the inner wall seed layer 311 and the seed layer island 331 are an integrated structure, which means that the whole formed by the inner wall seed layer 311 and the seed layer island 331 has good structural integrity, and there is no splicing transition area between the inner wall seed layer 311 and the seed layer island 331, so the inner wall seed layer 311 and the seed layer island 331 can be formed at one time through a deposition process, thereby reducing the preparation steps; the conductive core 313 and the first wiring 333 are an integrated structure, which means that the whole formed by the conductive core 313 and the first wiring 333 has good structural integrity, and there is no splicing transition area between the conductive core 313 and the first wiring 333, so the conductive core 313 and the first wiring 333 can be formed at one time through a deposition process, thereby reducing the preparation steps. Moreover, when the conductive core 313 and the first wiring 333 are formed at one time through a deposition process, the inner wall seed layer 311 and the seed layer island 331 are an integrated structure, which can also improve the good structural integrity of the whole formed by the conductive core 313 and the first wiring 333.

[0080] In these embodiments, the inner wall seed layer 311 is easily etched by the first etchant when in contact with the first etchant.

[0081] In some embodiments, the thickness of the first wiring 333 is 0-5 μm. The thickness of the first wiring 333 is the thickness of the first wiring 333 from the front surface 13 to the back surface 15 .

[0082] For example, the thickness of the first wiring 333 may be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm. Of course, the thickness of the first wiring 333 may also be any combination range of the above values.

[0083] Optionally, the material of the conductive core 313 and the material of the first wiring 333 are both metallic copper. The metallic copper has good conductivity, and the process of preparing the conductive core 313 and the first wiring 333 on the front surface 13 of the substrate 1 having a plurality of blind holes 11 is relatively mature, and the preparation difficulty is relatively low. Moreover, when depositing the surface copper, the thickness of the surface copper can be controlled within the range of 0 to 5 μm, so the deposited surface copper can be directly used as the first wiring 333, thereby avoiding grinding of the surface copper.

[0084] Please continue reading Figure 2 , Figure 2 This is a flow chart of preparing multiple conductive parts on the front side provided in the first aspect embodiment of the present application.

[0085] like Figure 2 As shown, in some embodiments, step S02 includes: Step S021: Figure 6As shown, a seed material is deposited on the front surface 13 to form an inner wall seed layer 311 covering the inner wall of the blind hole 11 and a seed layer 330 covering the front surface 13 .

[0086] Optionally, the seed material is deposited on the front surface 13 by using a physical vapor deposition method.

[0087] Optionally, the seed material may be preferably metallic titanium.

[0088] In these embodiments, the inner wall seed layer 311 and the seed layer 330 are formed at one time through a deposition process, which can reduce the number of preparation steps.

[0089] Step S022: Figure 7 As shown, a patterned first pattern layer 4 is prepared on the seed layer 330 , and the first pattern layer 4 has a plurality of first holes to be deposited 41 , each of which exposes each blind hole 11 and the seed layer 330 to form a first deposition area 33A.

[0090] Optionally, each first deposition area 33A is disposed around each blind hole 11 .

[0091] Optionally, the first pattern layer 4 can be formed by applying glue on the seed layer 330 and exposing and developing it, wherein the glue in the area where the first hole to be deposited 41 is located is removed by exposure and development to form the first hole to be deposited 41; the first pattern layer 4 can also be formed by laminating a dry film on the seed layer 330 and performing a laser window opening process, wherein the dry film in the area where the first hole to be deposited 41 is located is removed by laser window opening to form the first hole to be deposited 41.

[0092] Step S023: Figure 8 As shown, a metal material is deposited in the first to-be-deposited hole 41 to form a conductive core 313 on the inner wall seed layer 311 and a first trace 333 on the first deposition area 33A.

[0093] Optionally, in step S023 , deposition is performed using an electroplating process.

[0094] Optionally, the material of the conductive core 313 and the material of the first wiring 333 are both metal copper. In the electroplating process, the thickness of the deposited surface copper can be controlled within the range of 0-5 μm, so the deposited surface copper can be directly used as the first wiring 333, thereby avoiding grinding of the surface copper.

[0095] In these embodiments, the conductive core 313 and the first trace 333 are formed at one time through a deposition process, thereby reducing the number of manufacturing steps.

[0096] Step S024: Fig. 9As shown, the first pattern layer 4 is stripped off to expose the seed layer 330 to form a plurality of to-be-etched regions 33B.

[0097] Step S025: Fig. 9 and Fig.10 As shown, the to-be-etched area 33B is etched to pattern the seed layer 330 to form a plurality of seed layer islands 331 .

[0098] In some embodiments, the orthographic projection of the first trace 333 on the substrate 1 does not exceed the orthographic projection range of the integrated structure formed by the inner wall seed layer 311 and the seed layer island 331 on the substrate 1 .

[0099] In these embodiments, the orthographic projection of the first wiring 333 on the substrate 1 does not exceed the orthographic projection range of the integrated structure formed by the inner wall seed layer 311 and the seed layer island 331 on the substrate 1, which can avoid the occurrence of voids between the first wiring 333 and the substrate 1.

[0100] Optionally, the orthographic projection of the first wiring 333 on the substrate 1 coincides with the orthographic projection of the integrated structure formed by the inner wall seed layer 311 and the seed layer island 331 on the substrate 1 .

[0101] Please continue to refer to Figure 3. Figure 3 It is a flow chart of the method for preparing a through-hole interconnection structure provided in the embodiment of the first aspect of the present application.

[0102] like Figure 3 As shown, in some embodiments, after step S04 and before step 05, the preparation method further includes: Step S06: Fig.15 As shown, a dielectric layer 6 is prepared on the back surface 15 , and the dielectric layer 6 covers the back surface 15 and the conductive pillars 31 .

[0103] Step S07: Fig.16 As shown, the dielectric layer 6 is thinned to expose the conductive pillars 31. After the substrate 1 is etched, the conductive pillars 31 protrude from the back surface 15. The dielectric layer 6 covering the back surface 15 and the conductive pillars 31 is prepared on the back surface 15 to protect the conductive pillars 31.

[0104] Optionally, in step S07 , the dielectric layer 6 is subjected to a grinding and thinning process.

[0105] Optionally, the dielectric layer 6 is thinned until the conductive pillar 31 is ground and thinned. The dielectric layer 6 is thinned until the conductive pillar 31 is ground and thinned to ensure that the conductive pillar 31 is exposed.

[0106] In these optional embodiments, the dielectric layer 6 can be thinned until the conductive pillar 31 is ground and thinned to expose the conductive core 313, or it can be thinned until only the inner wall seed layer 311 is ground, but the inner wall seed layer 311 cannot be ground to such an extent that the conductive core 313 is exposed.

[0107] For example, as shown in the figure, the dielectric layer 6 can be thinned until the conductive pillar 31 is ground and thinned to expose the conductive core 313. Since the conductive performance of the conductive core 313 is greater than the conductive performance of the inner wall seed layer 311, the dielectric layer 6 is thinned until the conductive pillar 31 is ground and thinned to expose the conductive core 313, which can improve the conductive performance of the through-hole interconnect structure.

[0108] In these optional embodiments, the material of the dielectric layer 6 can be an organic material such as polyimide, polybenzoxazole, or an inorganic material such as silicon nitride or silicon oxynitride. On the one hand, during the grinding process, the dielectric layer 6 can protect the conductive pillars 31 and reduce the damage to the glass substrate during the grinding process. On the other hand, the dielectric layer 6 can also increase the adhesion between the second signal line 5 and the glass substrate, so that multiple second signal lines 5 can be directly deposited on the dielectric layer 6, thereby avoiding the need to first deposit a seed layer on the dielectric layer 6 and then deposit multiple second signal lines 5 on the deposited seed layer.

[0109] Please continue reading Figure 4 , Figure 4 It is a flow chart of preparing multiple second signal lines on the back side provided by the embodiment of the first aspect of the present application.

[0110] like Figure 4 As shown, in some embodiments, step S05 includes: Step S051: Fig.17 As shown, a patterned second pattern layer 7 is formed on the dielectric layer 6 , and the second pattern layer 7 has a plurality of second holes to be deposited 71 , each of which exposes each conductive pillar 31 and the dielectric layer 6 to form a second deposition area 6A.

[0111] Optionally, each second deposition area 6A is disposed around each conductive pillar 31 .

[0112] Optionally, the second pattern layer 7 can be formed by applying glue on the dielectric layer 6 and exposing and developing the glue, wherein the glue in the area where the second holes to be deposited 71 are located is removed by exposure and development to form the second holes to be deposited 71; the second pattern layer 7 can also be formed by laminating a dry film on the dielectric layer 6 and performing a laser window opening process, wherein the dry film in the area where the second holes to be deposited 71 are located is removed by laser window opening to form multiple second holes to be deposited 71.

[0113] Step S052: Fig.18As shown, a metal material is deposited in the second to-be-deposited holes 71 to form a plurality of second signal lines 5 on the second deposition area 6A.

[0114] Optionally, after step S052 , step S05 further includes: peeling off the second pattern layer 7 .

[0115] like Figure 3 As shown, in some embodiments, before step S03, the preparation method further includes: Step S08: Fig.11 As shown, a protective film 8 is attached, and the protective film 8 covers the plurality of conductive parts 3 .

[0116] like Figure 3 As shown, in some embodiments, after step S04 and before step S06, the preparation method further includes: step S09: removing the protective film 8, and temporarily bonding the front surface 13 to the carrier 9. On the one hand, the carrier 9 can protect the prepared multiple conductive parts 3 in the subsequent process steps, and on the other hand, during the grinding and thinning process of the dielectric layer 6, the carrier 9 can also provide support for the substrate 1 to improve the strength of the substrate 1.

[0117] In these embodiments, the front surface 13 and the carrier 9 are temporarily bonded via a removable adhesive 10 , and the removable adhesive 10 covers the plurality of conductive parts 3 .

[0118] In the above embodiment, after step S052, Fig.19 As shown, the preparation method further includes debonding the front surface 13 from the carrier 9. Thus, a through-hole interconnection structure is obtained.

[0119] Optionally, the front side 13 and the carrier board 9 are debonded by peeling off the peelable adhesive 10 and the carrier board 9 .

[0120] Optionally, the step of peeling off the second pattern layer 7 and the step of debonding the front surface 13 from the carrier 9 can be performed simultaneously or sequentially, which is not specifically limited in the present application.

[0121] by Figure 3 The flowchart shown in Figure 5 is taken as an example, and refer to Figure 5 to Fig.19 A method for preparing a through-hole interconnect structure provided in an embodiment of the present application is illustrated by way of example. Figures 5 to 18 is a schematic structural diagram of an intermediate product in the process of preparing a through-hole interconnection structure provided in an embodiment of the first aspect of the present application, Fig.19 It is a structural schematic diagram of a through-hole interconnect structure prepared by the method for preparing a through-hole interconnect structure provided in the embodiment of the first aspect of the present application.

[0122] Step 1: If Figure 5As shown, a plurality of blind holes 11 are formed in the substrate 1. The substrate 1 has a front surface 13 and a back surface 15 which are opposite to each other, and each blind hole 11 extends from the front surface 13 to the back surface 15.

[0123] Step 2: If Figure 6 As shown, a seed material is deposited on the front surface 13 to form an inner wall seed layer 311 covering the inner wall of the blind hole 11 and a seed layer 330 covering the front surface 13 .

[0124] Step 3: If Figure 7 As shown, a patterned first pattern layer 4 is prepared on the seed layer 330 , and the first pattern layer 4 has a plurality of first holes to be deposited 41 , each of which exposes each blind hole 11 and the seed layer 330 to form a first deposition area 33A.

[0125] Step 4: If Figure 8 As shown, a metal material is deposited in the first to-be-deposited hole 41 to form a conductive core 313 on the inner wall seed layer 311 and a first trace 333 on the first deposition area 33A.

[0126] Step 5: If Fig. 9 As shown, the first pattern layer 4 is stripped off to expose the seed layer 330 to form a plurality of to-be-etched regions 33B.

[0127] Step 6: If Fig. 9 and Fig.10 As shown, the to-be-etched area 33B is etched to pattern the seed layer 330 to form a plurality of seed layer islands 331 .

[0128] Step 7: If Fig.11 As shown, a protective film 8 is attached, and the protective film 8 covers the plurality of conductive parts 3 .

[0129] Step 8: If Fig.12 As shown, the substrate 1 is etched for the first time using a first etchant to thin the substrate 1 until a preset distance D exists between the back surface 15 and the conductive pillar 31 .

[0130] Step 9: If Fig.13 As shown, the substrate 1 is etched for the second time using a second etchant to thin the substrate 1 until the conductive pillars 31 protrude from the back surface 15 .

[0131] Step 10: Fig.14 As shown, the protective film 8 is removed and the front side 13 is temporarily bonded to the carrier 9 .

[0132] Step 11: Fig.15 As shown, a dielectric layer 6 is prepared on the back surface 15 , and the dielectric layer 6 covers the back surface 15 and the conductive pillars 31 .

[0133] Step 12: Fig.16As shown, the dielectric layer 6 is thinned to expose the conductive pillars 31 .

[0134] Step 13: Fig.17 As shown, a patterned second pattern layer 7 is formed on the dielectric layer 6 , and the second pattern layer 7 has a plurality of second holes to be deposited 71 , each of which exposes each conductive pillar 31 and the dielectric layer 6 to form a second deposition area 6A.

[0135] Step 14: Fig.18 As shown, a metal material is deposited in the second to-be-deposited holes 71 to form a plurality of second signal lines 5 on the second deposition area 6A.

[0136] Step 15: Fig.19 As shown, the through-hole interconnection structure can be obtained by peeling off the second pattern layer 7, the carrier 9 and the peelable adhesive 10.

[0137] The second embodiment of the present application also provides a through-hole interconnect structure, which is prepared by the preparation method of the through-hole interconnect structure of any of the first embodiments. Since the through-hole interconnect structure of the embodiment of the present application is prepared by the preparation method of the through-hole interconnect structure of any of the first embodiments, the through-hole interconnect structure of the present application has the beneficial effects of any of the preparation methods of the through-hole interconnect structure, which will not be described in detail here.

[0138] The through-hole interconnect structure includes, but is not limited to, being an interposer for 2.5D packaging, being a glass core substrate, or being an IC substrate.

[0139] Optionally, when the through-hole interconnection structure is used as a transfer plate, the thickness of the through-hole interconnection structure is less than 100 um.

[0140] Optionally, when the through-hole interconnect structure is used as a glass core carrier, the thickness of the through-hole interconnect structure is less than 200 um.

[0141] The application can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in the specific embodiment can be modified, and the system architecture does not depart from the basic spirit of the application. Therefore, the current embodiment is regarded as exemplary and non-restrictive in all aspects, and the scope of the application is defined by the attached claims rather than the above description, and all changes falling within the meaning of the claims and the scope of equivalents are thereby included in the scope of the application.

Claims

1. A method for preparing a through-hole interconnection structure, characterized in that: The following steps are involved: A plurality of blind holes are formed in a substrate, wherein the substrate has a front surface and a back surface opposite to each other, and each of the blind holes extends from the front surface to the back surface; A plurality of conductive parts are prepared on the front surface, each of the conductive parts comprises a conductive column and a first signal line connected to each other, the conductive column fills the blind hole, and the first signal line is formed on the front surface; Using a first etchant to perform a first etching on the substrate, so as to thin the substrate until a preset distance exists between the back surface and the conductive pillar; Using a second etchant to etch the substrate for a second time, so that the substrate is thinned until the conductive pillar protrudes from the back surface, the etching rate of the substrate by the second etchant is lower than the etching rate of the substrate by the first etchant, and the second etchant selectively etches the substrate between the substrate and the conductive pillar; A plurality of second signal lines are prepared on the side where the back surface is located, and each of the second signal lines is connected to each of the conductive pillars.

2. The method for preparing a through-hole interconnection structure according to claim 1, characterized in that: The preparation method satisfies at least one of the following conditions: The substrate is a glass substrate; The ratio of the etching rate of the first etchant on the substrate to the etching rate of the second etchant on the substrate is 5-20; The etching rate of the first etchant on the substrate is 1 μm / min to 10 μm / min in terms of thinning thickness; The etching rate of the second etchant on the substrate is 0.1 μm / min to 1 μm / min in terms of thinning thickness; The first etchant is an acidic etchant; The second etchant is an alkaline etchant.

3. The method for preparing a through-hole interconnection structure according to claim 1, characterized in that: The preparation method satisfies at least one of the following conditions: The preset spacing is 0-10 μm; The depth of the blind hole is 0-200 μm; Before the step of first etching the substrate using a first etchant, the thickness of the substrate is not less than 500 μm.

4. The method for preparing a through-hole interconnection structure according to claim 1, characterized in that: The conductive column comprises an inner wall seed layer covering the inner wall of the blind hole and a conductive core arranged on the inner wall seed layer; The first signal line includes a seed layer island disposed on the front side and a first routing line disposed on the seed layer island; The inner wall seed layer and the seed layer island are an integrated structure, and the conductive core and the first wiring are an integrated structure.

5. The method for preparing a through-hole interconnection structure according to claim 4, characterized in that: The thickness of the first wiring is 0-5 μm.

6. The method for preparing a through-hole interconnection structure according to claim 1, characterized in that: The step of preparing a plurality of conductive parts on the front side includes: Depositing a seed material on the front surface to form an inner wall seed layer covering the inner wall of the blind hole and a seed layer covering the front surface; Preparing a patterned first pattern layer on the seed layer, wherein the first pattern layer has a plurality of first holes to be deposited, each of the first holes to be deposited exposes each of the blind holes and the seed layer to form a first deposition area; Depositing a metal material in the first to-be-deposited hole to form a conductive core on the inner wall seed layer and a first trace on the first deposition area; Stripping the first pattern layer to expose the seed layer to form a plurality of to-be-etched areas; The to-be-etched area is etched to pattern the seed layer to form a plurality of seed layer islands.

7. The method for preparing a through-hole interconnection structure according to claim 6, characterized in that: The preparation method satisfies at least one of the following conditions: Each of the first deposition areas is arranged around each of the blind holes; In the step of depositing the metal material in the first hole to be deposited, the deposition is performed by using an electroplating process; The thickness of the first wiring is 0-5 μm.

8. The method for preparing a through-hole interconnection structure according to any one of claims 4 to 7, characterized in that: The orthographic projection of the first routing line on the substrate does not exceed the orthographic projection range of the integrated structure formed by the inner wall seed layer and the seed layer island on the substrate.

9. The method for preparing a through-hole interconnection structure according to claim 8, characterized in that: The orthographic projection of the first routing line on the substrate coincides with the orthographic projection of the integrated structure formed by the inner wall seed layer and the seed layer island on the substrate.

10. The method for preparing a through-hole interconnection structure according to claim 1, characterized in that: After the step of etching the substrate for a second time using a second etchant and before the step of preparing a plurality of second signal lines on the back side, the preparation method further includes: Prepare a dielectric layer on the back side, wherein the dielectric layer covers the back side and the conductive pillar; The dielectric layer is thinned to expose the conductive pillars.

11. The method for preparing a through-hole interconnection structure according to claim 10, characterized in that: In the step of thinning the dielectric layer, the dielectric layer is subjected to a grinding and thinning process.

12. The method for preparing a through-hole interconnection structure according to claim 11, characterized in that: The dielectric layer is thinned until the conductive pillar is ground and thinned.

13. The method for preparing a through-hole interconnection structure according to any one of claims 10 to 12, characterized in that: The step of preparing a plurality of second signal lines on the back side includes: Forming a patterned second pattern layer on the dielectric layer, wherein the second pattern layer has a plurality of second holes to be deposited, each of the second holes to be deposited exposes each of the conductive pillars and the dielectric layer to form a second deposition area; A metal material is deposited in the second to-be-deposited holes to form a plurality of second signal lines on the second deposition area.

14. The method for preparing a through-hole interconnection structure according to claim 13, characterized in that: Each of the second deposition areas is arranged around each of the conductive pillars; or / and, After the step of depositing the metal material in the second to-be-deposited hole, the step of preparing a plurality of second signal lines on the side where the back surface is located further includes: stripping the second pattern layer.

15. The method for preparing a through-hole interconnection structure according to claim 14, characterized in that: Before the step of etching the substrate for the first time using the first etchant, the preparation method further comprises: A protective film is attached, and the protective film covers the plurality of conductive parts.

16. The method for preparing a through-hole interconnection structure according to claim 15, characterized in that: After the step of etching the substrate for a second time using a second etchant and before the step of preparing a dielectric layer on the back side, the preparation method further includes: The protective film is removed and the front side is temporarily bonded to a carrier.

17. The method for preparing a through-hole interconnection structure according to claim 16, characterized in that: After the step of depositing the metal material in the second hole to be deposited, the preparation method further comprises: The front side is debonded from the carrier.

18. A through-hole interconnect structure, characterized in that: The through-hole interconnect structure is prepared by the method for preparing the through-hole interconnect structure as described in any one of claims 1 to 17.

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