Semiconductor device, manufacturing method, and wafer structure

Abstract

The present invention discloses a semiconductor device, a manufacturing method thereof, and a wafer structure. The manufacturing method includes: the semiconductor structure includes a device core region, a dicing street region, a semiconductor body, a first electrode, a first insulating layer, and a buffer layer; the first insulating layer is at least located in the dicing street region; the first electrode is located on a side of the first insulating layer away from the semiconductor body; the buffer layer is located in the device core region; a passivation layer is formed on a side of the buffer layer away from the first electrode, and the passivation layer is located in the device core region and the dicing street region; at least a part of the passivation layer in the device core region and the dicing street region is removed; the first insulating layer in the dicing street region is removed, and at least a part of the buffer layer is retained during the removal of the first insulating layer and covers the first electrode; the buffer layer is removed; dicing and cutting are performed in the dicing street region. The technical solution provided by the embodiments of the present invention improves the cutting accuracy during the manufacturing process of the semiconductor device when performing dicing and cutting in the dicing street region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device, a manufacturing method thereof, and a wafer structure. Background Art

[0002] The metal-oxide-semiconductor field-effect transistor (MOSFET) of the third-generation wide-bandgap semiconductor represented by silicon carbide has become a research hotspot of power semiconductor devices, which has excellent characteristics such as a wide bandgap, a high critical breakdown electric field, a high electron saturation migration rate, and a high thermal conductivity.

[0003] In the process of dicing and cutting from the dicing channel area of the existing semiconductor device, there is etching residue on the surface of the semiconductor body in the dicing channel area, which leads to low cutting accuracy in the dicing channel area. Summary of the Invention

[0004] The present invention provides a semiconductor device, a manufacturing method thereof, and a wafer structure to improve the cutting accuracy in the dicing channel area during the manufacturing process of the semiconductor device.

[0005] According to an aspect of the present invention, a manufacturing method of a semiconductor device is provided, including:

[0006] Providing a semiconductor structure, the semiconductor structure including a device core area and a dicing channel area; the dicing channel area is located on one side of the device core area; the semiconductor structure further includes a semiconductor body, a first electrode, a first insulating layer, and a buffer layer; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the first insulating layer is located on the first surface and at least in the dicing channel area; the first electrode is located on a side of the first insulating layer away from the semiconductor body and in the device core area; the buffer layer is located on a surface of the first electrode away from the semiconductor body, and the buffer layer is in the device core area;

[0007] Forming a passivation layer on a side of the buffer layer away from the first electrode, and the passivation layer is in the device core area and the dicing channel area;

[0008] Removing at least part of the passivation layer in the device core area and the dicing channel area;

[0009] Removing the first insulating layer in the dicing channel area, and at least part of the buffer layer is retained during the removal of the first insulating layer and covers the first electrode;

[0010] Removing at least part of the buffer layer;

[0011] Dicing and cutting are performed in the dicing street area.

[0012] According to another aspect of the present invention, there is provided a semiconductor device manufactured by the manufacturing method of any semiconductor device described in the embodiments of the present invention.

[0013] According to another aspect of the present invention, there is provided a wafer structure, comprising:

[0014] A semiconductor structure, the semiconductor structure includes a device core area and a dicing street area; the dicing street area is located on one side of the device core area; the semiconductor structure further includes a semiconductor body, a first electrode, a first insulating layer and a buffer layer; the semiconductor body includes a first surface and a second surface arranged opposite to each other; the first insulating layer is located on the first surface and at least in the dicing street area; the first electrode is located on the side of the first insulating layer away from the semiconductor body and in the device core area; the buffer layer is located on the surface of the first electrode away from the semiconductor body and in the device core area, and the buffer layer is used to at least partially remain during the removal process of the first insulating layer and cover the first electrode;

[0015] A passivation layer, located on the side of the buffer layer away from the first electrode, and the passivation layer is located in the device core area and the dicing street area.

[0016] For the semiconductor device, manufacturing method and wafer structure provided by the embodiments of the present invention, the technical solution provided by the embodiments of the present invention removes part or all of the passivation layer in the device core area and the dicing street area, and removes the first insulating layer in the dicing street area. The buffer layer at least partially remains during the removal process of the first insulating layer and covers the first electrode. That is, during the etching process of the passivation layer and the first insulating layer, it can be ensured that the first electrode is covered by the buffer layer, avoiding the generation of by-products covering the dicing street area during the etching of the first electrode. In the subsequent process of dicing and cutting in the dicing street area, there is no etching residue on the first surface of the semiconductor body in the dicing street area, thereby improving the accuracy of dicing and cutting.

[0017] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 It is a schematic structural diagram of a semiconductor device provided by the prior art;

[0020] Figure 2 It is a schematic structural diagram of another semiconductor device provided by the prior art;

[0021] Figure 3 It is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

[0022] Figures 4 - 13 It is a schematic structural diagram corresponding to each step of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

[0023] Figure 14 It is Figure 3 A flow example diagram provided in S110 in;

[0024] Figure 15 It is Figure 14 A schematic structural diagram corresponding to the relevant steps in;

[0025] Figure 16 It is Figure 3 Another flow example diagram provided in S110 in;

[0026] Figure 17 It is Figure 16 A schematic structural diagram corresponding to the relevant steps in;

[0027] Figure 18 It is Figure 3 Another flow schematic diagram provided in S110 in. Detailed implementation manners

[0028] To enable those skilled in the art to better understand the solutions of the present invention, the following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, rather than all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations of "comprising" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or components does not have to be limited to those steps or components clearly listed, but may include other steps or structures not clearly listed or inherent to these processes, methods, products or devices.

[0030] Figure 1 is a schematic structural diagram of a semiconductor device provided by the prior art. Figure 2 is a schematic structural diagram of another semiconductor device provided by the prior art. The manufacturing method of the semiconductor device in the prior art includes:

[0031] As Figure 1 shown, a semiconductor structure is provided. The semiconductor structure includes a device core region 01 and a dicing street region 02; the dicing street region 02 is located on one side of the device core region 01; the semiconductor structure further includes a semiconductor body 100, a first electrode 200 and a first insulating layer 300; the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged oppositely; the first insulating layer 300 is located on the first surface 101 and at least in the dicing street region 02; the first electrode 200 is located on the side of the first insulating layer 300 away from the semiconductor body 100 and in the device core region 01.

[0032] As Figure 1 shown, a passivation layer 400 is formed on the side of the first electrode 200 away from the semiconductor body 100, and the passivation layer 400 covers the device core region 01 and the dicing street region 02. Then a mask layer 401 is formed on the side of the passivation layer 400 away from the first electrode 200.

[0033] As Figure 2 shown, the passivation layer 400 and the first insulating layer 300 in the device core region 01 and the dicing street region 02 are removed by a dry etching process. Since in the process of removing the passivation layer 400 and the first insulating layer 300 by the dry etching process, it is inevitable that the dry etching particles continuously bombard the first electrode 200, and thus by-products are generated, and the by-products cover the dicing street region 02.

[0034] As Figure 2As shown, since the by-products cover the scribing lane region 02, during the process of removing the first insulating layer 300, there is an etching residue 300a of the first insulating layer 300 on the first surface 101 of the semiconductor body 100 within the scribing lane region 02.

[0035] As Figure 2 shown, when there is an etching residue 300a on the first surface 101 of the semiconductor body 100 within the scribing lane region 02, a laser cutting process is usually adopted. A laser beam with a high power density is irradiated onto the scribing lane region 02 for cutting. After the laser irradiates the etching residue 300a, scattering occurs, thus changing the cutting path of the laser, and further resulting in low precision of the scribing cutting.

[0036] It should be noted that Figure 1 and Figure 2 the manufacturing solution of a MOSFET semiconductor device is taken as an example for illustration.

[0037] In order to improve the cutting precision of scribing and cutting in the scribing lane region during the manufacturing process of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0038] As Figure 3 shown, Figure 3 is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention. The manufacturing method of the semiconductor device includes the following steps:

[0039] S110. Provide a semiconductor structure, where the semiconductor structure includes a device core region and a scribing lane region; the scribing lane region is located on one side of the device core region; the semiconductor structure further includes a semiconductor body, a first electrode, a first insulating layer, and a buffer layer; the semiconductor body includes a first surface and a second surface arranged opposite to each other; the first insulating layer is located on the first surface and at least in the scribing lane region; the first electrode is located on the side of the first insulating layer away from the semiconductor body and in the device core region; the buffer layer is located on the surface of the first electrode away from the semiconductor body and in the device core region.

[0040] The process of providing the semiconductor structure is as follows:

[0041] As Figure 4As shown, a semiconductor structure is provided. The semiconductor structure includes a device core region 01 and a dicing channel region 02; the dicing channel region 02 is located on one side of the device core region 01; the semiconductor structure further includes a semiconductor body 100, a first electrode 200, and a first insulating layer 300. The semiconductor body 100 includes a first surface 101 and a second surface 102 which are oppositely arranged. The first insulating layer 300 is located on the first surface 101 and at least in the dicing channel region 02; the first electrode 200 is located on the side of the first insulating layer 300 away from the semiconductor body 100 and in the device core region 01. In the embodiment of the present invention, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also only include the epitaxial layer 20. In some other embodiments of the present invention, the semiconductor body 100 may further include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 through a single epitaxial process, and the epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0042] As Figure 5 shown, a buffer layer 500 is formed on the surface of the first electrode 200 away from the semiconductor body 100.

[0043] As Figure 6 shown, a mask layer 001 is formed on the side of the buffer layer 500 away from the first electrode 200.

[0044] As Figure 7 shown, the buffer layer 500 is patterned, and the buffer layer 500 located in the device core region 01 is retained.

[0045] S120. A passivation layer is formed on the side of the buffer layer away from the first electrode, and the passivation layer is located in the device core region and the dicing channel region.

[0046] As Figure 8 shown, a passivation layer 400 is formed on the side of the buffer layer 500 away from the first electrode 200, and the passivation layer 400 is located in the device core region 01 and the dicing channel region 02. And a mask layer 002 is formed on the side of the passivation layer 400 away from the buffer layer 500.

[0047] S130. At least part of the passivation layer in the device core region and the dicing channel region is removed.

[0048] As Figure 11 shown, part or all of the passivation layer 400 in the device core region 01 and the dicing channel region 02 is removed.

[0049] S140. The first insulating layer in the dicing channel region is removed, and at least part of the buffer layer is retained during the removal process of the first insulating layer and covers the first electrode.

[0050] As shown in Figure 12 Figure [not provided], the first insulating layer 300 in the dicing street area 02 is removed. The buffer layer 500 is at least partially retained during the removal of the first insulating layer 300 and covers the first electrode 200.

[0051] S150. Remove at least part of the buffer layer.

[0052] As shown in Figure 13 Figure [not provided], at least part of the buffer layer 500 is removed.

[0053] S160. Perform dicing in the dicing street area.

[0054] As shown in Figure 13 Figure [not provided], dicing can be performed in the dicing street area 02 by a laser cutting process.

[0055] In the technical solution provided by the embodiment of the present invention, part or all of the passivation layer 400 in the device core area 01 and the dicing street area 02 is removed, and the first insulating layer 300 in the dicing street area 02 is removed. The buffer layer 500 is at least partially retained during the removal of the first insulating layer 300 and covers the first electrode 200. That is, during the etching of the passivation layer 400 and the first insulating layer 300, it can be ensured that the first electrode 200 is covered by the buffer layer 500, avoiding the generation of by-products covering the dicing street area 02 during the etching of the first electrode 200. During the subsequent dicing process in the dicing street area 02, there is no etching residue on the first surface 101 of the semiconductor body 100 in the dicing street area 02, thereby improving the dicing accuracy.

[0056] Optionally, on the basis of the above technical solution, the first insulating layer 300 and the buffer layer 500 are made of the same material; when removing the first insulating layer 300 in the dicing street area 02, the thickness of the buffer layer 500 is greater than the thickness of the first insulating layer 300 to ensure that the first electrode 200 is covered by the buffer layer 500 during the etching of the first insulating layer 300.

[0057] Optionally, on the basis of the above technical solution, the first insulating layer 300 and the buffer layer 500 are made of different materials; when removing the first insulating layer 300 in the dicing street area 02, an etching gas with an etching rate of the buffer layer 500 less than that of the first insulating layer 300 can be selected to control the removal rate of the buffer layer 500 to be less than that of the first insulating layer 300 to ensure that the first electrode 200 is covered by the buffer layer 500 during the etching of the first insulating layer 300.

[0058] Optionally, on the basis of the above technical solution, as shown in Figure 11 and Figure 12, the buffer layer 500 includes at least two sub-buffer layers. When removing the first insulating layer 300 in the dicing street area 02, an etching gas with an etching rate of at least part of the sub-buffer layer less than that of the first insulating layer 300 can be selected to control the removal rate of at least part of the sub-buffer layer to be less than that of the first insulating layer 300, so as to ensure that during the etching process of the first insulating layer 300, the first electrode 200 is covered by the buffer layer 500, avoiding over-etching during the etching process of the first insulating layer 300, that is, after the first insulating layer 300 is etched, further etching the buffer layer 500 and exposing the first electrode.

[0059] Exemplarily, in the embodiments of the present invention, the first insulating layer 300 includes two sub-insulating layers as an example for introduction, namely the first sub-insulating layer 301 and the second sub-insulating layer 302.

[0060] Exemplarily, Figure 8 in, the buffer layer 500 includes two sub-buffer layers, namely the first sub-buffer layer 501 and the second sub-buffer layer 502. Figure 9 in, the buffer layer 500 includes a single-layer structure. Figure 10 in, the buffer layer 500 includes three sub-buffer layers, namely the first sub-buffer layer 501, the second sub-buffer layer 502, and the third sub-buffer layer 503.

[0061] Optionally, on the basis of the above technical solution, when removing the first insulating layer 300 in the dicing street area 02, the removal rate of the bottom sub-buffer layer is less than that of the bottom sub-insulating layer. The bottom sub-buffer layer is the sub-buffer layer in the buffer layer 500 that contacts the first electrode 200, and the bottom sub-insulating layer is the sub-insulating layer in the first insulating layer 300 that contacts the first surface 101.

[0062] The above technical solution can ensure that after the first sub-insulating layer 301 in the dicing street area 02 is removed, there is still a bottom sub-buffer layer covering the first electrode 200 in the device core area 01. That is, during the etching process of the first insulating layer 300, it can be ensured that the first electrode 200 is covered by the buffer layer 500, avoiding the generation of by-products covering the dicing street area 02 by etching the first electrode 200, so that during the subsequent dicing process in the dicing street area 02, there is no etching residue on the first surface 101 of the semiconductor body 100 in the dicing street area 02, thereby improving the dicing accuracy.

[0063] Optionally, based on the above technical solution, when removing the passivation layer 400 in the dicing street region 02, an etching gas with an etching rate of at least part of the sub-buffer layer less than that of the passivation layer 400 can be selected to control the removal rate of at least part of the sub-buffer layer to be less than that of the passivation layer 400, so as to ensure that the first electrode 200 is covered by the buffer layer 500 during the etching of the passivation layer 400, and to avoid over-etching during the etching of the passivation layer 400, where after the passivation layer 400 is etched, the buffer layer 500 is further etched and the first electrode is exposed.

[0064] Optionally, based on the above technical solution, the sub-buffer layer includes any one or a combination of at least two of silicon oxide, silicon nitride, polysilicon, silicon, germanium, and silicon-germanium heterostructures.

[0065] Optionally, based on the above technical solution, as Figure 14 shown, S110 provides a semiconductor structure including:

[0066] S1101. Provide a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other; the semiconductor body further includes a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on a side of the first region away from the first surface. The semiconductor body further includes a second insulating layer, and the second insulating layer is located on the first surface.

[0067] As Figure 15 shown, provide a semiconductor body 100, the semiconductor body 100 including a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 further includes a well region 103 and a first region 104, the first region 104 being of a first conductivity type and located on the first surface 101, and the well region 103 being of a second conductivity type and located on a side of the first region 104 away from the first surface 101. The semiconductor body 100 further includes a second insulating layer 107, and the second insulating layer 107 is located on the first surface 101.

[0068] In other embodiments, the semiconductor body 100 further includes a second region 105, and the second region 105 is of a second conductivity type.

[0069] S1102. Form a gate on a side of the second insulating layer away from the first surface, and the second insulating layer is used to insulate and separate the semiconductor body and the gate.

[0070] As Figure 15 shown, form a gate 108 on a side of the second insulating layer 107 away from the first surface 101, and the second insulating layer 107 is used to insulate and separate the semiconductor body 100 and the gate 108.

[0071] S1103. Form an interlayer insulating layer on the side of the gate away from the semiconductor body.

[0072] As Figure 15 shown, form an interlayer insulating layer 109 on the side of the gate 108 away from the semiconductor body 100.

[0073] S1104. Form a first electrode on the first surface of the semiconductor body, and the first electrode is the source electrode; the interlayer insulating layer is used to insulate and separate the gate and the source electrode.

[0074] As Figure 15 shown, form a first electrode 200 on the first surface 101 of the semiconductor body 100, and the first electrode 200 is the source electrode; the interlayer insulating layer 109 is used to insulate and separate the gate 108 and the source electrode.

[0075] S1105. Form a drain electrode on the second surface of the semiconductor body.

[0076] As Figure 15 shown, form a drain electrode 600 on the second surface 102 of the semiconductor body 100.

[0077] Specifically, the above technical solution prepares a planar-structured MOSFET power device.

[0078] Optionally, on the basis of the above technical solution, as Figure 16 shown, S110 provides a semiconductor structure including:

[0079] S1106. Provide a semiconductor body, the semiconductor body includes a first surface and a second surface arranged opposite to each other; the semiconductor body further includes a well region and a first region, the first region is of a first conduction type and is located on the first surface, the well region is of a second conduction type and is located on the side of the first region away from the first surface; the first surface is provided with a gate trench, and the gate trench extends from the first surface into the semiconductor body. The semiconductor body further includes a second insulating layer, and the second insulating layer is located on the bottom surface and the side wall of the gate trench.

[0080] As Figure 17 shown, provide a semiconductor body 100, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 further includes a well region 103 and a first region 104, the first region 104 is of a first conduction type and is located on the first surface 101, the well region 103 is of a second conduction type and is located on the side of the first region 104 away from the first surface 101; the first surface 101 is provided with a gate trench T1, and the gate trench T1 extends from the first surface 101 into the semiconductor body 100. The semiconductor body 100 further includes a second insulating layer 107, and the second insulating layer 107 is located on the bottom surface and the side wall of the gate trench T1.

[0081] S1107. A gate is formed on a side of the second insulating layer away from the semiconductor body within the gate trench, and the second insulating layer is used to insulate and separate the semiconductor body and the gate.

[0082] As Figure 17 shown, a gate 108 is formed on a side of the second insulating layer 107 away from the semiconductor body 100 within the gate trench T1, and the second insulating layer 107 is used to insulate and separate the semiconductor body 100 and the gate 108.

[0083] S1108. An interlayer insulating layer is formed on a side of the gate away from the semiconductor body.

[0084] As Figure 17 shown, an interlayer insulating layer 109 is formed on a side of the gate 108 away from the semiconductor body 100.

[0085] S1109. A first electrode is formed on the first surface of the semiconductor body, and the first electrode is a source electrode; the interlayer insulating layer is used to insulate and separate the gate and the source electrode.

[0086] As Figure 17 shown, a first electrode 200 is formed on the first surface 101 of the semiconductor body 100, and the first electrode 200 is a source electrode; the interlayer insulating layer 109 is used to insulate and separate the gate 108 and the source electrode.

[0087] S11010. A drain is formed on the second surface of the semiconductor body.

[0088] As Figure 17 shown, a drain 600 is formed on the second surface 102 of the semiconductor body 100.

[0089] Specifically, the above technical solution prepares a MOSFET power device with a single trench structure.

[0090] Optionally, on the basis of the above technical solution, as Figure 18 shown, S110 provides a semiconductor structure including:

[0091] S11011. Provide a semiconductor body, the semiconductor body includes a first surface and a second surface arranged opposite to each other; the semiconductor body further includes a well region and a first region, the first region is of a first conduction type and is located on the first surface, the well region is of a second conduction type and is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; a source trench is provided on the first surface, and the source trench extends from the first surface into the semiconductor body. The semiconductor body further includes a second insulating layer and a third insulating layer, the second insulating layer is located on the bottom surface and side walls of the gate trench, and the third insulating layer is located on the bottom surface and side walls of the source trench.

[0092] As Figure 8As shown, a semiconductor body 100 is provided. The semiconductor body 100 includes a first surface 101 and a second surface 102 which are oppositely arranged; the semiconductor body 100 further includes a well region 103 and a first region 104. The first region 104 is of a first conduction type and is located on the first surface 101, and the well region 103 is of a second conduction type and is located on the side of the first region 104 away from the first surface 101; a gate trench T1 is provided on the first surface 101, and the gate trench T1 extends from the first surface 101 into the semiconductor body 100; a source trench T2 is provided on the first surface 101, and the source trench T2 extends from the first surface 101 into the semiconductor body 100. The semiconductor body 100 further includes a second insulating layer 107 and a third insulating layer 112. The second insulating layer 107 is located on the bottom surface and side walls of the gate trench T1, and the third insulating layer 112 is located on the bottom surface and side walls of the source trench T2.

[0093] S11012. Form a gate on the side of the second insulating layer away from the semiconductor body within the gate trench. The second insulating layer is used to insulate and separate the semiconductor body and the gate.

[0094] As Figure 8 shown, a gate 108 is formed on the side of the second insulating layer 107 away from the semiconductor body 100 within the gate trench T1. The second insulating layer 107 is used to insulate and separate the semiconductor body 100 and the gate 108.

[0095] S11013. Form an interlayer insulating layer on the side of the gate away from the semiconductor body. The interlayer insulating layer covers the gate.

[0096] As Figure 8 shown, an interlayer insulating layer 109 is formed on the side of the gate 108 away from the semiconductor body 100. The interlayer insulating layer 109 covers the gate 108.

[0097] S11014. Form a trench source structure on the side of the third insulating layer away from the semiconductor body within the source trench; the trench source structure includes a filling layer, and the third insulating layer is used to insulate and separate the semiconductor body and the filling layer.

[0098] As Figure 8 shown, a trench source structure is formed on the side of the third insulating layer 112 away from the semiconductor body 100 within the source trench T2; the trench source structure includes a filling layer 113, and the third insulating layer 112 is used to insulate and separate the semiconductor body 100 and the filling layer 113.

[0099] S11015. Form a first electrode on the side of the first surface away from the second surface; the interlayer insulating layer is used to insulate and separate the gate and the source.

[0100] As Figure 8As shown, a first electrode 200 is formed on a side of the first surface 101 away from the second surface 102, and the first electrode 200 serves as a source electrode; the interlayer insulating layer 109 is used to insulate and separate the gate electrode 108 and the source electrode.

[0101] S11016. A drain electrode is formed on the second surface of the semiconductor body.

[0102] As Figure 8 shown, a drain electrode 600 is formed on the second surface 102 of the semiconductor body 100.

[0103] Specifically, the above technical solution prepares a MOSFET power device with a double-groove structure.

[0104] Optionally, based on the above technical solution, as Figure 8 、 Figure 15 and Figure 17 shown, the first insulating layer 300 includes a first sub-insulating layer 301 and a second sub-insulating layer 302; the first sub-insulating layer 301 is located on the first surface 101 of the semiconductor body 100; the first sub-insulating layer 301 and the second insulating layer 107 are in the same layer; the second sub-insulating layer 302 is located on a side of the first sub-insulating layer 301 away from the first surface 101; the second sub-insulating layer 302 and the interlayer insulating layer 109 are in the same layer.

[0105] Specifically, while preparing the second insulating layer 107, the preparation of the first sub-insulating layer 301 is completed, and while preparing the interlayer insulating layer 109, the preparation of the second sub-insulating layer 302 is completed, which simplifies the manufacturing process and reduces the manufacturing cost.

[0106] The embodiment of the present invention further provides a semiconductor device, which is manufactured by the manufacturing method of the semiconductor device described in any of the embodiments of the present invention. Therefore, it has the beneficial effects of the manufacturing method of the semiconductor device described in any of the embodiments of the present invention, which will not be elaborated here.

[0107] The embodiment of the present invention further provides a wafer structure, as Figures 8 - 10As shown, the wafer structure includes: a semiconductor structure, which includes a device core region 01 and a dicing street region 02; the dicing street region 02 is located on one side of the device core region 01; the semiconductor structure further includes a semiconductor body 100, a first electrode 200, and a first insulating layer 300. The semiconductor body 100 includes a first surface 101 and a second surface 102 that are oppositely arranged. The first insulating layer 300 is located on the first surface 101 and at least in the dicing street region 02; a buffer layer 500 is used to at least partially remain during the removal of the first insulating layer 300 and cover the first electrode 200; a passivation layer 400 is located on the side of the buffer layer 500 away from the first electrode 200, and the passivation layer 400 is located in the device core region 01 and the dicing street region 02.

[0108] The wafer structure provided by the embodiment of the present invention can obtain a single semiconductor device after dicing and cutting in the dicing street region 02. During the cutting process, part or all of the passivation layer 400 in the device core region 01 and the dicing street region 02 is removed, and the first insulating layer 300 in the dicing street region 02 is removed. The buffer layer 500 at least partially remains during the removal of the first insulating layer 300 and covers the first electrode 200, that is, during the etching process of the passivation layer 400 and the first insulating layer 300, it can be ensured that the first electrode 200 is covered by the buffer layer 500, avoiding the generation of by-products covering the dicing street region 02 during the etching of the first electrode 200, so that during the subsequent dicing and cutting process in the dicing street region 02, there is no etching residue on the first surface 101 of the semiconductor body 100 in the dicing street region 02, thereby improving the accuracy of dicing and cutting.

[0109] Optionally, as Figure 8 、 Figure 15 and Figure 17 shown, the semiconductor structure further includes a terminal region 03; wherein, the terminal region 03 is located between the device core region 01 and the dicing street region 02; the terminal region 03 is provided with a semiconductor body 100, a first insulating layer 300, and a passivation layer 400; a terminal groove is provided on the first surface 101 of the semiconductor body 100 in the terminal region 03, and the first insulating layer 300 and the passivation layer 400 extend from the first surface 101 into the terminal groove; a plurality of third regions 114 arranged at intervals along the direction perpendicular to the second surface 102 and pointing to the first surface 101 are provided on the semiconductor body 100 at the bottom of the terminal groove, the third regions 114 are of the second conductivity type, and the semiconductor body 100 between the third regions 114 and the second surface 102 forms a depletion layer, thereby increasing the breakdown voltage performance of the terminal region 03.

[0110] Optionally, the semiconductor device further includes an ohmic contact layer 110 to form a good ohmic contact between the first electrode 200 and the semiconductor body 100.

[0111] It should be understood that the various forms of processes shown above can be used, with steps reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0112] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that, according to design requirements and other factors, various modifications, combinations, sub - combinations and substitutions can be made to multiple embodiments. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor structure is provided, the semiconductor structure comprising a device core region and a scribe line region; the scribe line region is located on one side of the device core region; the semiconductor structure further comprises a semiconductor body, a first electrode, a first insulating layer and a buffer layer; the semiconductor body comprises a first surface and a second surface arranged opposite to each other; the first insulating layer is located on the first surface and at least located in the scribe line region; the first electrode is located on a side of the first insulating layer away from the semiconductor body and located in the device core region; the buffer layer is located on a surface of the first electrode away from the semiconductor body, and the buffer layer is located in the device core region; Forming a passivation layer on a side of the buffer layer away from the first electrode, wherein the passivation layer is located in the device core region and the scribe line region; Removing at least a portion of the passivation layer in the device core region and the scribe line region; The first insulating layer in the scribe line region is removed, wherein the buffer layer is at least partially retained during the removal of the first insulating layer and covers the first electrode; removing at least a portion of the buffer layer; Performing scribing cuts in the scribing street area; Provide semiconductor structures including: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and being located on the first surface, the well region being of a second conductivity type and being located on a side of the first region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body; a source trench is provided on the first surface, the source trench extends from the first surface into the semiconductor body; the semiconductor body further comprising a second insulating layer and a third insulating layer, the second insulating layer being located on a bottom surface and a side wall of the gate trench, the third insulating layer being located on a bottom surface and a side wall of the source trench; A gate is formed in the gate trench on a side of the second insulating layer away from the semiconductor body, wherein the second insulating layer is used for insulating and spacing the semiconductor body and the gate; forming an interlayer insulating layer on a side of the gate away from the semiconductor body, wherein the interlayer insulating layer covers the gate; A trench source structure is formed in the source trench on a side of the third insulating layer away from the semiconductor body; the trench source structure includes a filling layer, and the third insulating layer is used for insulating and spacing the semiconductor body and the filling layer; A first electrode is formed on a side of the first surface away from the second surface, the first electrode being a source electrode; the interlayer insulating layer is used for insulating and spacing the gate electrode and the source electrode; A drain is formed on the second surface of the semiconductor body.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating layer and the buffer layer are made of the same material, and the buffer layer has a thickness greater than that of the first insulating layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating layer and the buffer layer are made of different materials; When removing the first insulating layer in the scribe line area, a removal rate of the buffer layer is controlled to be lower than a removal rate of the first insulating layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The buffer layer includes at least two sub-buffer layers. When the first insulating layer in the scribe line region is removed, a removal rate of at least a portion of the sub-buffer layers is controlled to be lower than a removal rate of the first insulating layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: When removing the passivation layer in the scribe line region, a removal rate of at least a portion of the sub-buffer layer is controlled to be lower than a removal rate of the passivation layer.

6. The method for manufacturing a semiconductor device according to claim 4, wherein: The sub-buffer layer includes any one of silicon oxide, silicon nitride, polysilicon, silicon, germanium, and a silicon-germanium heterostructure, or a combination of at least two thereof.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating layer includes a first sub-insulating layer and a second sub-insulating layer; The first sub-insulating layer is located on the first surface of the semiconductor body; the first sub-insulating layer and the second insulating layer are located on the same layer; The second sub-insulating layer is located on a side of the first sub-insulating layer away from the first surface; the second sub-insulating layer and the interlayer insulating layer are located in the same layer.

8. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 7.

9. A chip structure, characterized in that: include: A semiconductor structure, the semiconductor structure comprising a device core region and a scribe line region; the scribe line region is located on one side of the device core region; the semiconductor structure further comprises a semiconductor body, a first electrode, a first insulating layer and a buffer layer; the semiconductor body comprises a first surface and a second surface arranged opposite to each other; the first insulating layer is located on the first surface and at least located in the scribe line region; the first electrode is located on a side of the first insulating layer away from the semiconductor body and located in the device core region; the buffer layer is located on a surface of the first electrode away from the semiconductor body, and the buffer layer is located in the device core region, and the buffer layer is used to at least partially remain during the removal process of the first insulating layer and cover the first electrode; A passivation layer, located on a side of the buffer layer away from the first electrode, and the passivation layer is located in the device core area and the scribe line area; The semiconductor body further includes a well region and a first region, the first region is of a first conductivity type and is located on the first surface, and the well region is of a second conductivity type and is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; a source trench is provided on the first surface, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further includes a second insulating layer and a third insulating layer, the second insulating layer is located on the bottom surface and side walls of the gate trench, and the third insulating layer is located on the bottom surface and side walls of the source trench; a gate is located in the gate trench on a side of the second insulating layer away from the semiconductor body, and the second insulating layer is used for insulating and spacing the semiconductor body and the gate; An interlayer insulating layer, located at a side of the gate away from the semiconductor body, the interlayer insulating layer covering the gate; A trench source structure, located in the source trench on a side of the third insulating layer away from the semiconductor body, the trench source structure comprising a filling layer, and the third insulating layer is used for insulating and spacing the semiconductor body and the filling layer; The first electrode is a source electrode; The interlayer insulating layer is used for insulating and spacing the gate electrode and the source electrode; The drain is located on the second surface of the semiconductor body.

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