Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate which comprises a plurality of bit lines and initial bit line isolation structures covering each bit line, and also comprises node contact parts located between the adjacent initial bit line isolation structures; removing part of the initial bit line isolation structure to obtain a middle bit line isolation structure; an isolation material layer is deposited on the substrate, and gaps between the adjacent middle bit line isolation structures are filled with the isolation material layer; the isolation material layer on the node contact part is removed to obtain an ultimate bit line isolation structure with an isolation widening part, and the isolation widening part is located on the middle bit line isolation structure; and forming a plurality of landing pads arranged at intervals on the isolation widening part and the node contact part.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the semiconductor manufacturing process, the size of the landing pad affects the electrical transmission performance. Due to the shape characteristics of the bit line structure at the bottom of the landing pad, short circuits and landing pad peeling often occur between adjacent landing pads, affecting the electrical transmission performance and product yield of the product. Summary of the invention

[0003] In view of this, the main purpose of the present application is to provide a semiconductor structure and a manufacturing method thereof.

[0004] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0005] The present invention provides a method for manufacturing a semiconductor structure, comprising:

[0006] Providing a substrate, the substrate comprising a plurality of bit lines and an initial bit line isolation structure covering each of the bit lines, the substrate further comprising a node contact portion located between adjacent initial bit line isolation structures;

[0007] removing part of the initial bit line isolation structure to obtain an intermediate bit line isolation structure;

[0008] Depositing an isolation material layer on the substrate, wherein the isolation material layer fills the gap between adjacent intermediate bit line isolation structures;

[0009] removing the isolation material layer located on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure;

[0010] A plurality of landing pads arranged at intervals are formed on the isolation widening portion and the node contact portion.

[0011] In some embodiments, the initial bit line isolation structure includes a first isolation layer, an intermediate isolation layer and a second isolation layer, wherein the first isolation layer covers the bit line, the intermediate isolation layer is located on a side of the first isolation layer away from the bit line, and the second isolation layer is located on a side of the intermediate isolation layer away from the bit line;

[0012] The removing part of the initial bit line isolation structure comprises:

[0013] At least a portion of the second isolation layer is removed.

[0014] In some embodiments, a material of the isolation material layer is the same as a material of the second isolation layer.

[0015] In some embodiments, removing the isolation material layer on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure, comprises:

[0016] The isolation material layer is subjected to chemical mechanical polishing treatment, and the isolation material layer located on the node contact portion is etched away, so that in a direction parallel to the plane where the substrate is located, the difference between the bottom width and the top width of the bit line structure is within a preset range. The bit line structure includes the bit line and the ultimate bit line isolation structure covering the bit line.

[0017] In some embodiments, the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

[0018] In some embodiments, forming a plurality of landing pads spaced apart on the isolation widening portion and the node contact portion comprises:

[0019] Depositing a contact material layer and a landing material layer on the isolation widening portion and the node contact portion in sequence, wherein the contact material layer continuously covers the surface of the isolation widening portion and the surface of the node contact portion, and the landing material layer covers the contact material layer and at least fills the groove formed by the contact material layer;

[0020] Part of the landing material layer and part of the contact material layer between adjacent isolation widening portions are removed to obtain a plurality of landing pads arranged at intervals.

[0021] In some embodiments, the landing pad includes a first sub-pad, a second sub-pad, and a third sub-pad connecting the first sub-pad and the second sub-pad, wherein the first sub-pad is located on the top surface of the isolation widening portion, the second sub-pad is located on the top surface of the node contact portion, and the third sub-pad is located on the side of the isolation widening portion; wherein the third sub-pad is arranged vertically or substantially vertically to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane.

[0022] An embodiment of the present application also provides a semiconductor structure, including a substrate and a plurality of landing pads arranged at intervals, wherein the substrate includes a plurality of bit lines and an ultimate bit line isolation structure covering each of the bit lines, and the substrate also includes a node contact portion located between adjacent ultimate bit line isolation structures, wherein the ultimate bit line isolation structure has an isolation widening portion, the bit line and the ultimate bit line isolation structure constitute a bit line structure, and in a direction parallel to the plane where the substrate is located, the difference between the bottom width and the top width of the bit line structure is within a preset range; the plurality of landing pads arranged at intervals are located on the isolation widening portion and the node contact portion.

[0023] In some embodiments, the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

[0024] In some embodiments, the landing pad includes a first sub-pad, a second sub-pad, and a third sub-pad connecting the first sub-pad and the second sub-pad, wherein the first sub-pad is located on the top surface of the isolation widening portion, the second sub-pad is located on the top surface of the node contact portion, and the third sub-pad is located on the side of the isolation widening portion; wherein the third sub-pad is arranged vertically or substantially vertically to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane.

[0025] A method for manufacturing a semiconductor structure provided by an embodiment of the present application includes: providing a substrate, the substrate including a plurality of bit lines and an initial bit line isolation structure covering each bit line, the substrate also including a node contact portion located between adjacent initial bit line isolation structures; removing a portion of the initial bit line isolation structure to obtain an intermediate bit line isolation structure; depositing an isolation material layer on the substrate, the isolation material layer filling the gap between adjacent intermediate bit line isolation structures; removing the isolation material layer located on the node contact portion to obtain an ultimate bit line isolation structure having an isolation widening portion, the isolation widening portion being located on the intermediate bit line isolation structure; forming a plurality of landing pads arranged at intervals on the isolation widening portion and the node contact portion; the present application improves the shape of the top of the ultimate bit line isolation structure by filling the gap between adjacent intermediate bit line isolation structures with the isolation material layer to obtain the ultimate bit line isolation structure having the isolation widening portion, so that the landing pad can be better fixed on the top of the ultimate bit line isolation structure, avoiding short circuits between adjacent landing pads and peeling of the landing pads, reducing the failure rate, thereby improving the electrical transmission performance and product yield of the product, and improving the stability of the overall process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a to Figure 1g A schematic diagram of the basic structure of each component in the manufacturing process flow of a semiconductor structure in the related art;

[0027] Figure 2 A flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0028] Figure 3a to Figure 3f A schematic diagram of the basic structure of each component in the manufacturing process flow of the semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0030] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0031] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0032] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0035] like Figure 1a to Figure 1g As shown in FIG. 1 , a basic structural diagram of each component in the manufacturing process flow of a semiconductor structure in the related art is shown. In the manufacturing process flow of a semiconductor structure in the related art, first, Figure 1a As shown, a substrate 100 is provided, the substrate 100 includes a substrate 11, a plurality of bit lines 12 located on the substrate 11, and an initial bit line isolation structure 13 covering each of the bit lines 12, and the substrate 100 also includes a node contact portion 14 located between adjacent initial bit line isolation structures 13. The substrate 11 includes an active region 110 and an isolation structure 111 located between adjacent active regions 110, the bit line 12 is connected to the active region 110 through the bit line contact structure, the node contact portion 14 is connected to the active region 110, and the node contact portion 14 is insulated from the bit line 12. The initial bit line isolation structure 13 includes a first isolation layer 130, an intermediate isolation layer 131, and a second isolation layer 132, the first isolation layer 130 covers the bit line 12, the intermediate isolation layer 131 is located on the side of the first isolation layer 130 away from the bit line 12, and the second isolation layer 132 is located on the side of the intermediate isolation layer 131 away from the bit line 12.

[0036] Next, if Figure 1b As shown, a portion of the initial bit line isolation structure 13 is removed to obtain an intermediate bit line isolation structure 15. Specifically, when a portion of the initial bit line isolation structure 13 is removed, the initial bit line isolation structure 13 may be removed with inconsistent uniformity, resulting in inconsistent top widths of the intermediate bit line isolation structure 15. The top widths of some intermediate bit line isolation structures 15 are particularly small (e.g., Figure 1b ).

[0037] Next, if Figure 1cAs shown, a relatively thin isolation material layer 16 is deposited on the substrate 100, and the isolation material layer 16 is located on the surface of the intermediate bit line isolation structure 15 and the node contact portion 14. The isolation material layer 16 is used to compensate for the damage to the top of the intermediate bit line isolation structure 15 caused by removing part of the initial bit line isolation structure 13. Since the relatively thin isolation material layer 16 is deposited in the related art, the top width of the marked bit line isolation structure X is still small.

[0038] Next, if Figure 1d As shown, the isolation material layer 16 located on the node contact portion 14 is removed, and only the isolation material layer 16 located on the surface of the intermediate bit line isolation structure 15 is retained, and the isolation material layer 16 located on the surface of the intermediate bit line isolation structure 15 is combined with the intermediate bit line isolation structure 15 to form a final bit line isolation structure 17. It can be understood that since the landing pad 18 to be manufactured later needs to be connected to the node contact portion 14, the isolation material layer 16 located on the node contact portion 14 needs to be removed.

[0039] Next, if Figure 1e As shown, a contact material layer 180 and a landing material layer 181 are sequentially deposited on the isolation material layer 16 and the node contact portion 14 , wherein the contact material layer 180 continuously covers the surface of the isolation material layer 16 and the surface of the node contact portion 14 , and the landing material layer 181 covers the contact material layer 180 and at least fills the groove formed by the contact material layer 180 .

[0040] Next, if Figure 1f As shown, part of the landing material layer 181 and part of the contact material layer 180 between the adjacent ultimate bit line isolation structures 17 are removed to obtain a plurality of contact layers 1801 arranged at intervals and a landing layer 1811 located on the contact layer 1801, wherein one contact layer 1801 and the landing layer 1811 located on the contact layer 1801 are combined into a landing pad 18. It can be understood that, due to the small top width of the mark bit line isolation structure X, the contact material layer 180 located on the mark bit line isolation structure X is not in the target etching area. When the contact material layer 180 is removed, the contact layer 1801 located on the mark bit line isolation structure X is not etched and disconnected from the contact layer 1801 on the adjacent ultimate bit line isolation structure 17, thereby causing a short circuit between the landing pad 18 located on the mark bit line isolation structure X and the adjacent landing pad 18.

[0041] In addition, if Figure 1g As shown, since the top width of the mark bit line isolation structure X is small, the landing pad 18 located on the mark bit line isolation structure X may be peeled off during the formation process.

[0042] In summary, it can be understood that due to the poor uniformity of the top width of the ultimate bit line isolation structure 17 at the bottom of the landing pad 18, short circuits often occur between adjacent landing pads 18 and peeling of the landing pads 18 occurs during the manufacturing process, affecting the electrical transmission performance and product yield of the product. The embodiments of the present application can solve the above defects.

[0043] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application, wherein the method comprises:

[0044] S1. Providing a substrate, wherein the substrate comprises a plurality of bit lines and an initial bit line isolation structure covering each of the bit lines, and the substrate further comprises a node contact portion located between adjacent initial bit line isolation structures;

[0045] S2, removing part of the initial bit line isolation structure to obtain an intermediate bit line isolation structure;

[0046] S3, depositing an isolation material layer on the substrate, wherein the isolation material layer fills the gaps between adjacent middle bit line isolation structures;

[0047] S4, removing the isolation material layer located on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure;

[0048] S5. Form a plurality of landing pads disposed at intervals on the isolation widening portion and the node contact portion.

[0049] It can be understood that the present application compensates for the uniformity of the top width of the intermediate bit line isolation structure by filling the gap between adjacent intermediate bit line isolation structures with an isolation material layer, so as to obtain an ultimate bit line isolation structure with an isolation widening portion. The isolation widening portion increases the width of the top of the ultimate bit line isolation structure so that the landing pad can be better fixed on the top of the ultimate bit line isolation structure, avoiding short circuits between adjacent landing pads and landing pad peeling, reducing the failure rate, thereby improving the product's electrical transmission performance and product yield, and improving the stability of the overall process.

[0050] Next, combine Figure 3a to Figure 3f The method for manufacturing the semiconductor structure provided in the embodiment of the present application is described in detail. Figure 3a to Figure 3f A schematic diagram of the basic structure of each component in the manufacturing process flow of the semiconductor structure provided in an embodiment of the present application.

[0051] In step S1, if Figure 3aAs shown, a substrate 100 is provided, the substrate 100 includes a substrate 11, a plurality of bit lines 12 located on the substrate 11, and an initial bit line isolation structure 13 covering each of the bit lines 12, and the substrate 100 also includes a node contact portion 14 located between adjacent initial bit line isolation structures 13. The substrate 11 includes an active region 110 and an isolation structure 111 located between adjacent active regions 110, the bit line 12 is connected to the active region 110 through the bit line contact structure, the node contact portion 14 is connected to the active region 110, and the node contact portion 14 is insulated from the bit line 12. The initial bit line isolation structure 13 includes a first isolation layer 130, an intermediate isolation layer 131, and a second isolation layer 132, the first isolation layer 130 covers the bit line 12, the intermediate isolation layer 131 is located on the side of the first isolation layer 130 away from the bit line 12, and the second isolation layer 132 is located on the side of the intermediate isolation layer 131 away from the bit line 12.

[0052] It should be noted that the material of the substrate 11 is, for example, silicon, the material of the isolation structure 111 is, for example, silicon oxide, the material of the node contact portion 14 is, for example, polysilicon, the material of the bit line 12 includes a conductive material, the material of the first isolation layer 130 and the second isolation layer 132 is, for example, silicon nitride, and the material of the intermediate isolation layer 131 is, for example, silicon oxide.

[0053] In step S2, if Figure 3b As shown, an etching process is used to remove part of the initial bit line isolation structure 13 to obtain an intermediate bit line isolation structure 15. Specifically, when removing part of the initial bit line isolation structure 13, there may be a situation where the removal uniformity of the initial bit line isolation structure 13 is inconsistent, resulting in inconsistent top widths of the intermediate bit line isolation structure 15. The top widths of some intermediate bit line isolation structures 15 are particularly small (e.g., Figure 3b ).

[0054] In some embodiments, removing a portion of the initial bit line isolation structure 13 includes: removing at least a portion of the second isolation layer 132 .

[0055] It should be noted that, when removing part of the initial bit line isolation structure 13, only part of the second isolation layer 132 may be removed, or part of the second isolation layer 132 and part of the intermediate isolation layer 131 may be removed. Figure 3b In the figure, the removal of part of the second isolation layer 132 and part of the middle isolation layer 131 is taken as an example. In addition, part of the first isolation layer 130 in the mark bit line isolation structure X is also removed. This is an accidental situation, and the first isolation layer 130 is not the target removal object.

[0056] In step S3, if Figure 3c As shown, an isolation material layer 16 is deposited on the substrate 100 , and the isolation material layer 16 fills the gaps between the adjacent middle bit line isolation structures 15 .

[0057] It can be understood that the isolation material layer 16 is used to compensate for the damage to the top of the intermediate bit line isolation structure 15 caused by removing part of the initial bit line isolation structure 13, and because the isolation material layer 16 deposited in the present application fills the gap between adjacent intermediate bit line isolation structures 15, the top width of the intermediate bit line isolation structure 15 does not have the problem of poor uniformity.

[0058] In some embodiments, the material of the isolation material layer 16 is the same as the material of the second isolation layer 132. For example, the material of the isolation material layer 16 and the material of the second isolation layer 132 are both silicon nitride.

[0059] In step S4, Figure 3d As shown, the isolation material layer 16 located on the node contact portion 14 is removed by an etching process to obtain a final bit line isolation structure 17 having an isolation widening portion 19, and the isolation widening portion 19 is located on the intermediate bit line isolation structure 15. The isolation widening portion 19 and the intermediate bit line isolation structure 15 are combined into the final bit line isolation structure 17. It can be understood that since the landing pad 18 to be manufactured later needs to be connected to the node contact portion 14, the isolation material layer 16 located on the node contact portion 14 needs to be removed. In some embodiments, since the node contact portion 14 is easily oxidized, it is also necessary to etch and remove the oxide on the surface of the node contact portion 14.

[0060] It can be understood that, since the isolation material layer 16 deposited in the present application fills the gap between adjacent intermediate bit line isolation structures 15, when only the isolation material layer 16 located on the node contact portion 14 is removed, the isolation material layer 16 located on the intermediate bit line isolation structure 15 is still retained, namely, the isolation widening portion 19, and the isolation widening portion 19 makes up for the problem of uneven top width of the intermediate bit line isolation structure 15, so that the landing pad 18 formed subsequently can be better fixed on the top of the ultimate bit line isolation structure 17. In addition, this step of removing the isolation material layer 16 located on the node contact portion 14 can be performed in the array area and the peripheral area at the same time.

[0061] In some embodiments, the removing of the isolation material layer 16 on the node contact portion 14 to obtain a final bit line isolation structure 17 having an isolation widening portion 19, wherein the isolation widening portion 19 is located on the intermediate bit line isolation structure 15, comprises:

[0062] The isolation material layer 16 is subjected to chemical mechanical polishing treatment, and the isolation material layer 16 located on the node contact portion 14 is etched away, so that in a direction parallel to the plane where the substrate 100 is located, the difference between the bottom width and the top width of the bit line structure is within a preset range. The bit line structure includes the bit line 12 and the ultimate bit line isolation structure 17 covering the bit line 12.

[0063] It can be understood that, in this embodiment, the isolation material layer 16 is subjected to chemical mechanical polishing treatment to make the surface of the isolation material layer 16 more flat, which is conducive to the deposition of subsequent film layers. In addition, in this embodiment, the difference between the bottom width a and the top width b of the finally formed bit line structure is within a preset range, so that the top width of the bit line structure can be controlled and has good uniformity, thereby avoiding failure of the subsequently formed landing pad 18.

[0064] In some embodiments, the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers. For example, the difference between the bottom width a and the top width b of the bit line structure is 0.2 nanometers. It can be understood that the smaller the difference between the bottom width a and the top width b of the bit line structure, the lower the risk of failure of the landing pad 18.

[0065] In step S5, Figure 3f As shown, a plurality of landing pads 18 arranged at intervals are formed on the isolation widening portion 19 and the node contact portion 14 .

[0066] It can be understood that since the ultimate bit line isolation structure 17 includes the intermediate bit line isolation structure 15 and the isolation widening portion 19 located on the intermediate bit line isolation structure 15, the width of the top of the ultimate bit line isolation structure 17 is relatively large, and the uniformity of the width of the top of the ultimate bit line isolation structure 17 is relatively good, so it will not cause a short circuit between the landing pad 18 located on the marking bit line isolation structure X and the adjacent landing pad 18, nor will it cause the landing pad 18 located on the marking bit line isolation structure X to peel off during the formation process.

[0067] In some embodiments, Figure 3e As shown, a plurality of landing pads 18 arranged at intervals are formed on the isolation widening portion 19 and the node contact portion 14, including:

[0068] A contact material layer 180 and a landing material layer 181 are sequentially deposited on the isolation widening portion 19 and the node contact portion 14, wherein the contact material layer 180 continuously covers the surface of the isolation widening portion 19 and the surface of the node contact portion 14, and the landing material layer 181 covers the contact material layer 180 and at least fills the groove formed by the contact material layer 180;

[0069] Part of the landing material layer 181 and part of the contact material layer 180 between adjacent isolation widening portions 19 are removed to obtain a plurality of landing pads 18 arranged at intervals.

[0070] It is understandable that if Figure 3f As shown, a landing pad 18 includes a contact layer 1801 and a landing layer 1811 located on the contact layer 1801, wherein the contact layer 1801 is obtained by removing a portion of the contact material layer 180 between adjacent ultimate bit line isolation structures 17, and the landing layer 1811 is obtained by removing a portion of the landing material layer 181 between adjacent ultimate bit line isolation structures 17.

[0071] It should be noted that the material of the contact material layer 180 is, for example, titanium nitride, and the contact material layer 180 is for achieving ohmic contact; the material of the landing material layer 181 is, for example, tungsten.

[0072] It can be understood that, since the top width of the ultimate bit line isolation structure 17 becomes larger, that is, the volume occupied by the ultimate bit line isolation structure 17 becomes larger, the amount of the landing material layer 181 can be reduced, thereby saving production costs.

[0073] In some embodiments, Figure 3f As shown, the landing pad 18 includes a first sub-pad 182, a second sub-pad 183 and a third sub-pad 184 connecting the first sub-pad 182 and the second sub-pad 183, the first sub-pad 182 is located on the top surface of the isolation widening portion 19, the second sub-pad 183 is located on the top surface of the node contact portion 14, and the third sub-pad 184 is located on the side of the isolation widening portion 19; wherein the third sub-pad 184 is vertically or substantially vertically arranged with respect to the first sub-pad 182, the second sub-pad 183 is parallelly arranged with respect to the first sub-pad 182, and the surface of the second sub-pad 183 in contact with one of the ultimate bit line isolation structures 17 is a plane.

[0074] It can be understood that the shape of the landing pad 18 in the embodiment of the present application is changed compared with the shape of the landing pad 18 in the related art, which is caused by the difference in shape between the final bit line isolation structure 17 in the present application and the final bit line isolation structure 17 in the related art. However, the contact area between the landing pad 18 in the embodiment of the present application and the node contact portion 14 is not changed.

[0075] In some embodiments, the edge of the landing pad 18 on the isolated widening portion 19 is flush with the edge of the isolated widening portion 19 .

[0076] Next, if Figure 3fAs shown, an embodiment of the present application also provides a semiconductor structure, including a substrate 100 and a plurality of landing pads 18 arranged at intervals, the substrate 100 including a plurality of bit lines 12 and an ultimate bit line isolation structure 17 covering each of the bit lines 12, the substrate 100 also including a node contact portion 14 located between adjacent ultimate bit line isolation structures 17, wherein the ultimate bit line isolation structure 17 has an isolation widening portion 19, the bit lines 12 and the ultimate bit line isolation structure 17 constitute a bit line structure, and in a direction parallel to the plane where the substrate 100 is located, the difference between the bottom width and the top width of the bit line structure is within a preset range; the plurality of landing pads 18 arranged at intervals are located on the isolation widening portion 19 and the node contact portion 14.

[0077] It can be understood that the present application improves the shape of the top of the ultimate bit line isolation structure 17 by providing the ultimate bit line isolation structure 17 with an isolation widening portion 19, so as to facilitate the landing pad 18 to be better fixed on the top of the ultimate bit line isolation structure 17, avoid short circuits between adjacent landing pads 18 and the peeling of the landing pad 18, reduce the failure rate, thereby improving the electrical transmission performance and product yield of the product, and improving the stability of the overall process. In addition, the present application makes the difference between the bottom width a and the top width b of the bit line structure within a preset range, so that the top width of the bit line structure can be controlled and has good uniformity, further avoiding the failure of the landing pad 18.

[0078] In some embodiments, the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers. For example, the difference between the bottom width a and the top width b of the bit line structure is 0.2 nanometers. It can be understood that the smaller the difference between the bottom width a and the top width b of the bit line structure, the lower the risk of failure of the landing pad 18.

[0079] In some embodiments, the landing pad 18 includes a first sub-pad 182, a second sub-pad 183, and a third sub-pad 184 connecting the first sub-pad 182 and the second sub-pad 183, wherein the first sub-pad 182 is located on the top surface of the isolation widening portion 19, the second sub-pad 183 is located on the top surface of the node contact portion 14, and the third sub-pad 184 is located on the side of the isolation widening portion 19; wherein the third sub-pad 184 is arranged vertically or substantially vertically to the first sub-pad 182, the second sub-pad 183 is arranged parallel to the first sub-pad 182, and the surface of the second sub-pad 183 in contact with one of the ultimate bit line isolation structures 17 is a plane.

[0080] It can be understood that the shape of the landing pad 18 in the embodiment of the present application is changed compared with the shape of the landing pad 18 in the related art, which is caused by the difference in shape between the final bit line isolation structure 17 in the present application and the final bit line isolation structure 17 in the related art. However, the contact area between the landing pad 18 in the embodiment of the present application and the node contact portion 14 is not changed.

[0081] In some embodiments, the edge of the landing pad 18 on the isolated widening portion 19 is flush with the edge of the isolated widening portion 19 .

[0082] In summary, the present invention provides a semiconductor structure and a manufacturing method thereof, the manufacturing method comprising: providing a substrate, the substrate comprising a plurality of bit lines and an initial bit line isolation structure covering each bit line, the substrate further comprising a node contact portion located between adjacent initial bit line isolation structures; removing a portion of the initial bit line isolation structure to obtain an intermediate bit line isolation structure; depositing an isolation material layer on the substrate, the isolation material layer filling the gap between adjacent intermediate bit line isolation structures; removing the isolation material layer located on the node contact portion to obtain an ultimate bit line isolation structure having an isolation widening portion, the isolation widening portion being located on the intermediate bit line isolation structure; forming a A plurality of landing pads are arranged at intervals; the present application obtains a final bit line isolation structure with an isolation widening portion by filling the gaps between adjacent intermediate bit line isolation structures with an isolation material layer, thereby improving the shape of the top of the final bit line isolation structure, so that the landing pad can be better fixed on the top of the final bit line isolation structure, avoiding the occurrence of short circuits between adjacent landing pads and peeling of landing pads, reducing the failure rate, thereby improving the electrical transmission performance and product yield of the product, improving the stability of the overall process, and solving the technical problems of short circuits between adjacent landing pads and peeling of landing pads, which affect the electrical transmission performance and product yield of the product.

[0083] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of bit lines and an initial bit line isolation structure covering each of the bit lines, the substrate further comprising a node contact portion located between adjacent initial bit line isolation structures; removing part of the initial bit line isolation structure to obtain an intermediate bit line isolation structure; Depositing an isolation material layer on the substrate, wherein the isolation material layer fills the gap between adjacent intermediate bit line isolation structures; removing the isolation material layer located on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure; A plurality of landing pads arranged at intervals are formed on the isolation widening portion and the node contact portion.

2. The manufacturing method according to claim 1, characterized in that: The initial bit line isolation structure comprises a first isolation layer, an intermediate isolation layer and a second isolation layer, wherein the first isolation layer covers the bit line, the intermediate isolation layer is located on a side of the first isolation layer away from the bit line, and the second isolation layer is located on a side of the intermediate isolation layer away from the bit line; The removing part of the initial bit line isolation structure comprises: At least a portion of the second isolation layer is removed.

3. The manufacturing method according to claim 2, characterized in that: The material of the isolation material layer is the same as that of the second isolation layer.

4. The manufacturing method according to any one of claims 1 to 3, characterized in that: The step of removing the isolation material layer on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure, comprises: The isolation material layer is subjected to chemical mechanical polishing treatment, and the isolation material layer located on the node contact portion is etched away, so that in a direction parallel to the plane where the substrate is located, the difference between the bottom width and the top width of the bit line structure is within a preset range. The bit line structure includes the bit line and the ultimate bit line isolation structure covering the bit line.

5. The manufacturing method according to claim 4, characterized in that: The preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

6. The manufacturing method according to any one of claims 1 to 3, characterized in that: The step of forming a plurality of landing pads spaced apart on the isolation widening portion and the node contact portion comprises: Depositing a contact material layer and a landing material layer on the isolation widening portion and the node contact portion in sequence, wherein the contact material layer continuously covers the surface of the isolation widening portion and the surface of the node contact portion, and the landing material layer covers the contact material layer and at least fills the groove formed by the contact material layer; Part of the landing material layer and part of the contact material layer between adjacent isolation widening portions are removed to obtain a plurality of landing pads arranged at intervals.

7. The manufacturing method according to claim 6, characterized in that: The landing pad includes a first sub-pad, a second sub-pad, and a third sub-pad connecting the first sub-pad and the second sub-pad, the first sub-pad is located on the top surface of the isolation widening portion, the second sub-pad is located on the top surface of the node contact portion, and the third sub-pad is located on the side of the isolation widening portion; The third sub-pad is arranged vertically or substantially vertically to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane.

8. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a plurality of bit lines and an ultimate bit line isolation structure covering each of the bit lines, the substrate further comprising a node contact portion located between adjacent ultimate bit line isolation structures, wherein the ultimate bit line isolation structure has an isolation widening portion, the bit lines and the ultimate bit line isolation structure constitute a bit line structure, and in a direction parallel to the plane where the substrate is located, a difference between a bottom width and a top width of the bit line structure is within a preset range; A plurality of landing pads are disposed at intervals and are located on the isolation widening portion and the node contact portion.

9. The semiconductor structure according to claim 8, characterized in that: The preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

10. The semiconductor structure according to claim 8 or 9, characterized in that: The landing pad includes a first sub-pad, a second sub-pad, and a third sub-pad connecting the first sub-pad and the second sub-pad, the first sub-pad is located on the top surface of the isolation widening portion, the second sub-pad is located on the top surface of the node contact portion, and the third sub-pad is located on the side of the isolation widening portion; The third sub-pad is arranged vertically or substantially vertically to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane.

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